RDC Register Masks

Macros
#define	RDC_MDA_COUNT   (12U)
#define	RDC_PDAP_COUNT   (128U)
#define	RDC_MRSA_COUNT   (59U)
#define	RDC_MREA_COUNT   (59U)
#define	RDC_MRC_COUNT   (59U)
#define	RDC_MRVS_COUNT   (59U)
#define	RDC_MDA_COUNT   (12U)
#define	RDC_PDAP_COUNT   (128U)
#define	RDC_MRSA_COUNT   (59U)
#define	RDC_MREA_COUNT   (59U)
#define	RDC_MRC_COUNT   (59U)
#define	RDC_MRVS_COUNT   (59U)

VIR - Version Information
#define	RDC_VIR_NDID_MASK   (0xFU)
#define	RDC_VIR_NDID_SHIFT   (0U)
#define	RDC_VIR_NDID(x)   (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NDID_SHIFT)) & RDC_VIR_NDID_MASK)
#define	RDC_VIR_NMSTR_MASK   (0xFF0U)
#define	RDC_VIR_NMSTR_SHIFT   (4U)
#define	RDC_VIR_NMSTR(x)   (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NMSTR_SHIFT)) & RDC_VIR_NMSTR_MASK)
#define	RDC_VIR_NPER_MASK   (0xFF000U)
#define	RDC_VIR_NPER_SHIFT   (12U)
#define	RDC_VIR_NPER(x)   (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NPER_SHIFT)) & RDC_VIR_NPER_MASK)
#define	RDC_VIR_NRGN_MASK   (0xFF00000U)
#define	RDC_VIR_NRGN_SHIFT   (20U)
#define	RDC_VIR_NRGN(x)   (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NRGN_SHIFT)) & RDC_VIR_NRGN_MASK)

STAT - Status
#define	RDC_STAT_DID_MASK   (0xFU)
#define	RDC_STAT_DID_SHIFT   (0U)
#define	RDC_STAT_DID(x)   (((uint32_t)(((uint32_t)(x)) << RDC_STAT_DID_SHIFT)) & RDC_STAT_DID_MASK)
#define	RDC_STAT_PDS_MASK   (0x100U)
#define	RDC_STAT_PDS_SHIFT   (8U)
#define	RDC_STAT_PDS(x)   (((uint32_t)(((uint32_t)(x)) << RDC_STAT_PDS_SHIFT)) & RDC_STAT_PDS_MASK)

INTCTRL - Interrupt and Control
#define	RDC_INTCTRL_RCI_EN_MASK   (0x1U)
#define	RDC_INTCTRL_RCI_EN_SHIFT   (0U)
#define	RDC_INTCTRL_RCI_EN(x)   (((uint32_t)(((uint32_t)(x)) << RDC_INTCTRL_RCI_EN_SHIFT)) & RDC_INTCTRL_RCI_EN_MASK)

INTSTAT - Interrupt Status
#define	RDC_INTSTAT_INT_MASK   (0x1U)
#define	RDC_INTSTAT_INT_SHIFT   (0U)
#define	RDC_INTSTAT_INT(x)   (((uint32_t)(((uint32_t)(x)) << RDC_INTSTAT_INT_SHIFT)) & RDC_INTSTAT_INT_MASK)

MDA - Master Domain Assignment
#define	RDC_MDA_DID_MASK   (0x3U)
#define	RDC_MDA_DID_SHIFT   (0U)
#define	RDC_MDA_DID(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MDA_DID_SHIFT)) & RDC_MDA_DID_MASK)
#define	RDC_MDA_LCK_MASK   (0x80000000U)
#define	RDC_MDA_LCK_SHIFT   (31U)
#define	RDC_MDA_LCK(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MDA_LCK_SHIFT)) & RDC_MDA_LCK_MASK)

PDAP - Peripheral Domain Access Permissions
#define	RDC_PDAP_D0W_MASK   (0x1U)
#define	RDC_PDAP_D0W_SHIFT   (0U)
#define	RDC_PDAP_D0W(x)   (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0W_SHIFT)) & RDC_PDAP_D0W_MASK)
#define	RDC_PDAP_D0R_MASK   (0x2U)
#define	RDC_PDAP_D0R_SHIFT   (1U)
#define	RDC_PDAP_D0R(x)   (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0R_SHIFT)) & RDC_PDAP_D0R_MASK)
#define	RDC_PDAP_D1W_MASK   (0x4U)
#define	RDC_PDAP_D1W_SHIFT   (2U)
#define	RDC_PDAP_D1W(x)   (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1W_SHIFT)) & RDC_PDAP_D1W_MASK)
#define	RDC_PDAP_D1R_MASK   (0x8U)
#define	RDC_PDAP_D1R_SHIFT   (3U)
#define	RDC_PDAP_D1R(x)   (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1R_SHIFT)) & RDC_PDAP_D1R_MASK)
#define	RDC_PDAP_SREQ_MASK   (0x40000000U)
#define	RDC_PDAP_SREQ_SHIFT   (30U)
#define	RDC_PDAP_SREQ(x)   (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_SREQ_SHIFT)) & RDC_PDAP_SREQ_MASK)
#define	RDC_PDAP_LCK_MASK   (0x80000000U)
#define	RDC_PDAP_LCK_SHIFT   (31U)
#define	RDC_PDAP_LCK(x)   (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_LCK_SHIFT)) & RDC_PDAP_LCK_MASK)

MRSA - Memory Region Start Address
#define	RDC_MRSA_SADR_MASK   (0xFFFFFF80U)
#define	RDC_MRSA_SADR_SHIFT   (7U)
#define	RDC_MRSA_SADR(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MRSA_SADR_SHIFT)) & RDC_MRSA_SADR_MASK)

MREA - Memory Region End Address
#define	RDC_MREA_EADR_MASK   (0xFFFFFF80U)
#define	RDC_MREA_EADR_SHIFT   (7U)
#define	RDC_MREA_EADR(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MREA_EADR_SHIFT)) & RDC_MREA_EADR_MASK)

MRC - Memory Region Control
#define	RDC_MRC_D0W_MASK   (0x1U)
#define	RDC_MRC_D0W_SHIFT   (0U)
#define	RDC_MRC_D0W(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0W_SHIFT)) & RDC_MRC_D0W_MASK)
#define	RDC_MRC_D0R_MASK   (0x2U)
#define	RDC_MRC_D0R_SHIFT   (1U)
#define	RDC_MRC_D0R(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0R_SHIFT)) & RDC_MRC_D0R_MASK)
#define	RDC_MRC_D1W_MASK   (0x4U)
#define	RDC_MRC_D1W_SHIFT   (2U)
#define	RDC_MRC_D1W(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1W_SHIFT)) & RDC_MRC_D1W_MASK)
#define	RDC_MRC_D1R_MASK   (0x8U)
#define	RDC_MRC_D1R_SHIFT   (3U)
#define	RDC_MRC_D1R(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1R_SHIFT)) & RDC_MRC_D1R_MASK)
#define	RDC_MRC_ENA_MASK   (0x40000000U)
#define	RDC_MRC_ENA_SHIFT   (30U)
#define	RDC_MRC_ENA(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MRC_ENA_SHIFT)) & RDC_MRC_ENA_MASK)
#define	RDC_MRC_LCK_MASK   (0x80000000U)
#define	RDC_MRC_LCK_SHIFT   (31U)
#define	RDC_MRC_LCK(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MRC_LCK_SHIFT)) & RDC_MRC_LCK_MASK)

MRVS - Memory Region Violation Status
#define	RDC_MRVS_VDID_MASK   (0x3U)
#define	RDC_MRVS_VDID_SHIFT   (0U)
#define	RDC_MRVS_VDID(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VDID_SHIFT)) & RDC_MRVS_VDID_MASK)
#define	RDC_MRVS_AD_MASK   (0x10U)
#define	RDC_MRVS_AD_SHIFT   (4U)
#define	RDC_MRVS_AD(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_AD_SHIFT)) & RDC_MRVS_AD_MASK)
#define	RDC_MRVS_VADR_MASK   (0xFFFFFFE0U)
#define	RDC_MRVS_VADR_SHIFT   (5U)
#define	RDC_MRVS_VADR(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VADR_SHIFT)) & RDC_MRVS_VADR_MASK)

VIR - Version Information
#define	RDC_VIR_NDID_MASK   (0xFU)
#define	RDC_VIR_NDID_SHIFT   (0U)
#define	RDC_VIR_NDID(x)   (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NDID_SHIFT)) & RDC_VIR_NDID_MASK)
#define	RDC_VIR_NMSTR_MASK   (0xFF0U)
#define	RDC_VIR_NMSTR_SHIFT   (4U)
#define	RDC_VIR_NMSTR(x)   (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NMSTR_SHIFT)) & RDC_VIR_NMSTR_MASK)
#define	RDC_VIR_NPER_MASK   (0xFF000U)
#define	RDC_VIR_NPER_SHIFT   (12U)
#define	RDC_VIR_NPER(x)   (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NPER_SHIFT)) & RDC_VIR_NPER_MASK)
#define	RDC_VIR_NRGN_MASK   (0xFF00000U)
#define	RDC_VIR_NRGN_SHIFT   (20U)
#define	RDC_VIR_NRGN(x)   (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NRGN_SHIFT)) & RDC_VIR_NRGN_MASK)

STAT - Status
#define	RDC_STAT_DID_MASK   (0xFU)
#define	RDC_STAT_DID_SHIFT   (0U)
#define	RDC_STAT_DID(x)   (((uint32_t)(((uint32_t)(x)) << RDC_STAT_DID_SHIFT)) & RDC_STAT_DID_MASK)
#define	RDC_STAT_PDS_MASK   (0x100U)
#define	RDC_STAT_PDS_SHIFT   (8U)
#define	RDC_STAT_PDS(x)   (((uint32_t)(((uint32_t)(x)) << RDC_STAT_PDS_SHIFT)) & RDC_STAT_PDS_MASK)

INTCTRL - Interrupt and Control
#define	RDC_INTCTRL_RCI_EN_MASK   (0x1U)
#define	RDC_INTCTRL_RCI_EN_SHIFT   (0U)
#define	RDC_INTCTRL_RCI_EN(x)   (((uint32_t)(((uint32_t)(x)) << RDC_INTCTRL_RCI_EN_SHIFT)) & RDC_INTCTRL_RCI_EN_MASK)

INTSTAT - Interrupt Status
#define	RDC_INTSTAT_INT_MASK   (0x1U)
#define	RDC_INTSTAT_INT_SHIFT   (0U)
#define	RDC_INTSTAT_INT(x)   (((uint32_t)(((uint32_t)(x)) << RDC_INTSTAT_INT_SHIFT)) & RDC_INTSTAT_INT_MASK)

MDA - Master Domain Assignment
#define	RDC_MDA_DID_MASK   (0x3U)
#define	RDC_MDA_DID_SHIFT   (0U)
#define	RDC_MDA_DID(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MDA_DID_SHIFT)) & RDC_MDA_DID_MASK)
#define	RDC_MDA_LCK_MASK   (0x80000000U)
#define	RDC_MDA_LCK_SHIFT   (31U)
#define	RDC_MDA_LCK(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MDA_LCK_SHIFT)) & RDC_MDA_LCK_MASK)

PDAP - Peripheral Domain Access Permissions
#define	RDC_PDAP_D0W_MASK   (0x1U)
#define	RDC_PDAP_D0W_SHIFT   (0U)
#define	RDC_PDAP_D0W(x)   (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0W_SHIFT)) & RDC_PDAP_D0W_MASK)
#define	RDC_PDAP_D0R_MASK   (0x2U)
#define	RDC_PDAP_D0R_SHIFT   (1U)
#define	RDC_PDAP_D0R(x)   (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0R_SHIFT)) & RDC_PDAP_D0R_MASK)
#define	RDC_PDAP_D1W_MASK   (0x4U)
#define	RDC_PDAP_D1W_SHIFT   (2U)
#define	RDC_PDAP_D1W(x)   (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1W_SHIFT)) & RDC_PDAP_D1W_MASK)
#define	RDC_PDAP_D1R_MASK   (0x8U)
#define	RDC_PDAP_D1R_SHIFT   (3U)
#define	RDC_PDAP_D1R(x)   (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1R_SHIFT)) & RDC_PDAP_D1R_MASK)
#define	RDC_PDAP_SREQ_MASK   (0x40000000U)
#define	RDC_PDAP_SREQ_SHIFT   (30U)
#define	RDC_PDAP_SREQ(x)   (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_SREQ_SHIFT)) & RDC_PDAP_SREQ_MASK)
#define	RDC_PDAP_LCK_MASK   (0x80000000U)
#define	RDC_PDAP_LCK_SHIFT   (31U)
#define	RDC_PDAP_LCK(x)   (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_LCK_SHIFT)) & RDC_PDAP_LCK_MASK)

MRSA - Memory Region Start Address
#define	RDC_MRSA_SADR_MASK   (0xFFFFFF80U)
#define	RDC_MRSA_SADR_SHIFT   (7U)
#define	RDC_MRSA_SADR(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MRSA_SADR_SHIFT)) & RDC_MRSA_SADR_MASK)

MREA - Memory Region End Address
#define	RDC_MREA_EADR_MASK   (0xFFFFFF80U)
#define	RDC_MREA_EADR_SHIFT   (7U)
#define	RDC_MREA_EADR(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MREA_EADR_SHIFT)) & RDC_MREA_EADR_MASK)

MRC - Memory Region Control
#define	RDC_MRC_D0W_MASK   (0x1U)
#define	RDC_MRC_D0W_SHIFT   (0U)
#define	RDC_MRC_D0W(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0W_SHIFT)) & RDC_MRC_D0W_MASK)
#define	RDC_MRC_D0R_MASK   (0x2U)
#define	RDC_MRC_D0R_SHIFT   (1U)
#define	RDC_MRC_D0R(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0R_SHIFT)) & RDC_MRC_D0R_MASK)
#define	RDC_MRC_D1W_MASK   (0x4U)
#define	RDC_MRC_D1W_SHIFT   (2U)
#define	RDC_MRC_D1W(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1W_SHIFT)) & RDC_MRC_D1W_MASK)
#define	RDC_MRC_D1R_MASK   (0x8U)
#define	RDC_MRC_D1R_SHIFT   (3U)
#define	RDC_MRC_D1R(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1R_SHIFT)) & RDC_MRC_D1R_MASK)
#define	RDC_MRC_ENA_MASK   (0x40000000U)
#define	RDC_MRC_ENA_SHIFT   (30U)
#define	RDC_MRC_ENA(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MRC_ENA_SHIFT)) & RDC_MRC_ENA_MASK)
#define	RDC_MRC_LCK_MASK   (0x80000000U)
#define	RDC_MRC_LCK_SHIFT   (31U)
#define	RDC_MRC_LCK(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MRC_LCK_SHIFT)) & RDC_MRC_LCK_MASK)

MRVS - Memory Region Violation Status
#define	RDC_MRVS_VDID_MASK   (0x3U)
#define	RDC_MRVS_VDID_SHIFT   (0U)
#define	RDC_MRVS_VDID(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VDID_SHIFT)) & RDC_MRVS_VDID_MASK)
#define	RDC_MRVS_AD_MASK   (0x10U)
#define	RDC_MRVS_AD_SHIFT   (4U)
#define	RDC_MRVS_AD(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_AD_SHIFT)) & RDC_MRVS_AD_MASK)
#define	RDC_MRVS_VADR_MASK   (0xFFFFFFE0U)
#define	RDC_MRVS_VADR_SHIFT   (5U)
#define	RDC_MRVS_VADR(x)   (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VADR_SHIFT)) & RDC_MRVS_VADR_MASK)

Detailed Description

Macro Definition Documentation

RDC_INTCTRL_RCI_EN [1/2]

#define RDC_INTCTRL_RCI_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_INTCTRL_RCI_EN_SHIFT)) & RDC_INTCTRL_RCI_EN_MASK)

RCI_EN - Restoration Complete Interrupt 0b0..Interrupt Disabled 0b1..Interrupt Enabled

RDC_INTCTRL_RCI_EN [2/2]

#define RDC_INTCTRL_RCI_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_INTCTRL_RCI_EN_SHIFT)) & RDC_INTCTRL_RCI_EN_MASK)

RCI_EN - Restoration Complete Interrupt 0b0..Interrupt Disabled 0b1..Interrupt Enabled

RDC_INTSTAT_INT [1/2]

#define RDC_INTSTAT_INT

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_INTSTAT_INT_SHIFT)) & RDC_INTSTAT_INT_MASK)

INT - Interrupt Status 0b0..No Interrupt Pending 0b1..Interrupt Pending

RDC_INTSTAT_INT [2/2]

#define RDC_INTSTAT_INT

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_INTSTAT_INT_SHIFT)) & RDC_INTSTAT_INT_MASK)

INT - Interrupt Status 0b0..No Interrupt Pending 0b1..Interrupt Pending

RDC_MDA_DID [1/2]

#define RDC_MDA_DID

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MDA_DID_SHIFT)) & RDC_MDA_DID_MASK)

DID - Domain ID 0b00..Master assigned to Processing Domain 0 0b01..Master assigned to Processing Domain 1 0b10..Reserved 0b11..Reserved

RDC_MDA_DID [2/2]

#define RDC_MDA_DID

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MDA_DID_SHIFT)) & RDC_MDA_DID_MASK)

DID - Domain ID 0b00..Master assigned to Processing Domain 0 0b01..Master assigned to Processing Domain 1 0b10..Reserved 0b11..Reserved

RDC_MDA_LCK [1/2]

#define RDC_MDA_LCK

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MDA_LCK_SHIFT)) & RDC_MDA_LCK_MASK)

LCK - Assignment Lock 0b0..Not Locked 0b1..Locked

RDC_MDA_LCK [2/2]

#define RDC_MDA_LCK

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MDA_LCK_SHIFT)) & RDC_MDA_LCK_MASK)

LCK - Assignment Lock 0b0..Not Locked 0b1..Locked

RDC_MRC_D0R [1/2]

#define RDC_MRC_D0R

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0R_SHIFT)) & RDC_MRC_D0R_MASK)

D0R - Domain 0 Read Access to Region 0b0..Processing Domain 0 does not have Read access to the memory region 0b1..Processing Domain 0 has Read access to the memory region

RDC_MRC_D0R [2/2]

#define RDC_MRC_D0R

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0R_SHIFT)) & RDC_MRC_D0R_MASK)

D0R - Domain 0 Read Access to Region 0b0..Processing Domain 0 does not have Read access to the memory region 0b1..Processing Domain 0 has Read access to the memory region

RDC_MRC_D0W [1/2]

#define RDC_MRC_D0W

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0W_SHIFT)) & RDC_MRC_D0W_MASK)

D0W - Domain 0 Write Access to Region 0b0..Processing Domain 0 does not have Write access to the memory region 0b1..Processing Domain 0 has Write access to the memory region

RDC_MRC_D0W [2/2]

#define RDC_MRC_D0W

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0W_SHIFT)) & RDC_MRC_D0W_MASK)

D0W - Domain 0 Write Access to Region 0b0..Processing Domain 0 does not have Write access to the memory region 0b1..Processing Domain 0 has Write access to the memory region

RDC_MRC_D1R [1/2]

#define RDC_MRC_D1R

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1R_SHIFT)) & RDC_MRC_D1R_MASK)

D1R - Domain 1 Read Access to Region 0b0..Processing Domain 1 does not have Read access to the memory region 0b1..Processing Domain 1 has Read access to the memory region

RDC_MRC_D1R [2/2]

#define RDC_MRC_D1R

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1R_SHIFT)) & RDC_MRC_D1R_MASK)

D1R - Domain 1 Read Access to Region 0b0..Processing Domain 1 does not have Read access to the memory region 0b1..Processing Domain 1 has Read access to the memory region

RDC_MRC_D1W [1/2]

#define RDC_MRC_D1W

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1W_SHIFT)) & RDC_MRC_D1W_MASK)

D1W - Domain 1 Write Access to Region 0b0..Processing Domain 1 does not have Write access to the memory region 0b1..Processing Domain 1 has Write access to the memory region

RDC_MRC_D1W [2/2]

#define RDC_MRC_D1W

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1W_SHIFT)) & RDC_MRC_D1W_MASK)

D1W - Domain 1 Write Access to Region 0b0..Processing Domain 1 does not have Write access to the memory region 0b1..Processing Domain 1 has Write access to the memory region

RDC_MRC_ENA [1/2]

#define RDC_MRC_ENA

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MRC_ENA_SHIFT)) & RDC_MRC_ENA_MASK)

ENA - Region Enable 0b0..Memory region is not defined or restricted. 0b1..Memory boundaries, domain permissions and controls are in effect.

RDC_MRC_ENA [2/2]

#define RDC_MRC_ENA

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MRC_ENA_SHIFT)) & RDC_MRC_ENA_MASK)

ENA - Region Enable 0b0..Memory region is not defined or restricted. 0b1..Memory boundaries, domain permissions and controls are in effect.

RDC_MRC_LCK [1/2]

#define RDC_MRC_LCK

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MRC_LCK_SHIFT)) & RDC_MRC_LCK_MASK)

LCK - Region Lock 0b0..No Lock. All fields in this register may be modified. 0b1..Locked. No fields in this register may be modified except ENA, which may be set but not cleared.

RDC_MRC_LCK [2/2]

#define RDC_MRC_LCK

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MRC_LCK_SHIFT)) & RDC_MRC_LCK_MASK)

LCK - Region Lock 0b0..No Lock. All fields in this register may be modified. 0b1..Locked. No fields in this register may be modified except ENA, which may be set but not cleared.

RDC_MREA_EADR [1/2]

#define RDC_MREA_EADR

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MREA_EADR_SHIFT)) & RDC_MREA_EADR_MASK)

EADR - Upper bound for memory region

RDC_MREA_EADR [2/2]

#define RDC_MREA_EADR

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MREA_EADR_SHIFT)) & RDC_MREA_EADR_MASK)

EADR - Upper bound for memory region

RDC_MRSA_SADR [1/2]

#define RDC_MRSA_SADR

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MRSA_SADR_SHIFT)) & RDC_MRSA_SADR_MASK)

SADR - Start address for memory region

RDC_MRSA_SADR [2/2]

#define RDC_MRSA_SADR

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MRSA_SADR_SHIFT)) & RDC_MRSA_SADR_MASK)

SADR - Start address for memory region

RDC_MRVS_AD [1/2]

#define RDC_MRVS_AD

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MRVS_AD_SHIFT)) & RDC_MRVS_AD_MASK)

AD - Access Denied

RDC_MRVS_AD [2/2]

#define RDC_MRVS_AD

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MRVS_AD_SHIFT)) & RDC_MRVS_AD_MASK)

AD - Access Denied

RDC_MRVS_VADR [1/2]

#define RDC_MRVS_VADR

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VADR_SHIFT)) & RDC_MRVS_VADR_MASK)

VADR - Violating Address

RDC_MRVS_VADR [2/2]

#define RDC_MRVS_VADR

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VADR_SHIFT)) & RDC_MRVS_VADR_MASK)

VADR - Violating Address

RDC_MRVS_VDID [1/2]

#define RDC_MRVS_VDID

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VDID_SHIFT)) & RDC_MRVS_VDID_MASK)

VDID - Violating Domain ID 0b00..Processing Domain 0 0b01..Processing Domain 1 0b10..Reserved 0b11..Reserved

RDC_MRVS_VDID [2/2]

#define RDC_MRVS_VDID

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VDID_SHIFT)) & RDC_MRVS_VDID_MASK)

VDID - Violating Domain ID 0b00..Processing Domain 0 0b01..Processing Domain 1 0b10..Reserved 0b11..Reserved

RDC_PDAP_D0R [1/2]

#define RDC_PDAP_D0R

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0R_SHIFT)) & RDC_PDAP_D0R_MASK)

D0R - Domain 0 Read Access 0b0..No Read Access 0b1..Read Access Allowed

RDC_PDAP_D0R [2/2]

#define RDC_PDAP_D0R

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0R_SHIFT)) & RDC_PDAP_D0R_MASK)

D0R - Domain 0 Read Access 0b0..No Read Access 0b1..Read Access Allowed

RDC_PDAP_D0W [1/2]

#define RDC_PDAP_D0W

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0W_SHIFT)) & RDC_PDAP_D0W_MASK)

D0W - Domain 0 Write Access 0b0..No Write Access 0b1..Write Access Allowed

RDC_PDAP_D0W [2/2]

#define RDC_PDAP_D0W

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0W_SHIFT)) & RDC_PDAP_D0W_MASK)

D0W - Domain 0 Write Access 0b0..No Write Access 0b1..Write Access Allowed

RDC_PDAP_D1R [1/2]

#define RDC_PDAP_D1R

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1R_SHIFT)) & RDC_PDAP_D1R_MASK)

D1R - Domain 1 Read Access 0b0..No Read Access 0b1..Read Access Allowed

RDC_PDAP_D1R [2/2]

#define RDC_PDAP_D1R

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1R_SHIFT)) & RDC_PDAP_D1R_MASK)

D1R - Domain 1 Read Access 0b0..No Read Access 0b1..Read Access Allowed

RDC_PDAP_D1W [1/2]

#define RDC_PDAP_D1W

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1W_SHIFT)) & RDC_PDAP_D1W_MASK)

D1W - Domain 1 Write Access 0b0..No Write Access 0b1..Write Access Allowed

RDC_PDAP_D1W [2/2]

#define RDC_PDAP_D1W

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1W_SHIFT)) & RDC_PDAP_D1W_MASK)

D1W - Domain 1 Write Access 0b0..No Write Access 0b1..Write Access Allowed

RDC_PDAP_LCK [1/2]

#define RDC_PDAP_LCK

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_PDAP_LCK_SHIFT)) & RDC_PDAP_LCK_MASK)

LCK - Peripheral Permissions Lock 0b0..Not Locked 0b1..Locked

RDC_PDAP_LCK [2/2]

#define RDC_PDAP_LCK

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_PDAP_LCK_SHIFT)) & RDC_PDAP_LCK_MASK)

LCK - Peripheral Permissions Lock 0b0..Not Locked 0b1..Locked

RDC_PDAP_SREQ [1/2]

#define RDC_PDAP_SREQ

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_PDAP_SREQ_SHIFT)) & RDC_PDAP_SREQ_MASK)

SREQ - Semaphore Required 0b0..Semaphores have no effect 0b1..Semaphores are enforced

RDC_PDAP_SREQ [2/2]

#define RDC_PDAP_SREQ

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_PDAP_SREQ_SHIFT)) & RDC_PDAP_SREQ_MASK)

SREQ - Semaphore Required 0b0..Semaphores have no effect 0b1..Semaphores are enforced

RDC_STAT_DID [1/2]

#define RDC_STAT_DID

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_STAT_DID_SHIFT)) & RDC_STAT_DID_MASK)

DID - Domain ID

RDC_STAT_DID [2/2]

#define RDC_STAT_DID

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_STAT_DID_SHIFT)) & RDC_STAT_DID_MASK)

DID - Domain ID

RDC_STAT_PDS [1/2]

#define RDC_STAT_PDS

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_STAT_PDS_SHIFT)) & RDC_STAT_PDS_MASK)

PDS - Power Domain Status 0b0..Power Down Domain is OFF 0b1..Power Down Domain is ON

RDC_STAT_PDS [2/2]

#define RDC_STAT_PDS

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_STAT_PDS_SHIFT)) & RDC_STAT_PDS_MASK)

PDS - Power Domain Status 0b0..Power Down Domain is OFF 0b1..Power Down Domain is ON

RDC_VIR_NDID [1/2]

#define RDC_VIR_NDID

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_VIR_NDID_SHIFT)) & RDC_VIR_NDID_MASK)

NDID - Number of Domains

RDC_VIR_NDID [2/2]

#define RDC_VIR_NDID

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_VIR_NDID_SHIFT)) & RDC_VIR_NDID_MASK)

NDID - Number of Domains

RDC_VIR_NMSTR [1/2]

#define RDC_VIR_NMSTR

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_VIR_NMSTR_SHIFT)) & RDC_VIR_NMSTR_MASK)

NMSTR - Number of Masters

RDC_VIR_NMSTR [2/2]

#define RDC_VIR_NMSTR

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_VIR_NMSTR_SHIFT)) & RDC_VIR_NMSTR_MASK)

NMSTR - Number of Masters

RDC_VIR_NPER [1/2]

#define RDC_VIR_NPER

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_VIR_NPER_SHIFT)) & RDC_VIR_NPER_MASK)

NPER - Number of Peripherals

RDC_VIR_NPER [2/2]

#define RDC_VIR_NPER

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_VIR_NPER_SHIFT)) & RDC_VIR_NPER_MASK)

NPER - Number of Peripherals

RDC_VIR_NRGN [1/2]

#define RDC_VIR_NRGN

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_VIR_NRGN_SHIFT)) & RDC_VIR_NRGN_MASK)

NRGN - Number of Memory Regions

RDC_VIR_NRGN [2/2]

#define RDC_VIR_NRGN

(

x

)

(((uint32_t)(((uint32_t)(x)) << RDC_VIR_NRGN_SHIFT)) & RDC_VIR_NRGN_MASK)

NRGN - Number of Memory Regions