RTEMS 6.1-rc2
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Macros

Macros

#define RCC_CRS_SYNC_DIV1   (0x00000000U)
 
#define RCC_CRS_SYNC_DIV2   CRS_CFGR_SYNCDIV_0
 
#define RCC_CRS_SYNC_DIV4   CRS_CFGR_SYNCDIV_1
 
#define RCC_CRS_SYNC_DIV8   (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)
 
#define RCC_CRS_SYNC_DIV16   CRS_CFGR_SYNCDIV_2
 
#define RCC_CRS_SYNC_DIV32   (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)
 
#define RCC_CRS_SYNC_DIV64   (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)
 
#define RCC_CRS_SYNC_DIV128   CRS_CFGR_SYNCDIV
 

Detailed Description

Macro Definition Documentation

◆ RCC_CRS_SYNC_DIV1

#define RCC_CRS_SYNC_DIV1   (0x00000000U)

Synchro Signal not divided (default)

◆ RCC_CRS_SYNC_DIV128

#define RCC_CRS_SYNC_DIV128   CRS_CFGR_SYNCDIV

Synchro Signal divided by 128

◆ RCC_CRS_SYNC_DIV16

#define RCC_CRS_SYNC_DIV16   CRS_CFGR_SYNCDIV_2

Synchro Signal divided by 16

◆ RCC_CRS_SYNC_DIV2

#define RCC_CRS_SYNC_DIV2   CRS_CFGR_SYNCDIV_0

Synchro Signal divided by 2

◆ RCC_CRS_SYNC_DIV32

#define RCC_CRS_SYNC_DIV32   (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)

Synchro Signal divided by 32

◆ RCC_CRS_SYNC_DIV4

#define RCC_CRS_SYNC_DIV4   CRS_CFGR_SYNCDIV_1

Synchro Signal divided by 4

◆ RCC_CRS_SYNC_DIV64

#define RCC_CRS_SYNC_DIV64   (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)

Synchro Signal divided by 64

◆ RCC_CRS_SYNC_DIV8

#define RCC_CRS_SYNC_DIV8   (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)

Synchro Signal divided by 8