Macros
#define	OTFAD_KEY_COUNT (4U)

#define	OTFAD_KEY_COUNT2 (4U)

#define	OTFAD_CTR_COUNT (4U)

#define	OTFAD_CTR_COUNT2 (2U)

#define	OTFAD_RGD_W0_COUNT (4U)

#define	OTFAD_RGD_W1_COUNT (4U)

#define	OTFAD_KEY_COUNT (4U)

#define	OTFAD_KEY_COUNT2 (4U)

#define	OTFAD_CTR_COUNT (4U)

#define	OTFAD_CTR_COUNT2 (2U)

#define	OTFAD_RGD_W0_COUNT (4U)

#define	OTFAD_RGD_W1_COUNT (4U)

CR - Control Register
#define	OTFAD_CR_FERR_MASK (0x2U)

#define	OTFAD_CR_FERR_SHIFT (1U)

#define	OTFAD_CR_FERR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FERR_SHIFT)) & OTFAD_CR_FERR_MASK)

#define	OTFAD_CR_FLDM_MASK (0x8U)

#define	OTFAD_CR_FLDM_SHIFT (3U)

#define	OTFAD_CR_FLDM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FLDM_SHIFT)) & OTFAD_CR_FLDM_MASK)

#define	OTFAD_CR_KBSE_MASK (0x10U)

#define	OTFAD_CR_KBSE_SHIFT (4U)

#define	OTFAD_CR_KBSE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBSE_SHIFT)) & OTFAD_CR_KBSE_MASK)

#define	OTFAD_CR_KBPE_MASK (0x20U)

#define	OTFAD_CR_KBPE_SHIFT (5U)

#define	OTFAD_CR_KBPE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBPE_SHIFT)) & OTFAD_CR_KBPE_MASK)

#define	OTFAD_CR_RRAE_MASK (0x80U)

#define	OTFAD_CR_RRAE_SHIFT (7U)

#define	OTFAD_CR_RRAE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_RRAE_SHIFT)) & OTFAD_CR_RRAE_MASK)

#define	OTFAD_CR_SKBP_MASK (0x40000000U)

#define	OTFAD_CR_SKBP_SHIFT (30U)

#define	OTFAD_CR_SKBP(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_SKBP_SHIFT)) & OTFAD_CR_SKBP_MASK)

#define	OTFAD_CR_GE_MASK (0x80000000U)

#define	OTFAD_CR_GE_SHIFT (31U)

#define	OTFAD_CR_GE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_GE_SHIFT)) & OTFAD_CR_GE_MASK)

SR - Status Register
#define	OTFAD_SR_KBERR_MASK (0x1U)

#define	OTFAD_SR_KBERR_SHIFT (0U)

#define	OTFAD_SR_KBERR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBERR_SHIFT)) & OTFAD_SR_KBERR_MASK)

#define	OTFAD_SR_MDPCP_MASK (0x2U)

#define	OTFAD_SR_MDPCP_SHIFT (1U)

#define	OTFAD_SR_MDPCP(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MDPCP_SHIFT)) & OTFAD_SR_MDPCP_MASK)

#define	OTFAD_SR_MODE_MASK (0xCU)

#define	OTFAD_SR_MODE_SHIFT (2U)

#define	OTFAD_SR_MODE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MODE_SHIFT)) & OTFAD_SR_MODE_MASK)

#define	OTFAD_SR_NCTX_MASK (0xF0U)

#define	OTFAD_SR_NCTX_SHIFT (4U)

#define	OTFAD_SR_NCTX(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_NCTX_SHIFT)) & OTFAD_SR_NCTX_MASK)

#define	OTFAD_SR_CTXER0_MASK (0x100U)

#define	OTFAD_SR_CTXER0_SHIFT (8U)

#define	OTFAD_SR_CTXER0(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER0_SHIFT)) & OTFAD_SR_CTXER0_MASK)

#define	OTFAD_SR_CTXER1_MASK (0x200U)

#define	OTFAD_SR_CTXER1_SHIFT (9U)

#define	OTFAD_SR_CTXER1(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER1_SHIFT)) & OTFAD_SR_CTXER1_MASK)

#define	OTFAD_SR_CTXER2_MASK (0x400U)

#define	OTFAD_SR_CTXER2_SHIFT (10U)

#define	OTFAD_SR_CTXER2(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER2_SHIFT)) & OTFAD_SR_CTXER2_MASK)

#define	OTFAD_SR_CTXER3_MASK (0x800U)

#define	OTFAD_SR_CTXER3_SHIFT (11U)

#define	OTFAD_SR_CTXER3(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER3_SHIFT)) & OTFAD_SR_CTXER3_MASK)

#define	OTFAD_SR_CTXIE0_MASK (0x10000U)

#define	OTFAD_SR_CTXIE0_SHIFT (16U)

#define	OTFAD_SR_CTXIE0(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE0_SHIFT)) & OTFAD_SR_CTXIE0_MASK)

#define	OTFAD_SR_CTXIE1_MASK (0x20000U)

#define	OTFAD_SR_CTXIE1_SHIFT (17U)

#define	OTFAD_SR_CTXIE1(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE1_SHIFT)) & OTFAD_SR_CTXIE1_MASK)

#define	OTFAD_SR_CTXIE2_MASK (0x40000U)

#define	OTFAD_SR_CTXIE2_SHIFT (18U)

#define	OTFAD_SR_CTXIE2(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE2_SHIFT)) & OTFAD_SR_CTXIE2_MASK)

#define	OTFAD_SR_CTXIE3_MASK (0x80000U)

#define	OTFAD_SR_CTXIE3_SHIFT (19U)

#define	OTFAD_SR_CTXIE3(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE3_SHIFT)) & OTFAD_SR_CTXIE3_MASK)

#define	OTFAD_SR_HRL_MASK (0xF000000U)

#define	OTFAD_SR_HRL_SHIFT (24U)

#define	OTFAD_SR_HRL(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_HRL_SHIFT)) & OTFAD_SR_HRL_MASK)

#define	OTFAD_SR_RRAM_MASK (0x10000000U)

#define	OTFAD_SR_RRAM_SHIFT (28U)

#define	OTFAD_SR_RRAM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)

#define	OTFAD_SR_GEM_MASK (0x20000000U)

#define	OTFAD_SR_GEM_SHIFT (29U)

#define	OTFAD_SR_GEM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_GEM_SHIFT)) & OTFAD_SR_GEM_MASK)

#define	OTFAD_SR_KBPE_MASK (0x40000000U)

#define	OTFAD_SR_KBPE_SHIFT (30U)

#define	OTFAD_SR_KBPE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBPE_SHIFT)) & OTFAD_SR_KBPE_MASK)

#define	OTFAD_SR_KBD_MASK (0x80000000U)

#define	OTFAD_SR_KBD_SHIFT (31U)

#define	OTFAD_SR_KBD(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBD_SHIFT)) & OTFAD_SR_KBD_MASK)

#define	XRDC2_SR_DIN_MASK (0xFU)

#define	XRDC2_SR_DIN_SHIFT (0U)

#define	XRDC2_SR_DIN(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_DIN_SHIFT)) & XRDC2_SR_DIN_MASK)

#define	XRDC2_SR_HRL_MASK (0xF0U)

#define	XRDC2_SR_HRL_SHIFT (4U)

#define	XRDC2_SR_HRL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_HRL_SHIFT)) & XRDC2_SR_HRL_MASK)

#define	XRDC2_SR_GCLO_MASK (0xF00U)

#define	XRDC2_SR_GCLO_SHIFT (8U)

#define	XRDC2_SR_GCLO(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_GCLO_SHIFT)) & XRDC2_SR_GCLO_MASK)

KEY - AES Key Word
#define	OTFAD_KEY_KEY_MASK (0xFFFFFFFFU)

#define	OTFAD_KEY_KEY_SHIFT (0U)

#define	OTFAD_KEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_KEY_KEY_SHIFT)) & OTFAD_KEY_KEY_MASK)

CTR - AES Counter Word
#define	OTFAD_CTR_CTR_MASK (0xFFFFFFFFU)

#define	OTFAD_CTR_CTR_SHIFT (0U)

#define	OTFAD_CTR_CTR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTR_CTR_SHIFT)) & OTFAD_CTR_CTR_MASK)

RGD_W0 - AES Region Descriptor Word0
#define	OTFAD_RGD_W0_SRTADDR_MASK (0xFFFFFC00U)

#define	OTFAD_RGD_W0_SRTADDR_SHIFT (10U)

#define	OTFAD_RGD_W0_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W0_SRTADDR_SHIFT)) & OTFAD_RGD_W0_SRTADDR_MASK)

RGD_W1 - AES Region Descriptor Word1
#define	OTFAD_RGD_W1_VLD_MASK (0x1U)

#define	OTFAD_RGD_W1_VLD_SHIFT (0U)

#define	OTFAD_RGD_W1_VLD(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_VLD_SHIFT)) & OTFAD_RGD_W1_VLD_MASK)

#define	OTFAD_RGD_W1_ADE_MASK (0x2U)

#define	OTFAD_RGD_W1_ADE_SHIFT (1U)

#define	OTFAD_RGD_W1_ADE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ADE_SHIFT)) & OTFAD_RGD_W1_ADE_MASK)

#define	OTFAD_RGD_W1_RO_MASK (0x4U)

#define	OTFAD_RGD_W1_RO_SHIFT (2U)

#define	OTFAD_RGD_W1_RO(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_RO_SHIFT)) & OTFAD_RGD_W1_RO_MASK)

#define	OTFAD_RGD_W1_ENDADDR_MASK (0xFFFFFC00U)

#define	OTFAD_RGD_W1_ENDADDR_SHIFT (10U)

#define	OTFAD_RGD_W1_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ENDADDR_SHIFT)) & OTFAD_RGD_W1_ENDADDR_MASK)

CR - Control Register
#define	OTFAD_CR_FERR_MASK (0x2U)

#define	OTFAD_CR_FERR_SHIFT (1U)

#define	OTFAD_CR_FERR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FERR_SHIFT)) & OTFAD_CR_FERR_MASK)

#define	OTFAD_CR_FLDM_MASK (0x8U)

#define	OTFAD_CR_FLDM_SHIFT (3U)

#define	OTFAD_CR_FLDM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FLDM_SHIFT)) & OTFAD_CR_FLDM_MASK)

#define	OTFAD_CR_KBSE_MASK (0x10U)

#define	OTFAD_CR_KBSE_SHIFT (4U)

#define	OTFAD_CR_KBSE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBSE_SHIFT)) & OTFAD_CR_KBSE_MASK)

#define	OTFAD_CR_KBPE_MASK (0x20U)

#define	OTFAD_CR_KBPE_SHIFT (5U)

#define	OTFAD_CR_KBPE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBPE_SHIFT)) & OTFAD_CR_KBPE_MASK)

#define	OTFAD_CR_RRAE_MASK (0x80U)

#define	OTFAD_CR_RRAE_SHIFT (7U)

#define	OTFAD_CR_RRAE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_RRAE_SHIFT)) & OTFAD_CR_RRAE_MASK)

#define	OTFAD_CR_SKBP_MASK (0x40000000U)

#define	OTFAD_CR_SKBP_SHIFT (30U)

#define	OTFAD_CR_SKBP(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_SKBP_SHIFT)) & OTFAD_CR_SKBP_MASK)

#define	OTFAD_CR_GE_MASK (0x80000000U)

#define	OTFAD_CR_GE_SHIFT (31U)

#define	OTFAD_CR_GE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_GE_SHIFT)) & OTFAD_CR_GE_MASK)

SR - Status Register
#define	OTFAD_SR_KBERR_MASK (0x1U)

#define	OTFAD_SR_KBERR_SHIFT (0U)

#define	OTFAD_SR_KBERR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBERR_SHIFT)) & OTFAD_SR_KBERR_MASK)

#define	OTFAD_SR_MDPCP_MASK (0x2U)

#define	OTFAD_SR_MDPCP_SHIFT (1U)

#define	OTFAD_SR_MDPCP(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MDPCP_SHIFT)) & OTFAD_SR_MDPCP_MASK)

#define	OTFAD_SR_MODE_MASK (0xCU)

#define	OTFAD_SR_MODE_SHIFT (2U)

#define	OTFAD_SR_MODE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MODE_SHIFT)) & OTFAD_SR_MODE_MASK)

#define	OTFAD_SR_NCTX_MASK (0xF0U)

#define	OTFAD_SR_NCTX_SHIFT (4U)

#define	OTFAD_SR_NCTX(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_NCTX_SHIFT)) & OTFAD_SR_NCTX_MASK)

#define	OTFAD_SR_CTXER0_MASK (0x100U)

#define	OTFAD_SR_CTXER0_SHIFT (8U)

#define	OTFAD_SR_CTXER0(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER0_SHIFT)) & OTFAD_SR_CTXER0_MASK)

#define	OTFAD_SR_CTXER1_MASK (0x200U)

#define	OTFAD_SR_CTXER1_SHIFT (9U)

#define	OTFAD_SR_CTXER1(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER1_SHIFT)) & OTFAD_SR_CTXER1_MASK)

#define	OTFAD_SR_CTXER2_MASK (0x400U)

#define	OTFAD_SR_CTXER2_SHIFT (10U)

#define	OTFAD_SR_CTXER2(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER2_SHIFT)) & OTFAD_SR_CTXER2_MASK)

#define	OTFAD_SR_CTXER3_MASK (0x800U)

#define	OTFAD_SR_CTXER3_SHIFT (11U)

#define	OTFAD_SR_CTXER3(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER3_SHIFT)) & OTFAD_SR_CTXER3_MASK)

#define	OTFAD_SR_CTXIE0_MASK (0x10000U)

#define	OTFAD_SR_CTXIE0_SHIFT (16U)

#define	OTFAD_SR_CTXIE0(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE0_SHIFT)) & OTFAD_SR_CTXIE0_MASK)

#define	OTFAD_SR_CTXIE1_MASK (0x20000U)

#define	OTFAD_SR_CTXIE1_SHIFT (17U)

#define	OTFAD_SR_CTXIE1(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE1_SHIFT)) & OTFAD_SR_CTXIE1_MASK)

#define	OTFAD_SR_CTXIE2_MASK (0x40000U)

#define	OTFAD_SR_CTXIE2_SHIFT (18U)

#define	OTFAD_SR_CTXIE2(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE2_SHIFT)) & OTFAD_SR_CTXIE2_MASK)

#define	OTFAD_SR_CTXIE3_MASK (0x80000U)

#define	OTFAD_SR_CTXIE3_SHIFT (19U)

#define	OTFAD_SR_CTXIE3(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE3_SHIFT)) & OTFAD_SR_CTXIE3_MASK)

#define	OTFAD_SR_HRL_MASK (0xF000000U)

#define	OTFAD_SR_HRL_SHIFT (24U)

#define	OTFAD_SR_HRL(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_HRL_SHIFT)) & OTFAD_SR_HRL_MASK)

#define	OTFAD_SR_RRAM_MASK (0x10000000U)

#define	OTFAD_SR_RRAM_SHIFT (28U)

#define	OTFAD_SR_RRAM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)

#define	OTFAD_SR_GEM_MASK (0x20000000U)

#define	OTFAD_SR_GEM_SHIFT (29U)

#define	OTFAD_SR_GEM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_GEM_SHIFT)) & OTFAD_SR_GEM_MASK)

#define	OTFAD_SR_KBPE_MASK (0x40000000U)

#define	OTFAD_SR_KBPE_SHIFT (30U)

#define	OTFAD_SR_KBPE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBPE_SHIFT)) & OTFAD_SR_KBPE_MASK)

#define	OTFAD_SR_KBD_MASK (0x80000000U)

#define	OTFAD_SR_KBD_SHIFT (31U)

#define	OTFAD_SR_KBD(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBD_SHIFT)) & OTFAD_SR_KBD_MASK)

#define	XRDC2_SR_DIN_MASK (0xFU)

#define	XRDC2_SR_DIN_SHIFT (0U)

#define	XRDC2_SR_DIN(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_DIN_SHIFT)) & XRDC2_SR_DIN_MASK)

#define	XRDC2_SR_HRL_MASK (0xF0U)

#define	XRDC2_SR_HRL_SHIFT (4U)

#define	XRDC2_SR_HRL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_HRL_SHIFT)) & XRDC2_SR_HRL_MASK)

#define	XRDC2_SR_GCLO_MASK (0xF00U)

#define	XRDC2_SR_GCLO_SHIFT (8U)

#define	XRDC2_SR_GCLO(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_GCLO_SHIFT)) & XRDC2_SR_GCLO_MASK)

KEY - AES Key Word
#define	OTFAD_KEY_KEY_MASK (0xFFFFFFFFU)

#define	OTFAD_KEY_KEY_SHIFT (0U)

#define	OTFAD_KEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_KEY_KEY_SHIFT)) & OTFAD_KEY_KEY_MASK)

CTR - AES Counter Word
#define	OTFAD_CTR_CTR_MASK (0xFFFFFFFFU)

#define	OTFAD_CTR_CTR_SHIFT (0U)

#define	OTFAD_CTR_CTR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTR_CTR_SHIFT)) & OTFAD_CTR_CTR_MASK)

RGD_W0 - AES Region Descriptor Word0
#define	OTFAD_RGD_W0_SRTADDR_MASK (0xFFFFFC00U)

#define	OTFAD_RGD_W0_SRTADDR_SHIFT (10U)

#define	OTFAD_RGD_W0_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W0_SRTADDR_SHIFT)) & OTFAD_RGD_W0_SRTADDR_MASK)

RGD_W1 - AES Region Descriptor Word1
#define	OTFAD_RGD_W1_VLD_MASK (0x1U)

#define	OTFAD_RGD_W1_VLD_SHIFT (0U)

#define	OTFAD_RGD_W1_VLD(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_VLD_SHIFT)) & OTFAD_RGD_W1_VLD_MASK)

#define	OTFAD_RGD_W1_ADE_MASK (0x2U)

#define	OTFAD_RGD_W1_ADE_SHIFT (1U)

#define	OTFAD_RGD_W1_ADE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ADE_SHIFT)) & OTFAD_RGD_W1_ADE_MASK)

#define	OTFAD_RGD_W1_RO_MASK (0x4U)

#define	OTFAD_RGD_W1_RO_SHIFT (2U)

#define	OTFAD_RGD_W1_RO(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_RO_SHIFT)) & OTFAD_RGD_W1_RO_MASK)

#define	OTFAD_RGD_W1_ENDADDR_MASK (0xFFFFFC00U)

#define	OTFAD_RGD_W1_ENDADDR_SHIFT (10U)

#define	OTFAD_RGD_W1_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ENDADDR_SHIFT)) & OTFAD_RGD_W1_ENDADDR_MASK)

Detailed Description

Macro Definition Documentation

◆ OTFAD_CR_FERR [1/2]

#define OTFAD_CR_FERR ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FERR_SHIFT)) & OTFAD_CR_FERR_MASK)

FERR - Force Error 0b0..No effect on the SR[KBERE] indicator. 0b1..SR[KBERR] is immediately set after a write with this data bit set.

◆ OTFAD_CR_FERR [2/2]

#define OTFAD_CR_FERR ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FERR_SHIFT)) & OTFAD_CR_FERR_MASK)

FERR - Force Error 0b0..No effect on the SR[KBERE] indicator. 0b1..SR[KBERR] is immediately set after a write with this data bit set.

◆ OTFAD_CR_FLDM [1/2]

#define OTFAD_CR_FLDM ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FLDM_SHIFT)) & OTFAD_CR_FLDM_MASK)

FLDM - Force Logically Disabled Mode 0b0..No effect on the operating mode. 0b1..Force entry into LDM after a write with this data bit set. SR[MODE] signals the operating mode.

◆ OTFAD_CR_FLDM [2/2]

#define OTFAD_CR_FLDM ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FLDM_SHIFT)) & OTFAD_CR_FLDM_MASK)

FLDM - Force Logically Disabled Mode 0b0..No effect on the operating mode. 0b1..Force entry into LDM after a write with this data bit set. SR[MODE] signals the operating mode.

◆ OTFAD_CR_GE [1/2]

#define OTFAD_CR_GE ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_GE_SHIFT)) & OTFAD_CR_GE_MASK)

GE - Global OTFAD Enable 0b0..OTFAD has decryption disabled. All data fetched by the FlexSPI bypasses OTFAD processing. 0b1..OTFAD has decryption enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration.

◆ OTFAD_CR_GE [2/2]

#define OTFAD_CR_GE ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_GE_SHIFT)) & OTFAD_CR_GE_MASK)

GE - Global OTFAD Enable 0b0..OTFAD has decryption disabled. All data fetched by the FlexSPI bypasses OTFAD processing. 0b1..OTFAD has decryption enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration.

◆ OTFAD_CR_KBPE [1/2]

#define OTFAD_CR_KBPE ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBPE_SHIFT)) & OTFAD_CR_KBPE_MASK)

KBPE - Key Blob Processing Enable 0b0..Key blob processing is disabled. 0b1..Key blob processing is enabled.

◆ OTFAD_CR_KBPE [2/2]

#define OTFAD_CR_KBPE ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBPE_SHIFT)) & OTFAD_CR_KBPE_MASK)

KBPE - Key Blob Processing Enable 0b0..Key blob processing is disabled. 0b1..Key blob processing is enabled.

◆ OTFAD_CR_KBSE [1/2]

#define OTFAD_CR_KBSE ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBSE_SHIFT)) & OTFAD_CR_KBSE_MASK)

KBSE - Key Blob Scramble Enable 0b0..Key blob KEK scrambling is disabled. 0b1..Key blob KEK scrambling is enabled.

◆ OTFAD_CR_KBSE [2/2]

#define OTFAD_CR_KBSE ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBSE_SHIFT)) & OTFAD_CR_KBSE_MASK)

KBSE - Key Blob Scramble Enable 0b0..Key blob KEK scrambling is disabled. 0b1..Key blob KEK scrambling is enabled.

◆ OTFAD_CR_RRAE [1/2]

#define OTFAD_CR_RRAE ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_RRAE_SHIFT)) & OTFAD_CR_RRAE_MASK)

RRAE - Restricted Register Access Enable 0b0..Register access is fully enabled. The OTFAD programming model registers can be accessed "normally". 0b1..Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI.

◆ OTFAD_CR_RRAE [2/2]

#define OTFAD_CR_RRAE ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_RRAE_SHIFT)) & OTFAD_CR_RRAE_MASK)

RRAE - Restricted Register Access Enable 0b0..Register access is fully enabled. The OTFAD programming model registers can be accessed "normally". 0b1..Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI.

◆ OTFAD_CR_SKBP [1/2]

#define OTFAD_CR_SKBP ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_SKBP_SHIFT)) & OTFAD_CR_SKBP_MASK)

SKBP - Start key blob processing 0b0..Key blob processing is not initiated. 0b1..Properly-enabled key blob processing is initiated.

◆ OTFAD_CR_SKBP [2/2]

#define OTFAD_CR_SKBP ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_SKBP_SHIFT)) & OTFAD_CR_SKBP_MASK)

SKBP - Start key blob processing 0b0..Key blob processing is not initiated. 0b1..Properly-enabled key blob processing is initiated.

◆ OTFAD_CTR_CTR [1/2]

#define OTFAD_CTR_CTR ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTR_CTR_SHIFT)) & OTFAD_CTR_CTR_MASK)

CTR - AES Counter

◆ OTFAD_CTR_CTR [2/2]

#define OTFAD_CTR_CTR ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTR_CTR_SHIFT)) & OTFAD_CTR_CTR_MASK)

CTR - AES Counter

◆ OTFAD_KEY_KEY [1/2]

#define OTFAD_KEY_KEY ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_KEY_KEY_SHIFT)) & OTFAD_KEY_KEY_MASK)

KEY - AES Key

◆ OTFAD_KEY_KEY [2/2]

#define OTFAD_KEY_KEY ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_KEY_KEY_SHIFT)) & OTFAD_KEY_KEY_MASK)

KEY - AES Key

◆ OTFAD_RGD_W0_SRTADDR [1/2]

#define OTFAD_RGD_W0_SRTADDR ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W0_SRTADDR_SHIFT)) & OTFAD_RGD_W0_SRTADDR_MASK)

SRTADDR - Start Address

◆ OTFAD_RGD_W0_SRTADDR [2/2]

#define OTFAD_RGD_W0_SRTADDR ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W0_SRTADDR_SHIFT)) & OTFAD_RGD_W0_SRTADDR_MASK)

SRTADDR - Start Address

◆ OTFAD_RGD_W1_ADE [1/2]

#define OTFAD_RGD_W1_ADE ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ADE_SHIFT)) & OTFAD_RGD_W1_ADE_MASK)

ADE - AES Decryption Enable. 0b0..Bypass the fetched data. 0b1..Perform the CTR-AES128 mode decryption on the fetched data.

◆ OTFAD_RGD_W1_ADE [2/2]

#define OTFAD_RGD_W1_ADE ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ADE_SHIFT)) & OTFAD_RGD_W1_ADE_MASK)

ADE - AES Decryption Enable. 0b0..Bypass the fetched data. 0b1..Perform the CTR-AES128 mode decryption on the fetched data.

◆ OTFAD_RGD_W1_ENDADDR [1/2]

#define OTFAD_RGD_W1_ENDADDR ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ENDADDR_SHIFT)) & OTFAD_RGD_W1_ENDADDR_MASK)

ENDADDR - End Address

◆ OTFAD_RGD_W1_ENDADDR [2/2]

#define OTFAD_RGD_W1_ENDADDR ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ENDADDR_SHIFT)) & OTFAD_RGD_W1_ENDADDR_MASK)

ENDADDR - End Address

◆ OTFAD_RGD_W1_RO [1/2]

#define OTFAD_RGD_W1_RO ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_RO_SHIFT)) & OTFAD_RGD_W1_RO_MASK)

RO - Read-Only 0b0..The context registers can be accessed normally (as defined by SR[RRAM]). 0b1..The context registers are read-only and accesses may be further restricted based on SR[RRAM].

◆ OTFAD_RGD_W1_RO [2/2]

#define OTFAD_RGD_W1_RO ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_RO_SHIFT)) & OTFAD_RGD_W1_RO_MASK)

RO - Read-Only 0b0..The context registers can be accessed normally (as defined by SR[RRAM]). 0b1..The context registers are read-only and accesses may be further restricted based on SR[RRAM].

◆ OTFAD_RGD_W1_VLD [1/2]

#define OTFAD_RGD_W1_VLD ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_VLD_SHIFT)) & OTFAD_RGD_W1_VLD_MASK)

VLD - Valid 0b0..Context is invalid. 0b1..Context is valid.

◆ OTFAD_RGD_W1_VLD [2/2]

#define OTFAD_RGD_W1_VLD ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_VLD_SHIFT)) & OTFAD_RGD_W1_VLD_MASK)

VLD - Valid 0b0..Context is invalid. 0b1..Context is valid.

◆ OTFAD_SR_CTXER0 [1/2]

#define OTFAD_SR_CTXER0 ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER0_SHIFT)) & OTFAD_SR_CTXER0_MASK)

CTXER0 - Context Error 0b0..No key blob error was detected for context "n". 0b1..A key blob integrity error might have been detected in context "n".

◆ OTFAD_SR_CTXER0 [2/2]

#define OTFAD_SR_CTXER0 ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER0_SHIFT)) & OTFAD_SR_CTXER0_MASK)

CTXER0 - Context Error 0b0..No key blob error was detected for context "n". 0b1..A key blob integrity error might have been detected in context "n".

◆ OTFAD_SR_CTXER1 [1/2]

#define OTFAD_SR_CTXER1 ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER1_SHIFT)) & OTFAD_SR_CTXER1_MASK)

CTXER1 - Context Error 0b0..No key blob error was detected for context "n". 0b1..A key blob integrity error might have been detected in context "n".

◆ OTFAD_SR_CTXER1 [2/2]

#define OTFAD_SR_CTXER1 ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER1_SHIFT)) & OTFAD_SR_CTXER1_MASK)

CTXER1 - Context Error 0b0..No key blob error was detected for context "n". 0b1..A key blob integrity error might have been detected in context "n".

◆ OTFAD_SR_CTXER2 [1/2]

#define OTFAD_SR_CTXER2 ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER2_SHIFT)) & OTFAD_SR_CTXER2_MASK)

CTXER2 - Context Error 0b0..No key blob error was detected for context "n". 0b1..A key blob integrity error might have been detected in context "n".

◆ OTFAD_SR_CTXER2 [2/2]

#define OTFAD_SR_CTXER2 ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER2_SHIFT)) & OTFAD_SR_CTXER2_MASK)

CTXER2 - Context Error 0b0..No key blob error was detected for context "n". 0b1..A key blob integrity error might have been detected in context "n".

◆ OTFAD_SR_CTXER3 [1/2]

#define OTFAD_SR_CTXER3 ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER3_SHIFT)) & OTFAD_SR_CTXER3_MASK)

CTXER3 - Context Error 0b0..No key blob error was detected for context "n". 0b1..A key blob integrity error might have been detected in context "n".

◆ OTFAD_SR_CTXER3 [2/2]

#define OTFAD_SR_CTXER3 ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER3_SHIFT)) & OTFAD_SR_CTXER3_MASK)

CTXER3 - Context Error 0b0..No key blob error was detected for context "n". 0b1..A key blob integrity error might have been detected in context "n".

◆ OTFAD_SR_CTXIE0 [1/2]

#define OTFAD_SR_CTXIE0 ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE0_SHIFT)) & OTFAD_SR_CTXIE0_MASK)

CTXIE0 - Context Integrity Error 0b0..No key blob integrity error was detected for context "n". 0b1..A key blob integrity error was detected in context "n".

◆ OTFAD_SR_CTXIE0 [2/2]

#define OTFAD_SR_CTXIE0 ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE0_SHIFT)) & OTFAD_SR_CTXIE0_MASK)

CTXIE0 - Context Integrity Error 0b0..No key blob integrity error was detected for context "n". 0b1..A key blob integrity error was detected in context "n".

◆ OTFAD_SR_CTXIE1 [1/2]

#define OTFAD_SR_CTXIE1 ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE1_SHIFT)) & OTFAD_SR_CTXIE1_MASK)

CTXIE1 - Context Integrity Error 0b0..No key blob integrity error was detected for context "n". 0b1..A key blob integrity error was detected in context "n".

◆ OTFAD_SR_CTXIE1 [2/2]

#define OTFAD_SR_CTXIE1 ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE1_SHIFT)) & OTFAD_SR_CTXIE1_MASK)

CTXIE1 - Context Integrity Error 0b0..No key blob integrity error was detected for context "n". 0b1..A key blob integrity error was detected in context "n".

◆ OTFAD_SR_CTXIE2 [1/2]

#define OTFAD_SR_CTXIE2 ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE2_SHIFT)) & OTFAD_SR_CTXIE2_MASK)

CTXIE2 - Context Integrity Error 0b0..No key blob integrity error was detected for context "n". 0b1..A key blob integrity error was detected in context "n".

◆ OTFAD_SR_CTXIE2 [2/2]

#define OTFAD_SR_CTXIE2 ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE2_SHIFT)) & OTFAD_SR_CTXIE2_MASK)

CTXIE2 - Context Integrity Error 0b0..No key blob integrity error was detected for context "n". 0b1..A key blob integrity error was detected in context "n".

◆ OTFAD_SR_CTXIE3 [1/2]

#define OTFAD_SR_CTXIE3 ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE3_SHIFT)) & OTFAD_SR_CTXIE3_MASK)

CTXIE3 - Context Integrity Error 0b0..No key blob integrity error was detected for context "n". 0b1..A key blob integrity error was detected in context "n".

◆ OTFAD_SR_CTXIE3 [2/2]

#define OTFAD_SR_CTXIE3 ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE3_SHIFT)) & OTFAD_SR_CTXIE3_MASK)

CTXIE3 - Context Integrity Error 0b0..No key blob integrity error was detected for context "n". 0b1..A key blob integrity error was detected in context "n".

◆ OTFAD_SR_GEM [1/2]

#define OTFAD_SR_GEM ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_GEM_SHIFT)) & OTFAD_SR_GEM_MASK)

GEM - Global Enable Mode 0b0..OTFAD is disabled. All data fetched by the FlexSPI bypasses OTFAD processing. 0b1..OTFAD is enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration.

◆ OTFAD_SR_GEM [2/2]

#define OTFAD_SR_GEM ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_GEM_SHIFT)) & OTFAD_SR_GEM_MASK)

GEM - Global Enable Mode 0b0..OTFAD is disabled. All data fetched by the FlexSPI bypasses OTFAD processing. 0b1..OTFAD is enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration.

◆ OTFAD_SR_HRL [1/2]

#define OTFAD_SR_HRL ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_HRL_SHIFT)) & OTFAD_SR_HRL_MASK)

HRL - Hardware Revision Level

◆ OTFAD_SR_HRL [2/2]

#define OTFAD_SR_HRL ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_HRL_SHIFT)) & OTFAD_SR_HRL_MASK)

HRL - Hardware Revision Level

◆ OTFAD_SR_KBD [1/2]

#define OTFAD_SR_KBD ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBD_SHIFT)) & OTFAD_SR_KBD_MASK)

KBD - Key Blob Processing Done 0b0..Key blob processing was not enabled, or is not complete. 0b1..Key blob processing was enabled and is complete.

◆ OTFAD_SR_KBD [2/2]

#define OTFAD_SR_KBD ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBD_SHIFT)) & OTFAD_SR_KBD_MASK)

KBD - Key Blob Processing Done 0b0..Key blob processing was not enabled, or is not complete. 0b1..Key blob processing was enabled and is complete.

◆ OTFAD_SR_KBERR [1/2]

#define OTFAD_SR_KBERR ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBERR_SHIFT)) & OTFAD_SR_KBERR_MASK)

KBERR - Key Blob Error 0b0..No key blob error detected. 0b1..One or more key blob errors has been detected.

◆ OTFAD_SR_KBERR [2/2]

#define OTFAD_SR_KBERR ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBERR_SHIFT)) & OTFAD_SR_KBERR_MASK)

KBERR - Key Blob Error 0b0..No key blob error detected. 0b1..One or more key blob errors has been detected.

◆ OTFAD_SR_KBPE [1/2]

#define OTFAD_SR_KBPE ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBPE_SHIFT)) & OTFAD_SR_KBPE_MASK)

KBPE - Key Blob Processing Enable 0b0..Key blob processing is not enabled. 0b1..Key blob processing is enabled.

◆ OTFAD_SR_KBPE [2/2]

#define OTFAD_SR_KBPE ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBPE_SHIFT)) & OTFAD_SR_KBPE_MASK)

KBPE - Key Blob Processing Enable 0b0..Key blob processing is not enabled. 0b1..Key blob processing is enabled.

◆ OTFAD_SR_MDPCP [1/2]

#define OTFAD_SR_MDPCP ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MDPCP_SHIFT)) & OTFAD_SR_MDPCP_MASK)

MDPCP - MDPC Present

◆ OTFAD_SR_MDPCP [2/2]

#define OTFAD_SR_MDPCP ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MDPCP_SHIFT)) & OTFAD_SR_MDPCP_MASK)

MDPCP - MDPC Present

◆ OTFAD_SR_MODE [1/2]

#define OTFAD_SR_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MODE_SHIFT)) & OTFAD_SR_MODE_MASK)

MODE - Operating Mode 0b00..Operating in Normal mode (NRM) 0b01..Unused (reserved) 0b10..Unused (reserved) 0b11..Operating in Logically Disabled Mode (LDM)

◆ OTFAD_SR_MODE [2/2]

#define OTFAD_SR_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MODE_SHIFT)) & OTFAD_SR_MODE_MASK)

MODE - Operating Mode 0b00..Operating in Normal mode (NRM) 0b01..Unused (reserved) 0b10..Unused (reserved) 0b11..Operating in Logically Disabled Mode (LDM)

◆ OTFAD_SR_NCTX [1/2]

#define OTFAD_SR_NCTX ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_NCTX_SHIFT)) & OTFAD_SR_NCTX_MASK)

NCTX - Number of Contexts

◆ OTFAD_SR_NCTX [2/2]

#define OTFAD_SR_NCTX ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_NCTX_SHIFT)) & OTFAD_SR_NCTX_MASK)

NCTX - Number of Contexts

◆ OTFAD_SR_RRAM [1/2]

#define OTFAD_SR_RRAM ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)

RRAM - Restricted Register Access Mode 0b0..Register access is fully enabled. The OTFAD programming model registers can be accessed "normally". 0b1..Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI.

◆ OTFAD_SR_RRAM [2/2]

#define OTFAD_SR_RRAM ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)

RRAM - Restricted Register Access Mode 0b0..Register access is fully enabled. The OTFAD programming model registers can be accessed "normally". 0b1..Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI.

◆ XRDC2_SR_DIN [1/2]

#define XRDC2_SR_DIN ( x ) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_DIN_SHIFT)) & XRDC2_SR_DIN_MASK)

DIN - Domain Identifier Number

◆ XRDC2_SR_DIN [2/2]

#define XRDC2_SR_DIN ( x ) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_DIN_SHIFT)) & XRDC2_SR_DIN_MASK)

DIN - Domain Identifier Number

◆ XRDC2_SR_GCLO [1/2]

#define XRDC2_SR_GCLO ( x ) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_GCLO_SHIFT)) & XRDC2_SR_GCLO_MASK)

GCLO - Global Configuration Lock Owner

◆ XRDC2_SR_GCLO [2/2]

#define XRDC2_SR_GCLO ( x ) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_GCLO_SHIFT)) & XRDC2_SR_GCLO_MASK)

GCLO - Global Configuration Lock Owner

◆ XRDC2_SR_HRL [1/2]

#define XRDC2_SR_HRL ( x ) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_HRL_SHIFT)) & XRDC2_SR_HRL_MASK)

HRL - Hardware Revision Level

◆ XRDC2_SR_HRL [2/2]

#define XRDC2_SR_HRL ( x ) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_HRL_SHIFT)) & XRDC2_SR_HRL_MASK)

HRL - Hardware Revision Level

Macros

CR - Control Register

SR - Status Register

KEY - AES Key Word

CTR - AES Counter Word

RGD_W0 - AES Region Descriptor Word0

RGD_W1 - AES Region Descriptor Word1

CR - Control Register

SR - Status Register

KEY - AES Key Word

CTR - AES Counter Word

RGD_W0 - AES Region Descriptor Word0

RGD_W1 - AES Region Descriptor Word1

Detailed Description

Macro Definition Documentation

◆ OTFAD_CR_FERR [1/2]

◆ OTFAD_CR_FERR [2/2]

◆ OTFAD_CR_FLDM [1/2]

◆ OTFAD_CR_FLDM [2/2]

◆ OTFAD_CR_GE [1/2]

◆ OTFAD_CR_GE [2/2]

◆ OTFAD_CR_KBPE [1/2]

◆ OTFAD_CR_KBPE [2/2]

◆ OTFAD_CR_KBSE [1/2]

◆ OTFAD_CR_KBSE [2/2]

◆ OTFAD_CR_RRAE [1/2]

◆ OTFAD_CR_RRAE [2/2]

◆ OTFAD_CR_SKBP [1/2]

◆ OTFAD_CR_SKBP [2/2]

◆ OTFAD_CTR_CTR [1/2]

◆ OTFAD_CTR_CTR [2/2]

◆ OTFAD_KEY_KEY [1/2]

◆ OTFAD_KEY_KEY [2/2]

◆ OTFAD_RGD_W0_SRTADDR [1/2]

◆ OTFAD_RGD_W0_SRTADDR [2/2]

◆ OTFAD_RGD_W1_ADE [1/2]

◆ OTFAD_RGD_W1_ADE [2/2]

◆ OTFAD_RGD_W1_ENDADDR [1/2]

◆ OTFAD_RGD_W1_ENDADDR [2/2]

◆ OTFAD_RGD_W1_RO [1/2]

◆ OTFAD_RGD_W1_RO [2/2]

◆ OTFAD_RGD_W1_VLD [1/2]

◆ OTFAD_RGD_W1_VLD [2/2]

◆ OTFAD_SR_CTXER0 [1/2]

◆ OTFAD_SR_CTXER0 [2/2]

◆ OTFAD_SR_CTXER1 [1/2]

◆ OTFAD_SR_CTXER1 [2/2]

◆ OTFAD_SR_CTXER2 [1/2]

◆ OTFAD_SR_CTXER2 [2/2]

◆ OTFAD_SR_CTXER3 [1/2]

◆ OTFAD_SR_CTXER3 [2/2]

◆ OTFAD_SR_CTXIE0 [1/2]

◆ OTFAD_SR_CTXIE0 [2/2]

◆ OTFAD_SR_CTXIE1 [1/2]

◆ OTFAD_SR_CTXIE1 [2/2]

◆ OTFAD_SR_CTXIE2 [1/2]

◆ OTFAD_SR_CTXIE2 [2/2]

◆ OTFAD_SR_CTXIE3 [1/2]

◆ OTFAD_SR_CTXIE3 [2/2]

◆ OTFAD_SR_GEM [1/2]

◆ OTFAD_SR_GEM [2/2]

◆ OTFAD_SR_HRL [1/2]

◆ OTFAD_SR_HRL [2/2]

◆ OTFAD_SR_KBD [1/2]

◆ OTFAD_SR_KBD [2/2]

◆ OTFAD_SR_KBERR [1/2]

◆ OTFAD_SR_KBERR [2/2]

◆ OTFAD_SR_KBPE [1/2]

◆ OTFAD_SR_KBPE [2/2]

◆ OTFAD_SR_MDPCP [1/2]

◆ OTFAD_SR_MDPCP [2/2]

◆ OTFAD_SR_MODE [1/2]

◆ OTFAD_SR_MODE [2/2]

◆ OTFAD_SR_NCTX [1/2]

◆ OTFAD_SR_NCTX [2/2]

◆ OTFAD_SR_RRAM [1/2]

◆ OTFAD_SR_RRAM [2/2]

◆ XRDC2_SR_DIN [1/2]

◆ XRDC2_SR_DIN [2/2]

◆ XRDC2_SR_GCLO [1/2]