Macros
#define	MU_TR_COUNT (4U)

#define	MU_RR_COUNT (4U)

#define	MU_TR_COUNT (4U)

#define	MU_RR_COUNT (4U)

TR - Processor B Transmit Register 0..Processor B Transmit Register 3
#define	MU_TR_DATA_MASK (0xFFFFFFFFU)

#define	MU_TR_DATA_SHIFT (0U)

#define	MU_TR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_DATA_SHIFT)) & MU_TR_DATA_MASK)

RR - Processor B Receive Register 0..Processor B Receive Register 3
#define	MU_RR_DATA_MASK (0xFFFFFFFFU)

#define	MU_RR_DATA_SHIFT (0U)

#define	MU_RR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_DATA_SHIFT)) & MU_RR_DATA_MASK)

SR - Processor B Status Register
#define	MU_SR_Fn_MASK (0x7U)

#define	MU_SR_Fn_SHIFT (0U)

#define	MU_SR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK)

#define	MU_SR_EP_MASK (0x10U)

#define	MU_SR_EP_SHIFT (4U)

#define	MU_SR_EP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK)

#define	MU_SR_RS_MASK (0x80U)

#define	MU_SR_RS_SHIFT (7U)

#define	MU_SR_RS(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RS_SHIFT)) & MU_SR_RS_MASK)

#define	MU_SR_FUP_MASK (0x100U)

#define	MU_SR_FUP_SHIFT (8U)

#define	MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK)

#define	MU_SR_TEn_MASK (0xF00000U)

#define	MU_SR_TEn_SHIFT (20U)

#define	MU_SR_TEn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK)

#define	MU_SR_RFn_MASK (0xF000000U)

#define	MU_SR_RFn_SHIFT (24U)

#define	MU_SR_RFn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK)

#define	MU_SR_GIPn_MASK (0xF0000000U)

#define	MU_SR_GIPn_SHIFT (28U)

#define	MU_SR_GIPn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK)

CR - Processor B Control Register
#define	MU_CR_Fn_MASK (0x7U)

#define	MU_CR_Fn_SHIFT (0U)

#define	MU_CR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_Fn_SHIFT)) & MU_CR_Fn_MASK)

#define	MU_CR_GIRn_MASK (0xF0000U)

#define	MU_CR_GIRn_SHIFT (16U)

#define	MU_CR_GIRn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)

#define	MU_CR_TIEn_MASK (0xF00000U)

#define	MU_CR_TIEn_SHIFT (20U)

#define	MU_CR_TIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK)

#define	MU_CR_RIEn_MASK (0xF000000U)

#define	MU_CR_RIEn_SHIFT (24U)

#define	MU_CR_RIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK)

#define	MU_CR_GIEn_MASK (0xF0000000U)

#define	MU_CR_GIEn_SHIFT (28U)

#define	MU_CR_GIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK)

TR - Processor A Transmit Register 0..Processor A Transmit Register 3
#define	MU_TR_DATA_MASK (0xFFFFFFFFU)

#define	MU_TR_DATA_SHIFT (0U)

#define	MU_TR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_DATA_SHIFT)) & MU_TR_DATA_MASK)

RR - Processor A Receive Register 0..Processor A Receive Register 3
#define	MU_RR_DATA_MASK (0xFFFFFFFFU)

#define	MU_RR_DATA_SHIFT (0U)

#define	MU_RR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_DATA_SHIFT)) & MU_RR_DATA_MASK)

SR - Processor A Status Register
#define	MU_SR_Fn_MASK (0x7U)

#define	MU_SR_Fn_SHIFT (0U)

#define	MU_SR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK)

#define	MU_SR_EP_MASK (0x10U)

#define	MU_SR_EP_SHIFT (4U)

#define	MU_SR_EP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK)

#define	MU_SR_RS_MASK (0x80U)

#define	MU_SR_RS_SHIFT (7U)

#define	MU_SR_RS(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RS_SHIFT)) & MU_SR_RS_MASK)

#define	MU_SR_FUP_MASK (0x100U)

#define	MU_SR_FUP_SHIFT (8U)

#define	MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK)

#define	MU_SR_TEn_MASK (0xF00000U)

#define	MU_SR_TEn_SHIFT (20U)

#define	MU_SR_TEn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK)

#define	MU_SR_RFn_MASK (0xF000000U)

#define	MU_SR_RFn_SHIFT (24U)

#define	MU_SR_RFn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK)

#define	MU_SR_GIPn_MASK (0xF0000000U)

#define	MU_SR_GIPn_SHIFT (28U)

#define	MU_SR_GIPn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK)

CR - Processor A Control Register
#define	MU_CR_Fn_MASK (0x7U)

#define	MU_CR_Fn_SHIFT (0U)

#define	MU_CR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_Fn_SHIFT)) & MU_CR_Fn_MASK)

#define	MU_CR_MUR_MASK (0x20U)

#define	MU_CR_MUR_SHIFT (5U)

#define	MU_CR_MUR(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)

#define	MU_CR_GIRn_MASK (0xF0000U)

#define	MU_CR_GIRn_SHIFT (16U)

#define	MU_CR_GIRn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)

#define	MU_CR_TIEn_MASK (0xF00000U)

#define	MU_CR_TIEn_SHIFT (20U)

#define	MU_CR_TIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK)

#define	MU_CR_RIEn_MASK (0xF000000U)

#define	MU_CR_RIEn_SHIFT (24U)

#define	MU_CR_RIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK)

#define	MU_CR_GIEn_MASK (0xF0000000U)

#define	MU_CR_GIEn_SHIFT (28U)

#define	MU_CR_GIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK)

Detailed Description

Macro Definition Documentation

◆ MU_CR_Fn [1/2]

#define MU_CR_Fn ( x ) (((uint32_t)(((uint32_t)(x)) << MU_CR_Fn_SHIFT)) & MU_CR_Fn_MASK)

Fn - Fn 0b000..Clears the Fn bit in the MUA.SR register. 0b001..Sets the Fn bit in the MUA.SR register.

◆ MU_CR_Fn [2/2]

#define MU_CR_Fn ( x ) (((uint32_t)(((uint32_t)(x)) << MU_CR_Fn_SHIFT)) & MU_CR_Fn_MASK)

Fn - Fn 0b000..N/A. Self clearing bit (default). 0b001..Asserts the Processor A MU reset.

◆ MU_CR_GIEn [1/2]

#define MU_CR_GIEn ( x ) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK)

GIEn - GIEn 0b0000..Disables Processor B General Interrupt n. (default) 0b0001..Enables Processor B General Interrupt n.

◆ MU_CR_GIEn [2/2]

#define MU_CR_GIEn ( x ) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK)

GIEn - GIEn 0b0000..Disables Processor A General Interrupt n. (default) 0b0001..Enables Processor A General Interrupt n.

◆ MU_CR_GIRn [1/2]

#define MU_CR_GIRn ( x ) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)

GIRn - GIRn 0b0000..Processor B General Interrupt n is not requested to the Processor A (default). 0b0001..Processor B General Interrupt n is requested to the Processor A.

◆ MU_CR_GIRn [2/2]

#define MU_CR_GIRn ( x ) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)

GIRn - GIRn 0b0000..Processor A General Interrupt n is not requested to the Processor B (default). 0b0001..Processor A General Interrupt n is requested to the Processor B.

◆ MU_CR_MUR

#define MU_CR_MUR ( x ) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)

MUR - MUR 0b0..N/A. Self clearing bit (default). 0b1..Asserts the Processor A MU reset.

◆ MU_CR_RIEn [1/2]

#define MU_CR_RIEn ( x ) (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK)

RIEn - RIEn 0b0000..Disables Processor B Receive Interrupt n. (default) 0b0001..Enables Processor B Receive Interrupt n.

◆ MU_CR_RIEn [2/2]

#define MU_CR_RIEn ( x ) (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK)

RIEn - RIEn 0b0000..Disables Processor A Receive Interrupt n. (default) 0b0001..Enables Processor A Receive Interrupt n.

◆ MU_CR_TIEn [1/2]

#define MU_CR_TIEn ( x ) (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK)

TIEn - TIEn 0b0000..Disables Processor B Transmit Interrupt n. (default) 0b0001..Enables Processor B Transmit Interrupt n.

◆ MU_CR_TIEn [2/2]

#define MU_CR_TIEn ( x ) (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK)

TIEn - TIEn 0b0000..Disables Processor A Transmit Interrupt n. (default) 0b0001..Enables Processor A Transmit Interrupt n.

◆ MU_RR_DATA [1/2]

#define MU_RR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MU_RR_DATA_SHIFT)) & MU_RR_DATA_MASK)

DATA - RR3

◆ MU_RR_DATA [2/2]

#define MU_RR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MU_RR_DATA_SHIFT)) & MU_RR_DATA_MASK)

DATA - RR3

◆ MU_SR_EP [1/2]

#define MU_SR_EP ( x ) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK)

EP - EP 0b0..The Processor B-side event is not pending (default). 0b1..The Processor B-side event is pending.

◆ MU_SR_EP [2/2]

#define MU_SR_EP ( x ) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK)

EP - EP 0b0..The Processor A-side event is not pending (default). 0b1..The Processor A-side event is pending.

◆ MU_SR_Fn [1/2]

#define MU_SR_Fn ( x ) (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK)

Fn - Fn 0b000..ABFn bit in MUA.CR register is written 0 (default). 0b001..ABFn bit in MUA.CR register is written 1.

◆ MU_SR_Fn [2/2]

#define MU_SR_Fn ( x ) (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK)

Fn - Fn 0b000..BAFn bit in MUB.CR register is written 0 (default). 0b001..BAFn bit in MUB.CR register is written 1.

◆ MU_SR_FUP [1/2]

#define MU_SR_FUP ( x ) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK)

FUP - FUP 0b0..No flags updated, initiated by the Processor B, in progress (default) 0b1..Processor B initiated flags update, processing

◆ MU_SR_FUP [2/2]

#define MU_SR_FUP ( x ) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK)

FUP - FUP 0b0..No flags updated, initiated by the Processor A, in progress (default) 0b1..Processor A initiated flags update, processing

◆ MU_SR_GIPn [1/2]

#define MU_SR_GIPn ( x ) (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK)

GIPn - GIPn 0b0000..Processor B general purpose interrupt n is not pending. (default) 0b0001..Processor B general purpose interrupt n is pending.

◆ MU_SR_GIPn [2/2]

#define MU_SR_GIPn ( x ) (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK)

GIPn - GIPn 0b0000..Processor A general purpose interrupt n is not pending. (default) 0b0001..Processor A general purpose interrupt n is pending.

◆ MU_SR_RFn [1/2]

#define MU_SR_RFn ( x ) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK)

RFn - RFn 0b0000..MUB.RRn register is not full (default). 0b0001..MUB.RRn register has received data from MUA.TRn register and is ready to be read by the Processor B.

◆ MU_SR_RFn [2/2]

#define MU_SR_RFn ( x ) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK)

RFn - RFn 0b0000..MUA.RRn register is not full (default). 0b0001..MUA.RRn register has received data from MUB.TRn register and is ready to be read by the Processor A.

◆ MU_SR_RS [1/2]

#define MU_SR_RS ( x ) (((uint32_t)(((uint32_t)(x)) << MU_SR_RS_SHIFT)) & MU_SR_RS_MASK)

RS - RS 0b0..The Processor A or the Processor A-side of the MU is not in reset. 0b1..The Processor A or the Processor A-side of the MU is in reset.

◆ MU_SR_RS [2/2]

#define MU_SR_RS ( x ) (((uint32_t)(((uint32_t)(x)) << MU_SR_RS_SHIFT)) & MU_SR_RS_MASK)

RS - RS 0b0..The Processor B-side of the MU is not in reset. 0b1..The Processor B-side of the MU is in reset.

◆ MU_SR_TEn [1/2]

#define MU_SR_TEn ( x ) (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK)

TEn - TEn 0b0000..MUB.TRn register is not empty. 0b0001..MUB.TRn register is empty (default).

◆ MU_SR_TEn [2/2]