ERR_STATUS - Error Interrupt Status Register
#define	MECC_ERR_STATUS_SINGLE_ERR0_MASK (0x1U)

#define	MECC_ERR_STATUS_SINGLE_ERR0_SHIFT (0U)

#define	MECC_ERR_STATUS_SINGLE_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR0_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR0_MASK)

#define	MECC_ERR_STATUS_SINGLE_ERR1_MASK (0x2U)

#define	MECC_ERR_STATUS_SINGLE_ERR1_SHIFT (1U)

#define	MECC_ERR_STATUS_SINGLE_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR1_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR1_MASK)

#define	MECC_ERR_STATUS_SINGLE_ERR2_MASK (0x4U)

#define	MECC_ERR_STATUS_SINGLE_ERR2_SHIFT (2U)

#define	MECC_ERR_STATUS_SINGLE_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR2_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR2_MASK)

#define	MECC_ERR_STATUS_SINGLE_ERR3_MASK (0x8U)

#define	MECC_ERR_STATUS_SINGLE_ERR3_SHIFT (3U)

#define	MECC_ERR_STATUS_SINGLE_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR3_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR3_MASK)

#define	MECC_ERR_STATUS_MULTI_ERR0_MASK (0x10U)

#define	MECC_ERR_STATUS_MULTI_ERR0_SHIFT (4U)

#define	MECC_ERR_STATUS_MULTI_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR0_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR0_MASK)

#define	MECC_ERR_STATUS_MULTI_ERR1_MASK (0x20U)

#define	MECC_ERR_STATUS_MULTI_ERR1_SHIFT (5U)

#define	MECC_ERR_STATUS_MULTI_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR1_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR1_MASK)

#define	MECC_ERR_STATUS_MULTI_ERR2_MASK (0x40U)

#define	MECC_ERR_STATUS_MULTI_ERR2_SHIFT (6U)

#define	MECC_ERR_STATUS_MULTI_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR2_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR2_MASK)

#define	MECC_ERR_STATUS_MULTI_ERR3_MASK (0x80U)

#define	MECC_ERR_STATUS_MULTI_ERR3_SHIFT (7U)

#define	MECC_ERR_STATUS_MULTI_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR3_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR3_MASK)

#define	MECC_ERR_STATUS_STRB_ERR0_MASK (0x100U)

#define	MECC_ERR_STATUS_STRB_ERR0_SHIFT (8U)

#define	MECC_ERR_STATUS_STRB_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR0_SHIFT)) & MECC_ERR_STATUS_STRB_ERR0_MASK)

#define	MECC_ERR_STATUS_STRB_ERR1_MASK (0x200U)

#define	MECC_ERR_STATUS_STRB_ERR1_SHIFT (9U)

#define	MECC_ERR_STATUS_STRB_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR1_SHIFT)) & MECC_ERR_STATUS_STRB_ERR1_MASK)

#define	MECC_ERR_STATUS_STRB_ERR2_MASK (0x400U)

#define	MECC_ERR_STATUS_STRB_ERR2_SHIFT (10U)

#define	MECC_ERR_STATUS_STRB_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR2_SHIFT)) & MECC_ERR_STATUS_STRB_ERR2_MASK)

#define	MECC_ERR_STATUS_STRB_ERR3_MASK (0x800U)

#define	MECC_ERR_STATUS_STRB_ERR3_SHIFT (11U)

#define	MECC_ERR_STATUS_STRB_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR3_SHIFT)) & MECC_ERR_STATUS_STRB_ERR3_MASK)

#define	MECC_ERR_STATUS_ADDR_ERR0_MASK (0x1000U)

#define	MECC_ERR_STATUS_ADDR_ERR0_SHIFT (12U)

#define	MECC_ERR_STATUS_ADDR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR0_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR0_MASK)

#define	MECC_ERR_STATUS_ADDR_ERR1_MASK (0x2000U)

#define	MECC_ERR_STATUS_ADDR_ERR1_SHIFT (13U)

#define	MECC_ERR_STATUS_ADDR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR1_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR1_MASK)

#define	MECC_ERR_STATUS_ADDR_ERR2_MASK (0x4000U)

#define	MECC_ERR_STATUS_ADDR_ERR2_SHIFT (14U)

#define	MECC_ERR_STATUS_ADDR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR2_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR2_MASK)

#define	MECC_ERR_STATUS_ADDR_ERR3_MASK (0x8000U)

#define	MECC_ERR_STATUS_ADDR_ERR3_SHIFT (15U)

#define	MECC_ERR_STATUS_ADDR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR3_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR3_MASK)

#define	XECC_ERR_STATUS_SINGLE_ERR_MASK (0x1U)

#define	XECC_ERR_STATUS_SINGLE_ERR_SHIFT (0U)

#define	XECC_ERR_STATUS_SINGLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_SINGLE_ERR_SHIFT)) & XECC_ERR_STATUS_SINGLE_ERR_MASK)

#define	XECC_ERR_STATUS_MULTI_ERR_MASK (0x2U)

#define	XECC_ERR_STATUS_MULTI_ERR_SHIFT (1U)

#define	XECC_ERR_STATUS_MULTI_ERR(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_MULTI_ERR_SHIFT)) & XECC_ERR_STATUS_MULTI_ERR_MASK)

#define	XECC_ERR_STATUS_Reserved1_MASK (0xFFFFFFFCU)

#define	XECC_ERR_STATUS_Reserved1_SHIFT (2U)

#define	XECC_ERR_STATUS_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_Reserved1_SHIFT)) & XECC_ERR_STATUS_Reserved1_MASK)

ERR_STAT_EN - Error Interrupt Status Enable Register
#define	MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK (0x1U)

#define	MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_SHIFT (0U)

#define	MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK (0x2U)

#define	MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_SHIFT (1U)

#define	MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK (0x4U)

#define	MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_SHIFT (2U)

#define	MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK (0x8U)

#define	MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_SHIFT (3U)

#define	MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK (0x10U)

#define	MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_SHIFT (4U)

#define	MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK (0x20U)

#define	MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_SHIFT (5U)

#define	MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK (0x40U)

#define	MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_SHIFT (6U)

#define	MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK (0x80U)

#define	MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_SHIFT (7U)

#define	MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK (0x100U)

#define	MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_SHIFT (8U)

#define	MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK (0x200U)

#define	MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_SHIFT (9U)

#define	MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK (0x400U)

#define	MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_SHIFT (10U)

#define	MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK (0x800U)

#define	MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_SHIFT (11U)

#define	MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK (0x1000U)

#define	MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_SHIFT (12U)

#define	MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK (0x2000U)

#define	MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_SHIFT (13U)

#define	MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK (0x4000U)

#define	MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_SHIFT (14U)

#define	MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK (0x8000U)

#define	MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_SHIFT (15U)

#define	MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK)

#define	XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_MASK (0x1U)

#define	XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_SHIFT (0U)

#define	XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_SHIFT)) & XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_MASK)

#define	XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_MASK (0x2U)

#define	XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_SHIFT (1U)

#define	XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_SHIFT)) & XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_MASK)

#define	XECC_ERR_STAT_EN_Reserved1_MASK (0xFFFFFFFCU)

#define	XECC_ERR_STAT_EN_Reserved1_SHIFT (2U)

#define	XECC_ERR_STAT_EN_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_Reserved1_SHIFT)) & XECC_ERR_STAT_EN_Reserved1_MASK)

ERR_SIG_EN - Error Interrupt Enable Register
#define	MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK (0x1U)

#define	MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_SHIFT (0U)

#define	MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK (0x2U)

#define	MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_SHIFT (1U)

#define	MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK (0x4U)

#define	MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_SHIFT (2U)

#define	MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK (0x8U)

#define	MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_SHIFT (3U)

#define	MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK (0x10U)

#define	MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_SHIFT (4U)

#define	MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK (0x20U)

#define	MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_SHIFT (5U)

#define	MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK (0x40U)

#define	MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_SHIFT (6U)

#define	MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK (0x80U)

#define	MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_SHIFT (7U)

#define	MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK (0x100U)

#define	MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_SHIFT (8U)

#define	MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK (0x200U)

#define	MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_SHIFT (9U)

#define	MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK (0x400U)

#define	MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_SHIFT (10U)

#define	MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK (0x800U)

#define	MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_SHIFT (11U)

#define	MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK (0x1000U)

#define	MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_SHIFT (12U)

#define	MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK (0x2000U)

#define	MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_SHIFT (13U)

#define	MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK (0x4000U)

#define	MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_SHIFT (14U)

#define	MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK (0x8000U)

#define	MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_SHIFT (15U)

#define	MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK)

#define	XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_MASK (0x1U)

#define	XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_SHIFT (0U)

#define	XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_SHIFT)) & XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_MASK)

#define	XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_MASK (0x2U)

#define	XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_SHIFT (1U)

#define	XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_SHIFT)) & XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_MASK)

#define	XECC_ERR_SIG_EN_Reserved1_MASK (0xFFFFFFFCU)

#define	XECC_ERR_SIG_EN_Reserved1_SHIFT (2U)

#define	XECC_ERR_SIG_EN_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_Reserved1_SHIFT)) & XECC_ERR_SIG_EN_Reserved1_MASK)

ERR_DATA_INJ_LOW0 - Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data
#define	MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_MASK (0xFFFFFFFFU)

#define	MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_SHIFT (0U)

#define	MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_MASK)

ERR_DATA_INJ_HIGH0 - Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data
#define	MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_MASK (0xFFFFFFFFU)

#define	MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_SHIFT (0U)

#define	MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_MASK)

ERR_ECC_INJ0 - Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data
#define	MECC_ERR_ECC_INJ0_ERR_ECC_INJ_MASK (0xFFU)

#define	MECC_ERR_ECC_INJ0_ERR_ECC_INJ_SHIFT (0U)

#define	MECC_ERR_ECC_INJ0_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ0_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ0_ERR_ECC_INJ_MASK)

ERR_DATA_INJ_LOW1 - Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data
#define	MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_MASK (0xFFFFFFFFU)

#define	MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_SHIFT (0U)

#define	MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_MASK)

ERR_DATA_INJ_HIGH1 - Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data
#define	MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_MASK (0xFFFFFFFFU)

#define	MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_SHIFT (0U)

#define	MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_MASK)

ERR_ECC_INJ1 - Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data
#define	MECC_ERR_ECC_INJ1_ERR_ECC_INJ_MASK (0xFFU)

#define	MECC_ERR_ECC_INJ1_ERR_ECC_INJ_SHIFT (0U)

#define	MECC_ERR_ECC_INJ1_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ1_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ1_ERR_ECC_INJ_MASK)

ERR_DATA_INJ_LOW2 - Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data
#define	MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_MASK (0xFFFFFFFFU)

#define	MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_SHIFT (0U)

#define	MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_MASK)

ERR_DATA_INJ_HIGH2 - Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data
#define	MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_MASK (0xFFFFFFFFU)

#define	MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_SHIFT (0U)

#define	MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_MASK)

ERR_ECC_INJ2 - Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data
#define	MECC_ERR_ECC_INJ2_ERR_ECC_INJ_MASK (0xFFU)

#define	MECC_ERR_ECC_INJ2_ERR_ECC_INJ_SHIFT (0U)

#define	MECC_ERR_ECC_INJ2_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ2_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ2_ERR_ECC_INJ_MASK)

ERR_DATA_INJ_LOW3 - Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data
#define	MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_MASK (0xFFFFFFFFU)

#define	MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_SHIFT (0U)

#define	MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_MASK)

ERR_DATA_INJ_HIGH3 - Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data
#define	MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_MASK (0xFFFFFFFFU)

#define	MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_SHIFT (0U)

#define	MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_MASK)

ERR_ECC_INJ3 - Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data
#define	MECC_ERR_ECC_INJ3_ERR_ECC_INJ_MASK (0xFFU)

#define	MECC_ERR_ECC_INJ3_ERR_ECC_INJ_SHIFT (0U)

#define	MECC_ERR_ECC_INJ3_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ3_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ3_ERR_ECC_INJ_MASK)

SINGLE_ERR_ADDR_ECC0 - Single Error Address And ECC code On OCRAM Bank0
#define	MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_MASK (0xFFU)

#define	MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_SHIFT (0U)

#define	MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_MASK)

#define	MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)

#define	MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_SHIFT (8U)

#define	MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_MASK)

SINGLE_ERR_DATA_LOW0 - LOW 32 Bits Single Error Read Data On OCRAM Bank0
#define	MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_SHIFT (0U)

#define	MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_DATA_HIGH0 - HIGH 32 Bits Single Error Read Data On OCRAM Bank0
#define	MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_SHIFT (0U)

#define	MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_POS_LOW0 - LOW Single Error Bit Position On OCRAM Bank0
#define	MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_SHIFT (0U)

#define	MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_MASK)

SINGLE_ERR_POS_HIGH0 - HIGH Single Error Bit Position On OCRAM Bank0
#define	MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_SHIFT (0U)

#define	MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_MASK)

SINGLE_ERR_ADDR_ECC1 - Single Error Address And ECC code On OCRAM Bank1
#define	MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_MASK (0xFFU)

#define	MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_SHIFT (0U)

#define	MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_MASK)

#define	MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)

#define	MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_SHIFT (8U)

#define	MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_MASK)

SINGLE_ERR_DATA_LOW1 - LOW 32 Bits Single Error Read Data On OCRAM Bank1
#define	MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_SHIFT (0U)

#define	MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_DATA_HIGH1 - HIGH 32 Bits Single Error Read Data On OCRAM Bank1
#define	MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_SHIFT (0U)

#define	MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_POS_LOW1 - LOW Single Error Bit Position On OCRAM Bank1
#define	MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_SHIFT (0U)

#define	MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_MASK)

SINGLE_ERR_POS_HIGH1 - HIGH Single Error Bit Position On OCRAM Bank1
#define	MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_SHIFT (0U)

#define	MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_MASK)

SINGLE_ERR_ADDR_ECC2 - Single Error Address And ECC code On OCRAM Bank2
#define	MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_MASK (0xFFU)

#define	MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_SHIFT (0U)

#define	MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_MASK)

#define	MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)

#define	MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_SHIFT (8U)

#define	MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_MASK)

SINGLE_ERR_DATA_LOW2 - LOW 32 Bits Single Error Read Data On OCRAM Bank2
#define	MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_SHIFT (0U)

#define	MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_DATA_HIGH2 - HIGH 32 Bits Single Error Read Data On OCRAM Bank2
#define	MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_SHIFT (0U)

#define	MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_POS_LOW2 - LOW Single Error Bit Position On OCRAM Bank2
#define	MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_SHIFT (0U)

#define	MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_MASK)

SINGLE_ERR_POS_HIGH2 - HIGH Single Error Bit Position On OCRAM Bank2
#define	MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_SHIFT (0U)

#define	MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_MASK)

SINGLE_ERR_ADDR_ECC3 - Single Error Address And ECC code On OCRAM Bank3
#define	MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_MASK (0xFFU)

#define	MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_SHIFT (0U)

#define	MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_MASK)

#define	MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)

#define	MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_SHIFT (8U)

#define	MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_MASK)

SINGLE_ERR_DATA_LOW3 - LOW 32 Bits Single Error Read Data On OCRAM Bank3
#define	MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_SHIFT (0U)

#define	MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_DATA_HIGH3 - HIGH 32 Bits Single Error Read Data On OCRAM Bank3
#define	MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_SHIFT (0U)

#define	MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_POS_LOW3 - LOW Single Error Bit Position On OCRAM Bank3
#define	MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_SHIFT (0U)

#define	MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_MASK)

SINGLE_ERR_POS_HIGH3 - HIGH Single Error Bit Position On OCRAM Bank3
#define	MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_SHIFT (0U)

#define	MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_MASK)

MULTI_ERR_ADDR_ECC0 - Multiple Error Address And ECC code On OCRAM Bank0
#define	MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_MASK (0xFFU)

#define	MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_SHIFT (0U)

#define	MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_MASK)

#define	MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_MASK (0x7FFFF00U)

#define	MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_SHIFT (8U)

#define	MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_MASK)

MULTI_ERR_DATA_LOW0 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank0
#define	MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_SHIFT (0U)

#define	MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_MASK)

MULTI_ERR_DATA_HIGH0 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0
#define	MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_SHIFT (0U)

#define	MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_MASK)

MULTI_ERR_ADDR_ECC1 - Multiple Error Address And ECC code On OCRAM Bank1
#define	MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_MASK (0xFFU)

#define	MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_SHIFT (0U)

#define	MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_MASK)

#define	MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_MASK (0x7FFFF00U)

#define	MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_SHIFT (8U)

#define	MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_MASK)

MULTI_ERR_DATA_LOW1 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank1
#define	MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_SHIFT (0U)

#define	MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_MASK)

MULTI_ERR_DATA_HIGH1 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1
#define	MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_SHIFT (0U)

#define	MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_MASK)

MULTI_ERR_ADDR_ECC2 - Multiple Error Address And ECC code On OCRAM Bank2
#define	MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_MASK (0xFFU)

#define	MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_SHIFT (0U)

#define	MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_MASK)

#define	MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_MASK (0x7FFFF00U)

#define	MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_SHIFT (8U)

#define	MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_MASK)

MULTI_ERR_DATA_LOW2 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank2
#define	MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_SHIFT (0U)

#define	MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_MASK)

MULTI_ERR_DATA_HIGH2 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2
#define	MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_SHIFT (0U)

#define	MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_MASK)

MULTI_ERR_ADDR_ECC3 - Multiple Error Address And ECC code On OCRAM Bank3
#define	MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_MASK (0xFFU)

#define	MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_SHIFT (0U)

#define	MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_MASK)

#define	MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_MASK (0x7FFFF00U)

#define	MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_SHIFT (8U)

#define	MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_MASK)

MULTI_ERR_DATA_LOW3 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank3
#define	MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_SHIFT (0U)

#define	MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_MASK)

MULTI_ERR_DATA_HIGH3 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3
#define	MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_SHIFT (0U)

#define	MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_MASK)

PIPE_ECC_EN - OCRAM Pipeline And ECC Enable
#define	MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_MASK (0x1U)

#define	MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_SHIFT (0U)

#define	MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_SHIFT)) & MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_MASK)

#define	MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_MASK (0x2U)

#define	MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_SHIFT (1U)

#define	MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_MASK)

#define	MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_MASK (0x4U)

#define	MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_SHIFT (2U)

#define	MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_MASK)

#define	MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_MASK (0x8U)

#define	MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_SHIFT (3U)

#define	MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_MASK)

#define	MECC_PIPE_ECC_EN_ECC_EN_MASK (0x10U)

#define	MECC_PIPE_ECC_EN_ECC_EN_SHIFT (4U)

#define	MECC_PIPE_ECC_EN_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_ECC_EN_SHIFT)) & MECC_PIPE_ECC_EN_ECC_EN_MASK)

PENDING_STAT - Pending Status
#define	MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_MASK (0x1U)

#define	MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_SHIFT (0U)

#define	MECC_PENDING_STAT_READ_DATA_WAIT_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_SHIFT)) & MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_MASK)

#define	MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_MASK (0x2U)

#define	MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_SHIFT (1U)

#define	MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_MASK)

#define	MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_MASK (0x4U)

#define	MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_SHIFT (2U)

#define	MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_MASK)

#define	MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_MASK (0x8U)

#define	MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_SHIFT (3U)

#define	MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_MASK)

ERR_STATUS - Error Interrupt Status Register
#define	MECC_ERR_STATUS_SINGLE_ERR0_MASK (0x1U)

#define	MECC_ERR_STATUS_SINGLE_ERR0_SHIFT (0U)

#define	MECC_ERR_STATUS_SINGLE_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR0_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR0_MASK)

#define	MECC_ERR_STATUS_SINGLE_ERR1_MASK (0x2U)

#define	MECC_ERR_STATUS_SINGLE_ERR1_SHIFT (1U)

#define	MECC_ERR_STATUS_SINGLE_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR1_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR1_MASK)

#define	MECC_ERR_STATUS_SINGLE_ERR2_MASK (0x4U)

#define	MECC_ERR_STATUS_SINGLE_ERR2_SHIFT (2U)

#define	MECC_ERR_STATUS_SINGLE_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR2_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR2_MASK)

#define	MECC_ERR_STATUS_SINGLE_ERR3_MASK (0x8U)

#define	MECC_ERR_STATUS_SINGLE_ERR3_SHIFT (3U)

#define	MECC_ERR_STATUS_SINGLE_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR3_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR3_MASK)

#define	MECC_ERR_STATUS_MULTI_ERR0_MASK (0x10U)

#define	MECC_ERR_STATUS_MULTI_ERR0_SHIFT (4U)

#define	MECC_ERR_STATUS_MULTI_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR0_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR0_MASK)

#define	MECC_ERR_STATUS_MULTI_ERR1_MASK (0x20U)

#define	MECC_ERR_STATUS_MULTI_ERR1_SHIFT (5U)

#define	MECC_ERR_STATUS_MULTI_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR1_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR1_MASK)

#define	MECC_ERR_STATUS_MULTI_ERR2_MASK (0x40U)

#define	MECC_ERR_STATUS_MULTI_ERR2_SHIFT (6U)

#define	MECC_ERR_STATUS_MULTI_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR2_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR2_MASK)

#define	MECC_ERR_STATUS_MULTI_ERR3_MASK (0x80U)

#define	MECC_ERR_STATUS_MULTI_ERR3_SHIFT (7U)

#define	MECC_ERR_STATUS_MULTI_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR3_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR3_MASK)

#define	MECC_ERR_STATUS_STRB_ERR0_MASK (0x100U)

#define	MECC_ERR_STATUS_STRB_ERR0_SHIFT (8U)

#define	MECC_ERR_STATUS_STRB_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR0_SHIFT)) & MECC_ERR_STATUS_STRB_ERR0_MASK)

#define	MECC_ERR_STATUS_STRB_ERR1_MASK (0x200U)

#define	MECC_ERR_STATUS_STRB_ERR1_SHIFT (9U)

#define	MECC_ERR_STATUS_STRB_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR1_SHIFT)) & MECC_ERR_STATUS_STRB_ERR1_MASK)

#define	MECC_ERR_STATUS_STRB_ERR2_MASK (0x400U)

#define	MECC_ERR_STATUS_STRB_ERR2_SHIFT (10U)

#define	MECC_ERR_STATUS_STRB_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR2_SHIFT)) & MECC_ERR_STATUS_STRB_ERR2_MASK)

#define	MECC_ERR_STATUS_STRB_ERR3_MASK (0x800U)

#define	MECC_ERR_STATUS_STRB_ERR3_SHIFT (11U)

#define	MECC_ERR_STATUS_STRB_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR3_SHIFT)) & MECC_ERR_STATUS_STRB_ERR3_MASK)

#define	MECC_ERR_STATUS_ADDR_ERR0_MASK (0x1000U)

#define	MECC_ERR_STATUS_ADDR_ERR0_SHIFT (12U)

#define	MECC_ERR_STATUS_ADDR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR0_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR0_MASK)

#define	MECC_ERR_STATUS_ADDR_ERR1_MASK (0x2000U)

#define	MECC_ERR_STATUS_ADDR_ERR1_SHIFT (13U)

#define	MECC_ERR_STATUS_ADDR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR1_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR1_MASK)

#define	MECC_ERR_STATUS_ADDR_ERR2_MASK (0x4000U)

#define	MECC_ERR_STATUS_ADDR_ERR2_SHIFT (14U)

#define	MECC_ERR_STATUS_ADDR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR2_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR2_MASK)

#define	MECC_ERR_STATUS_ADDR_ERR3_MASK (0x8000U)

#define	MECC_ERR_STATUS_ADDR_ERR3_SHIFT (15U)

#define	MECC_ERR_STATUS_ADDR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR3_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR3_MASK)

#define	XECC_ERR_STATUS_SINGLE_ERR_MASK (0x1U)

#define	XECC_ERR_STATUS_SINGLE_ERR_SHIFT (0U)

#define	XECC_ERR_STATUS_SINGLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_SINGLE_ERR_SHIFT)) & XECC_ERR_STATUS_SINGLE_ERR_MASK)

#define	XECC_ERR_STATUS_MULTI_ERR_MASK (0x2U)

#define	XECC_ERR_STATUS_MULTI_ERR_SHIFT (1U)

#define	XECC_ERR_STATUS_MULTI_ERR(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_MULTI_ERR_SHIFT)) & XECC_ERR_STATUS_MULTI_ERR_MASK)

#define	XECC_ERR_STATUS_Reserved1_MASK (0xFFFFFFFCU)

#define	XECC_ERR_STATUS_Reserved1_SHIFT (2U)

#define	XECC_ERR_STATUS_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_Reserved1_SHIFT)) & XECC_ERR_STATUS_Reserved1_MASK)

ERR_STAT_EN - Error Interrupt Status Enable Register
#define	MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK (0x1U)

#define	MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_SHIFT (0U)

#define	MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK (0x2U)

#define	MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_SHIFT (1U)

#define	MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK (0x4U)

#define	MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_SHIFT (2U)

#define	MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK (0x8U)

#define	MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_SHIFT (3U)

#define	MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK (0x10U)

#define	MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_SHIFT (4U)

#define	MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK (0x20U)

#define	MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_SHIFT (5U)

#define	MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK (0x40U)

#define	MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_SHIFT (6U)

#define	MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK (0x80U)

#define	MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_SHIFT (7U)

#define	MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK (0x100U)

#define	MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_SHIFT (8U)

#define	MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK (0x200U)

#define	MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_SHIFT (9U)

#define	MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK (0x400U)

#define	MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_SHIFT (10U)

#define	MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK (0x800U)

#define	MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_SHIFT (11U)

#define	MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK (0x1000U)

#define	MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_SHIFT (12U)

#define	MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK (0x2000U)

#define	MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_SHIFT (13U)

#define	MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK (0x4000U)

#define	MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_SHIFT (14U)

#define	MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK)

#define	MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK (0x8000U)

#define	MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_SHIFT (15U)

#define	MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK)

#define	XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_MASK (0x1U)

#define	XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_SHIFT (0U)

#define	XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_SHIFT)) & XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_MASK)

#define	XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_MASK (0x2U)

#define	XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_SHIFT (1U)

#define	XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_SHIFT)) & XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_MASK)

#define	XECC_ERR_STAT_EN_Reserved1_MASK (0xFFFFFFFCU)

#define	XECC_ERR_STAT_EN_Reserved1_SHIFT (2U)

#define	XECC_ERR_STAT_EN_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_Reserved1_SHIFT)) & XECC_ERR_STAT_EN_Reserved1_MASK)

ERR_SIG_EN - Error Interrupt Enable Register
#define	MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK (0x1U)

#define	MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_SHIFT (0U)

#define	MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK (0x2U)

#define	MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_SHIFT (1U)

#define	MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK (0x4U)

#define	MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_SHIFT (2U)

#define	MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK (0x8U)

#define	MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_SHIFT (3U)

#define	MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK (0x10U)

#define	MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_SHIFT (4U)

#define	MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK (0x20U)

#define	MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_SHIFT (5U)

#define	MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK (0x40U)

#define	MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_SHIFT (6U)

#define	MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK (0x80U)

#define	MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_SHIFT (7U)

#define	MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK (0x100U)

#define	MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_SHIFT (8U)

#define	MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK (0x200U)

#define	MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_SHIFT (9U)

#define	MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK (0x400U)

#define	MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_SHIFT (10U)

#define	MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK (0x800U)

#define	MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_SHIFT (11U)

#define	MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK (0x1000U)

#define	MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_SHIFT (12U)

#define	MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK (0x2000U)

#define	MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_SHIFT (13U)

#define	MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK (0x4000U)

#define	MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_SHIFT (14U)

#define	MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK)

#define	MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK (0x8000U)

#define	MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_SHIFT (15U)

#define	MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK)

#define	XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_MASK (0x1U)

#define	XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_SHIFT (0U)

#define	XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_SHIFT)) & XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_MASK)

#define	XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_MASK (0x2U)

#define	XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_SHIFT (1U)

#define	XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_SHIFT)) & XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_MASK)

#define	XECC_ERR_SIG_EN_Reserved1_MASK (0xFFFFFFFCU)

#define	XECC_ERR_SIG_EN_Reserved1_SHIFT (2U)

#define	XECC_ERR_SIG_EN_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_Reserved1_SHIFT)) & XECC_ERR_SIG_EN_Reserved1_MASK)

ERR_DATA_INJ_LOW0 - Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data
#define	MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_MASK (0xFFFFFFFFU)

#define	MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_SHIFT (0U)

#define	MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_MASK)

ERR_DATA_INJ_HIGH0 - Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data
#define	MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_MASK (0xFFFFFFFFU)

#define	MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_SHIFT (0U)

#define	MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_MASK)

ERR_ECC_INJ0 - Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data
#define	MECC_ERR_ECC_INJ0_ERR_ECC_INJ_MASK (0xFFU)

#define	MECC_ERR_ECC_INJ0_ERR_ECC_INJ_SHIFT (0U)

#define	MECC_ERR_ECC_INJ0_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ0_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ0_ERR_ECC_INJ_MASK)

ERR_DATA_INJ_LOW1 - Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data
#define	MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_MASK (0xFFFFFFFFU)

#define	MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_SHIFT (0U)

#define	MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_MASK)

ERR_DATA_INJ_HIGH1 - Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data
#define	MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_MASK (0xFFFFFFFFU)

#define	MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_SHIFT (0U)

#define	MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_MASK)

ERR_ECC_INJ1 - Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data
#define	MECC_ERR_ECC_INJ1_ERR_ECC_INJ_MASK (0xFFU)

#define	MECC_ERR_ECC_INJ1_ERR_ECC_INJ_SHIFT (0U)

#define	MECC_ERR_ECC_INJ1_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ1_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ1_ERR_ECC_INJ_MASK)

ERR_DATA_INJ_LOW2 - Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data
#define	MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_MASK (0xFFFFFFFFU)

#define	MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_SHIFT (0U)

#define	MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_MASK)

ERR_DATA_INJ_HIGH2 - Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data
#define	MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_MASK (0xFFFFFFFFU)

#define	MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_SHIFT (0U)

#define	MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_MASK)

ERR_ECC_INJ2 - Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data
#define	MECC_ERR_ECC_INJ2_ERR_ECC_INJ_MASK (0xFFU)

#define	MECC_ERR_ECC_INJ2_ERR_ECC_INJ_SHIFT (0U)

#define	MECC_ERR_ECC_INJ2_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ2_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ2_ERR_ECC_INJ_MASK)

ERR_DATA_INJ_LOW3 - Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data
#define	MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_MASK (0xFFFFFFFFU)

#define	MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_SHIFT (0U)

#define	MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_MASK)

ERR_DATA_INJ_HIGH3 - Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data
#define	MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_MASK (0xFFFFFFFFU)

#define	MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_SHIFT (0U)

#define	MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_MASK)

ERR_ECC_INJ3 - Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data
#define	MECC_ERR_ECC_INJ3_ERR_ECC_INJ_MASK (0xFFU)

#define	MECC_ERR_ECC_INJ3_ERR_ECC_INJ_SHIFT (0U)

#define	MECC_ERR_ECC_INJ3_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ3_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ3_ERR_ECC_INJ_MASK)

SINGLE_ERR_ADDR_ECC0 - Single Error Address And ECC code On OCRAM Bank0
#define	MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_MASK (0xFFU)

#define	MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_SHIFT (0U)

#define	MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_MASK)

#define	MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)

#define	MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_SHIFT (8U)

#define	MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_MASK)

SINGLE_ERR_DATA_LOW0 - LOW 32 Bits Single Error Read Data On OCRAM Bank0
#define	MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_SHIFT (0U)

#define	MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_DATA_HIGH0 - HIGH 32 Bits Single Error Read Data On OCRAM Bank0
#define	MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_SHIFT (0U)

#define	MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_POS_LOW0 - LOW Single Error Bit Position On OCRAM Bank0
#define	MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_SHIFT (0U)

#define	MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_MASK)

SINGLE_ERR_POS_HIGH0 - HIGH Single Error Bit Position On OCRAM Bank0
#define	MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_SHIFT (0U)

#define	MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_MASK)

SINGLE_ERR_ADDR_ECC1 - Single Error Address And ECC code On OCRAM Bank1
#define	MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_MASK (0xFFU)

#define	MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_SHIFT (0U)

#define	MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_MASK)

#define	MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)

#define	MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_SHIFT (8U)

#define	MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_MASK)

SINGLE_ERR_DATA_LOW1 - LOW 32 Bits Single Error Read Data On OCRAM Bank1
#define	MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_SHIFT (0U)

#define	MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_DATA_HIGH1 - HIGH 32 Bits Single Error Read Data On OCRAM Bank1
#define	MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_SHIFT (0U)

#define	MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_POS_LOW1 - LOW Single Error Bit Position On OCRAM Bank1
#define	MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_SHIFT (0U)

#define	MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_MASK)

SINGLE_ERR_POS_HIGH1 - HIGH Single Error Bit Position On OCRAM Bank1
#define	MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_SHIFT (0U)

#define	MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_MASK)

SINGLE_ERR_ADDR_ECC2 - Single Error Address And ECC code On OCRAM Bank2
#define	MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_MASK (0xFFU)

#define	MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_SHIFT (0U)

#define	MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_MASK)

#define	MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)

#define	MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_SHIFT (8U)

#define	MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_MASK)

SINGLE_ERR_DATA_LOW2 - LOW 32 Bits Single Error Read Data On OCRAM Bank2
#define	MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_SHIFT (0U)

#define	MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_DATA_HIGH2 - HIGH 32 Bits Single Error Read Data On OCRAM Bank2
#define	MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_SHIFT (0U)

#define	MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_POS_LOW2 - LOW Single Error Bit Position On OCRAM Bank2
#define	MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_SHIFT (0U)

#define	MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_MASK)

SINGLE_ERR_POS_HIGH2 - HIGH Single Error Bit Position On OCRAM Bank2
#define	MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_SHIFT (0U)

#define	MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_MASK)

SINGLE_ERR_ADDR_ECC3 - Single Error Address And ECC code On OCRAM Bank3
#define	MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_MASK (0xFFU)

#define	MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_SHIFT (0U)

#define	MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_MASK)

#define	MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)

#define	MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_SHIFT (8U)

#define	MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_MASK)

SINGLE_ERR_DATA_LOW3 - LOW 32 Bits Single Error Read Data On OCRAM Bank3
#define	MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_SHIFT (0U)

#define	MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_DATA_HIGH3 - HIGH 32 Bits Single Error Read Data On OCRAM Bank3
#define	MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_SHIFT (0U)

#define	MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_POS_LOW3 - LOW Single Error Bit Position On OCRAM Bank3
#define	MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_SHIFT (0U)

#define	MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_MASK)

SINGLE_ERR_POS_HIGH3 - HIGH Single Error Bit Position On OCRAM Bank3
#define	MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)

#define	MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_SHIFT (0U)

#define	MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_MASK)

MULTI_ERR_ADDR_ECC0 - Multiple Error Address And ECC code On OCRAM Bank0
#define	MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_MASK (0xFFU)

#define	MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_SHIFT (0U)

#define	MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_MASK)

#define	MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_MASK (0x7FFFF00U)

#define	MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_SHIFT (8U)

#define	MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_MASK)

MULTI_ERR_DATA_LOW0 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank0
#define	MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_SHIFT (0U)

#define	MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_MASK)

MULTI_ERR_DATA_HIGH0 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0
#define	MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_SHIFT (0U)

#define	MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_MASK)

MULTI_ERR_ADDR_ECC1 - Multiple Error Address And ECC code On OCRAM Bank1
#define	MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_MASK (0xFFU)

#define	MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_SHIFT (0U)

#define	MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_MASK)

#define	MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_MASK (0x7FFFF00U)

#define	MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_SHIFT (8U)

#define	MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_MASK)

MULTI_ERR_DATA_LOW1 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank1
#define	MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_SHIFT (0U)

#define	MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_MASK)

MULTI_ERR_DATA_HIGH1 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1
#define	MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_SHIFT (0U)

#define	MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_MASK)

MULTI_ERR_ADDR_ECC2 - Multiple Error Address And ECC code On OCRAM Bank2
#define	MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_MASK (0xFFU)

#define	MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_SHIFT (0U)

#define	MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_MASK)

#define	MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_MASK (0x7FFFF00U)

#define	MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_SHIFT (8U)

#define	MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_MASK)

MULTI_ERR_DATA_LOW2 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank2
#define	MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_SHIFT (0U)

#define	MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_MASK)

MULTI_ERR_DATA_HIGH2 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2
#define	MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_SHIFT (0U)

#define	MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_MASK)

MULTI_ERR_ADDR_ECC3 - Multiple Error Address And ECC code On OCRAM Bank3
#define	MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_MASK (0xFFU)

#define	MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_SHIFT (0U)

#define	MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_MASK)

#define	MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_MASK (0x7FFFF00U)

#define	MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_SHIFT (8U)

#define	MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_MASK)

MULTI_ERR_DATA_LOW3 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank3
#define	MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_SHIFT (0U)

#define	MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_MASK)

MULTI_ERR_DATA_HIGH3 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3
#define	MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)

#define	MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_SHIFT (0U)

#define	MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_MASK)

PIPE_ECC_EN - OCRAM Pipeline And ECC Enable
#define	MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_MASK (0x1U)

#define	MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_SHIFT (0U)

#define	MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_SHIFT)) & MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_MASK)

#define	MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_MASK (0x2U)

#define	MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_SHIFT (1U)

#define	MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_MASK)

#define	MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_MASK (0x4U)

#define	MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_SHIFT (2U)

#define	MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_MASK)

#define	MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_MASK (0x8U)

#define	MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_SHIFT (3U)

#define	MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_MASK)

#define	MECC_PIPE_ECC_EN_ECC_EN_MASK (0x10U)

#define	MECC_PIPE_ECC_EN_ECC_EN_SHIFT (4U)

#define	MECC_PIPE_ECC_EN_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_ECC_EN_SHIFT)) & MECC_PIPE_ECC_EN_ECC_EN_MASK)

PENDING_STAT - Pending Status
#define	MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_MASK (0x1U)

#define	MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_SHIFT (0U)

#define	MECC_PENDING_STAT_READ_DATA_WAIT_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_SHIFT)) & MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_MASK)

#define	MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_MASK (0x2U)

#define	MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_SHIFT (1U)

#define	MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_MASK)

#define	MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_MASK (0x4U)

#define	MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_SHIFT (2U)

#define	MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_MASK)

#define	MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_MASK (0x8U)

#define	MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_SHIFT (3U)

#define	MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_MASK)

Detailed Description

Macro Definition Documentation

◆ MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ [1/2]

#define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_MASK)

ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data

◆ MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ [2/2]

#define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_MASK)

ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data

◆ MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ [1/2]

#define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_MASK)

ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data

◆ MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ [2/2]

#define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_MASK)

ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data

◆ MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ [1/2]

#define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_MASK)

ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data

◆ MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ [2/2]

#define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_MASK)

ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data

◆ MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ [1/2]

#define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_MASK)

ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data

◆ MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ [2/2]

#define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_MASK)

ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data

◆ MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ [1/2]

#define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_MASK)

ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data

◆ MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ [2/2]

#define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_MASK)

ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data

◆ MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ [1/2]

#define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_MASK)

ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data

◆ MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ [2/2]

#define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_MASK)

ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data

◆ MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ [1/2]

#define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_MASK)

ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data

◆ MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ [2/2]

#define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_MASK)

ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data

◆ MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ [1/2]

#define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_MASK)

ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data

◆ MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ [2/2]

#define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_MASK)

ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data

◆ MECC_ERR_ECC_INJ0_ERR_ECC_INJ [1/2]

#define MECC_ERR_ECC_INJ0_ERR_ECC_INJ ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ0_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ0_ERR_ECC_INJ_MASK)

ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data

◆ MECC_ERR_ECC_INJ0_ERR_ECC_INJ [2/2]

#define MECC_ERR_ECC_INJ0_ERR_ECC_INJ ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ0_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ0_ERR_ECC_INJ_MASK)

ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data

◆ MECC_ERR_ECC_INJ1_ERR_ECC_INJ [1/2]

#define MECC_ERR_ECC_INJ1_ERR_ECC_INJ ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ1_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ1_ERR_ECC_INJ_MASK)

ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data

◆ MECC_ERR_ECC_INJ1_ERR_ECC_INJ [2/2]

#define MECC_ERR_ECC_INJ1_ERR_ECC_INJ ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ1_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ1_ERR_ECC_INJ_MASK)

ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data

◆ MECC_ERR_ECC_INJ2_ERR_ECC_INJ [1/2]

#define MECC_ERR_ECC_INJ2_ERR_ECC_INJ ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ2_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ2_ERR_ECC_INJ_MASK)

ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data

◆ MECC_ERR_ECC_INJ2_ERR_ECC_INJ [2/2]

#define MECC_ERR_ECC_INJ2_ERR_ECC_INJ ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ2_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ2_ERR_ECC_INJ_MASK)

ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data

◆ MECC_ERR_ECC_INJ3_ERR_ECC_INJ [1/2]

#define MECC_ERR_ECC_INJ3_ERR_ECC_INJ ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ3_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ3_ERR_ECC_INJ_MASK)

ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data

◆ MECC_ERR_ECC_INJ3_ERR_ECC_INJ [2/2]

#define MECC_ERR_ECC_INJ3_ERR_ECC_INJ ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ3_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ3_ERR_ECC_INJ_MASK)

ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data

◆ MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN [1/2]

#define MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK)

ADDR_ERR0_SIG_EN - OCRAM Access Error Interrupt Enable On Bank0 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN [2/2]

#define MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK)

ADDR_ERR0_SIG_EN - OCRAM Access Error Interrupt Enable On Bank0 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN [1/2]

#define MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK)

ADDR_ERR1_SIG_EN - OCRAM Access Error Interrupt Enable On Bank1 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN [2/2]

#define MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK)

ADDR_ERR1_SIG_EN - OCRAM Access Error Interrupt Enable On Bank1 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN [1/2]

#define MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK)

ADDR_ERR2_SIG_EN - OCRAM Access Error Interrupt Enable On Bank2 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN [2/2]

#define MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK)

ADDR_ERR2_SIG_EN - OCRAM Access Error Interrupt Enable On Bank2 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN [1/2]

#define MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK)

ADDR_ERR3_SIG_EN - OCRAM Access Error Interrupt Enable On Bank3 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN [2/2]

#define MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK)

ADDR_ERR3_SIG_EN - OCRAM Access Error Interrupt Enable On Bank3 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN [1/2]

#define MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK)

MULTI_ERR0_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank0 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN [2/2]

#define MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK)

MULTI_ERR0_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank0 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN [1/2]

#define MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK)

MULTI_ERR1_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank1 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN [2/2]

#define MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK)

MULTI_ERR1_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank1 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN [1/2]

#define MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK)

MULTI_ERR2_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank2 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN [2/2]

#define MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK)

MULTI_ERR2_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank2 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN [1/2]

#define MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK)

MULTI_ERR3_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank3 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN [2/2]

#define MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK)

MULTI_ERR3_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank3 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN [1/2]

#define MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK)

SINGLE_ERR0_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank0 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN [2/2]

#define MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK)

SINGLE_ERR0_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank0 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN [1/2]

#define MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK)

SINGLE_ERR1_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank1 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN [2/2]

#define MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK)

SINGLE_ERR1_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank1 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN [1/2]

#define MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK)

SINGLE_ERR2_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank2 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN [2/2]

#define MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK)

SINGLE_ERR2_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank2 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN [1/2]

#define MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK)

SINGLE_ERR3_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank3 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN [2/2]

#define MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK)

SINGLE_ERR3_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank3 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN [1/2]

#define MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK)

STRB_ERR0_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank0 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN [2/2]

#define MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK)

STRB_ERR0_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank0 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN [1/2]

#define MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK)

STRB_ERR1_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank1 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN [2/2]

#define MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK)

STRB_ERR1_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank1 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN [1/2]

#define MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK)

STRB_ERR2_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank2 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN [2/2]

#define MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK)

STRB_ERR2_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank2 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN [1/2]

#define MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK)

STRB_ERR3_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank3 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN [2/2]

#define MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK)

STRB_ERR3_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank3 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN [1/2]

#define MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK)

ADDR_ERR0_STAT_EN - OCRAM Access Error Status Enable On Bank0 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN [2/2]

#define MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK)

ADDR_ERR0_STAT_EN - OCRAM Access Error Status Enable On Bank0 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN [1/2]

#define MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK)

ADDR_ERR1_STAT_EN - OCRAM Access Error Status Enable On Bank1 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN [2/2]

#define MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK)

ADDR_ERR1_STAT_EN - OCRAM Access Error Status Enable On Bank1 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN [1/2]

#define MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK)

ADDR_ERR2_STAT_EN - OCRAM Access Error Status Enable On Bank2 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN [2/2]

#define MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK)

ADDR_ERR2_STAT_EN - OCRAM Access Error Status Enable On Bank2 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN [1/2]

#define MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK)

ADDR_ERR3_STAT_EN - OCRAM Access Error Status Enable On Bank3 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN [2/2]

#define MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK)

ADDR_ERR3_STAT_EN - OCRAM Access Error Status Enable On Bank3 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN [1/2]

#define MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK)

MULTI_ERR0_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank0 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN [2/2]

#define MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK)

MULTI_ERR0_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank0 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN [1/2]

#define MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK)

MULTI_ERR1_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank1 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN [2/2]

#define MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK)

MULTI_ERR1_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank1 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN [1/2]

#define MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK)

MULTI_ERR2_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank2 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN [2/2]

#define MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK)

MULTI_ERR2_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank2 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN [1/2]

#define MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK)

MULTI_ERR3_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank3 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN [2/2]

#define MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK)

MULTI_ERR3_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank3 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN [1/2]

#define MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK)

SINGLE_ERR0_STAT_EN - Single Bit Error Status Enable On OCRAM Bank0 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN [2/2]

#define MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK)

SINGLE_ERR0_STAT_EN - Single Bit Error Status Enable On OCRAM Bank0 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN [1/2]

#define MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK)

SINGLE_ERR1_STAT_EN - Single Bit Error Status Enable On OCRAM Bank1 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN [2/2]

#define MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK)

SINGLE_ERR1_STAT_EN - Single Bit Error Status Enable On OCRAM Bank1 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN [1/2]

#define MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK)

SINGLE_ERR2_STAT_EN - Single Bit Error Status Enable On OCRAM Bank2 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN [2/2]

#define MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK)

SINGLE_ERR2_STAT_EN - Single Bit Error Status Enable On OCRAM Bank2 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN [1/2]

#define MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK)

SINGLE_ERR3_STAT_EN - Single Bit Error Status Enable On OCRAM Bank3 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN [2/2]

#define MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK)

SINGLE_ERR3_STAT_EN - Single Bit Error Status Enable On OCRAM Bank3 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN [1/2]

#define MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK)

STRB_ERR0_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank0 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN [2/2]

#define MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK)

STRB_ERR0_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank0 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN [1/2]

#define MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK)

STRB_ERR1_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank1 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN [2/2]

#define MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK)

STRB_ERR1_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank1 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN [1/2]

#define MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK)

STRB_ERR2_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank2 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN [2/2]

#define MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK)

STRB_ERR2_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank2 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN [1/2]

#define MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK)

STRB_ERR3_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank3 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN [2/2]

#define MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK)

STRB_ERR3_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank3 0b0..Disabled 0b1..Enabled

◆ MECC_ERR_STATUS_ADDR_ERR0 [1/2]

#define MECC_ERR_STATUS_ADDR_ERR0 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR0_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR0_MASK)

ADDR_ERR0 - OCRAM Access Error On Bank0 0b0..OCRAM access error does not happen on OCRAM bank0. 0b1..OCRAM access error happens on OCRAM bank0.

◆ MECC_ERR_STATUS_ADDR_ERR0 [2/2]

#define MECC_ERR_STATUS_ADDR_ERR0 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR0_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR0_MASK)

ADDR_ERR0 - OCRAM Access Error On Bank0 0b0..OCRAM access error does not happen on OCRAM bank0. 0b1..OCRAM access error happens on OCRAM bank0.

◆ MECC_ERR_STATUS_ADDR_ERR1 [1/2]

#define MECC_ERR_STATUS_ADDR_ERR1 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR1_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR1_MASK)

ADDR_ERR1 - OCRAM Access Error On Bank1 0b0..OCRAM access error does not happen on OCRAM bank1. 0b1..OCRAM access error happens on OCRAM bank1.

◆ MECC_ERR_STATUS_ADDR_ERR1 [2/2]

#define MECC_ERR_STATUS_ADDR_ERR1 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR1_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR1_MASK)

ADDR_ERR1 - OCRAM Access Error On Bank1 0b0..OCRAM access error does not happen on OCRAM bank1. 0b1..OCRAM access error happens on OCRAM bank1.

◆ MECC_ERR_STATUS_ADDR_ERR2 [1/2]

#define MECC_ERR_STATUS_ADDR_ERR2 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR2_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR2_MASK)

ADDR_ERR2 - OCRAM Access Error On Bank2 0b0..OCRAM access error does not happen on OCRAM bank2. 0b1..OCRAM access error happens on OCRAM bank2.

◆ MECC_ERR_STATUS_ADDR_ERR2 [2/2]

#define MECC_ERR_STATUS_ADDR_ERR2 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR2_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR2_MASK)

ADDR_ERR2 - OCRAM Access Error On Bank2 0b0..OCRAM access error does not happen on OCRAM bank2. 0b1..OCRAM access error happens on OCRAM bank2.

◆ MECC_ERR_STATUS_ADDR_ERR3 [1/2]

#define MECC_ERR_STATUS_ADDR_ERR3 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR3_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR3_MASK)

ADDR_ERR3 - OCRAM Access Error On Bank3 0b0..OCRAM access error does not happen on OCRAM bank3. 0b1..OCRAM access error happens on OCRAM bank3.

◆ MECC_ERR_STATUS_ADDR_ERR3 [2/2]

#define MECC_ERR_STATUS_ADDR_ERR3 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR3_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR3_MASK)

ADDR_ERR3 - OCRAM Access Error On Bank3 0b0..OCRAM access error does not happen on OCRAM bank3. 0b1..OCRAM access error happens on OCRAM bank3.

◆ MECC_ERR_STATUS_MULTI_ERR0 [1/2]

#define MECC_ERR_STATUS_MULTI_ERR0 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR0_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR0_MASK)

MULTI_ERR0 - Multiple Bits Error On OCRAM Bank0 0b0..Multiple bits error does not happen on OCRAM bank0. 0b1..Multiple bits error happens on OCRAM bank0.

◆ MECC_ERR_STATUS_MULTI_ERR0 [2/2]

#define MECC_ERR_STATUS_MULTI_ERR0 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR0_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR0_MASK)

MULTI_ERR0 - Multiple Bits Error On OCRAM Bank0 0b0..Multiple bits error does not happen on OCRAM bank0. 0b1..Multiple bits error happens on OCRAM bank0.

◆ MECC_ERR_STATUS_MULTI_ERR1 [1/2]

#define MECC_ERR_STATUS_MULTI_ERR1 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR1_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR1_MASK)

MULTI_ERR1 - Multiple Bits Error On OCRAM Bank1 0b0..Multiple bits error does not happen on OCRAM bank1. 0b1..Multiple bits error happens on OCRAM bank1.

◆ MECC_ERR_STATUS_MULTI_ERR1 [2/2]

#define MECC_ERR_STATUS_MULTI_ERR1 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR1_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR1_MASK)

MULTI_ERR1 - Multiple Bits Error On OCRAM Bank1 0b0..Multiple bits error does not happen on OCRAM bank1. 0b1..Multiple bits error happens on OCRAM bank1.

◆ MECC_ERR_STATUS_MULTI_ERR2 [1/2]

#define MECC_ERR_STATUS_MULTI_ERR2 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR2_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR2_MASK)

MULTI_ERR2 - Multiple Bits Error On OCRAM Bank2 0b0..Multiple bits error does not happen on OCRAM bank2. 0b1..Multiple bits error happens on OCRAM bank2.

◆ MECC_ERR_STATUS_MULTI_ERR2 [2/2]

#define MECC_ERR_STATUS_MULTI_ERR2 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR2_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR2_MASK)

MULTI_ERR2 - Multiple Bits Error On OCRAM Bank2 0b0..Multiple bits error does not happen on OCRAM bank2. 0b1..Multiple bits error happens on OCRAM bank2.

◆ MECC_ERR_STATUS_MULTI_ERR3 [1/2]

#define MECC_ERR_STATUS_MULTI_ERR3 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR3_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR3_MASK)

MULTI_ERR3 - Multiple Bits Error On OCRAM Bank3 0b0..Multiple bits error does not happen on OCRAM bank3. 0b1..Multiple bits error happens on OCRAM bank3.

◆ MECC_ERR_STATUS_MULTI_ERR3 [2/2]

#define MECC_ERR_STATUS_MULTI_ERR3 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR3_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR3_MASK)

MULTI_ERR3 - Multiple Bits Error On OCRAM Bank3 0b0..Multiple bits error does not happen on OCRAM bank3. 0b1..Multiple bits error happens on OCRAM bank3.

◆ MECC_ERR_STATUS_SINGLE_ERR0 [1/2]

#define MECC_ERR_STATUS_SINGLE_ERR0 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR0_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR0_MASK)

SINGLE_ERR0 - Single Bit Error On OCRAM Bank0 0b0..Single bit error does not happen on OCRAM bank0. 0b1..Single bit error happens on OCRAM bank0.

◆ MECC_ERR_STATUS_SINGLE_ERR0 [2/2]

#define MECC_ERR_STATUS_SINGLE_ERR0 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR0_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR0_MASK)

SINGLE_ERR0 - Single Bit Error On OCRAM Bank0 0b0..Single bit error does not happen on OCRAM bank0. 0b1..Single bit error happens on OCRAM bank0.

◆ MECC_ERR_STATUS_SINGLE_ERR1 [1/2]

#define MECC_ERR_STATUS_SINGLE_ERR1 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR1_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR1_MASK)

SINGLE_ERR1 - Single Bit Error On OCRAM Bank1 0b0..Single bit error does not happen on OCRAM bank1. 0b1..Single bit error happens on OCRAM bank1.

◆ MECC_ERR_STATUS_SINGLE_ERR1 [2/2]

#define MECC_ERR_STATUS_SINGLE_ERR1 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR1_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR1_MASK)

SINGLE_ERR1 - Single Bit Error On OCRAM Bank1 0b0..Single bit error does not happen on OCRAM bank1. 0b1..Single bit error happens on OCRAM bank1.

◆ MECC_ERR_STATUS_SINGLE_ERR2 [1/2]

#define MECC_ERR_STATUS_SINGLE_ERR2 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR2_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR2_MASK)

SINGLE_ERR2 - Single Bit Error On OCRAM Bank2 0b0..Single bit error does not happen on OCRAM bank2. 0b1..Single bit error happens on OCRAM bank2.

◆ MECC_ERR_STATUS_SINGLE_ERR2 [2/2]

#define MECC_ERR_STATUS_SINGLE_ERR2 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR2_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR2_MASK)

SINGLE_ERR2 - Single Bit Error On OCRAM Bank2 0b0..Single bit error does not happen on OCRAM bank2. 0b1..Single bit error happens on OCRAM bank2.

◆ MECC_ERR_STATUS_SINGLE_ERR3 [1/2]

#define MECC_ERR_STATUS_SINGLE_ERR3 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR3_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR3_MASK)

SINGLE_ERR3 - Single Bit Error On OCRAM Bank3 0b0..Single bit error does not happen on OCRAM bank3. 0b1..Single bit error happens on OCRAM bank3.

◆ MECC_ERR_STATUS_SINGLE_ERR3 [2/2]

#define MECC_ERR_STATUS_SINGLE_ERR3 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR3_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR3_MASK)

SINGLE_ERR3 - Single Bit Error On OCRAM Bank3 0b0..Single bit error does not happen on OCRAM bank3. 0b1..Single bit error happens on OCRAM bank3.

◆ MECC_ERR_STATUS_STRB_ERR0 [1/2]

#define MECC_ERR_STATUS_STRB_ERR0 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR0_SHIFT)) & MECC_ERR_STATUS_STRB_ERR0_MASK)

STRB_ERR0 - AXI Strobe Error On OCRAM Bank0 0b0..AXI strobe error does not happen on OCRAM bank0. 0b1..AXI strobe error happens on OCRAM bank0.

◆ MECC_ERR_STATUS_STRB_ERR0 [2/2]

#define MECC_ERR_STATUS_STRB_ERR0 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR0_SHIFT)) & MECC_ERR_STATUS_STRB_ERR0_MASK)

STRB_ERR0 - AXI Strobe Error On OCRAM Bank0 0b0..AXI strobe error does not happen on OCRAM bank0. 0b1..AXI strobe error happens on OCRAM bank0.

◆ MECC_ERR_STATUS_STRB_ERR1 [1/2]

#define MECC_ERR_STATUS_STRB_ERR1 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR1_SHIFT)) & MECC_ERR_STATUS_STRB_ERR1_MASK)

STRB_ERR1 - AXI Strobe Error On OCRAM Bank1 0b0..AXI strobe error does not happen on OCRAM bank1. 0b1..AXI strobe error happens on OCRAM bank1.

◆ MECC_ERR_STATUS_STRB_ERR1 [2/2]

#define MECC_ERR_STATUS_STRB_ERR1 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR1_SHIFT)) & MECC_ERR_STATUS_STRB_ERR1_MASK)

STRB_ERR1 - AXI Strobe Error On OCRAM Bank1 0b0..AXI strobe error does not happen on OCRAM bank1. 0b1..AXI strobe error happens on OCRAM bank1.

◆ MECC_ERR_STATUS_STRB_ERR2 [1/2]

#define MECC_ERR_STATUS_STRB_ERR2 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR2_SHIFT)) & MECC_ERR_STATUS_STRB_ERR2_MASK)

STRB_ERR2 - AXI Strobe Error On OCRAM Bank2 0b0..AXI strobe error does not happen on OCRAM bank2. 0b1..AXI strobe error happens on OCRAM bank2.

◆ MECC_ERR_STATUS_STRB_ERR2 [2/2]

#define MECC_ERR_STATUS_STRB_ERR2 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR2_SHIFT)) & MECC_ERR_STATUS_STRB_ERR2_MASK)

STRB_ERR2 - AXI Strobe Error On OCRAM Bank2 0b0..AXI strobe error does not happen on OCRAM bank2. 0b1..AXI strobe error happens on OCRAM bank2.

◆ MECC_ERR_STATUS_STRB_ERR3 [1/2]

#define MECC_ERR_STATUS_STRB_ERR3 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR3_SHIFT)) & MECC_ERR_STATUS_STRB_ERR3_MASK)

STRB_ERR3 - AXI Strobe Error On OCRAM Bank3 0b0..AXI strobe error does not happen on OCRAM bank3. 0b1..AXI strobe error happens on OCRAM bank3.

◆ MECC_ERR_STATUS_STRB_ERR3 [2/2]

#define MECC_ERR_STATUS_STRB_ERR3 ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR3_SHIFT)) & MECC_ERR_STATUS_STRB_ERR3_MASK)

STRB_ERR3 - AXI Strobe Error On OCRAM Bank3 0b0..AXI strobe error does not happen on OCRAM bank3. 0b1..AXI strobe error happens on OCRAM bank3.

◆ MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR [1/2]

#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_MASK)

MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank0

◆ MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR [2/2]

#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_MASK)

MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank0

◆ MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC [1/2]

#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_MASK)

MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank0

◆ MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC [2/2]

#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_MASK)

MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank0

◆ MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR [1/2]

#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_MASK)

MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank1

◆ MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR [2/2]

#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_MASK)

MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank1

◆ MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC [1/2]

#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_MASK)

MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank1

◆ MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC [2/2]

#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_MASK)

MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank1

◆ MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR [1/2]

#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_MASK)

MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank2

◆ MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR [2/2]

#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_MASK)

MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank2

◆ MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC [1/2]

#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_MASK)

MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank2

◆ MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC [2/2]

#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_MASK)

MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank2

◆ MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR [1/2]

#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_MASK)

MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank3

◆ MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR [2/2]

#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_MASK)

MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank3

◆ MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC [1/2]

#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_MASK)

MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank3

◆ MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC [2/2]

#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_MASK)

MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank3

◆ MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA [1/2]

#define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_MASK)

MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0

◆ MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA [2/2]

#define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_MASK)

MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0

◆ MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA [1/2]

#define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_MASK)

MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1

◆ MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA [2/2]

#define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_MASK)

MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1

◆ MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA [1/2]

#define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_MASK)

MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2

◆ MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA [2/2]

#define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_MASK)

MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2

◆ MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA [1/2]

#define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_MASK)

MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3

◆ MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA [2/2]

#define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_MASK)

MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3

◆ MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA [1/2]

#define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_MASK)

MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank0

◆ MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA [2/2]

#define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_MASK)

MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank0

◆ MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA [1/2]

#define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_MASK)

MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank1

◆ MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA [2/2]

#define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_MASK)

MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank1

◆ MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA [1/2]

#define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_MASK)

MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank2

◆ MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA [2/2]

#define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_MASK)

MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank2

◆ MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA [1/2]

#define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_MASK)

MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank3

◆ MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA [2/2]

#define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_MASK)

MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank3

◆ MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING [1/2]

#define MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_MASK)

READ_ADDR_PIPE_PENDING - Read Address Pipeline Pending 0b0..No update pending status for READ_ADDR_PIPE_EN. 0b1..When READ_ADDR_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.

◆ MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING [2/2]

#define MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_MASK)

READ_ADDR_PIPE_PENDING - Read Address Pipeline Pending 0b0..No update pending status for READ_ADDR_PIPE_EN. 0b1..When READ_ADDR_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.

◆ MECC_PENDING_STAT_READ_DATA_WAIT_PENDING [1/2]

#define MECC_PENDING_STAT_READ_DATA_WAIT_PENDING ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_SHIFT)) & MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_MASK)

READ_DATA_WAIT_PENDING - Read Data Wait Pending 0b0..No update pending status for READ_DATA_WAIT_EN. 0b1..When READ_DATA_WAIT_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.

◆ MECC_PENDING_STAT_READ_DATA_WAIT_PENDING [2/2]

#define MECC_PENDING_STAT_READ_DATA_WAIT_PENDING ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_SHIFT)) & MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_MASK)

READ_DATA_WAIT_PENDING - Read Data Wait Pending 0b0..No update pending status for READ_DATA_WAIT_EN. 0b1..When READ_DATA_WAIT_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.

◆ MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING [1/2]

#define MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_MASK)

WRITE_ADDR_PIPE_PENDING - Write Address Pipeline Pending 0b0..No update pending status for WRITE_ADDR_PIPE_EN. 0b1..When WRITE_ADDR_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.

◆ MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING [2/2]

#define MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_MASK)

WRITE_ADDR_PIPE_PENDING - Write Address Pipeline Pending 0b0..No update pending status for WRITE_ADDR_PIPE_EN. 0b1..When WRITE_ADDR_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.

◆ MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING [1/2]

#define MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_MASK)

WRITE_DATA_PIPE_PENDING - Write Data Pipeline Pending 0b0..No update pending status for WRITE_DATA_PIPE_EN. 0b1..When WRITE_DATA_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.

◆ MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING [2/2]

#define MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_MASK)

WRITE_DATA_PIPE_PENDING - Write Data Pipeline Pending 0b0..No update pending status for WRITE_DATA_PIPE_EN. 0b1..When WRITE_DATA_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.

◆ MECC_PIPE_ECC_EN_ECC_EN [1/2]

#define MECC_PIPE_ECC_EN_ECC_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_ECC_EN_SHIFT)) & MECC_PIPE_ECC_EN_ECC_EN_MASK)

ECC_EN - ECC Function Enable 0b0..Disable. 0b1..Enable.

◆ MECC_PIPE_ECC_EN_ECC_EN [2/2]

#define MECC_PIPE_ECC_EN_ECC_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_ECC_EN_SHIFT)) & MECC_PIPE_ECC_EN_ECC_EN_MASK)

ECC_EN - ECC Function Enable 0b0..Disable. 0b1..Enable.

◆ MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN [1/2]

#define MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_MASK)

READ_ADDR_PIPE_EN - Read Address Pipeline Enable 0b0..Disable. 0b1..Enable.

◆ MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN [2/2]

#define MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_MASK)

READ_ADDR_PIPE_EN - Read Address Pipeline Enable 0b0..Disable. 0b1..Enable.

◆ MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN [1/2]

#define MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_SHIFT)) & MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_MASK)

READ_DATA_WAIT_EN - Read Data Wait Enable 0b0..Disable. 0b1..Enable.

◆ MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN [2/2]

#define MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_SHIFT)) & MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_MASK)

READ_DATA_WAIT_EN - Read Data Wait Enable 0b0..Disable. 0b1..Enable.

◆ MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN [1/2]

#define MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_MASK)

WRITE_ADDR_PIPE_EN - Write Address Pipeline Enable 0b0..Disable. 0b1..Enable.

◆ MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN [2/2]

#define MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_MASK)

WRITE_ADDR_PIPE_EN - Write Address Pipeline Enable 0b0..Disable. 0b1..Enable.

◆ MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN [1/2]

#define MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_MASK)

WRITE_DATA_PIPE_EN - Write Data Pipeline Enable 0b0..Disable. 0b1..Enable.

◆ MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN [2/2]

#define MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_MASK)

WRITE_DATA_PIPE_EN - Write Data Pipeline Enable 0b0..Disable. 0b1..Enable.

◆ MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR [1/2]

#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_MASK)

SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank0

◆ MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR [2/2]

#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_MASK)

SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank0

◆ MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC [1/2]

#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_MASK)

SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank0

◆ MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC [2/2]

#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_MASK)

SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank0

◆ MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR [1/2]

#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_MASK)

SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank1

◆ MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR [2/2]

#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_MASK)

SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank1

◆ MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC [1/2]

#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_MASK)

SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank1

◆ MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC [2/2]

#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_MASK)

SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank1

◆ MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR [1/2]

#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_MASK)

SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank2

◆ MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR [2/2]

#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_MASK)

SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank2

◆ MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC [1/2]

#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_MASK)

SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank2

◆ MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC [2/2]

#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_MASK)

SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank2

◆ MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR [1/2]

#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_MASK)

SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank3

◆ MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR [2/2]

#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_MASK)

SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank3

◆ MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC [1/2]

#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_MASK)

SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank3

◆ MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC [2/2]

#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_MASK)

SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank3

◆ MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA [1/2]

#define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank0

◆ MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA [2/2]

#define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank0

◆ MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA [1/2]

#define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank1

◆ MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA [2/2]

#define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank1

◆ MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA [1/2]

#define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank2

◆ MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA [2/2]

#define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank2

◆ MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA [1/2]

#define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank3

◆ MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA [2/2]

#define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank3

◆ MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA [1/2]

#define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank0

◆ MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA [2/2]

#define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank0

◆ MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA [1/2]

#define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank1

◆ MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA [2/2]

#define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank1

◆ MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA [1/2]

#define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank2

◆ MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA [2/2]

#define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank2

◆ MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA [1/2]

#define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank3

◆ MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA [2/2]

#define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_MASK)

SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank3

◆ MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS [1/2]

#define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_MASK)

SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank0

◆ MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS [2/2]

#define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_MASK)

SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank0

◆ MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS [1/2]

#define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_MASK)

SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank1

◆ MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS [2/2]

#define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_MASK)

SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank1

◆ MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS [1/2]

#define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_MASK)

SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank2

◆ MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS [2/2]

#define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_MASK)

SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank2

◆ MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS [1/2]

#define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_MASK)

SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank3

◆ MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS [2/2]

#define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_MASK)

SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank3

◆ MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS [1/2]

#define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_MASK)

SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank0

◆ MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS [2/2]

#define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_MASK)

SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank0

◆ MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS [1/2]

#define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_MASK)

SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank1

◆ MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS [2/2]

#define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_MASK)

SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank1

◆ MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS [1/2]

#define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_MASK)

SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank2

◆ MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS [2/2]

#define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_MASK)

SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank2

◆ MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS [1/2]

#define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_MASK)

SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank3

◆ MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS [2/2]

#define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS ( x ) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_MASK)

SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank3

◆ XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN [1/2]

#define XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_SHIFT)) & XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_MASK)

MULTI_ERR_SIG_EN - Multiple Bits Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN [2/2]

#define XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_SHIFT)) & XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_MASK)

MULTI_ERR_SIG_EN - Multiple Bits Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ XECC_ERR_SIG_EN_Reserved1 [1/2]

#define XECC_ERR_SIG_EN_Reserved1 ( x ) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_Reserved1_SHIFT)) & XECC_ERR_SIG_EN_Reserved1_MASK)

Reserved1 - Reserved

◆ XECC_ERR_SIG_EN_Reserved1 [2/2]

#define XECC_ERR_SIG_EN_Reserved1 ( x ) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_Reserved1_SHIFT)) & XECC_ERR_SIG_EN_Reserved1_MASK)

Reserved1 - Reserved

◆ XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN [1/2]

#define XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_SHIFT)) & XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_MASK)

SINGLE_ERR_SIG_EN - Single Bit Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN [2/2]

#define XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_SHIFT)) & XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_MASK)

SINGLE_ERR_SIG_EN - Single Bit Error Interrupt Enable 0b0..Masked 0b1..Enabled

◆ XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN [1/2]

#define XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_SHIFT)) & XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_MASK)

MULIT_ERR_STAT_EN - Multiple Bits Error Status Enable 0b0..Masked 0b1..Enabled

◆ XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN [2/2]

#define XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_SHIFT)) & XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_MASK)

MULIT_ERR_STAT_EN - Multiple Bits Error Status Enable 0b0..Masked 0b1..Enabled

◆ XECC_ERR_STAT_EN_Reserved1 [1/2]

#define XECC_ERR_STAT_EN_Reserved1 ( x ) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_Reserved1_SHIFT)) & XECC_ERR_STAT_EN_Reserved1_MASK)

Reserved1 - Reserved

◆ XECC_ERR_STAT_EN_Reserved1 [2/2]

#define XECC_ERR_STAT_EN_Reserved1 ( x ) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_Reserved1_SHIFT)) & XECC_ERR_STAT_EN_Reserved1_MASK)

Reserved1 - Reserved

◆ XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN [1/2]

#define XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_SHIFT)) & XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_MASK)

SINGLE_ERR_STAT_EN - Single Bit Error Status Enable 0b0..Masked 0b1..Enabled

◆ XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN [2/2]

#define XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_SHIFT)) & XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_MASK)

SINGLE_ERR_STAT_EN - Single Bit Error Status Enable 0b0..Masked 0b1..Enabled

◆ XECC_ERR_STATUS_MULTI_ERR [1/2]

#define XECC_ERR_STATUS_MULTI_ERR ( x ) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_MULTI_ERR_SHIFT)) & XECC_ERR_STATUS_MULTI_ERR_MASK)

MULTI_ERR - Multiple Bits Error 0b0..Multiple bits error does not happen. 0b1..Multiple bits error happens.

◆ XECC_ERR_STATUS_MULTI_ERR [2/2]

#define XECC_ERR_STATUS_MULTI_ERR ( x ) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_MULTI_ERR_SHIFT)) & XECC_ERR_STATUS_MULTI_ERR_MASK)

MULTI_ERR - Multiple Bits Error 0b0..Multiple bits error does not happen. 0b1..Multiple bits error happens.

◆ XECC_ERR_STATUS_Reserved1 [1/2]

#define XECC_ERR_STATUS_Reserved1 ( x ) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_Reserved1_SHIFT)) & XECC_ERR_STATUS_Reserved1_MASK)

Reserved1 - Reserved

◆ XECC_ERR_STATUS_Reserved1 [2/2]

#define XECC_ERR_STATUS_Reserved1 ( x ) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_Reserved1_SHIFT)) & XECC_ERR_STATUS_Reserved1_MASK)

Reserved1 - Reserved

◆ XECC_ERR_STATUS_SINGLE_ERR [1/2]

#define XECC_ERR_STATUS_SINGLE_ERR ( x ) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_SINGLE_ERR_SHIFT)) & XECC_ERR_STATUS_SINGLE_ERR_MASK)

SINGLE_ERR - Single Bit Error 0b0..Single bit error does not happen. 0b1..Single bit error happens.

◆ XECC_ERR_STATUS_SINGLE_ERR [2/2]

#define XECC_ERR_STATUS_SINGLE_ERR ( x ) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_SINGLE_ERR_SHIFT)) & XECC_ERR_STATUS_SINGLE_ERR_MASK)

SINGLE_ERR - Single Bit Error 0b0..Single bit error does not happen. 0b1..Single bit error happens.

ERR_STATUS - Error Interrupt Status Register

ERR_STAT_EN - Error Interrupt Status Enable Register

ERR_SIG_EN - Error Interrupt Enable Register

ERR_DATA_INJ_LOW0 - Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data

ERR_DATA_INJ_HIGH0 - Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data

ERR_ECC_INJ0 - Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data

ERR_DATA_INJ_LOW1 - Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data

ERR_DATA_INJ_HIGH1 - Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data

ERR_ECC_INJ1 - Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data

ERR_DATA_INJ_LOW2 - Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data

ERR_DATA_INJ_HIGH2 - Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data

ERR_ECC_INJ2 - Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data

ERR_DATA_INJ_LOW3 - Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data

ERR_DATA_INJ_HIGH3 - Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data

ERR_ECC_INJ3 - Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data

SINGLE_ERR_ADDR_ECC0 - Single Error Address And ECC code On OCRAM Bank0

SINGLE_ERR_DATA_LOW0 - LOW 32 Bits Single Error Read Data On OCRAM Bank0

SINGLE_ERR_DATA_HIGH0 - HIGH 32 Bits Single Error Read Data On OCRAM Bank0

SINGLE_ERR_POS_LOW0 - LOW Single Error Bit Position On OCRAM Bank0

SINGLE_ERR_POS_HIGH0 - HIGH Single Error Bit Position On OCRAM Bank0

SINGLE_ERR_ADDR_ECC1 - Single Error Address And ECC code On OCRAM Bank1

SINGLE_ERR_DATA_LOW1 - LOW 32 Bits Single Error Read Data On OCRAM Bank1

SINGLE_ERR_DATA_HIGH1 - HIGH 32 Bits Single Error Read Data On OCRAM Bank1

SINGLE_ERR_POS_LOW1 - LOW Single Error Bit Position On OCRAM Bank1

SINGLE_ERR_POS_HIGH1 - HIGH Single Error Bit Position On OCRAM Bank1

SINGLE_ERR_ADDR_ECC2 - Single Error Address And ECC code On OCRAM Bank2

SINGLE_ERR_DATA_LOW2 - LOW 32 Bits Single Error Read Data On OCRAM Bank2

SINGLE_ERR_DATA_HIGH2 - HIGH 32 Bits Single Error Read Data On OCRAM Bank2

SINGLE_ERR_POS_LOW2 - LOW Single Error Bit Position On OCRAM Bank2

SINGLE_ERR_POS_HIGH2 - HIGH Single Error Bit Position On OCRAM Bank2

SINGLE_ERR_ADDR_ECC3 - Single Error Address And ECC code On OCRAM Bank3

SINGLE_ERR_DATA_LOW3 - LOW 32 Bits Single Error Read Data On OCRAM Bank3

SINGLE_ERR_DATA_HIGH3 - HIGH 32 Bits Single Error Read Data On OCRAM Bank3

SINGLE_ERR_POS_LOW3 - LOW Single Error Bit Position On OCRAM Bank3

SINGLE_ERR_POS_HIGH3 - HIGH Single Error Bit Position On OCRAM Bank3

MULTI_ERR_ADDR_ECC0 - Multiple Error Address And ECC code On OCRAM Bank0

MULTI_ERR_DATA_LOW0 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank0

MULTI_ERR_DATA_HIGH0 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0

MULTI_ERR_ADDR_ECC1 - Multiple Error Address And ECC code On OCRAM Bank1

MULTI_ERR_DATA_LOW1 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank1

MULTI_ERR_DATA_HIGH1 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1

MULTI_ERR_ADDR_ECC2 - Multiple Error Address And ECC code On OCRAM Bank2

MULTI_ERR_DATA_LOW2 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank2

MULTI_ERR_DATA_HIGH2 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2

MULTI_ERR_ADDR_ECC3 - Multiple Error Address And ECC code On OCRAM Bank3

MULTI_ERR_DATA_LOW3 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank3

MULTI_ERR_DATA_HIGH3 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3

PIPE_ECC_EN - OCRAM Pipeline And ECC Enable

PENDING_STAT - Pending Status

ERR_STATUS - Error Interrupt Status Register

ERR_STAT_EN - Error Interrupt Status Enable Register

ERR_SIG_EN - Error Interrupt Enable Register

ERR_DATA_INJ_LOW0 - Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data

ERR_DATA_INJ_HIGH0 - Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data

ERR_ECC_INJ0 - Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data

ERR_DATA_INJ_LOW1 - Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data

ERR_DATA_INJ_HIGH1 - Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data

ERR_ECC_INJ1 - Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data

ERR_DATA_INJ_LOW2 - Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data

ERR_DATA_INJ_HIGH2 - Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data

ERR_ECC_INJ2 - Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data

ERR_DATA_INJ_LOW3 - Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data

ERR_DATA_INJ_HIGH3 - Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data

ERR_ECC_INJ3 - Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data

SINGLE_ERR_ADDR_ECC0 - Single Error Address And ECC code On OCRAM Bank0

SINGLE_ERR_DATA_LOW0 - LOW 32 Bits Single Error Read Data On OCRAM Bank0

SINGLE_ERR_DATA_HIGH0 - HIGH 32 Bits Single Error Read Data On OCRAM Bank0

SINGLE_ERR_POS_LOW0 - LOW Single Error Bit Position On OCRAM Bank0

SINGLE_ERR_POS_HIGH0 - HIGH Single Error Bit Position On OCRAM Bank0

SINGLE_ERR_ADDR_ECC1 - Single Error Address And ECC code On OCRAM Bank1

SINGLE_ERR_DATA_LOW1 - LOW 32 Bits Single Error Read Data On OCRAM Bank1

SINGLE_ERR_DATA_HIGH1 - HIGH 32 Bits Single Error Read Data On OCRAM Bank1

SINGLE_ERR_POS_LOW1 - LOW Single Error Bit Position On OCRAM Bank1

SINGLE_ERR_POS_HIGH1 - HIGH Single Error Bit Position On OCRAM Bank1

SINGLE_ERR_ADDR_ECC2 - Single Error Address And ECC code On OCRAM Bank2

SINGLE_ERR_DATA_LOW2 - LOW 32 Bits Single Error Read Data On OCRAM Bank2

SINGLE_ERR_DATA_HIGH2 - HIGH 32 Bits Single Error Read Data On OCRAM Bank2

SINGLE_ERR_POS_LOW2 - LOW Single Error Bit Position On OCRAM Bank2

SINGLE_ERR_POS_HIGH2 - HIGH Single Error Bit Position On OCRAM Bank2

SINGLE_ERR_ADDR_ECC3 - Single Error Address And ECC code On OCRAM Bank3