VERID - Version ID Register
#define	LPI2C_VERID_FEATURE_MASK (0xFFFFU)

#define	LPI2C_VERID_FEATURE_SHIFT (0U)

#define	LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)

#define	LPI2C_VERID_MINOR_MASK (0xFF0000U)

#define	LPI2C_VERID_MINOR_SHIFT (16U)

#define	LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)

#define	LPI2C_VERID_MAJOR_MASK (0xFF000000U)

#define	LPI2C_VERID_MAJOR_SHIFT (24U)

#define	LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)

PARAM - Parameter Register
#define	LPI2C_PARAM_MTXFIFO_MASK (0xFU)

#define	LPI2C_PARAM_MTXFIFO_SHIFT (0U)

#define	LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)

#define	LPI2C_PARAM_MRXFIFO_MASK (0xF00U)

#define	LPI2C_PARAM_MRXFIFO_SHIFT (8U)

#define	LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)

MCR - Master Control Register
#define	LPI2C_MCR_MEN_MASK (0x1U)

#define	LPI2C_MCR_MEN_SHIFT (0U)

#define	LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)

#define	LPI2C_MCR_RST_MASK (0x2U)

#define	LPI2C_MCR_RST_SHIFT (1U)

#define	LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)

#define	LPI2C_MCR_DOZEN_MASK (0x4U)

#define	LPI2C_MCR_DOZEN_SHIFT (2U)

#define	LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)

#define	LPI2C_MCR_DBGEN_MASK (0x8U)

#define	LPI2C_MCR_DBGEN_SHIFT (3U)

#define	LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)

#define	LPI2C_MCR_RTF_MASK (0x100U)

#define	LPI2C_MCR_RTF_SHIFT (8U)

#define	LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)

#define	LPI2C_MCR_RRF_MASK (0x200U)

#define	LPI2C_MCR_RRF_SHIFT (9U)

#define	LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)

MSR - Master Status Register
#define	LPI2C_MSR_TDF_MASK (0x1U)

#define	LPI2C_MSR_TDF_SHIFT (0U)

#define	LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)

#define	LPI2C_MSR_RDF_MASK (0x2U)

#define	LPI2C_MSR_RDF_SHIFT (1U)

#define	LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)

#define	LPI2C_MSR_EPF_MASK (0x100U)

#define	LPI2C_MSR_EPF_SHIFT (8U)

#define	LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)

#define	LPI2C_MSR_SDF_MASK (0x200U)

#define	LPI2C_MSR_SDF_SHIFT (9U)

#define	LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)

#define	LPI2C_MSR_NDF_MASK (0x400U)

#define	LPI2C_MSR_NDF_SHIFT (10U)

#define	LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)

#define	LPI2C_MSR_ALF_MASK (0x800U)

#define	LPI2C_MSR_ALF_SHIFT (11U)

#define	LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)

#define	LPI2C_MSR_FEF_MASK (0x1000U)

#define	LPI2C_MSR_FEF_SHIFT (12U)

#define	LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)

#define	LPI2C_MSR_PLTF_MASK (0x2000U)

#define	LPI2C_MSR_PLTF_SHIFT (13U)

#define	LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)

#define	LPI2C_MSR_DMF_MASK (0x4000U)

#define	LPI2C_MSR_DMF_SHIFT (14U)

#define	LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)

#define	LPI2C_MSR_MBF_MASK (0x1000000U)

#define	LPI2C_MSR_MBF_SHIFT (24U)

#define	LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)

#define	LPI2C_MSR_BBF_MASK (0x2000000U)

#define	LPI2C_MSR_BBF_SHIFT (25U)

#define	LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)

MIER - Master Interrupt Enable Register
#define	LPI2C_MIER_TDIE_MASK (0x1U)

#define	LPI2C_MIER_TDIE_SHIFT (0U)

#define	LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)

#define	LPI2C_MIER_RDIE_MASK (0x2U)

#define	LPI2C_MIER_RDIE_SHIFT (1U)

#define	LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)

#define	LPI2C_MIER_EPIE_MASK (0x100U)

#define	LPI2C_MIER_EPIE_SHIFT (8U)

#define	LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)

#define	LPI2C_MIER_SDIE_MASK (0x200U)

#define	LPI2C_MIER_SDIE_SHIFT (9U)

#define	LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)

#define	LPI2C_MIER_NDIE_MASK (0x400U)

#define	LPI2C_MIER_NDIE_SHIFT (10U)

#define	LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)

#define	LPI2C_MIER_ALIE_MASK (0x800U)

#define	LPI2C_MIER_ALIE_SHIFT (11U)

#define	LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)

#define	LPI2C_MIER_FEIE_MASK (0x1000U)

#define	LPI2C_MIER_FEIE_SHIFT (12U)

#define	LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)

#define	LPI2C_MIER_PLTIE_MASK (0x2000U)

#define	LPI2C_MIER_PLTIE_SHIFT (13U)

#define	LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)

#define	LPI2C_MIER_DMIE_MASK (0x4000U)

#define	LPI2C_MIER_DMIE_SHIFT (14U)

#define	LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)

MDER - Master DMA Enable Register
#define	LPI2C_MDER_TDDE_MASK (0x1U)

#define	LPI2C_MDER_TDDE_SHIFT (0U)

#define	LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)

#define	LPI2C_MDER_RDDE_MASK (0x2U)

#define	LPI2C_MDER_RDDE_SHIFT (1U)

#define	LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)

MCFGR0 - Master Configuration Register 0
#define	LPI2C_MCFGR0_HREN_MASK (0x1U)

#define	LPI2C_MCFGR0_HREN_SHIFT (0U)

#define	LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)

#define	LPI2C_MCFGR0_HRPOL_MASK (0x2U)

#define	LPI2C_MCFGR0_HRPOL_SHIFT (1U)

#define	LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)

#define	LPI2C_MCFGR0_HRSEL_MASK (0x4U)

#define	LPI2C_MCFGR0_HRSEL_SHIFT (2U)

#define	LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)

#define	LPI2C_MCFGR0_CIRFIFO_MASK (0x100U)

#define	LPI2C_MCFGR0_CIRFIFO_SHIFT (8U)

#define	LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)

#define	LPI2C_MCFGR0_RDMO_MASK (0x200U)

#define	LPI2C_MCFGR0_RDMO_SHIFT (9U)

#define	LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)

MCFGR1 - Master Configuration Register 1
#define	LPI2C_MCFGR1_PRESCALE_MASK (0x7U)

#define	LPI2C_MCFGR1_PRESCALE_SHIFT (0U)

#define	LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)

#define	LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U)

#define	LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U)

#define	LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)

#define	LPI2C_MCFGR1_IGNACK_MASK (0x200U)

#define	LPI2C_MCFGR1_IGNACK_SHIFT (9U)

#define	LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)

#define	LPI2C_MCFGR1_TIMECFG_MASK (0x400U)

#define	LPI2C_MCFGR1_TIMECFG_SHIFT (10U)

#define	LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)

#define	LPI2C_MCFGR1_MATCFG_MASK (0x70000U)

#define	LPI2C_MCFGR1_MATCFG_SHIFT (16U)

#define	LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)

#define	LPI2C_MCFGR1_PINCFG_MASK (0x7000000U)

#define	LPI2C_MCFGR1_PINCFG_SHIFT (24U)

#define	LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)

MCFGR2 - Master Configuration Register 2
#define	LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU)

#define	LPI2C_MCFGR2_BUSIDLE_SHIFT (0U)

#define	LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)

#define	LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U)

#define	LPI2C_MCFGR2_FILTSCL_SHIFT (16U)

#define	LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)

#define	LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U)

#define	LPI2C_MCFGR2_FILTSDA_SHIFT (24U)

#define	LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)

MCFGR3 - Master Configuration Register 3
#define	LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U)

#define	LPI2C_MCFGR3_PINLOW_SHIFT (8U)

#define	LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)

MDMR - Master Data Match Register
#define	LPI2C_MDMR_MATCH0_MASK (0xFFU)

#define	LPI2C_MDMR_MATCH0_SHIFT (0U)

#define	LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)

#define	LPI2C_MDMR_MATCH1_MASK (0xFF0000U)

#define	LPI2C_MDMR_MATCH1_SHIFT (16U)

#define	LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)

MCCR0 - Master Clock Configuration Register 0
#define	LPI2C_MCCR0_CLKLO_MASK (0x3FU)

#define	LPI2C_MCCR0_CLKLO_SHIFT (0U)

#define	LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)

#define	LPI2C_MCCR0_CLKHI_MASK (0x3F00U)

#define	LPI2C_MCCR0_CLKHI_SHIFT (8U)

#define	LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)

#define	LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U)

#define	LPI2C_MCCR0_SETHOLD_SHIFT (16U)

#define	LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)

#define	LPI2C_MCCR0_DATAVD_MASK (0x3F000000U)

#define	LPI2C_MCCR0_DATAVD_SHIFT (24U)

#define	LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)

MCCR1 - Master Clock Configuration Register 1
#define	LPI2C_MCCR1_CLKLO_MASK (0x3FU)

#define	LPI2C_MCCR1_CLKLO_SHIFT (0U)

#define	LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)

#define	LPI2C_MCCR1_CLKHI_MASK (0x3F00U)

#define	LPI2C_MCCR1_CLKHI_SHIFT (8U)

#define	LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)

#define	LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U)

#define	LPI2C_MCCR1_SETHOLD_SHIFT (16U)

#define	LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)

#define	LPI2C_MCCR1_DATAVD_MASK (0x3F000000U)

#define	LPI2C_MCCR1_DATAVD_SHIFT (24U)

#define	LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)

MFCR - Master FIFO Control Register
#define	LPI2C_MFCR_TXWATER_MASK (0x3U)

#define	LPI2C_MFCR_TXWATER_SHIFT (0U)

#define	LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)

#define	LPI2C_MFCR_RXWATER_MASK (0x30000U)

#define	LPI2C_MFCR_RXWATER_SHIFT (16U)

#define	LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)

MFSR - Master FIFO Status Register
#define	LPI2C_MFSR_TXCOUNT_MASK (0x7U)

#define	LPI2C_MFSR_TXCOUNT_SHIFT (0U)

#define	LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)

#define	LPI2C_MFSR_RXCOUNT_MASK (0x70000U)

#define	LPI2C_MFSR_RXCOUNT_SHIFT (16U)

#define	LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)

MTDR - Master Transmit Data Register
#define	LPI2C_MTDR_DATA_MASK (0xFFU)

#define	LPI2C_MTDR_DATA_SHIFT (0U)

#define	LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)

#define	LPI2C_MTDR_CMD_MASK (0x700U)

#define	LPI2C_MTDR_CMD_SHIFT (8U)

#define	LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)

MRDR - Master Receive Data Register
#define	LPI2C_MRDR_DATA_MASK (0xFFU)

#define	LPI2C_MRDR_DATA_SHIFT (0U)

#define	LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)

#define	LPI2C_MRDR_RXEMPTY_MASK (0x4000U)

#define	LPI2C_MRDR_RXEMPTY_SHIFT (14U)

#define	LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)

SCR - Slave Control Register
#define	LPI2C_SCR_SEN_MASK (0x1U)

#define	LPI2C_SCR_SEN_SHIFT (0U)

#define	LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)

#define	LPI2C_SCR_RST_MASK (0x2U)

#define	LPI2C_SCR_RST_SHIFT (1U)

#define	LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)

#define	LPI2C_SCR_FILTEN_MASK (0x10U)

#define	LPI2C_SCR_FILTEN_SHIFT (4U)

#define	LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)

#define	LPI2C_SCR_FILTDZ_MASK (0x20U)

#define	LPI2C_SCR_FILTDZ_SHIFT (5U)

#define	LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)

#define	LPI2C_SCR_RTF_MASK (0x100U)

#define	LPI2C_SCR_RTF_SHIFT (8U)

#define	LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)

#define	LPI2C_SCR_RRF_MASK (0x200U)

#define	LPI2C_SCR_RRF_SHIFT (9U)

#define	LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)

SSR - Slave Status Register
#define	LPI2C_SSR_TDF_MASK (0x1U)

#define	LPI2C_SSR_TDF_SHIFT (0U)

#define	LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)

#define	LPI2C_SSR_RDF_MASK (0x2U)

#define	LPI2C_SSR_RDF_SHIFT (1U)

#define	LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)

#define	LPI2C_SSR_AVF_MASK (0x4U)

#define	LPI2C_SSR_AVF_SHIFT (2U)

#define	LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)

#define	LPI2C_SSR_TAF_MASK (0x8U)

#define	LPI2C_SSR_TAF_SHIFT (3U)

#define	LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)

#define	LPI2C_SSR_RSF_MASK (0x100U)

#define	LPI2C_SSR_RSF_SHIFT (8U)

#define	LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)

#define	LPI2C_SSR_SDF_MASK (0x200U)

#define	LPI2C_SSR_SDF_SHIFT (9U)

#define	LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)

#define	LPI2C_SSR_BEF_MASK (0x400U)

#define	LPI2C_SSR_BEF_SHIFT (10U)

#define	LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)

#define	LPI2C_SSR_FEF_MASK (0x800U)

#define	LPI2C_SSR_FEF_SHIFT (11U)

#define	LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)

#define	LPI2C_SSR_AM0F_MASK (0x1000U)

#define	LPI2C_SSR_AM0F_SHIFT (12U)

#define	LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)

#define	LPI2C_SSR_AM1F_MASK (0x2000U)

#define	LPI2C_SSR_AM1F_SHIFT (13U)

#define	LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)

#define	LPI2C_SSR_GCF_MASK (0x4000U)

#define	LPI2C_SSR_GCF_SHIFT (14U)

#define	LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)

#define	LPI2C_SSR_SARF_MASK (0x8000U)

#define	LPI2C_SSR_SARF_SHIFT (15U)

#define	LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)

#define	LPI2C_SSR_SBF_MASK (0x1000000U)

#define	LPI2C_SSR_SBF_SHIFT (24U)

#define	LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)

#define	LPI2C_SSR_BBF_MASK (0x2000000U)

#define	LPI2C_SSR_BBF_SHIFT (25U)

#define	LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)

SIER - Slave Interrupt Enable Register
#define	LPI2C_SIER_TDIE_MASK (0x1U)

#define	LPI2C_SIER_TDIE_SHIFT (0U)

#define	LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)

#define	LPI2C_SIER_RDIE_MASK (0x2U)

#define	LPI2C_SIER_RDIE_SHIFT (1U)

#define	LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)

#define	LPI2C_SIER_AVIE_MASK (0x4U)

#define	LPI2C_SIER_AVIE_SHIFT (2U)

#define	LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)

#define	LPI2C_SIER_TAIE_MASK (0x8U)

#define	LPI2C_SIER_TAIE_SHIFT (3U)

#define	LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)

#define	LPI2C_SIER_RSIE_MASK (0x100U)

#define	LPI2C_SIER_RSIE_SHIFT (8U)

#define	LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)

#define	LPI2C_SIER_SDIE_MASK (0x200U)

#define	LPI2C_SIER_SDIE_SHIFT (9U)

#define	LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)

#define	LPI2C_SIER_BEIE_MASK (0x400U)

#define	LPI2C_SIER_BEIE_SHIFT (10U)

#define	LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)

#define	LPI2C_SIER_FEIE_MASK (0x800U)

#define	LPI2C_SIER_FEIE_SHIFT (11U)

#define	LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)

#define	LPI2C_SIER_AM0IE_MASK (0x1000U)

#define	LPI2C_SIER_AM0IE_SHIFT (12U)

#define	LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)

#define	LPI2C_SIER_AM1F_MASK (0x2000U)

#define	LPI2C_SIER_AM1F_SHIFT (13U)

#define	LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)

#define	LPI2C_SIER_GCIE_MASK (0x4000U)

#define	LPI2C_SIER_GCIE_SHIFT (14U)

#define	LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)

#define	LPI2C_SIER_SARIE_MASK (0x8000U)

#define	LPI2C_SIER_SARIE_SHIFT (15U)

#define	LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)

SDER - Slave DMA Enable Register
#define	LPI2C_SDER_TDDE_MASK (0x1U)

#define	LPI2C_SDER_TDDE_SHIFT (0U)

#define	LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)

#define	LPI2C_SDER_RDDE_MASK (0x2U)

#define	LPI2C_SDER_RDDE_SHIFT (1U)

#define	LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)

#define	LPI2C_SDER_AVDE_MASK (0x4U)

#define	LPI2C_SDER_AVDE_SHIFT (2U)

#define	LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)

SCFGR1 - Slave Configuration Register 1
#define	LPI2C_SCFGR1_ADRSTALL_MASK (0x1U)

#define	LPI2C_SCFGR1_ADRSTALL_SHIFT (0U)

#define	LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)

#define	LPI2C_SCFGR1_RXSTALL_MASK (0x2U)

#define	LPI2C_SCFGR1_RXSTALL_SHIFT (1U)

#define	LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)

#define	LPI2C_SCFGR1_TXDSTALL_MASK (0x4U)

#define	LPI2C_SCFGR1_TXDSTALL_SHIFT (2U)

#define	LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)

#define	LPI2C_SCFGR1_ACKSTALL_MASK (0x8U)

#define	LPI2C_SCFGR1_ACKSTALL_SHIFT (3U)

#define	LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)

#define	LPI2C_SCFGR1_GCEN_MASK (0x100U)

#define	LPI2C_SCFGR1_GCEN_SHIFT (8U)

#define	LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)

#define	LPI2C_SCFGR1_SAEN_MASK (0x200U)

#define	LPI2C_SCFGR1_SAEN_SHIFT (9U)

#define	LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)

#define	LPI2C_SCFGR1_TXCFG_MASK (0x400U)

#define	LPI2C_SCFGR1_TXCFG_SHIFT (10U)

#define	LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)

#define	LPI2C_SCFGR1_RXCFG_MASK (0x800U)

#define	LPI2C_SCFGR1_RXCFG_SHIFT (11U)

#define	LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)

#define	LPI2C_SCFGR1_IGNACK_MASK (0x1000U)

#define	LPI2C_SCFGR1_IGNACK_SHIFT (12U)

#define	LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)

#define	LPI2C_SCFGR1_HSMEN_MASK (0x2000U)

#define	LPI2C_SCFGR1_HSMEN_SHIFT (13U)

#define	LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)

#define	LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U)

#define	LPI2C_SCFGR1_ADDRCFG_SHIFT (16U)

#define	LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)

SCFGR2 - Slave Configuration Register 2
#define	LPI2C_SCFGR2_CLKHOLD_MASK (0xFU)

#define	LPI2C_SCFGR2_CLKHOLD_SHIFT (0U)

#define	LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)

#define	LPI2C_SCFGR2_DATAVD_MASK (0x3F00U)

#define	LPI2C_SCFGR2_DATAVD_SHIFT (8U)

#define	LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)

#define	LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U)

#define	LPI2C_SCFGR2_FILTSCL_SHIFT (16U)

#define	LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)

#define	LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U)

#define	LPI2C_SCFGR2_FILTSDA_SHIFT (24U)

#define	LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)

SAMR - Slave Address Match Register
#define	LPI2C_SAMR_ADDR0_MASK (0x7FEU)

#define	LPI2C_SAMR_ADDR0_SHIFT (1U)

#define	LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)

#define	LPI2C_SAMR_ADDR1_MASK (0x7FE0000U)

#define	LPI2C_SAMR_ADDR1_SHIFT (17U)

#define	LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)

SASR - Slave Address Status Register
#define	LPI2C_SASR_RADDR_MASK (0x7FFU)

#define	LPI2C_SASR_RADDR_SHIFT (0U)

#define	LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)

#define	LPI2C_SASR_ANV_MASK (0x4000U)

#define	LPI2C_SASR_ANV_SHIFT (14U)

#define	LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)

STAR - Slave Transmit ACK Register
#define	LPI2C_STAR_TXNACK_MASK (0x1U)

#define	LPI2C_STAR_TXNACK_SHIFT (0U)

#define	LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)

STDR - Slave Transmit Data Register
#define	LPI2C_STDR_DATA_MASK (0xFFU)

#define	LPI2C_STDR_DATA_SHIFT (0U)

#define	LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)

SRDR - Slave Receive Data Register
#define	LPI2C_SRDR_DATA_MASK (0xFFU)

#define	LPI2C_SRDR_DATA_SHIFT (0U)

#define	LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)

#define	LPI2C_SRDR_RXEMPTY_MASK (0x4000U)

#define	LPI2C_SRDR_RXEMPTY_SHIFT (14U)

#define	LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)

#define	LPI2C_SRDR_SOF_MASK (0x8000U)

#define	LPI2C_SRDR_SOF_SHIFT (15U)

#define	LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)

VERID - Version ID
#define	LPI2C_VERID_FEATURE_MASK (0xFFFFU)

#define	LPI2C_VERID_FEATURE_SHIFT (0U)

#define	LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)

#define	LPI2C_VERID_MINOR_MASK (0xFF0000U)

#define	LPI2C_VERID_MINOR_SHIFT (16U)

#define	LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)

#define	LPI2C_VERID_MAJOR_MASK (0xFF000000U)

#define	LPI2C_VERID_MAJOR_SHIFT (24U)

#define	LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)

PARAM - Parameter
#define	LPI2C_PARAM_MTXFIFO_MASK (0xFU)

#define	LPI2C_PARAM_MTXFIFO_SHIFT (0U)

#define	LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)

#define	LPI2C_PARAM_MRXFIFO_MASK (0xF00U)

#define	LPI2C_PARAM_MRXFIFO_SHIFT (8U)

#define	LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)

MCR - Master Control
#define	LPI2C_MCR_MEN_MASK (0x1U)

#define	LPI2C_MCR_MEN_SHIFT (0U)

#define	LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)

#define	LPI2C_MCR_RST_MASK (0x2U)

#define	LPI2C_MCR_RST_SHIFT (1U)

#define	LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)

#define	LPI2C_MCR_DOZEN_MASK (0x4U)

#define	LPI2C_MCR_DOZEN_SHIFT (2U)

#define	LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)

#define	LPI2C_MCR_DBGEN_MASK (0x8U)

#define	LPI2C_MCR_DBGEN_SHIFT (3U)

#define	LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)

#define	LPI2C_MCR_RTF_MASK (0x100U)

#define	LPI2C_MCR_RTF_SHIFT (8U)

#define	LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)

#define	LPI2C_MCR_RRF_MASK (0x200U)

#define	LPI2C_MCR_RRF_SHIFT (9U)

#define	LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)

MSR - Master Status
#define	LPI2C_MSR_TDF_MASK (0x1U)

#define	LPI2C_MSR_TDF_SHIFT (0U)

#define	LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)

#define	LPI2C_MSR_RDF_MASK (0x2U)

#define	LPI2C_MSR_RDF_SHIFT (1U)

#define	LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)

#define	LPI2C_MSR_EPF_MASK (0x100U)

#define	LPI2C_MSR_EPF_SHIFT (8U)

#define	LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)

#define	LPI2C_MSR_SDF_MASK (0x200U)

#define	LPI2C_MSR_SDF_SHIFT (9U)

#define	LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)

#define	LPI2C_MSR_NDF_MASK (0x400U)

#define	LPI2C_MSR_NDF_SHIFT (10U)

#define	LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)

#define	LPI2C_MSR_ALF_MASK (0x800U)

#define	LPI2C_MSR_ALF_SHIFT (11U)

#define	LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)

#define	LPI2C_MSR_FEF_MASK (0x1000U)

#define	LPI2C_MSR_FEF_SHIFT (12U)

#define	LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)

#define	LPI2C_MSR_PLTF_MASK (0x2000U)

#define	LPI2C_MSR_PLTF_SHIFT (13U)

#define	LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)

#define	LPI2C_MSR_DMF_MASK (0x4000U)

#define	LPI2C_MSR_DMF_SHIFT (14U)

#define	LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)

#define	LPI2C_MSR_MBF_MASK (0x1000000U)

#define	LPI2C_MSR_MBF_SHIFT (24U)

#define	LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)

#define	LPI2C_MSR_BBF_MASK (0x2000000U)

#define	LPI2C_MSR_BBF_SHIFT (25U)

#define	LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)

MIER - Master Interrupt Enable
#define	LPI2C_MIER_TDIE_MASK (0x1U)

#define	LPI2C_MIER_TDIE_SHIFT (0U)

#define	LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)

#define	LPI2C_MIER_RDIE_MASK (0x2U)

#define	LPI2C_MIER_RDIE_SHIFT (1U)

#define	LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)

#define	LPI2C_MIER_EPIE_MASK (0x100U)

#define	LPI2C_MIER_EPIE_SHIFT (8U)

#define	LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)

#define	LPI2C_MIER_SDIE_MASK (0x200U)

#define	LPI2C_MIER_SDIE_SHIFT (9U)

#define	LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)

#define	LPI2C_MIER_NDIE_MASK (0x400U)

#define	LPI2C_MIER_NDIE_SHIFT (10U)

#define	LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)

#define	LPI2C_MIER_ALIE_MASK (0x800U)

#define	LPI2C_MIER_ALIE_SHIFT (11U)

#define	LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)

#define	LPI2C_MIER_FEIE_MASK (0x1000U)

#define	LPI2C_MIER_FEIE_SHIFT (12U)

#define	LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)

#define	LPI2C_MIER_PLTIE_MASK (0x2000U)

#define	LPI2C_MIER_PLTIE_SHIFT (13U)

#define	LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)

#define	LPI2C_MIER_DMIE_MASK (0x4000U)

#define	LPI2C_MIER_DMIE_SHIFT (14U)

#define	LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)

MDER - Master DMA Enable
#define	LPI2C_MDER_TDDE_MASK (0x1U)

#define	LPI2C_MDER_TDDE_SHIFT (0U)

#define	LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)

#define	LPI2C_MDER_RDDE_MASK (0x2U)

#define	LPI2C_MDER_RDDE_SHIFT (1U)

#define	LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)

MCFGR0 - Master Configuration 0
#define	LPI2C_MCFGR0_HREN_MASK (0x1U)

#define	LPI2C_MCFGR0_HREN_SHIFT (0U)

#define	LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)

#define	LPI2C_MCFGR0_HRPOL_MASK (0x2U)

#define	LPI2C_MCFGR0_HRPOL_SHIFT (1U)

#define	LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)

#define	LPI2C_MCFGR0_HRSEL_MASK (0x4U)

#define	LPI2C_MCFGR0_HRSEL_SHIFT (2U)

#define	LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)

#define	LPI2C_MCFGR0_CIRFIFO_MASK (0x100U)

#define	LPI2C_MCFGR0_CIRFIFO_SHIFT (8U)

#define	LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)

#define	LPI2C_MCFGR0_RDMO_MASK (0x200U)

#define	LPI2C_MCFGR0_RDMO_SHIFT (9U)

#define	LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)

MCFGR1 - Master Configuration 1
#define	LPI2C_MCFGR1_PRESCALE_MASK (0x7U)

#define	LPI2C_MCFGR1_PRESCALE_SHIFT (0U)

#define	LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)

#define	LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U)

#define	LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U)

#define	LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)

#define	LPI2C_MCFGR1_IGNACK_MASK (0x200U)

#define	LPI2C_MCFGR1_IGNACK_SHIFT (9U)

#define	LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)

#define	LPI2C_MCFGR1_TIMECFG_MASK (0x400U)

#define	LPI2C_MCFGR1_TIMECFG_SHIFT (10U)

#define	LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)

#define	LPI2C_MCFGR1_MATCFG_MASK (0x70000U)

#define	LPI2C_MCFGR1_MATCFG_SHIFT (16U)

#define	LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)

#define	LPI2C_MCFGR1_PINCFG_MASK (0x7000000U)

#define	LPI2C_MCFGR1_PINCFG_SHIFT (24U)

#define	LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)

MCFGR2 - Master Configuration 2
#define	LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU)

#define	LPI2C_MCFGR2_BUSIDLE_SHIFT (0U)

#define	LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)

#define	LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U)

#define	LPI2C_MCFGR2_FILTSCL_SHIFT (16U)

#define	LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)

#define	LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U)

#define	LPI2C_MCFGR2_FILTSDA_SHIFT (24U)

#define	LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)

MCFGR3 - Master Configuration 3
#define	LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U)

#define	LPI2C_MCFGR3_PINLOW_SHIFT (8U)

#define	LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)

MDMR - Master Data Match
#define	LPI2C_MDMR_MATCH0_MASK (0xFFU)

#define	LPI2C_MDMR_MATCH0_SHIFT (0U)

#define	LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)

#define	LPI2C_MDMR_MATCH1_MASK (0xFF0000U)

#define	LPI2C_MDMR_MATCH1_SHIFT (16U)

#define	LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)

MCCR0 - Master Clock Configuration 0
#define	LPI2C_MCCR0_CLKLO_MASK (0x3FU)

#define	LPI2C_MCCR0_CLKLO_SHIFT (0U)

#define	LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)

#define	LPI2C_MCCR0_CLKHI_MASK (0x3F00U)

#define	LPI2C_MCCR0_CLKHI_SHIFT (8U)

#define	LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)

#define	LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U)

#define	LPI2C_MCCR0_SETHOLD_SHIFT (16U)

#define	LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)

#define	LPI2C_MCCR0_DATAVD_MASK (0x3F000000U)

#define	LPI2C_MCCR0_DATAVD_SHIFT (24U)

#define	LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)

MCCR1 - Master Clock Configuration 1
#define	LPI2C_MCCR1_CLKLO_MASK (0x3FU)

#define	LPI2C_MCCR1_CLKLO_SHIFT (0U)

#define	LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)

#define	LPI2C_MCCR1_CLKHI_MASK (0x3F00U)

#define	LPI2C_MCCR1_CLKHI_SHIFT (8U)

#define	LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)

#define	LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U)

#define	LPI2C_MCCR1_SETHOLD_SHIFT (16U)

#define	LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)

#define	LPI2C_MCCR1_DATAVD_MASK (0x3F000000U)

#define	LPI2C_MCCR1_DATAVD_SHIFT (24U)

#define	LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)

MFCR - Master FIFO Control
#define	LPI2C_MFCR_TXWATER_MASK (0x3U)

#define	LPI2C_MFCR_TXWATER_SHIFT (0U)

#define	LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)

#define	LPI2C_MFCR_RXWATER_MASK (0x30000U)

#define	LPI2C_MFCR_RXWATER_SHIFT (16U)

#define	LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)

MFSR - Master FIFO Status
#define	LPI2C_MFSR_TXCOUNT_MASK (0x7U)

#define	LPI2C_MFSR_TXCOUNT_SHIFT (0U)

#define	LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)

#define	LPI2C_MFSR_RXCOUNT_MASK (0x70000U)

#define	LPI2C_MFSR_RXCOUNT_SHIFT (16U)

#define	LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)

MTDR - Master Transmit Data
#define	LPI2C_MTDR_DATA_MASK (0xFFU)

#define	LPI2C_MTDR_DATA_SHIFT (0U)

#define	LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)

#define	LPI2C_MTDR_CMD_MASK (0x700U)

#define	LPI2C_MTDR_CMD_SHIFT (8U)

#define	LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)

MRDR - Master Receive Data
#define	LPI2C_MRDR_DATA_MASK (0xFFU)

#define	LPI2C_MRDR_DATA_SHIFT (0U)

#define	LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)

#define	LPI2C_MRDR_RXEMPTY_MASK (0x4000U)

#define	LPI2C_MRDR_RXEMPTY_SHIFT (14U)

#define	LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)

SCR - Slave Control
#define	LPI2C_SCR_SEN_MASK (0x1U)

#define	LPI2C_SCR_SEN_SHIFT (0U)

#define	LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)

#define	LPI2C_SCR_RST_MASK (0x2U)

#define	LPI2C_SCR_RST_SHIFT (1U)

#define	LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)

#define	LPI2C_SCR_FILTEN_MASK (0x10U)

#define	LPI2C_SCR_FILTEN_SHIFT (4U)

#define	LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)

#define	LPI2C_SCR_FILTDZ_MASK (0x20U)

#define	LPI2C_SCR_FILTDZ_SHIFT (5U)

#define	LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)

#define	LPI2C_SCR_RTF_MASK (0x100U)

#define	LPI2C_SCR_RTF_SHIFT (8U)

#define	LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)

#define	LPI2C_SCR_RRF_MASK (0x200U)

#define	LPI2C_SCR_RRF_SHIFT (9U)

#define	LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)

SSR - Slave Status
#define	LPI2C_SSR_TDF_MASK (0x1U)

#define	LPI2C_SSR_TDF_SHIFT (0U)

#define	LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)

#define	LPI2C_SSR_RDF_MASK (0x2U)

#define	LPI2C_SSR_RDF_SHIFT (1U)

#define	LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)

#define	LPI2C_SSR_AVF_MASK (0x4U)

#define	LPI2C_SSR_AVF_SHIFT (2U)

#define	LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)

#define	LPI2C_SSR_TAF_MASK (0x8U)

#define	LPI2C_SSR_TAF_SHIFT (3U)

#define	LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)

#define	LPI2C_SSR_RSF_MASK (0x100U)

#define	LPI2C_SSR_RSF_SHIFT (8U)

#define	LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)

#define	LPI2C_SSR_SDF_MASK (0x200U)

#define	LPI2C_SSR_SDF_SHIFT (9U)

#define	LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)

#define	LPI2C_SSR_BEF_MASK (0x400U)

#define	LPI2C_SSR_BEF_SHIFT (10U)

#define	LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)

#define	LPI2C_SSR_FEF_MASK (0x800U)

#define	LPI2C_SSR_FEF_SHIFT (11U)

#define	LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)

#define	LPI2C_SSR_AM0F_MASK (0x1000U)

#define	LPI2C_SSR_AM0F_SHIFT (12U)

#define	LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)

#define	LPI2C_SSR_AM1F_MASK (0x2000U)

#define	LPI2C_SSR_AM1F_SHIFT (13U)

#define	LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)

#define	LPI2C_SSR_GCF_MASK (0x4000U)

#define	LPI2C_SSR_GCF_SHIFT (14U)

#define	LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)

#define	LPI2C_SSR_SARF_MASK (0x8000U)

#define	LPI2C_SSR_SARF_SHIFT (15U)

#define	LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)

#define	LPI2C_SSR_SBF_MASK (0x1000000U)

#define	LPI2C_SSR_SBF_SHIFT (24U)

#define	LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)

#define	LPI2C_SSR_BBF_MASK (0x2000000U)

#define	LPI2C_SSR_BBF_SHIFT (25U)

#define	LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)

SIER - Slave Interrupt Enable
#define	LPI2C_SIER_TDIE_MASK (0x1U)

#define	LPI2C_SIER_TDIE_SHIFT (0U)

#define	LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)

#define	LPI2C_SIER_RDIE_MASK (0x2U)

#define	LPI2C_SIER_RDIE_SHIFT (1U)

#define	LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)

#define	LPI2C_SIER_AVIE_MASK (0x4U)

#define	LPI2C_SIER_AVIE_SHIFT (2U)

#define	LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)

#define	LPI2C_SIER_TAIE_MASK (0x8U)

#define	LPI2C_SIER_TAIE_SHIFT (3U)

#define	LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)

#define	LPI2C_SIER_RSIE_MASK (0x100U)

#define	LPI2C_SIER_RSIE_SHIFT (8U)

#define	LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)

#define	LPI2C_SIER_SDIE_MASK (0x200U)

#define	LPI2C_SIER_SDIE_SHIFT (9U)

#define	LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)

#define	LPI2C_SIER_BEIE_MASK (0x400U)

#define	LPI2C_SIER_BEIE_SHIFT (10U)

#define	LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)

#define	LPI2C_SIER_FEIE_MASK (0x800U)

#define	LPI2C_SIER_FEIE_SHIFT (11U)

#define	LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)

#define	LPI2C_SIER_AM0IE_MASK (0x1000U)

#define	LPI2C_SIER_AM0IE_SHIFT (12U)

#define	LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)

#define	LPI2C_SIER_AM1IE_MASK (0x2000U)

#define	LPI2C_SIER_AM1IE_SHIFT (13U)

#define	LPI2C_SIER_AM1IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK)

#define	LPI2C_SIER_GCIE_MASK (0x4000U)

#define	LPI2C_SIER_GCIE_SHIFT (14U)

#define	LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)

#define	LPI2C_SIER_SARIE_MASK (0x8000U)

#define	LPI2C_SIER_SARIE_SHIFT (15U)

#define	LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)

SDER - Slave DMA Enable
#define	LPI2C_SDER_TDDE_MASK (0x1U)

#define	LPI2C_SDER_TDDE_SHIFT (0U)

#define	LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)

#define	LPI2C_SDER_RDDE_MASK (0x2U)

#define	LPI2C_SDER_RDDE_SHIFT (1U)

#define	LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)

#define	LPI2C_SDER_AVDE_MASK (0x4U)

#define	LPI2C_SDER_AVDE_SHIFT (2U)

#define	LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)

SCFGR1 - Slave Configuration 1
#define	LPI2C_SCFGR1_ADRSTALL_MASK (0x1U)

#define	LPI2C_SCFGR1_ADRSTALL_SHIFT (0U)

#define	LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)

#define	LPI2C_SCFGR1_RXSTALL_MASK (0x2U)

#define	LPI2C_SCFGR1_RXSTALL_SHIFT (1U)

#define	LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)

#define	LPI2C_SCFGR1_TXDSTALL_MASK (0x4U)

#define	LPI2C_SCFGR1_TXDSTALL_SHIFT (2U)

#define	LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)

#define	LPI2C_SCFGR1_ACKSTALL_MASK (0x8U)

#define	LPI2C_SCFGR1_ACKSTALL_SHIFT (3U)

#define	LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)

#define	LPI2C_SCFGR1_GCEN_MASK (0x100U)

#define	LPI2C_SCFGR1_GCEN_SHIFT (8U)

#define	LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)

#define	LPI2C_SCFGR1_SAEN_MASK (0x200U)

#define	LPI2C_SCFGR1_SAEN_SHIFT (9U)

#define	LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)

#define	LPI2C_SCFGR1_TXCFG_MASK (0x400U)

#define	LPI2C_SCFGR1_TXCFG_SHIFT (10U)

#define	LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)

#define	LPI2C_SCFGR1_RXCFG_MASK (0x800U)

#define	LPI2C_SCFGR1_RXCFG_SHIFT (11U)

#define	LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)

#define	LPI2C_SCFGR1_IGNACK_MASK (0x1000U)

#define	LPI2C_SCFGR1_IGNACK_SHIFT (12U)

#define	LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)

#define	LPI2C_SCFGR1_HSMEN_MASK (0x2000U)

#define	LPI2C_SCFGR1_HSMEN_SHIFT (13U)

#define	LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)

#define	LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U)

#define	LPI2C_SCFGR1_ADDRCFG_SHIFT (16U)

#define	LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)

SCFGR2 - Slave Configuration 2
#define	LPI2C_SCFGR2_CLKHOLD_MASK (0xFU)

#define	LPI2C_SCFGR2_CLKHOLD_SHIFT (0U)

#define	LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)

#define	LPI2C_SCFGR2_DATAVD_MASK (0x3F00U)

#define	LPI2C_SCFGR2_DATAVD_SHIFT (8U)

#define	LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)

#define	LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U)

#define	LPI2C_SCFGR2_FILTSCL_SHIFT (16U)

#define	LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)

#define	LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U)

#define	LPI2C_SCFGR2_FILTSDA_SHIFT (24U)

#define	LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)

SAMR - Slave Address Match
#define	LPI2C_SAMR_ADDR0_MASK (0x7FEU)

#define	LPI2C_SAMR_ADDR0_SHIFT (1U)

#define	LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)

#define	LPI2C_SAMR_ADDR1_MASK (0x7FE0000U)

#define	LPI2C_SAMR_ADDR1_SHIFT (17U)

#define	LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)

SASR - Slave Address Status
#define	LPI2C_SASR_RADDR_MASK (0x7FFU)

#define	LPI2C_SASR_RADDR_SHIFT (0U)

#define	LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)

#define	LPI2C_SASR_ANV_MASK (0x4000U)

#define	LPI2C_SASR_ANV_SHIFT (14U)

#define	LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)

STAR - Slave Transmit ACK
#define	LPI2C_STAR_TXNACK_MASK (0x1U)

#define	LPI2C_STAR_TXNACK_SHIFT (0U)

#define	LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)

STDR - Slave Transmit Data
#define	LPI2C_STDR_DATA_MASK (0xFFU)

#define	LPI2C_STDR_DATA_SHIFT (0U)

#define	LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)

SRDR - Slave Receive Data
#define	LPI2C_SRDR_DATA_MASK (0xFFU)

#define	LPI2C_SRDR_DATA_SHIFT (0U)

#define	LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)

#define	LPI2C_SRDR_RXEMPTY_MASK (0x4000U)

#define	LPI2C_SRDR_RXEMPTY_SHIFT (14U)

#define	LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)

#define	LPI2C_SRDR_SOF_MASK (0x8000U)

#define	LPI2C_SRDR_SOF_SHIFT (15U)

#define	LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)

VERID - Version ID
#define	LPI2C_VERID_FEATURE_MASK (0xFFFFU)

#define	LPI2C_VERID_FEATURE_SHIFT (0U)

#define	LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)

#define	LPI2C_VERID_MINOR_MASK (0xFF0000U)

#define	LPI2C_VERID_MINOR_SHIFT (16U)

#define	LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)

#define	LPI2C_VERID_MAJOR_MASK (0xFF000000U)

#define	LPI2C_VERID_MAJOR_SHIFT (24U)

#define	LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)

PARAM - Parameter
#define	LPI2C_PARAM_MTXFIFO_MASK (0xFU)

#define	LPI2C_PARAM_MTXFIFO_SHIFT (0U)

#define	LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)

#define	LPI2C_PARAM_MRXFIFO_MASK (0xF00U)

#define	LPI2C_PARAM_MRXFIFO_SHIFT (8U)

#define	LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)

MCR - Master Control
#define	LPI2C_MCR_MEN_MASK (0x1U)

#define	LPI2C_MCR_MEN_SHIFT (0U)

#define	LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)

#define	LPI2C_MCR_RST_MASK (0x2U)

#define	LPI2C_MCR_RST_SHIFT (1U)

#define	LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)

#define	LPI2C_MCR_DOZEN_MASK (0x4U)

#define	LPI2C_MCR_DOZEN_SHIFT (2U)

#define	LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)

#define	LPI2C_MCR_DBGEN_MASK (0x8U)

#define	LPI2C_MCR_DBGEN_SHIFT (3U)

#define	LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)

#define	LPI2C_MCR_RTF_MASK (0x100U)

#define	LPI2C_MCR_RTF_SHIFT (8U)

#define	LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)

#define	LPI2C_MCR_RRF_MASK (0x200U)

#define	LPI2C_MCR_RRF_SHIFT (9U)

#define	LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)

MSR - Master Status
#define	LPI2C_MSR_TDF_MASK (0x1U)

#define	LPI2C_MSR_TDF_SHIFT (0U)

#define	LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)

#define	LPI2C_MSR_RDF_MASK (0x2U)

#define	LPI2C_MSR_RDF_SHIFT (1U)

#define	LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)

#define	LPI2C_MSR_EPF_MASK (0x100U)

#define	LPI2C_MSR_EPF_SHIFT (8U)

#define	LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)

#define	LPI2C_MSR_SDF_MASK (0x200U)

#define	LPI2C_MSR_SDF_SHIFT (9U)

#define	LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)

#define	LPI2C_MSR_NDF_MASK (0x400U)

#define	LPI2C_MSR_NDF_SHIFT (10U)

#define	LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)

#define	LPI2C_MSR_ALF_MASK (0x800U)

#define	LPI2C_MSR_ALF_SHIFT (11U)

#define	LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)

#define	LPI2C_MSR_FEF_MASK (0x1000U)

#define	LPI2C_MSR_FEF_SHIFT (12U)

#define	LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)

#define	LPI2C_MSR_PLTF_MASK (0x2000U)

#define	LPI2C_MSR_PLTF_SHIFT (13U)

#define	LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)

#define	LPI2C_MSR_DMF_MASK (0x4000U)

#define	LPI2C_MSR_DMF_SHIFT (14U)

#define	LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)

#define	LPI2C_MSR_MBF_MASK (0x1000000U)

#define	LPI2C_MSR_MBF_SHIFT (24U)

#define	LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)

#define	LPI2C_MSR_BBF_MASK (0x2000000U)

#define	LPI2C_MSR_BBF_SHIFT (25U)

#define	LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)

MIER - Master Interrupt Enable
#define	LPI2C_MIER_TDIE_MASK (0x1U)

#define	LPI2C_MIER_TDIE_SHIFT (0U)

#define	LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)

#define	LPI2C_MIER_RDIE_MASK (0x2U)

#define	LPI2C_MIER_RDIE_SHIFT (1U)

#define	LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)

#define	LPI2C_MIER_EPIE_MASK (0x100U)

#define	LPI2C_MIER_EPIE_SHIFT (8U)

#define	LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)

#define	LPI2C_MIER_SDIE_MASK (0x200U)

#define	LPI2C_MIER_SDIE_SHIFT (9U)

#define	LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)

#define	LPI2C_MIER_NDIE_MASK (0x400U)

#define	LPI2C_MIER_NDIE_SHIFT (10U)

#define	LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)

#define	LPI2C_MIER_ALIE_MASK (0x800U)

#define	LPI2C_MIER_ALIE_SHIFT (11U)

#define	LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)

#define	LPI2C_MIER_FEIE_MASK (0x1000U)

#define	LPI2C_MIER_FEIE_SHIFT (12U)

#define	LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)

#define	LPI2C_MIER_PLTIE_MASK (0x2000U)

#define	LPI2C_MIER_PLTIE_SHIFT (13U)

#define	LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)

#define	LPI2C_MIER_DMIE_MASK (0x4000U)

#define	LPI2C_MIER_DMIE_SHIFT (14U)

#define	LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)

MDER - Master DMA Enable
#define	LPI2C_MDER_TDDE_MASK (0x1U)

#define	LPI2C_MDER_TDDE_SHIFT (0U)

#define	LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)

#define	LPI2C_MDER_RDDE_MASK (0x2U)

#define	LPI2C_MDER_RDDE_SHIFT (1U)

#define	LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)

MCFGR0 - Master Configuration 0
#define	LPI2C_MCFGR0_HREN_MASK (0x1U)

#define	LPI2C_MCFGR0_HREN_SHIFT (0U)

#define	LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)

#define	LPI2C_MCFGR0_HRPOL_MASK (0x2U)

#define	LPI2C_MCFGR0_HRPOL_SHIFT (1U)

#define	LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)

#define	LPI2C_MCFGR0_HRSEL_MASK (0x4U)

#define	LPI2C_MCFGR0_HRSEL_SHIFT (2U)

#define	LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)

#define	LPI2C_MCFGR0_CIRFIFO_MASK (0x100U)

#define	LPI2C_MCFGR0_CIRFIFO_SHIFT (8U)

#define	LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)

#define	LPI2C_MCFGR0_RDMO_MASK (0x200U)

#define	LPI2C_MCFGR0_RDMO_SHIFT (9U)

#define	LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)

MCFGR1 - Master Configuration 1
#define	LPI2C_MCFGR1_PRESCALE_MASK (0x7U)

#define	LPI2C_MCFGR1_PRESCALE_SHIFT (0U)

#define	LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)

#define	LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U)

#define	LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U)

#define	LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)

#define	LPI2C_MCFGR1_IGNACK_MASK (0x200U)

#define	LPI2C_MCFGR1_IGNACK_SHIFT (9U)

#define	LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)

#define	LPI2C_MCFGR1_TIMECFG_MASK (0x400U)

#define	LPI2C_MCFGR1_TIMECFG_SHIFT (10U)

#define	LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)

#define	LPI2C_MCFGR1_MATCFG_MASK (0x70000U)

#define	LPI2C_MCFGR1_MATCFG_SHIFT (16U)

#define	LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)

#define	LPI2C_MCFGR1_PINCFG_MASK (0x7000000U)

#define	LPI2C_MCFGR1_PINCFG_SHIFT (24U)

#define	LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)

MCFGR2 - Master Configuration 2
#define	LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU)

#define	LPI2C_MCFGR2_BUSIDLE_SHIFT (0U)

#define	LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)

#define	LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U)

#define	LPI2C_MCFGR2_FILTSCL_SHIFT (16U)

#define	LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)

#define	LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U)

#define	LPI2C_MCFGR2_FILTSDA_SHIFT (24U)

#define	LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)

MCFGR3 - Master Configuration 3
#define	LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U)

#define	LPI2C_MCFGR3_PINLOW_SHIFT (8U)

#define	LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)

MDMR - Master Data Match
#define	LPI2C_MDMR_MATCH0_MASK (0xFFU)

#define	LPI2C_MDMR_MATCH0_SHIFT (0U)

#define	LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)

#define	LPI2C_MDMR_MATCH1_MASK (0xFF0000U)

#define	LPI2C_MDMR_MATCH1_SHIFT (16U)

#define	LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)

MCCR0 - Master Clock Configuration 0
#define	LPI2C_MCCR0_CLKLO_MASK (0x3FU)

#define	LPI2C_MCCR0_CLKLO_SHIFT (0U)

#define	LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)

#define	LPI2C_MCCR0_CLKHI_MASK (0x3F00U)

#define	LPI2C_MCCR0_CLKHI_SHIFT (8U)

#define	LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)

#define	LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U)

#define	LPI2C_MCCR0_SETHOLD_SHIFT (16U)

#define	LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)

#define	LPI2C_MCCR0_DATAVD_MASK (0x3F000000U)

#define	LPI2C_MCCR0_DATAVD_SHIFT (24U)

#define	LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)

MCCR1 - Master Clock Configuration 1
#define	LPI2C_MCCR1_CLKLO_MASK (0x3FU)

#define	LPI2C_MCCR1_CLKLO_SHIFT (0U)

#define	LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)

#define	LPI2C_MCCR1_CLKHI_MASK (0x3F00U)

#define	LPI2C_MCCR1_CLKHI_SHIFT (8U)

#define	LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)

#define	LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U)

#define	LPI2C_MCCR1_SETHOLD_SHIFT (16U)

#define	LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)

#define	LPI2C_MCCR1_DATAVD_MASK (0x3F000000U)

#define	LPI2C_MCCR1_DATAVD_SHIFT (24U)

#define	LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)

MFCR - Master FIFO Control
#define	LPI2C_MFCR_TXWATER_MASK (0x3U)

#define	LPI2C_MFCR_TXWATER_SHIFT (0U)

#define	LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)

#define	LPI2C_MFCR_RXWATER_MASK (0x30000U)

#define	LPI2C_MFCR_RXWATER_SHIFT (16U)

#define	LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)

MFSR - Master FIFO Status
#define	LPI2C_MFSR_TXCOUNT_MASK (0x7U)

#define	LPI2C_MFSR_TXCOUNT_SHIFT (0U)

#define	LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)

#define	LPI2C_MFSR_RXCOUNT_MASK (0x70000U)

#define	LPI2C_MFSR_RXCOUNT_SHIFT (16U)

#define	LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)

MTDR - Master Transmit Data
#define	LPI2C_MTDR_DATA_MASK (0xFFU)

#define	LPI2C_MTDR_DATA_SHIFT (0U)

#define	LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)

#define	LPI2C_MTDR_CMD_MASK (0x700U)

#define	LPI2C_MTDR_CMD_SHIFT (8U)

#define	LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)

MRDR - Master Receive Data
#define	LPI2C_MRDR_DATA_MASK (0xFFU)

#define	LPI2C_MRDR_DATA_SHIFT (0U)

#define	LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)

#define	LPI2C_MRDR_RXEMPTY_MASK (0x4000U)

#define	LPI2C_MRDR_RXEMPTY_SHIFT (14U)

#define	LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)

SCR - Slave Control
#define	LPI2C_SCR_SEN_MASK (0x1U)

#define	LPI2C_SCR_SEN_SHIFT (0U)

#define	LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)

#define	LPI2C_SCR_RST_MASK (0x2U)

#define	LPI2C_SCR_RST_SHIFT (1U)

#define	LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)

#define	LPI2C_SCR_FILTEN_MASK (0x10U)

#define	LPI2C_SCR_FILTEN_SHIFT (4U)

#define	LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)

#define	LPI2C_SCR_FILTDZ_MASK (0x20U)

#define	LPI2C_SCR_FILTDZ_SHIFT (5U)

#define	LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)

#define	LPI2C_SCR_RTF_MASK (0x100U)

#define	LPI2C_SCR_RTF_SHIFT (8U)

#define	LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)

#define	LPI2C_SCR_RRF_MASK (0x200U)

#define	LPI2C_SCR_RRF_SHIFT (9U)

#define	LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)

SSR - Slave Status
#define	LPI2C_SSR_TDF_MASK (0x1U)

#define	LPI2C_SSR_TDF_SHIFT (0U)

#define	LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)

#define	LPI2C_SSR_RDF_MASK (0x2U)

#define	LPI2C_SSR_RDF_SHIFT (1U)

#define	LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)

#define	LPI2C_SSR_AVF_MASK (0x4U)

#define	LPI2C_SSR_AVF_SHIFT (2U)

#define	LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)

#define	LPI2C_SSR_TAF_MASK (0x8U)

#define	LPI2C_SSR_TAF_SHIFT (3U)

#define	LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)

#define	LPI2C_SSR_RSF_MASK (0x100U)

#define	LPI2C_SSR_RSF_SHIFT (8U)

#define	LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)

#define	LPI2C_SSR_SDF_MASK (0x200U)

#define	LPI2C_SSR_SDF_SHIFT (9U)

#define	LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)

#define	LPI2C_SSR_BEF_MASK (0x400U)

#define	LPI2C_SSR_BEF_SHIFT (10U)

#define	LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)

#define	LPI2C_SSR_FEF_MASK (0x800U)

#define	LPI2C_SSR_FEF_SHIFT (11U)

#define	LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)

#define	LPI2C_SSR_AM0F_MASK (0x1000U)

#define	LPI2C_SSR_AM0F_SHIFT (12U)

#define	LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)

#define	LPI2C_SSR_AM1F_MASK (0x2000U)

#define	LPI2C_SSR_AM1F_SHIFT (13U)

#define	LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)

#define	LPI2C_SSR_GCF_MASK (0x4000U)

#define	LPI2C_SSR_GCF_SHIFT (14U)

#define	LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)

#define	LPI2C_SSR_SARF_MASK (0x8000U)

#define	LPI2C_SSR_SARF_SHIFT (15U)

#define	LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)

#define	LPI2C_SSR_SBF_MASK (0x1000000U)

#define	LPI2C_SSR_SBF_SHIFT (24U)

#define	LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)

#define	LPI2C_SSR_BBF_MASK (0x2000000U)

#define	LPI2C_SSR_BBF_SHIFT (25U)

#define	LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)

SIER - Slave Interrupt Enable
#define	LPI2C_SIER_TDIE_MASK (0x1U)

#define	LPI2C_SIER_TDIE_SHIFT (0U)

#define	LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)

#define	LPI2C_SIER_RDIE_MASK (0x2U)

#define	LPI2C_SIER_RDIE_SHIFT (1U)

#define	LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)

#define	LPI2C_SIER_AVIE_MASK (0x4U)

#define	LPI2C_SIER_AVIE_SHIFT (2U)

#define	LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)

#define	LPI2C_SIER_TAIE_MASK (0x8U)

#define	LPI2C_SIER_TAIE_SHIFT (3U)

#define	LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)

#define	LPI2C_SIER_RSIE_MASK (0x100U)

#define	LPI2C_SIER_RSIE_SHIFT (8U)

#define	LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)

#define	LPI2C_SIER_SDIE_MASK (0x200U)

#define	LPI2C_SIER_SDIE_SHIFT (9U)

#define	LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)

#define	LPI2C_SIER_BEIE_MASK (0x400U)

#define	LPI2C_SIER_BEIE_SHIFT (10U)

#define	LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)

#define	LPI2C_SIER_FEIE_MASK (0x800U)

#define	LPI2C_SIER_FEIE_SHIFT (11U)

#define	LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)

#define	LPI2C_SIER_AM0IE_MASK (0x1000U)

#define	LPI2C_SIER_AM0IE_SHIFT (12U)

#define	LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)

#define	LPI2C_SIER_AM1IE_MASK (0x2000U)

#define	LPI2C_SIER_AM1IE_SHIFT (13U)

#define	LPI2C_SIER_AM1IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK)

#define	LPI2C_SIER_GCIE_MASK (0x4000U)

#define	LPI2C_SIER_GCIE_SHIFT (14U)

#define	LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)

#define	LPI2C_SIER_SARIE_MASK (0x8000U)

#define	LPI2C_SIER_SARIE_SHIFT (15U)

#define	LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)

SDER - Slave DMA Enable
#define	LPI2C_SDER_TDDE_MASK (0x1U)

#define	LPI2C_SDER_TDDE_SHIFT (0U)

#define	LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)

#define	LPI2C_SDER_RDDE_MASK (0x2U)

#define	LPI2C_SDER_RDDE_SHIFT (1U)

#define	LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)

#define	LPI2C_SDER_AVDE_MASK (0x4U)

#define	LPI2C_SDER_AVDE_SHIFT (2U)

#define	LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)

SCFGR1 - Slave Configuration 1
#define	LPI2C_SCFGR1_ADRSTALL_MASK (0x1U)

#define	LPI2C_SCFGR1_ADRSTALL_SHIFT (0U)

#define	LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)

#define	LPI2C_SCFGR1_RXSTALL_MASK (0x2U)

#define	LPI2C_SCFGR1_RXSTALL_SHIFT (1U)

#define	LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)

#define	LPI2C_SCFGR1_TXDSTALL_MASK (0x4U)

#define	LPI2C_SCFGR1_TXDSTALL_SHIFT (2U)

#define	LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)

#define	LPI2C_SCFGR1_ACKSTALL_MASK (0x8U)

#define	LPI2C_SCFGR1_ACKSTALL_SHIFT (3U)

#define	LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)

#define	LPI2C_SCFGR1_GCEN_MASK (0x100U)

#define	LPI2C_SCFGR1_GCEN_SHIFT (8U)

#define	LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)

#define	LPI2C_SCFGR1_SAEN_MASK (0x200U)

#define	LPI2C_SCFGR1_SAEN_SHIFT (9U)

#define	LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)

#define	LPI2C_SCFGR1_TXCFG_MASK (0x400U)

#define	LPI2C_SCFGR1_TXCFG_SHIFT (10U)

#define	LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)

#define	LPI2C_SCFGR1_RXCFG_MASK (0x800U)

#define	LPI2C_SCFGR1_RXCFG_SHIFT (11U)

#define	LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)

#define	LPI2C_SCFGR1_IGNACK_MASK (0x1000U)

#define	LPI2C_SCFGR1_IGNACK_SHIFT (12U)

#define	LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)

#define	LPI2C_SCFGR1_HSMEN_MASK (0x2000U)

#define	LPI2C_SCFGR1_HSMEN_SHIFT (13U)

#define	LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)

#define	LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U)

#define	LPI2C_SCFGR1_ADDRCFG_SHIFT (16U)

#define	LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)

SCFGR2 - Slave Configuration 2
#define	LPI2C_SCFGR2_CLKHOLD_MASK (0xFU)

#define	LPI2C_SCFGR2_CLKHOLD_SHIFT (0U)

#define	LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)

#define	LPI2C_SCFGR2_DATAVD_MASK (0x3F00U)

#define	LPI2C_SCFGR2_DATAVD_SHIFT (8U)

#define	LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)

#define	LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U)

#define	LPI2C_SCFGR2_FILTSCL_SHIFT (16U)

#define	LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)

#define	LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U)

#define	LPI2C_SCFGR2_FILTSDA_SHIFT (24U)

#define	LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)

SAMR - Slave Address Match
#define	LPI2C_SAMR_ADDR0_MASK (0x7FEU)

#define	LPI2C_SAMR_ADDR0_SHIFT (1U)

#define	LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)

#define	LPI2C_SAMR_ADDR1_MASK (0x7FE0000U)

#define	LPI2C_SAMR_ADDR1_SHIFT (17U)

#define	LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)

SASR - Slave Address Status
#define	LPI2C_SASR_RADDR_MASK (0x7FFU)

#define	LPI2C_SASR_RADDR_SHIFT (0U)

#define	LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)

#define	LPI2C_SASR_ANV_MASK (0x4000U)

#define	LPI2C_SASR_ANV_SHIFT (14U)

#define	LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)

STAR - Slave Transmit ACK
#define	LPI2C_STAR_TXNACK_MASK (0x1U)

#define	LPI2C_STAR_TXNACK_SHIFT (0U)

#define	LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)

STDR - Slave Transmit Data
#define	LPI2C_STDR_DATA_MASK (0xFFU)

#define	LPI2C_STDR_DATA_SHIFT (0U)

#define	LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)

SRDR - Slave Receive Data
#define	LPI2C_SRDR_DATA_MASK (0xFFU)

#define	LPI2C_SRDR_DATA_SHIFT (0U)

#define	LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)

#define	LPI2C_SRDR_RXEMPTY_MASK (0x4000U)

#define	LPI2C_SRDR_RXEMPTY_SHIFT (14U)

#define	LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)

#define	LPI2C_SRDR_SOF_MASK (0x8000U)

#define	LPI2C_SRDR_SOF_SHIFT (15U)

#define	LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)

Detailed Description

Macro Definition Documentation

◆ LPI2C_MCCR0_CLKHI [1/3]

#define LPI2C_MCCR0_CLKHI ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)

CLKHI - Clock High Period

◆ LPI2C_MCCR0_CLKHI [2/3]

#define LPI2C_MCCR0_CLKHI ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)

CLKHI - Clock High Period

◆ LPI2C_MCCR0_CLKHI [3/3]

#define LPI2C_MCCR0_CLKHI ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)

CLKHI - Clock High Period

◆ LPI2C_MCCR0_CLKLO [1/3]

#define LPI2C_MCCR0_CLKLO ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)

CLKLO - Clock Low Period

◆ LPI2C_MCCR0_CLKLO [2/3]

#define LPI2C_MCCR0_CLKLO ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)

CLKLO - Clock Low Period

◆ LPI2C_MCCR0_CLKLO [3/3]

#define LPI2C_MCCR0_CLKLO ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)

CLKLO - Clock Low Period

◆ LPI2C_MCCR0_DATAVD [1/3]

#define LPI2C_MCCR0_DATAVD ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)

DATAVD - Data Valid Delay

◆ LPI2C_MCCR0_DATAVD [2/3]

#define LPI2C_MCCR0_DATAVD ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)

DATAVD - Data Valid Delay

◆ LPI2C_MCCR0_DATAVD [3/3]

#define LPI2C_MCCR0_DATAVD ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)

DATAVD - Data Valid Delay

◆ LPI2C_MCCR0_SETHOLD [1/3]

#define LPI2C_MCCR0_SETHOLD ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)

SETHOLD - Setup Hold Delay

◆ LPI2C_MCCR0_SETHOLD [2/3]

#define LPI2C_MCCR0_SETHOLD ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)

SETHOLD - Setup Hold Delay

◆ LPI2C_MCCR0_SETHOLD [3/3]

#define LPI2C_MCCR0_SETHOLD ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)

SETHOLD - Setup Hold Delay

◆ LPI2C_MCCR1_CLKHI [1/3]

#define LPI2C_MCCR1_CLKHI ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)

CLKHI - Clock High Period

◆ LPI2C_MCCR1_CLKHI [2/3]

#define LPI2C_MCCR1_CLKHI ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)

CLKHI - Clock High Period

◆ LPI2C_MCCR1_CLKHI [3/3]

#define LPI2C_MCCR1_CLKHI ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)

CLKHI - Clock High Period

◆ LPI2C_MCCR1_CLKLO [1/3]

#define LPI2C_MCCR1_CLKLO ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)

CLKLO - Clock Low Period

◆ LPI2C_MCCR1_CLKLO [2/3]

#define LPI2C_MCCR1_CLKLO ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)

CLKLO - Clock Low Period

◆ LPI2C_MCCR1_CLKLO [3/3]

#define LPI2C_MCCR1_CLKLO ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)

CLKLO - Clock Low Period

◆ LPI2C_MCCR1_DATAVD [1/3]

#define LPI2C_MCCR1_DATAVD ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)

DATAVD - Data Valid Delay

◆ LPI2C_MCCR1_DATAVD [2/3]

#define LPI2C_MCCR1_DATAVD ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)

DATAVD - Data Valid Delay

◆ LPI2C_MCCR1_DATAVD [3/3]

#define LPI2C_MCCR1_DATAVD ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)

DATAVD - Data Valid Delay

◆ LPI2C_MCCR1_SETHOLD [1/3]

#define LPI2C_MCCR1_SETHOLD ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)

SETHOLD - Setup Hold Delay

◆ LPI2C_MCCR1_SETHOLD [2/3]

#define LPI2C_MCCR1_SETHOLD ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)

SETHOLD - Setup Hold Delay

◆ LPI2C_MCCR1_SETHOLD [3/3]

#define LPI2C_MCCR1_SETHOLD ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)

SETHOLD - Setup Hold Delay

◆ LPI2C_MCFGR0_CIRFIFO [1/3]

#define LPI2C_MCFGR0_CIRFIFO ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)

CIRFIFO - Circular FIFO Enable 0b0..Circular FIFO is disabled 0b1..Circular FIFO is enabled

◆ LPI2C_MCFGR0_CIRFIFO [2/3]

#define LPI2C_MCFGR0_CIRFIFO ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)

CIRFIFO - Circular FIFO Enable 0b0..Circular FIFO is disabled 0b1..Circular FIFO is enabled

◆ LPI2C_MCFGR0_CIRFIFO [3/3]

#define LPI2C_MCFGR0_CIRFIFO ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)

CIRFIFO - Circular FIFO Enable 0b0..Circular FIFO is disabled 0b1..Circular FIFO is enabled

◆ LPI2C_MCFGR0_HREN [1/3]

#define LPI2C_MCFGR0_HREN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)

HREN - Host Request Enable 0b0..Host request input is disabled 0b1..Host request input is enabled

◆ LPI2C_MCFGR0_HREN [2/3]

#define LPI2C_MCFGR0_HREN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)

HREN - Host Request Enable 0b0..Host request input is disabled 0b1..Host request input is enabled

◆ LPI2C_MCFGR0_HREN [3/3]

#define LPI2C_MCFGR0_HREN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)

HREN - Host Request Enable 0b0..Host request input is disabled 0b1..Host request input is enabled

◆ LPI2C_MCFGR0_HRPOL [1/3]

#define LPI2C_MCFGR0_HRPOL ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)

HRPOL - Host Request Polarity 0b0..Active low 0b1..Active high

◆ LPI2C_MCFGR0_HRPOL [2/3]

#define LPI2C_MCFGR0_HRPOL ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)

HRPOL - Host Request Polarity 0b0..Active low 0b1..Active high

◆ LPI2C_MCFGR0_HRPOL [3/3]

#define LPI2C_MCFGR0_HRPOL ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)

HRPOL - Host Request Polarity 0b0..Active low 0b1..Active high

◆ LPI2C_MCFGR0_HRSEL [1/3]

#define LPI2C_MCFGR0_HRSEL ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)

HRSEL - Host Request Select 0b0..Host request input is pin HREQ 0b1..Host request input is input trigger

◆ LPI2C_MCFGR0_HRSEL [2/3]

#define LPI2C_MCFGR0_HRSEL ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)

HRSEL - Host Request Select 0b0..Host request input is pin HREQ 0b1..Host request input is input trigger

◆ LPI2C_MCFGR0_HRSEL [3/3]

#define LPI2C_MCFGR0_HRSEL ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)

HRSEL - Host Request Select 0b0..Host request input is pin HREQ 0b1..Host request input is input trigger

◆ LPI2C_MCFGR0_RDMO [1/3]

#define LPI2C_MCFGR0_RDMO ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)

RDMO - Receive Data Match Only 0b0..Received data is stored in the receive FIFO 0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set

◆ LPI2C_MCFGR0_RDMO [2/3]

#define LPI2C_MCFGR0_RDMO ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)

RDMO - Receive Data Match Only 0b0..Received data is stored in the receive FIFO 0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set

◆ LPI2C_MCFGR0_RDMO [3/3]

#define LPI2C_MCFGR0_RDMO ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)

RDMO - Receive Data Match Only 0b0..Received data is stored in the receive FIFO 0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set

◆ LPI2C_MCFGR1_AUTOSTOP [1/3]

#define LPI2C_MCFGR1_AUTOSTOP ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)

AUTOSTOP - Automatic STOP Generation 0b0..No effect 0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy

◆ LPI2C_MCFGR1_AUTOSTOP [2/3]

#define LPI2C_MCFGR1_AUTOSTOP ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)

AUTOSTOP - Automatic STOP Generation 0b0..No effect 0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy

◆ LPI2C_MCFGR1_AUTOSTOP [3/3]

#define LPI2C_MCFGR1_AUTOSTOP ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)

AUTOSTOP - Automatic STOP Generation 0b0..No effect 0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy

◆ LPI2C_MCFGR1_IGNACK [1/3]

#define LPI2C_MCFGR1_IGNACK ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)

IGNACK - IGNACK 0b0..LPI2C Master will receive ACK and NACK normally 0b1..LPI2C Master will treat a received NACK as if it (NACK) was an ACK

◆ LPI2C_MCFGR1_IGNACK [2/3]

#define LPI2C_MCFGR1_IGNACK ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)

IGNACK - IGNACK 0b0..LPI2C Master receives ACK and NACK normally 0b1..LPI2C Master treats a received NACK as if it (NACK) was an ACK

◆ LPI2C_MCFGR1_IGNACK [3/3]

#define LPI2C_MCFGR1_IGNACK ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)

IGNACK - IGNACK 0b0..LPI2C Master receives ACK and NACK normally 0b1..LPI2C Master treats a received NACK as if it (NACK) was an ACK

◆ LPI2C_MCFGR1_MATCFG [1/3]

#define LPI2C_MCFGR1_MATCFG ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)

MATCFG - Match Configuration 0b000..Match is disabled 0b001..Reserved 0b010..Match is enabled (1st data word equals MATCH0 OR MATCH1) 0b011..Match is enabled (any data word equals MATCH0 OR MATCH1) 0b100..Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1) 0b101..Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1) 0b110..Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) 0b111..Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1)

◆ LPI2C_MCFGR1_MATCFG [2/3]

#define LPI2C_MCFGR1_MATCFG ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)

MATCFG - Match Configuration 0b000..Match is disabled 0b001..Reserved 0b010..Match is enabled (1st data word equals MDMR[MATCH0] OR MDMR[MATCH1]) 0b011..Match is enabled (any data word equals MDMR[MATCH0] OR MDMR[MATCH1]) 0b100..Match is enabled (1st data word equals MDMR[MATCH0] AND 2nd data word equals MDMR[MATCH1) 0b101..Match is enabled (any data word equals MDMR[MATCH0] AND next data word equals MDMR[MATCH1) 0b110..Match is enabled (1st data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1]) 0b111..Match is enabled (any data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1])

◆ LPI2C_MCFGR1_MATCFG [3/3]

#define LPI2C_MCFGR1_MATCFG ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)

MATCFG - Match Configuration 0b000..Match is disabled 0b001..Reserved 0b010..Match is enabled (1st data word equals MDMR[MATCH0] OR MDMR[MATCH1]) 0b011..Match is enabled (any data word equals MDMR[MATCH0] OR MDMR[MATCH1]) 0b100..Match is enabled (1st data word equals MDMR[MATCH0] AND 2nd data word equals MDMR[MATCH1) 0b101..Match is enabled (any data word equals MDMR[MATCH0] AND next data word equals MDMR[MATCH1) 0b110..Match is enabled (1st data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1]) 0b111..Match is enabled (any data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1])

◆ LPI2C_MCFGR1_PINCFG [1/3]

#define LPI2C_MCFGR1_PINCFG ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)

PINCFG - Pin Configuration 0b000..2-pin open drain mode 0b001..2-pin output only mode (ultra-fast mode) 0b010..2-pin push-pull mode 0b011..4-pin push-pull mode 0b100..2-pin open drain mode with separate LPI2C slave 0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave 0b110..2-pin push-pull mode with separate LPI2C slave 0b111..4-pin push-pull mode (inverted outputs)

◆ LPI2C_MCFGR1_PINCFG [2/3]

#define LPI2C_MCFGR1_PINCFG ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)

PINCFG - Pin Configuration 0b000..2-pin open drain mode 0b001..2-pin output only mode (ultra-fast mode) 0b010..2-pin push-pull mode 0b011..4-pin push-pull mode 0b100..2-pin open drain mode with separate LPI2C slave 0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave 0b110..2-pin push-pull mode with separate LPI2C slave 0b111..4-pin push-pull mode (inverted outputs)

◆ LPI2C_MCFGR1_PINCFG [3/3]

#define LPI2C_MCFGR1_PINCFG ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)

PINCFG - Pin Configuration 0b000..2-pin open drain mode 0b001..2-pin output only mode (ultra-fast mode) 0b010..2-pin push-pull mode 0b011..4-pin push-pull mode 0b100..2-pin open drain mode with separate LPI2C slave 0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave 0b110..2-pin push-pull mode with separate LPI2C slave 0b111..4-pin push-pull mode (inverted outputs)

◆ LPI2C_MCFGR1_PRESCALE [1/3]

#define LPI2C_MCFGR1_PRESCALE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)

PRESCALE - Prescaler 0b000..Divide by 1 0b001..Divide by 2 0b010..Divide by 4 0b011..Divide by 8 0b100..Divide by 16 0b101..Divide by 32 0b110..Divide by 64 0b111..Divide by 128

◆ LPI2C_MCFGR1_PRESCALE [2/3]

#define LPI2C_MCFGR1_PRESCALE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)

PRESCALE - Prescaler 0b000..Divide by 1 0b001..Divide by 2 0b010..Divide by 4 0b011..Divide by 8 0b100..Divide by 16 0b101..Divide by 32 0b110..Divide by 64 0b111..Divide by 128

◆ LPI2C_MCFGR1_PRESCALE [3/3]

#define LPI2C_MCFGR1_PRESCALE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)

PRESCALE - Prescaler 0b000..Divide by 1 0b001..Divide by 2 0b010..Divide by 4 0b011..Divide by 8 0b100..Divide by 16 0b101..Divide by 32 0b110..Divide by 64 0b111..Divide by 128

◆ LPI2C_MCFGR1_TIMECFG [1/3]

#define LPI2C_MCFGR1_TIMECFG ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)

TIMECFG - Timeout Configuration 0b0..Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout 0b1..Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout

◆ LPI2C_MCFGR1_TIMECFG [2/3]

#define LPI2C_MCFGR1_TIMECFG ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)

TIMECFG - Timeout Configuration 0b0..MSR[PLTF] sets if SCL is low for longer than the configured timeout 0b1..MSR[PLTF] sets if either SCL or SDA is low for longer than the configured timeout

◆ LPI2C_MCFGR1_TIMECFG [3/3]

#define LPI2C_MCFGR1_TIMECFG ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)

TIMECFG - Timeout Configuration 0b0..MSR[PLTF] sets if SCL is low for longer than the configured timeout 0b1..MSR[PLTF] sets if either SCL or SDA is low for longer than the configured timeout

◆ LPI2C_MCFGR2_BUSIDLE [1/3]

#define LPI2C_MCFGR2_BUSIDLE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)

BUSIDLE - Bus Idle Timeout

◆ LPI2C_MCFGR2_BUSIDLE [2/3]

#define LPI2C_MCFGR2_BUSIDLE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)

BUSIDLE - Bus Idle Timeout

◆ LPI2C_MCFGR2_BUSIDLE [3/3]

#define LPI2C_MCFGR2_BUSIDLE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)

BUSIDLE - Bus Idle Timeout

◆ LPI2C_MCFGR2_FILTSCL [1/3]

#define LPI2C_MCFGR2_FILTSCL ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)

FILTSCL - Glitch Filter SCL

◆ LPI2C_MCFGR2_FILTSCL [2/3]

#define LPI2C_MCFGR2_FILTSCL ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)

FILTSCL - Glitch Filter SCL

◆ LPI2C_MCFGR2_FILTSCL [3/3]

#define LPI2C_MCFGR2_FILTSCL ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)

FILTSCL - Glitch Filter SCL

◆ LPI2C_MCFGR2_FILTSDA [1/3]

#define LPI2C_MCFGR2_FILTSDA ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)

FILTSDA - Glitch Filter SDA

◆ LPI2C_MCFGR2_FILTSDA [2/3]

#define LPI2C_MCFGR2_FILTSDA ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)

FILTSDA - Glitch Filter SDA

◆ LPI2C_MCFGR2_FILTSDA [3/3]

#define LPI2C_MCFGR2_FILTSDA ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)

FILTSDA - Glitch Filter SDA

◆ LPI2C_MCFGR3_PINLOW [1/3]

#define LPI2C_MCFGR3_PINLOW ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)

PINLOW - Pin Low Timeout

◆ LPI2C_MCFGR3_PINLOW [2/3]

#define LPI2C_MCFGR3_PINLOW ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)

PINLOW - Pin Low Timeout

◆ LPI2C_MCFGR3_PINLOW [3/3]

#define LPI2C_MCFGR3_PINLOW ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)

PINLOW - Pin Low Timeout

◆ LPI2C_MCR_DBGEN [1/3]

#define LPI2C_MCR_DBGEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)

DBGEN - Debug Enable 0b0..Master is disabled in debug mode 0b1..Master is enabled in debug mode

◆ LPI2C_MCR_DBGEN [2/3]

#define LPI2C_MCR_DBGEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)

DBGEN - Debug Enable 0b0..Master is disabled in debug mode 0b1..Master is enabled in debug mode

◆ LPI2C_MCR_DBGEN [3/3]

#define LPI2C_MCR_DBGEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)

DBGEN - Debug Enable 0b0..Master is disabled in debug mode 0b1..Master is enabled in debug mode

◆ LPI2C_MCR_DOZEN [1/3]

#define LPI2C_MCR_DOZEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)

DOZEN - Doze mode enable 0b0..Master is enabled in Doze mode 0b1..Master is disabled in Doze mode

◆ LPI2C_MCR_DOZEN [2/3]

#define LPI2C_MCR_DOZEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)

DOZEN - Doze mode enable 0b0..Master is enabled in Doze mode 0b1..Master is disabled in Doze mode

◆ LPI2C_MCR_DOZEN [3/3]

#define LPI2C_MCR_DOZEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)

DOZEN - Doze mode enable 0b0..Master is enabled in Doze mode 0b1..Master is disabled in Doze mode

◆ LPI2C_MCR_MEN [1/3]

#define LPI2C_MCR_MEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)

MEN - Master Enable 0b0..Master logic is disabled 0b1..Master logic is enabled

◆ LPI2C_MCR_MEN [2/3]

#define LPI2C_MCR_MEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)

MEN - Master Enable 0b0..Master logic is disabled 0b1..Master logic is enabled

◆ LPI2C_MCR_MEN [3/3]

#define LPI2C_MCR_MEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)

MEN - Master Enable 0b0..Master logic is disabled 0b1..Master logic is enabled

◆ LPI2C_MCR_RRF [1/3]

#define LPI2C_MCR_RRF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)

RRF - Reset Receive FIFO 0b0..No effect 0b1..Receive FIFO is reset

◆ LPI2C_MCR_RRF [2/3]

#define LPI2C_MCR_RRF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)

RRF - Reset Receive FIFO 0b0..No effect 0b1..Receive FIFO is reset

◆ LPI2C_MCR_RRF [3/3]

#define LPI2C_MCR_RRF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)

RRF - Reset Receive FIFO 0b0..No effect 0b1..Receive FIFO is reset

◆ LPI2C_MCR_RST [1/3]

#define LPI2C_MCR_RST ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)

RST - Software Reset 0b0..Master logic is not reset 0b1..Master logic is reset

◆ LPI2C_MCR_RST [2/3]

#define LPI2C_MCR_RST ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)

RST - Software Reset 0b0..Master logic is not reset 0b1..Master logic is reset

◆ LPI2C_MCR_RST [3/3]

#define LPI2C_MCR_RST ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)

RST - Software Reset 0b0..Master logic is not reset 0b1..Master logic is reset

◆ LPI2C_MCR_RTF [1/3]

#define LPI2C_MCR_RTF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)

RTF - Reset Transmit FIFO 0b0..No effect 0b1..Transmit FIFO is reset

◆ LPI2C_MCR_RTF [2/3]

#define LPI2C_MCR_RTF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)

RTF - Reset Transmit FIFO 0b0..No effect 0b1..Transmit FIFO is reset

◆ LPI2C_MCR_RTF [3/3]

#define LPI2C_MCR_RTF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)

RTF - Reset Transmit FIFO 0b0..No effect 0b1..Transmit FIFO is reset

◆ LPI2C_MDER_RDDE [1/3]

#define LPI2C_MDER_RDDE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)

RDDE - Receive Data DMA Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

◆ LPI2C_MDER_RDDE [2/3]

#define LPI2C_MDER_RDDE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)

RDDE - Receive Data DMA Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

◆ LPI2C_MDER_RDDE [3/3]

#define LPI2C_MDER_RDDE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)

RDDE - Receive Data DMA Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

◆ LPI2C_MDER_TDDE [1/3]

#define LPI2C_MDER_TDDE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)

TDDE - Transmit Data DMA Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

◆ LPI2C_MDER_TDDE [2/3]

#define LPI2C_MDER_TDDE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)

TDDE - Transmit Data DMA Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

◆ LPI2C_MDER_TDDE [3/3]

#define LPI2C_MDER_TDDE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)

TDDE - Transmit Data DMA Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

◆ LPI2C_MDMR_MATCH0 [1/3]

#define LPI2C_MDMR_MATCH0 ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)

MATCH0 - Match 0 Value

◆ LPI2C_MDMR_MATCH0 [2/3]

#define LPI2C_MDMR_MATCH0 ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)

MATCH0 - Match 0 Value

◆ LPI2C_MDMR_MATCH0 [3/3]

#define LPI2C_MDMR_MATCH0 ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)

MATCH0 - Match 0 Value

◆ LPI2C_MDMR_MATCH1 [1/3]

#define LPI2C_MDMR_MATCH1 ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)

MATCH1 - Match 1 Value

◆ LPI2C_MDMR_MATCH1 [2/3]

#define LPI2C_MDMR_MATCH1 ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)

MATCH1 - Match 1 Value

◆ LPI2C_MDMR_MATCH1 [3/3]

#define LPI2C_MDMR_MATCH1 ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)

MATCH1 - Match 1 Value

◆ LPI2C_MFCR_RXWATER [1/3]

#define LPI2C_MFCR_RXWATER ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)

RXWATER - Receive FIFO Watermark

◆ LPI2C_MFCR_RXWATER [2/3]

#define LPI2C_MFCR_RXWATER ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)

RXWATER - Receive FIFO Watermark

◆ LPI2C_MFCR_RXWATER [3/3]

#define LPI2C_MFCR_RXWATER ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)

RXWATER - Receive FIFO Watermark

◆ LPI2C_MFCR_TXWATER [1/3]

#define LPI2C_MFCR_TXWATER ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)

TXWATER - Transmit FIFO Watermark

◆ LPI2C_MFCR_TXWATER [2/3]

#define LPI2C_MFCR_TXWATER ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)

TXWATER - Transmit FIFO Watermark

◆ LPI2C_MFCR_TXWATER [3/3]

#define LPI2C_MFCR_TXWATER ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)

TXWATER - Transmit FIFO Watermark

◆ LPI2C_MFSR_RXCOUNT [1/3]

#define LPI2C_MFSR_RXCOUNT ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)

RXCOUNT - Receive FIFO Count

◆ LPI2C_MFSR_RXCOUNT [2/3]

#define LPI2C_MFSR_RXCOUNT ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)

RXCOUNT - Receive FIFO Count

◆ LPI2C_MFSR_RXCOUNT [3/3]

#define LPI2C_MFSR_RXCOUNT ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)

RXCOUNT - Receive FIFO Count

◆ LPI2C_MFSR_TXCOUNT [1/3]

#define LPI2C_MFSR_TXCOUNT ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)

TXCOUNT - Transmit FIFO Count

◆ LPI2C_MFSR_TXCOUNT [2/3]

#define LPI2C_MFSR_TXCOUNT ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)

TXCOUNT - Transmit FIFO Count

◆ LPI2C_MFSR_TXCOUNT [3/3]

#define LPI2C_MFSR_TXCOUNT ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)

TXCOUNT - Transmit FIFO Count

◆ LPI2C_MIER_ALIE [1/3]

#define LPI2C_MIER_ALIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)

ALIE - Arbitration Lost Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_MIER_ALIE [2/3]

#define LPI2C_MIER_ALIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)

ALIE - Arbitration Lost Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_MIER_ALIE [3/3]

#define LPI2C_MIER_ALIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)

ALIE - Arbitration Lost Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_MIER_DMIE [1/3]

#define LPI2C_MIER_DMIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)

DMIE - Data Match Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_MIER_DMIE [2/3]

#define LPI2C_MIER_DMIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)

DMIE - Data Match Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_MIER_DMIE [3/3]

#define LPI2C_MIER_DMIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)

DMIE - Data Match Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_MIER_EPIE [1/3]

#define LPI2C_MIER_EPIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)

EPIE - End Packet Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_MIER_EPIE [2/3]

#define LPI2C_MIER_EPIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)

EPIE - End Packet Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_MIER_EPIE [3/3]

#define LPI2C_MIER_EPIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)

EPIE - End Packet Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_MIER_FEIE [1/3]

#define LPI2C_MIER_FEIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)

FEIE - FIFO Error Interrupt Enable 0b0..Enabled 0b1..Disabled

◆ LPI2C_MIER_FEIE [2/3]

#define LPI2C_MIER_FEIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)

FEIE - FIFO Error Interrupt Enable 0b0..Enabled 0b1..Disabled

◆ LPI2C_MIER_FEIE [3/3]

#define LPI2C_MIER_FEIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)

FEIE - FIFO Error Interrupt Enable 0b0..Enabled 0b1..Disabled

◆ LPI2C_MIER_NDIE [1/3]

#define LPI2C_MIER_NDIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)

NDIE - NACK Detect Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_MIER_NDIE [2/3]

#define LPI2C_MIER_NDIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)

NDIE - NACK Detect Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_MIER_NDIE [3/3]

#define LPI2C_MIER_NDIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)

NDIE - NACK Detect Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_MIER_PLTIE [1/3]

#define LPI2C_MIER_PLTIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)

PLTIE - Pin Low Timeout Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_MIER_PLTIE [2/3]

#define LPI2C_MIER_PLTIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)

PLTIE - Pin Low Timeout Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_MIER_PLTIE [3/3]

#define LPI2C_MIER_PLTIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)

PLTIE - Pin Low Timeout Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_MIER_RDIE [1/3]

#define LPI2C_MIER_RDIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)

RDIE - Receive Data Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_MIER_RDIE [2/3]

#define LPI2C_MIER_RDIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)

RDIE - Receive Data Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_MIER_RDIE [3/3]

#define LPI2C_MIER_RDIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)

RDIE - Receive Data Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_MIER_SDIE [1/3]

#define LPI2C_MIER_SDIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)

SDIE - STOP Detect Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_MIER_SDIE [2/3]

#define LPI2C_MIER_SDIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)

SDIE - STOP Detect Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_MIER_SDIE [3/3]

#define LPI2C_MIER_SDIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)

SDIE - STOP Detect Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_MIER_TDIE [1/3]

#define LPI2C_MIER_TDIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)

TDIE - Transmit Data Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_MIER_TDIE [2/3]

#define LPI2C_MIER_TDIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)

TDIE - Transmit Data Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_MIER_TDIE [3/3]

#define LPI2C_MIER_TDIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)

TDIE - Transmit Data Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_MRDR_DATA [1/3]

#define LPI2C_MRDR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)

DATA - Receive Data

◆ LPI2C_MRDR_DATA [2/3]

#define LPI2C_MRDR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)

DATA - Receive Data

◆ LPI2C_MRDR_DATA [3/3]

#define LPI2C_MRDR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)

DATA - Receive Data

◆ LPI2C_MRDR_RXEMPTY [1/3]

#define LPI2C_MRDR_RXEMPTY ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)

RXEMPTY - RX Empty 0b0..Receive FIFO is not empty 0b1..Receive FIFO is empty

◆ LPI2C_MRDR_RXEMPTY [2/3]

#define LPI2C_MRDR_RXEMPTY ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)

RXEMPTY - RX Empty 0b0..Receive FIFO is not empty 0b1..Receive FIFO is empty

◆ LPI2C_MRDR_RXEMPTY [3/3]

#define LPI2C_MRDR_RXEMPTY ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)

RXEMPTY - RX Empty 0b0..Receive FIFO is not empty 0b1..Receive FIFO is empty

◆ LPI2C_MSR_ALF [1/3]

#define LPI2C_MSR_ALF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)

ALF - Arbitration Lost Flag 0b0..Master has not lost arbitration 0b1..Master has lost arbitration

◆ LPI2C_MSR_ALF [2/3]

#define LPI2C_MSR_ALF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)

ALF - Arbitration Lost Flag 0b0..Master has not lost arbitration 0b1..Master has lost arbitration

◆ LPI2C_MSR_ALF [3/3]

#define LPI2C_MSR_ALF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)

ALF - Arbitration Lost Flag 0b0..Master has not lost arbitration 0b1..Master has lost arbitration

◆ LPI2C_MSR_BBF [1/3]

#define LPI2C_MSR_BBF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)

BBF - Bus Busy Flag 0b0..I2C Bus is idle 0b1..I2C Bus is busy

◆ LPI2C_MSR_BBF [2/3]

#define LPI2C_MSR_BBF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)

BBF - Bus Busy Flag 0b0..I2C Bus is idle 0b1..I2C Bus is busy

◆ LPI2C_MSR_BBF [3/3]

#define LPI2C_MSR_BBF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)

BBF - Bus Busy Flag 0b0..I2C Bus is idle 0b1..I2C Bus is busy

◆ LPI2C_MSR_DMF [1/3]

#define LPI2C_MSR_DMF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)

DMF - Data Match Flag 0b0..Have not received matching data 0b1..Have received matching data

◆ LPI2C_MSR_DMF [2/3]

#define LPI2C_MSR_DMF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)

DMF - Data Match Flag 0b0..Have not received matching data 0b1..Have received matching data

◆ LPI2C_MSR_DMF [3/3]

#define LPI2C_MSR_DMF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)

DMF - Data Match Flag 0b0..Have not received matching data 0b1..Have received matching data

◆ LPI2C_MSR_EPF [1/3]

#define LPI2C_MSR_EPF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)

EPF - End Packet Flag 0b0..Master has not generated a STOP or Repeated START condition 0b1..Master has generated a STOP or Repeated START condition

◆ LPI2C_MSR_EPF [2/3]

#define LPI2C_MSR_EPF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)

EPF - End Packet Flag 0b0..Master has not generated a STOP or Repeated START condition 0b1..Master has generated a STOP or Repeated START condition

◆ LPI2C_MSR_EPF [3/3]

#define LPI2C_MSR_EPF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)

EPF - End Packet Flag 0b0..Master has not generated a STOP or Repeated START condition 0b1..Master has generated a STOP or Repeated START condition

◆ LPI2C_MSR_FEF [1/3]

#define LPI2C_MSR_FEF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)

FEF - FIFO Error Flag 0b0..No error 0b1..Master sending or receiving data without a START condition

◆ LPI2C_MSR_FEF [2/3]

#define LPI2C_MSR_FEF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)

FEF - FIFO Error Flag 0b0..No error 0b1..Master sending or receiving data without a START condition

◆ LPI2C_MSR_FEF [3/3]

#define LPI2C_MSR_FEF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)

FEF - FIFO Error Flag 0b0..No error 0b1..Master sending or receiving data without a START condition

◆ LPI2C_MSR_MBF [1/3]

#define LPI2C_MSR_MBF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)

MBF - Master Busy Flag 0b0..I2C Master is idle 0b1..I2C Master is busy

◆ LPI2C_MSR_MBF [2/3]

#define LPI2C_MSR_MBF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)

MBF - Master Busy Flag 0b0..I2C Master is idle 0b1..I2C Master is busy

◆ LPI2C_MSR_MBF [3/3]

#define LPI2C_MSR_MBF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)

MBF - Master Busy Flag 0b0..I2C Master is idle 0b1..I2C Master is busy

◆ LPI2C_MSR_NDF [1/3]

#define LPI2C_MSR_NDF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)

NDF - NACK Detect Flag 0b0..Unexpected NACK was not detected 0b1..Unexpected NACK was detected

◆ LPI2C_MSR_NDF [2/3]

#define LPI2C_MSR_NDF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)

NDF - NACK Detect Flag 0b0..Unexpected NACK was not detected 0b1..Unexpected NACK was detected

◆ LPI2C_MSR_NDF [3/3]

#define LPI2C_MSR_NDF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)

NDF - NACK Detect Flag 0b0..Unexpected NACK was not detected 0b1..Unexpected NACK was detected

◆ LPI2C_MSR_PLTF [1/3]

#define LPI2C_MSR_PLTF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)

PLTF - Pin Low Timeout Flag 0b0..Pin low timeout has not occurred or is disabled 0b1..Pin low timeout has occurred

◆ LPI2C_MSR_PLTF [2/3]

#define LPI2C_MSR_PLTF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)

PLTF - Pin Low Timeout Flag 0b0..Pin low timeout has not occurred or is disabled 0b1..Pin low timeout has occurred

◆ LPI2C_MSR_PLTF [3/3]

#define LPI2C_MSR_PLTF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)

PLTF - Pin Low Timeout Flag 0b0..Pin low timeout has not occurred or is disabled 0b1..Pin low timeout has occurred

◆ LPI2C_MSR_RDF [1/3]

#define LPI2C_MSR_RDF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)

RDF - Receive Data Flag 0b0..Receive Data is not ready 0b1..Receive data is ready

◆ LPI2C_MSR_RDF [2/3]

#define LPI2C_MSR_RDF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)

RDF - Receive Data Flag 0b0..Receive Data is not ready 0b1..Receive data is ready

◆ LPI2C_MSR_RDF [3/3]

#define LPI2C_MSR_RDF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)

RDF - Receive Data Flag 0b0..Receive Data is not ready 0b1..Receive data is ready

◆ LPI2C_MSR_SDF [1/3]

#define LPI2C_MSR_SDF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)

SDF - STOP Detect Flag 0b0..Master has not generated a STOP condition 0b1..Master has generated a STOP condition

◆ LPI2C_MSR_SDF [2/3]

#define LPI2C_MSR_SDF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)

SDF - STOP Detect Flag 0b0..Master has not generated a STOP condition 0b1..Master has generated a STOP condition

◆ LPI2C_MSR_SDF [3/3]

#define LPI2C_MSR_SDF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)

SDF - STOP Detect Flag 0b0..Master has not generated a STOP condition 0b1..Master has generated a STOP condition

◆ LPI2C_MSR_TDF [1/3]

#define LPI2C_MSR_TDF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)

TDF - Transmit Data Flag 0b0..Transmit data is not requested 0b1..Transmit data is requested

◆ LPI2C_MSR_TDF [2/3]

#define LPI2C_MSR_TDF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)

TDF - Transmit Data Flag 0b0..Transmit data is not requested 0b1..Transmit data is requested

◆ LPI2C_MSR_TDF [3/3]

#define LPI2C_MSR_TDF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)

TDF - Transmit Data Flag 0b0..Transmit data is not requested 0b1..Transmit data is requested

◆ LPI2C_MTDR_CMD [1/3]

#define LPI2C_MTDR_CMD ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)

CMD - Command Data 0b000..Transmit DATA[7:0] 0b001..Receive (DATA[7:0] + 1) bytes 0b010..Generate STOP condition 0b011..Receive and discard (DATA[7:0] + 1) bytes 0b100..Generate (repeated) START and transmit address in DATA[7:0] 0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. 0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode 0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned.

◆ LPI2C_MTDR_CMD [2/3]

#define LPI2C_MTDR_CMD ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)

CMD - Command Data 0b000..Transmit DATA[7:0] 0b001..Receive (DATA[7:0] + 1) bytes 0b010..Generate STOP condition 0b011..Receive and discard (DATA[7:0] + 1) bytes 0b100..Generate (repeated) START and transmit address in DATA[7:0] 0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. 0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode 0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned.

◆ LPI2C_MTDR_CMD [3/3]

#define LPI2C_MTDR_CMD ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)

CMD - Command Data 0b000..Transmit DATA[7:0] 0b001..Receive (DATA[7:0] + 1) bytes 0b010..Generate STOP condition 0b011..Receive and discard (DATA[7:0] + 1) bytes 0b100..Generate (repeated) START and transmit address in DATA[7:0] 0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. 0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode 0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned.

◆ LPI2C_MTDR_DATA [1/3]

#define LPI2C_MTDR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)

DATA - Transmit Data

◆ LPI2C_MTDR_DATA [2/3]

#define LPI2C_MTDR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)

DATA - Transmit Data

◆ LPI2C_MTDR_DATA [3/3]

#define LPI2C_MTDR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)

DATA - Transmit Data

◆ LPI2C_PARAM_MRXFIFO [1/3]

#define LPI2C_PARAM_MRXFIFO ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)

MRXFIFO - Master Receive FIFO Size

◆ LPI2C_PARAM_MRXFIFO [2/3]

#define LPI2C_PARAM_MRXFIFO ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)

MRXFIFO - Master Receive FIFO Size

◆ LPI2C_PARAM_MRXFIFO [3/3]

#define LPI2C_PARAM_MRXFIFO ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)

MRXFIFO - Master Receive FIFO Size

◆ LPI2C_PARAM_MTXFIFO [1/3]

#define LPI2C_PARAM_MTXFIFO ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)

MTXFIFO - Master Transmit FIFO Size

◆ LPI2C_PARAM_MTXFIFO [2/3]

#define LPI2C_PARAM_MTXFIFO ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)

MTXFIFO - Master Transmit FIFO Size

◆ LPI2C_PARAM_MTXFIFO [3/3]

#define LPI2C_PARAM_MTXFIFO ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)

MTXFIFO - Master Transmit FIFO Size

◆ LPI2C_SAMR_ADDR0 [1/3]

#define LPI2C_SAMR_ADDR0 ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)

ADDR0 - Address 0 Value

◆ LPI2C_SAMR_ADDR0 [2/3]

#define LPI2C_SAMR_ADDR0 ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)

ADDR0 - Address 0 Value

◆ LPI2C_SAMR_ADDR0 [3/3]

#define LPI2C_SAMR_ADDR0 ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)

ADDR0 - Address 0 Value

◆ LPI2C_SAMR_ADDR1 [1/3]

#define LPI2C_SAMR_ADDR1 ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)

ADDR1 - Address 1 Value

◆ LPI2C_SAMR_ADDR1 [2/3]

#define LPI2C_SAMR_ADDR1 ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)

ADDR1 - Address 1 Value

◆ LPI2C_SAMR_ADDR1 [3/3]

#define LPI2C_SAMR_ADDR1 ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)

ADDR1 - Address 1 Value

◆ LPI2C_SASR_ANV [1/3]

#define LPI2C_SASR_ANV ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)

ANV - Address Not Valid 0b0..Received Address (RADDR) is valid 0b1..Received Address (RADDR) is not valid

◆ LPI2C_SASR_ANV [2/3]

#define LPI2C_SASR_ANV ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)

ANV - Address Not Valid 0b0..Received Address (RADDR) is valid 0b1..Received Address (RADDR) is not valid

◆ LPI2C_SASR_ANV [3/3]

#define LPI2C_SASR_ANV ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)

ANV - Address Not Valid 0b0..Received Address (RADDR) is valid 0b1..Received Address (RADDR) is not valid

◆ LPI2C_SASR_RADDR [1/3]

#define LPI2C_SASR_RADDR ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)

RADDR - Received Address

◆ LPI2C_SASR_RADDR [2/3]

#define LPI2C_SASR_RADDR ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)

RADDR - Received Address

◆ LPI2C_SASR_RADDR [3/3]

#define LPI2C_SASR_RADDR ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)

RADDR - Received Address

◆ LPI2C_SCFGR1_ACKSTALL [1/3]

#define LPI2C_SCFGR1_ACKSTALL ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)

ACKSTALL - ACK SCL Stall 0b0..Clock stretching is disabled 0b1..Clock stretching is enabled

◆ LPI2C_SCFGR1_ACKSTALL [2/3]

#define LPI2C_SCFGR1_ACKSTALL ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)

ACKSTALL - ACK SCL Stall 0b0..Clock stretching is disabled 0b1..Clock stretching is enabled

◆ LPI2C_SCFGR1_ACKSTALL [3/3]

#define LPI2C_SCFGR1_ACKSTALL ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)

ACKSTALL - ACK SCL Stall 0b0..Clock stretching is disabled 0b1..Clock stretching is enabled

◆ LPI2C_SCFGR1_ADDRCFG [1/3]

#define LPI2C_SCFGR1_ADDRCFG ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)

ADDRCFG - Address Configuration 0b000..Address match 0 (7-bit) 0b001..Address match 0 (10-bit) 0b010..Address match 0 (7-bit) or Address match 1 (7-bit) 0b011..Address match 0 (10-bit) or Address match 1 (10-bit) 0b100..Address match 0 (7-bit) or Address match 1 (10-bit) 0b101..Address match 0 (10-bit) or Address match 1 (7-bit) 0b110..From Address match 0 (7-bit) to Address match 1 (7-bit) 0b111..From Address match 0 (10-bit) to Address match 1 (10-bit)

◆ LPI2C_SCFGR1_ADDRCFG [2/3]

#define LPI2C_SCFGR1_ADDRCFG ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)

ADDRCFG - Address Configuration 0b000..Address match 0 (7-bit) 0b001..Address match 0 (10-bit) 0b010..Address match 0 (7-bit) or Address match 1 (7-bit) 0b011..Address match 0 (10-bit) or Address match 1 (10-bit) 0b100..Address match 0 (7-bit) or Address match 1 (10-bit) 0b101..Address match 0 (10-bit) or Address match 1 (7-bit) 0b110..From Address match 0 (7-bit) to Address match 1 (7-bit) 0b111..From Address match 0 (10-bit) to Address match 1 (10-bit)

◆ LPI2C_SCFGR1_ADDRCFG [3/3]

#define LPI2C_SCFGR1_ADDRCFG ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)

ADDRCFG - Address Configuration 0b000..Address match 0 (7-bit) 0b001..Address match 0 (10-bit) 0b010..Address match 0 (7-bit) or Address match 1 (7-bit) 0b011..Address match 0 (10-bit) or Address match 1 (10-bit) 0b100..Address match 0 (7-bit) or Address match 1 (10-bit) 0b101..Address match 0 (10-bit) or Address match 1 (7-bit) 0b110..From Address match 0 (7-bit) to Address match 1 (7-bit) 0b111..From Address match 0 (10-bit) to Address match 1 (10-bit)

◆ LPI2C_SCFGR1_ADRSTALL [1/3]

#define LPI2C_SCFGR1_ADRSTALL ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)

ADRSTALL - Address SCL Stall 0b0..Clock stretching is disabled 0b1..Clock stretching is enabled

◆ LPI2C_SCFGR1_ADRSTALL [2/3]

#define LPI2C_SCFGR1_ADRSTALL ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)

ADRSTALL - Address SCL Stall 0b0..Clock stretching is disabled 0b1..Clock stretching is enabled

◆ LPI2C_SCFGR1_ADRSTALL [3/3]

#define LPI2C_SCFGR1_ADRSTALL ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)

ADRSTALL - Address SCL Stall 0b0..Clock stretching is disabled 0b1..Clock stretching is enabled

◆ LPI2C_SCFGR1_GCEN [1/3]

#define LPI2C_SCFGR1_GCEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)

GCEN - General Call Enable 0b0..General Call address is disabled 0b1..General Call address is enabled

◆ LPI2C_SCFGR1_GCEN [2/3]

#define LPI2C_SCFGR1_GCEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)

GCEN - General Call Enable 0b0..General Call address is disabled 0b1..General Call address is enabled

◆ LPI2C_SCFGR1_GCEN [3/3]

#define LPI2C_SCFGR1_GCEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)

GCEN - General Call Enable 0b0..General Call address is disabled 0b1..General Call address is enabled

◆ LPI2C_SCFGR1_HSMEN [1/3]

#define LPI2C_SCFGR1_HSMEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)

HSMEN - High Speed Mode Enable 0b0..Disables detection of HS-mode master code 0b1..Enables detection of HS-mode master code

◆ LPI2C_SCFGR1_HSMEN [2/3]

#define LPI2C_SCFGR1_HSMEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)

HSMEN - High Speed Mode Enable 0b0..Disables detection of HS-mode master code 0b1..Enables detection of HS-mode master code

◆ LPI2C_SCFGR1_HSMEN [3/3]

#define LPI2C_SCFGR1_HSMEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)

HSMEN - High Speed Mode Enable 0b0..Disables detection of HS-mode master code 0b1..Enables detection of HS-mode master code

◆ LPI2C_SCFGR1_IGNACK [1/3]

#define LPI2C_SCFGR1_IGNACK ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)

IGNACK - Ignore NACK 0b0..Slave will end transfer when NACK is detected 0b1..Slave will not end transfer when NACK detected

◆ LPI2C_SCFGR1_IGNACK [2/3]

#define LPI2C_SCFGR1_IGNACK ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)

IGNACK - Ignore NACK 0b0..Slave ends transfer when NACK is detected 0b1..Slave does not end transfer when NACK detected

◆ LPI2C_SCFGR1_IGNACK [3/3]

#define LPI2C_SCFGR1_IGNACK ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)

IGNACK - Ignore NACK 0b0..Slave ends transfer when NACK is detected 0b1..Slave does not end transfer when NACK detected

◆ LPI2C_SCFGR1_RXCFG [1/3]

#define LPI2C_SCFGR1_RXCFG ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)

RXCFG - Receive Data Configuration 0b0..Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]). 0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]).

◆ LPI2C_SCFGR1_RXCFG [2/3]

#define LPI2C_SCFGR1_RXCFG ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)

RXCFG - Receive Data Configuration 0b0..Reading the Receive Data register returns received data and clears the Receive Data flag (MSR[RDF]). 0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, returns the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, returns received data and clears the Receive Data flag (MSR[RDF]).

◆ LPI2C_SCFGR1_RXCFG [3/3]

#define LPI2C_SCFGR1_RXCFG ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)

RXCFG - Receive Data Configuration 0b0..Reading the Receive Data register returns received data and clears the Receive Data flag (MSR[RDF]). 0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, returns the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, returns received data and clears the Receive Data flag (MSR[RDF]).

◆ LPI2C_SCFGR1_RXSTALL [1/3]

#define LPI2C_SCFGR1_RXSTALL ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)

RXSTALL - RX SCL Stall 0b0..Clock stretching is disabled 0b1..Clock stretching is enabled

◆ LPI2C_SCFGR1_RXSTALL [2/3]

#define LPI2C_SCFGR1_RXSTALL ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)

RXSTALL - RX SCL Stall 0b0..Clock stretching is disabled 0b1..Clock stretching is enabled

◆ LPI2C_SCFGR1_RXSTALL [3/3]

#define LPI2C_SCFGR1_RXSTALL ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)

RXSTALL - RX SCL Stall 0b0..Clock stretching is disabled 0b1..Clock stretching is enabled

◆ LPI2C_SCFGR1_SAEN [1/3]

#define LPI2C_SCFGR1_SAEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)

SAEN - SMBus Alert Enable 0b0..Disables match on SMBus Alert 0b1..Enables match on SMBus Alert

◆ LPI2C_SCFGR1_SAEN [2/3]

#define LPI2C_SCFGR1_SAEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)

SAEN - SMBus Alert Enable 0b0..Disables match on SMBus Alert 0b1..Enables match on SMBus Alert

◆ LPI2C_SCFGR1_SAEN [3/3]

#define LPI2C_SCFGR1_SAEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)

SAEN - SMBus Alert Enable 0b0..Disables match on SMBus Alert 0b1..Enables match on SMBus Alert

◆ LPI2C_SCFGR1_TXCFG [1/3]

#define LPI2C_SCFGR1_TXCFG ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)

TXCFG - Transmit Flag Configuration 0b0..Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty 0b1..Transmit Data Flag will assert whenever the Transmit Data register is empty

◆ LPI2C_SCFGR1_TXCFG [2/3]

#define LPI2C_SCFGR1_TXCFG ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)

TXCFG - Transmit Flag Configuration 0b0..Transmit Data Flag only asserts during a slave-transmit transfer when the Transmit Data register is empty 0b1..Transmit Data Flag asserts whenever the Transmit Data register is empty

◆ LPI2C_SCFGR1_TXCFG [3/3]

#define LPI2C_SCFGR1_TXCFG ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)

TXCFG - Transmit Flag Configuration 0b0..Transmit Data Flag only asserts during a slave-transmit transfer when the Transmit Data register is empty 0b1..Transmit Data Flag asserts whenever the Transmit Data register is empty

◆ LPI2C_SCFGR1_TXDSTALL [1/3]

#define LPI2C_SCFGR1_TXDSTALL ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)

TXDSTALL - TX Data SCL Stall 0b0..Clock stretching is disabled 0b1..Clock stretching is enabled

◆ LPI2C_SCFGR1_TXDSTALL [2/3]

#define LPI2C_SCFGR1_TXDSTALL ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)

TXDSTALL - TX Data SCL Stall 0b0..Clock stretching is disabled 0b1..Clock stretching is enabled

◆ LPI2C_SCFGR1_TXDSTALL [3/3]

#define LPI2C_SCFGR1_TXDSTALL ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)

TXDSTALL - TX Data SCL Stall 0b0..Clock stretching is disabled 0b1..Clock stretching is enabled

◆ LPI2C_SCFGR2_CLKHOLD [1/3]

#define LPI2C_SCFGR2_CLKHOLD ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)

CLKHOLD - Clock Hold Time

◆ LPI2C_SCFGR2_CLKHOLD [2/3]

#define LPI2C_SCFGR2_CLKHOLD ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)

CLKHOLD - Clock Hold Time

◆ LPI2C_SCFGR2_CLKHOLD [3/3]

#define LPI2C_SCFGR2_CLKHOLD ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)

CLKHOLD - Clock Hold Time

◆ LPI2C_SCFGR2_DATAVD [1/3]

#define LPI2C_SCFGR2_DATAVD ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)

DATAVD - Data Valid Delay

◆ LPI2C_SCFGR2_DATAVD [2/3]

#define LPI2C_SCFGR2_DATAVD ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)

DATAVD - Data Valid Delay

◆ LPI2C_SCFGR2_DATAVD [3/3]

#define LPI2C_SCFGR2_DATAVD ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)

DATAVD - Data Valid Delay

◆ LPI2C_SCFGR2_FILTSCL [1/3]

#define LPI2C_SCFGR2_FILTSCL ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)

FILTSCL - Glitch Filter SCL

◆ LPI2C_SCFGR2_FILTSCL [2/3]

#define LPI2C_SCFGR2_FILTSCL ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)

FILTSCL - Glitch Filter SCL

◆ LPI2C_SCFGR2_FILTSCL [3/3]

#define LPI2C_SCFGR2_FILTSCL ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)

FILTSCL - Glitch Filter SCL

◆ LPI2C_SCFGR2_FILTSDA [1/3]

#define LPI2C_SCFGR2_FILTSDA ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)

FILTSDA - Glitch Filter SDA

◆ LPI2C_SCFGR2_FILTSDA [2/3]

#define LPI2C_SCFGR2_FILTSDA ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)

FILTSDA - Glitch Filter SDA

◆ LPI2C_SCFGR2_FILTSDA [3/3]

#define LPI2C_SCFGR2_FILTSDA ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)

FILTSDA - Glitch Filter SDA

◆ LPI2C_SCR_FILTDZ [1/3]

#define LPI2C_SCR_FILTDZ ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)

FILTDZ - Filter Doze Enable 0b0..Filter remains enabled in Doze mode 0b1..Filter is disabled in Doze mode

◆ LPI2C_SCR_FILTDZ [2/3]

#define LPI2C_SCR_FILTDZ ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)

FILTDZ - Filter Doze Enable 0b0..Filter remains enabled in Doze mode 0b1..Filter is disabled in Doze mode

◆ LPI2C_SCR_FILTDZ [3/3]

#define LPI2C_SCR_FILTDZ ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)

FILTDZ - Filter Doze Enable 0b0..Filter remains enabled in Doze mode 0b1..Filter is disabled in Doze mode

◆ LPI2C_SCR_FILTEN [1/3]

#define LPI2C_SCR_FILTEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)

FILTEN - Filter Enable 0b0..Disable digital filter and output delay counter for slave mode 0b1..Enable digital filter and output delay counter for slave mode

◆ LPI2C_SCR_FILTEN [2/3]

#define LPI2C_SCR_FILTEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)

FILTEN - Filter Enable 0b0..Disable digital filter and output delay counter for slave mode 0b1..Enable digital filter and output delay counter for slave mode

◆ LPI2C_SCR_FILTEN [3/3]

#define LPI2C_SCR_FILTEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)

FILTEN - Filter Enable 0b0..Disable digital filter and output delay counter for slave mode 0b1..Enable digital filter and output delay counter for slave mode

◆ LPI2C_SCR_RRF [1/3]

#define LPI2C_SCR_RRF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)

RRF - Reset Receive FIFO 0b0..No effect 0b1..Receive Data Register is now empty

◆ LPI2C_SCR_RRF [2/3]

#define LPI2C_SCR_RRF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)

RRF - Reset Receive FIFO 0b0..No effect 0b1..Receive Data Register is now empty

◆ LPI2C_SCR_RRF [3/3]

#define LPI2C_SCR_RRF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)

RRF - Reset Receive FIFO 0b0..No effect 0b1..Receive Data Register is now empty

◆ LPI2C_SCR_RST [1/3]

#define LPI2C_SCR_RST ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)

RST - Software Reset 0b0..Slave mode logic is not reset 0b1..Slave mode logic is reset

◆ LPI2C_SCR_RST [2/3]

#define LPI2C_SCR_RST ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)

RST - Software Reset 0b0..Slave mode logic is not reset 0b1..Slave mode logic is reset

◆ LPI2C_SCR_RST [3/3]

#define LPI2C_SCR_RST ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)

RST - Software Reset 0b0..Slave mode logic is not reset 0b1..Slave mode logic is reset

◆ LPI2C_SCR_RTF [1/3]

#define LPI2C_SCR_RTF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)

RTF - Reset Transmit FIFO 0b0..No effect 0b1..Transmit Data Register is now empty

◆ LPI2C_SCR_RTF [2/3]

#define LPI2C_SCR_RTF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)

RTF - Reset Transmit FIFO 0b0..No effect 0b1..Transmit Data Register is now empty

◆ LPI2C_SCR_RTF [3/3]

#define LPI2C_SCR_RTF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)

RTF - Reset Transmit FIFO 0b0..No effect 0b1..Transmit Data Register is now empty

◆ LPI2C_SCR_SEN [1/3]

#define LPI2C_SCR_SEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)

SEN - Slave Enable 0b0..I2C Slave mode is disabled 0b1..I2C Slave mode is enabled

◆ LPI2C_SCR_SEN [2/3]

#define LPI2C_SCR_SEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)

SEN - Slave Enable 0b0..I2C Slave mode is disabled 0b1..I2C Slave mode is enabled

◆ LPI2C_SCR_SEN [3/3]

#define LPI2C_SCR_SEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)

SEN - Slave Enable 0b0..I2C Slave mode is disabled 0b1..I2C Slave mode is enabled

◆ LPI2C_SDER_AVDE [1/3]

#define LPI2C_SDER_AVDE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)

AVDE - Address Valid DMA Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

◆ LPI2C_SDER_AVDE [2/3]

#define LPI2C_SDER_AVDE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)

AVDE - Address Valid DMA Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

◆ LPI2C_SDER_AVDE [3/3]

#define LPI2C_SDER_AVDE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)

AVDE - Address Valid DMA Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

◆ LPI2C_SDER_RDDE [1/3]

#define LPI2C_SDER_RDDE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)

RDDE - Receive Data DMA Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

◆ LPI2C_SDER_RDDE [2/3]

#define LPI2C_SDER_RDDE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)

RDDE - Receive Data DMA Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

◆ LPI2C_SDER_RDDE [3/3]

#define LPI2C_SDER_RDDE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)

RDDE - Receive Data DMA Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

◆ LPI2C_SDER_TDDE [1/3]

#define LPI2C_SDER_TDDE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)

TDDE - Transmit Data DMA Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

◆ LPI2C_SDER_TDDE [2/3]

#define LPI2C_SDER_TDDE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)

TDDE - Transmit Data DMA Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

◆ LPI2C_SDER_TDDE [3/3]

#define LPI2C_SDER_TDDE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)

TDDE - Transmit Data DMA Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

◆ LPI2C_SIER_AM0IE [1/3]

#define LPI2C_SIER_AM0IE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)

AM0IE - Address Match 0 Interrupt Enable 0b0..Enabled 0b1..Disabled

◆ LPI2C_SIER_AM0IE [2/3]

#define LPI2C_SIER_AM0IE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)

AM0IE - Address Match 0 Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_AM0IE [3/3]

#define LPI2C_SIER_AM0IE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)

AM0IE - Address Match 0 Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_AM1F

#define LPI2C_SIER_AM1F ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)

AM1F - Address Match 1 Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_AM1IE [1/2]

#define LPI2C_SIER_AM1IE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK)

AM1IE - Address Match 1 Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_AM1IE [2/2]

#define LPI2C_SIER_AM1IE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK)

AM1IE - Address Match 1 Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_AVIE [1/3]

#define LPI2C_SIER_AVIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)

AVIE - Address Valid Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_AVIE [2/3]

#define LPI2C_SIER_AVIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)

AVIE - Address Valid Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_AVIE [3/3]

#define LPI2C_SIER_AVIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)

AVIE - Address Valid Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_BEIE [1/3]

#define LPI2C_SIER_BEIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)

BEIE - Bit Error Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_BEIE [2/3]

#define LPI2C_SIER_BEIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)

BEIE - Bit Error Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_BEIE [3/3]

#define LPI2C_SIER_BEIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)

BEIE - Bit Error Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_FEIE [1/3]

#define LPI2C_SIER_FEIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)

FEIE - FIFO Error Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_FEIE [2/3]

#define LPI2C_SIER_FEIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)

FEIE - FIFO Error Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_FEIE [3/3]

#define LPI2C_SIER_FEIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)

FEIE - FIFO Error Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_GCIE [1/3]

#define LPI2C_SIER_GCIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)

GCIE - General Call Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_GCIE [2/3]

#define LPI2C_SIER_GCIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)

GCIE - General Call Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_GCIE [3/3]

#define LPI2C_SIER_GCIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)

GCIE - General Call Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_RDIE [1/3]

#define LPI2C_SIER_RDIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)

RDIE - Receive Data Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_RDIE [2/3]

#define LPI2C_SIER_RDIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)

RDIE - Receive Data Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_RDIE [3/3]

#define LPI2C_SIER_RDIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)

RDIE - Receive Data Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_RSIE [1/3]

#define LPI2C_SIER_RSIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)

RSIE - Repeated Start Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_RSIE [2/3]

#define LPI2C_SIER_RSIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)

RSIE - Repeated Start Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_RSIE [3/3]

#define LPI2C_SIER_RSIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)

RSIE - Repeated Start Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_SARIE [1/3]

#define LPI2C_SIER_SARIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)

SARIE - SMBus Alert Response Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_SARIE [2/3]

#define LPI2C_SIER_SARIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)

SARIE - SMBus Alert Response Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_SARIE [3/3]

#define LPI2C_SIER_SARIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)

SARIE - SMBus Alert Response Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_SDIE [1/3]

#define LPI2C_SIER_SDIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)

SDIE - STOP Detect Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_SDIE [2/3]

#define LPI2C_SIER_SDIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)

SDIE - STOP Detect Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_SDIE [3/3]

#define LPI2C_SIER_SDIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)

SDIE - STOP Detect Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_TAIE [1/3]

#define LPI2C_SIER_TAIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)

TAIE - Transmit ACK Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_TAIE [2/3]

#define LPI2C_SIER_TAIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)

TAIE - Transmit ACK Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_TAIE [3/3]

#define LPI2C_SIER_TAIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)

TAIE - Transmit ACK Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_TDIE [1/3]

#define LPI2C_SIER_TDIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)

TDIE - Transmit Data Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_TDIE [2/3]

#define LPI2C_SIER_TDIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)

TDIE - Transmit Data Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SIER_TDIE [3/3]

#define LPI2C_SIER_TDIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)

TDIE - Transmit Data Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ LPI2C_SRDR_DATA [1/3]

#define LPI2C_SRDR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)

DATA - Receive Data

◆ LPI2C_SRDR_DATA [2/3]

#define LPI2C_SRDR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)

DATA - Receive Data

◆ LPI2C_SRDR_DATA [3/3]

#define LPI2C_SRDR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)

DATA - Receive Data

◆ LPI2C_SRDR_RXEMPTY [1/3]

#define LPI2C_SRDR_RXEMPTY ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)

RXEMPTY - RX Empty 0b0..The Receive Data Register is not empty 0b1..The Receive Data Register is empty

◆ LPI2C_SRDR_RXEMPTY [2/3]

#define LPI2C_SRDR_RXEMPTY ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)

RXEMPTY - RX Empty 0b0..The Receive Data Register is not empty 0b1..The Receive Data Register is empty

◆ LPI2C_SRDR_RXEMPTY [3/3]

#define LPI2C_SRDR_RXEMPTY ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)

RXEMPTY - RX Empty 0b0..The Receive Data Register is not empty 0b1..The Receive Data Register is empty

◆ LPI2C_SRDR_SOF [1/3]

#define LPI2C_SRDR_SOF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)

SOF - Start Of Frame 0b0..Indicates this is not the first data word since a (repeated) START or STOP condition 0b1..Indicates this is the first data word since a (repeated) START or STOP condition

◆ LPI2C_SRDR_SOF [2/3]

#define LPI2C_SRDR_SOF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)

SOF - Start Of Frame 0b0..Indicates this is not the first data word since a (repeated) START or STOP condition 0b1..Indicates this is the first data word since a (repeated) START or STOP condition

◆ LPI2C_SRDR_SOF [3/3]

#define LPI2C_SRDR_SOF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)

SOF - Start Of Frame 0b0..Indicates this is not the first data word since a (repeated) START or STOP condition 0b1..Indicates this is the first data word since a (repeated) START or STOP condition

◆ LPI2C_SSR_AM0F [1/3]

#define LPI2C_SSR_AM0F ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)

AM0F - Address Match 0 Flag 0b0..Have not received an ADDR0 matching address 0b1..Have received an ADDR0 matching address

◆ LPI2C_SSR_AM0F [2/3]

#define LPI2C_SSR_AM0F ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)

AM0F - Address Match 0 Flag 0b0..Have not received an ADDR0 matching address 0b1..Have received an ADDR0 matching address

◆ LPI2C_SSR_AM0F [3/3]

#define LPI2C_SSR_AM0F ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)

AM0F - Address Match 0 Flag 0b0..Have not received an ADDR0 matching address 0b1..Have received an ADDR0 matching address

◆ LPI2C_SSR_AM1F [1/3]

#define LPI2C_SSR_AM1F ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)

AM1F - Address Match 1 Flag 0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address 0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address

◆ LPI2C_SSR_AM1F [2/3]

#define LPI2C_SSR_AM1F ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)

AM1F - Address Match 1 Flag 0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address 0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address

◆ LPI2C_SSR_AM1F [3/3]

#define LPI2C_SSR_AM1F ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)

AM1F - Address Match 1 Flag 0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address 0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address

◆ LPI2C_SSR_AVF [1/3]

#define LPI2C_SSR_AVF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)

AVF - Address Valid Flag 0b0..Address Status Register is not valid 0b1..Address Status Register is valid

◆ LPI2C_SSR_AVF [2/3]

#define LPI2C_SSR_AVF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)

AVF - Address Valid Flag 0b0..Address Status Register is not valid 0b1..Address Status Register is valid

◆ LPI2C_SSR_AVF [3/3]

#define LPI2C_SSR_AVF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)

AVF - Address Valid Flag 0b0..Address Status Register is not valid 0b1..Address Status Register is valid

◆ LPI2C_SSR_BBF [1/3]

#define LPI2C_SSR_BBF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)

BBF - Bus Busy Flag 0b0..I2C Bus is idle 0b1..I2C Bus is busy

◆ LPI2C_SSR_BBF [2/3]

#define LPI2C_SSR_BBF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)

BBF - Bus Busy Flag 0b0..I2C Bus is idle 0b1..I2C Bus is busy

◆ LPI2C_SSR_BBF [3/3]

#define LPI2C_SSR_BBF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)

BBF - Bus Busy Flag 0b0..I2C Bus is idle 0b1..I2C Bus is busy

◆ LPI2C_SSR_BEF [1/3]

#define LPI2C_SSR_BEF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)

BEF - Bit Error Flag 0b0..Slave has not detected a bit error 0b1..Slave has detected a bit error

◆ LPI2C_SSR_BEF [2/3]

#define LPI2C_SSR_BEF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)

BEF - Bit Error Flag 0b0..Slave has not detected a bit error 0b1..Slave has detected a bit error

◆ LPI2C_SSR_BEF [3/3]

#define LPI2C_SSR_BEF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)

BEF - Bit Error Flag 0b0..Slave has not detected a bit error 0b1..Slave has detected a bit error

◆ LPI2C_SSR_FEF [1/3]

#define LPI2C_SSR_FEF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)

FEF - FIFO Error Flag 0b0..FIFO underflow or overflow was not detected 0b1..FIFO underflow or overflow was detected

◆ LPI2C_SSR_FEF [2/3]

#define LPI2C_SSR_FEF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)

FEF - FIFO Error Flag 0b0..FIFO underflow or overflow was not detected 0b1..FIFO underflow or overflow was detected

◆ LPI2C_SSR_FEF [3/3]

#define LPI2C_SSR_FEF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)

FEF - FIFO Error Flag 0b0..FIFO underflow or overflow was not detected 0b1..FIFO underflow or overflow was detected

◆ LPI2C_SSR_GCF [1/3]

#define LPI2C_SSR_GCF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)

GCF - General Call Flag 0b0..Slave has not detected the General Call Address or the General Call Address is disabled 0b1..Slave has detected the General Call Address

◆ LPI2C_SSR_GCF [2/3]

#define LPI2C_SSR_GCF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)

GCF - General Call Flag 0b0..Slave has not detected the General Call Address or the General Call Address is disabled 0b1..Slave has detected the General Call Address

◆ LPI2C_SSR_GCF [3/3]

#define LPI2C_SSR_GCF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)

GCF - General Call Flag 0b0..Slave has not detected the General Call Address or the General Call Address is disabled 0b1..Slave has detected the General Call Address

◆ LPI2C_SSR_RDF [1/3]

#define LPI2C_SSR_RDF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)

RDF - Receive Data Flag 0b0..Receive data is not ready 0b1..Receive data is ready

◆ LPI2C_SSR_RDF [2/3]

#define LPI2C_SSR_RDF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)

RDF - Receive Data Flag 0b0..Receive data is not ready 0b1..Receive data is ready

◆ LPI2C_SSR_RDF [3/3]

#define LPI2C_SSR_RDF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)

RDF - Receive Data Flag 0b0..Receive data is not ready 0b1..Receive data is ready

◆ LPI2C_SSR_RSF [1/3]

#define LPI2C_SSR_RSF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)

RSF - Repeated Start Flag 0b0..Slave has not detected a Repeated START condition 0b1..Slave has detected a Repeated START condition

◆ LPI2C_SSR_RSF [2/3]

#define LPI2C_SSR_RSF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)

RSF - Repeated Start Flag 0b0..Slave has not detected a Repeated START condition 0b1..Slave has detected a Repeated START condition

◆ LPI2C_SSR_RSF [3/3]

#define LPI2C_SSR_RSF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)

RSF - Repeated Start Flag 0b0..Slave has not detected a Repeated START condition 0b1..Slave has detected a Repeated START condition

◆ LPI2C_SSR_SARF [1/3]

#define LPI2C_SSR_SARF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)

SARF - SMBus Alert Response Flag 0b0..SMBus Alert Response is disabled or not detected 0b1..SMBus Alert Response is enabled and detected

◆ LPI2C_SSR_SARF [2/3]

#define LPI2C_SSR_SARF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)

SARF - SMBus Alert Response Flag 0b0..SMBus Alert Response is disabled or not detected 0b1..SMBus Alert Response is enabled and detected

◆ LPI2C_SSR_SARF [3/3]

#define LPI2C_SSR_SARF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)

SARF - SMBus Alert Response Flag 0b0..SMBus Alert Response is disabled or not detected 0b1..SMBus Alert Response is enabled and detected

◆ LPI2C_SSR_SBF [1/3]

#define LPI2C_SSR_SBF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)

SBF - Slave Busy Flag 0b0..I2C Slave is idle 0b1..I2C Slave is busy

◆ LPI2C_SSR_SBF [2/3]

#define LPI2C_SSR_SBF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)

SBF - Slave Busy Flag 0b0..I2C Slave is idle 0b1..I2C Slave is busy

◆ LPI2C_SSR_SBF [3/3]

#define LPI2C_SSR_SBF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)

SBF - Slave Busy Flag 0b0..I2C Slave is idle 0b1..I2C Slave is busy

◆ LPI2C_SSR_SDF [1/3]

#define LPI2C_SSR_SDF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)

SDF - STOP Detect Flag 0b0..Slave has not detected a STOP condition 0b1..Slave has detected a STOP condition

◆ LPI2C_SSR_SDF [2/3]

#define LPI2C_SSR_SDF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)

SDF - STOP Detect Flag 0b0..Slave has not detected a STOP condition 0b1..Slave has detected a STOP condition

◆ LPI2C_SSR_SDF [3/3]

#define LPI2C_SSR_SDF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)

SDF - STOP Detect Flag 0b0..Slave has not detected a STOP condition 0b1..Slave has detected a STOP condition

◆ LPI2C_SSR_TAF [1/3]

#define LPI2C_SSR_TAF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)

TAF - Transmit ACK Flag 0b0..Transmit ACK/NACK is not required 0b1..Transmit ACK/NACK is required

◆ LPI2C_SSR_TAF [2/3]

#define LPI2C_SSR_TAF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)

TAF - Transmit ACK Flag 0b0..Transmit ACK/NACK is not required 0b1..Transmit ACK/NACK is required

◆ LPI2C_SSR_TAF [3/3]

#define LPI2C_SSR_TAF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)

TAF - Transmit ACK Flag 0b0..Transmit ACK/NACK is not required 0b1..Transmit ACK/NACK is required

◆ LPI2C_SSR_TDF [1/3]

#define LPI2C_SSR_TDF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)

TDF - Transmit Data Flag 0b0..Transmit data not requested 0b1..Transmit data is requested

◆ LPI2C_SSR_TDF [2/3]

#define LPI2C_SSR_TDF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)

TDF - Transmit Data Flag 0b0..Transmit data not requested 0b1..Transmit data is requested

◆ LPI2C_SSR_TDF [3/3]

#define LPI2C_SSR_TDF ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)

TDF - Transmit Data Flag 0b0..Transmit data not requested 0b1..Transmit data is requested

◆ LPI2C_STAR_TXNACK [1/3]

#define LPI2C_STAR_TXNACK ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)

TXNACK - Transmit NACK 0b0..Write a Transmit ACK for each received word 0b1..Write a Transmit NACK for each received word

◆ LPI2C_STAR_TXNACK [2/3]

#define LPI2C_STAR_TXNACK ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)

TXNACK - Transmit NACK 0b0..Write a Transmit ACK for each received word 0b1..Write a Transmit NACK for each received word

◆ LPI2C_STAR_TXNACK [3/3]

#define LPI2C_STAR_TXNACK ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)

TXNACK - Transmit NACK 0b0..Write a Transmit ACK for each received word 0b1..Write a Transmit NACK for each received word

◆ LPI2C_STDR_DATA [1/3]

#define LPI2C_STDR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)

DATA - Transmit Data

◆ LPI2C_STDR_DATA [2/3]

#define LPI2C_STDR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)

DATA - Transmit Data

◆ LPI2C_STDR_DATA [3/3]

#define LPI2C_STDR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)

DATA - Transmit Data

◆ LPI2C_VERID_FEATURE [1/3]

#define LPI2C_VERID_FEATURE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)

FEATURE - Feature Specification Number 0b0000000000000010..Master only, with standard feature set 0b0000000000000011..Master and slave, with standard feature set

◆ LPI2C_VERID_FEATURE [2/3]

#define LPI2C_VERID_FEATURE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)

FEATURE - Feature Specification Number 0b0000000000000010..Master only, with standard feature set 0b0000000000000011..Master and slave, with standard feature set

◆ LPI2C_VERID_FEATURE [3/3]

#define LPI2C_VERID_FEATURE ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)

FEATURE - Feature Specification Number 0b0000000000000010..Master only, with standard feature set 0b0000000000000011..Master and slave, with standard feature set

◆ LPI2C_VERID_MAJOR [1/3]

#define LPI2C_VERID_MAJOR ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)

MAJOR - Major Version Number

◆ LPI2C_VERID_MAJOR [2/3]

#define LPI2C_VERID_MAJOR ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)

MAJOR - Major Version Number

◆ LPI2C_VERID_MAJOR [3/3]

#define LPI2C_VERID_MAJOR ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)

MAJOR - Major Version Number

◆ LPI2C_VERID_MINOR [1/3]

#define LPI2C_VERID_MINOR ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)

MINOR - Minor Version Number

◆ LPI2C_VERID_MINOR [2/3]

#define LPI2C_VERID_MINOR ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)

MINOR - Minor Version Number

◆ LPI2C_VERID_MINOR [3/3]

#define LPI2C_VERID_MINOR ( x ) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)

MINOR - Minor Version Number

VERID - Version ID Register

PARAM - Parameter Register

MCR - Master Control Register

MSR - Master Status Register

MIER - Master Interrupt Enable Register

MDER - Master DMA Enable Register

MCFGR0 - Master Configuration Register 0

MCFGR1 - Master Configuration Register 1

MCFGR2 - Master Configuration Register 2

MCFGR3 - Master Configuration Register 3

MDMR - Master Data Match Register

MCCR0 - Master Clock Configuration Register 0

MCCR1 - Master Clock Configuration Register 1

MFCR - Master FIFO Control Register

MFSR - Master FIFO Status Register

MTDR - Master Transmit Data Register

MRDR - Master Receive Data Register

SCR - Slave Control Register

SSR - Slave Status Register

SIER - Slave Interrupt Enable Register

SDER - Slave DMA Enable Register

SCFGR1 - Slave Configuration Register 1

SCFGR2 - Slave Configuration Register 2

SAMR - Slave Address Match Register

SASR - Slave Address Status Register

STAR - Slave Transmit ACK Register

STDR - Slave Transmit Data Register

SRDR - Slave Receive Data Register

VERID - Version ID

PARAM - Parameter

MCR - Master Control

MSR - Master Status

MIER - Master Interrupt Enable

MDER - Master DMA Enable

MCFGR0 - Master Configuration 0

MCFGR1 - Master Configuration 1

MCFGR2 - Master Configuration 2

MCFGR3 - Master Configuration 3

MDMR - Master Data Match

MCCR0 - Master Clock Configuration 0

MCCR1 - Master Clock Configuration 1

MFCR - Master FIFO Control

MFSR - Master FIFO Status

MTDR - Master Transmit Data

MRDR - Master Receive Data

SCR - Slave Control

SSR - Slave Status

SIER - Slave Interrupt Enable

SDER - Slave DMA Enable

SCFGR1 - Slave Configuration 1

SCFGR2 - Slave Configuration 2

SAMR - Slave Address Match

SASR - Slave Address Status

STAR - Slave Transmit ACK

STDR - Slave Transmit Data

SRDR - Slave Receive Data

VERID - Version ID

PARAM - Parameter

MCR - Master Control

MSR - Master Status

MIER - Master Interrupt Enable

MDER - Master DMA Enable

MCFGR0 - Master Configuration 0

MCFGR1 - Master Configuration 1

MCFGR2 - Master Configuration 2

MCFGR3 - Master Configuration 3

MDMR - Master Data Match

MCCR0 - Master Clock Configuration 0

MCCR1 - Master Clock Configuration 1

MFCR - Master FIFO Control

MFSR - Master FIFO Status

MTDR - Master Transmit Data

MRDR - Master Receive Data

SCR - Slave Control

SSR - Slave Status

SIER - Slave Interrupt Enable

SDER - Slave DMA Enable

SCFGR1 - Slave Configuration 1

SCFGR2 - Slave Configuration 2

SAMR - Slave Address Match