Macros
#define	LCDIF_PIGEON_0_COUNT (12U)

#define	LCDIF_PIGEON_1_COUNT (12U)

#define	LCDIF_PIGEON_2_COUNT (12U)

#define	LCDIF_PIGEON_0_COUNT (12U)

#define	LCDIF_PIGEON_1_COUNT (12U)

#define	LCDIF_PIGEON_2_COUNT (12U)

#define	LCDIF_PIGEON_0_COUNT (12U)

#define	LCDIF_PIGEON_1_COUNT (12U)

#define	LCDIF_PIGEON_2_COUNT (12U)

CTRL - LCDIF General Control Register
#define	LCDIF_CTRL_RUN_MASK (0x1U)

#define	LCDIF_CTRL_RUN_SHIFT (0U)

#define	LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK)

#define	LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U)

#define	LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U)

#define	LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK)

#define	LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U)

#define	LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U)

#define	LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK)

#define	LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U)

#define	LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U)

#define	LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK)

#define	LCDIF_CTRL_RSRVD0_MASK (0x10U)

#define	LCDIF_CTRL_RSRVD0_SHIFT (4U)

#define	LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK)

#define	LCDIF_CTRL_MASTER_MASK (0x20U)

#define	LCDIF_CTRL_MASTER_SHIFT (5U)

#define	LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK)

#define	LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U)

#define	LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U)

#define	LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK)

#define	LCDIF_CTRL_WORD_LENGTH_MASK (0x300U)

#define	LCDIF_CTRL_WORD_LENGTH_SHIFT (8U)

#define	LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK)

#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U)

#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U)

#define	LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK)

#define	LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U)

#define	LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U)

#define	LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK)

#define	LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U)

#define	LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U)

#define	LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK)

#define	LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U)

#define	LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U)

#define	LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK)

#define	LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U)

#define	LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U)

#define	LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK)

#define	LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U)

#define	LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U)

#define	LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK)

#define	LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U)

#define	LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U)

#define	LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK)

#define	LCDIF_CTRL_CLKGATE_MASK (0x40000000U)

#define	LCDIF_CTRL_CLKGATE_SHIFT (30U)

#define	LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK)

#define	LCDIF_CTRL_SFTRST_MASK (0x80000000U)

#define	LCDIF_CTRL_SFTRST_SHIFT (31U)

#define	LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK)

CTRL_SET - LCDIF General Control Register
#define	LCDIF_CTRL_SET_RUN_MASK (0x1U)

#define	LCDIF_CTRL_SET_RUN_SHIFT (0U)

#define	LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK)

#define	LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U)

#define	LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U)

#define	LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK)

#define	LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U)

#define	LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U)

#define	LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK)

#define	LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U)

#define	LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U)

#define	LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK)

#define	LCDIF_CTRL_SET_RSRVD0_MASK (0x10U)

#define	LCDIF_CTRL_SET_RSRVD0_SHIFT (4U)

#define	LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK)

#define	LCDIF_CTRL_SET_MASTER_MASK (0x20U)

#define	LCDIF_CTRL_SET_MASTER_SHIFT (5U)

#define	LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK)

#define	LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U)

#define	LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U)

#define	LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK)

#define	LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U)

#define	LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U)

#define	LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK)

#define	LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U)

#define	LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U)

#define	LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK)

#define	LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U)

#define	LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U)

#define	LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK)

#define	LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U)

#define	LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U)

#define	LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK)

#define	LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U)

#define	LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U)

#define	LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK)

#define	LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U)

#define	LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U)

#define	LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK)

#define	LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U)

#define	LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U)

#define	LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK)

#define	LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U)

#define	LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U)

#define	LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK)

#define	LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U)

#define	LCDIF_CTRL_SET_CLKGATE_SHIFT (30U)

#define	LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK)

#define	LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U)

#define	LCDIF_CTRL_SET_SFTRST_SHIFT (31U)

#define	LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK)

CTRL_CLR - LCDIF General Control Register
#define	LCDIF_CTRL_CLR_RUN_MASK (0x1U)

#define	LCDIF_CTRL_CLR_RUN_SHIFT (0U)

#define	LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK)

#define	LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U)

#define	LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U)

#define	LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK)

#define	LCDIF_CTRL_CLR_MASTER_MASK (0x20U)

#define	LCDIF_CTRL_CLR_MASTER_SHIFT (5U)

#define	LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK)

#define	LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U)

#define	LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U)

#define	LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK)

#define	LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U)

#define	LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U)

#define	LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK)

#define	LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U)

#define	LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U)

#define	LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK)

#define	LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U)

#define	LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U)

#define	LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK)

#define	LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U)

#define	LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U)

#define	LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK)

#define	LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U)

#define	LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U)

#define	LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK)

#define	LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U)

#define	LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U)

#define	LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK)

#define	LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U)

#define	LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U)

#define	LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK)

#define	LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U)

#define	LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U)

#define	LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK)

#define	LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U)

#define	LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U)

#define	LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK)

#define	LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U)

#define	LCDIF_CTRL_CLR_SFTRST_SHIFT (31U)

#define	LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK)

CTRL_TOG - LCDIF General Control Register
#define	LCDIF_CTRL_TOG_RUN_MASK (0x1U)

#define	LCDIF_CTRL_TOG_RUN_SHIFT (0U)

#define	LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK)

#define	LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U)

#define	LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U)

#define	LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK)

#define	LCDIF_CTRL_TOG_MASTER_MASK (0x20U)

#define	LCDIF_CTRL_TOG_MASTER_SHIFT (5U)

#define	LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK)

#define	LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U)

#define	LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U)

#define	LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK)

#define	LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U)

#define	LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U)

#define	LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK)

#define	LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U)

#define	LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U)

#define	LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK)

#define	LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U)

#define	LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U)

#define	LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK)

#define	LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U)

#define	LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U)

#define	LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK)

#define	LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U)

#define	LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U)

#define	LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK)

#define	LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U)

#define	LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U)

#define	LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK)

#define	LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U)

#define	LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U)

#define	LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK)

#define	LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U)

#define	LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U)

#define	LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK)

#define	LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U)

#define	LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U)

#define	LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK)

#define	LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U)

#define	LCDIF_CTRL_TOG_SFTRST_SHIFT (31U)

#define	LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK)

CTRL1 - LCDIF General Control1 Register
#define	LCDIF_CTRL1_RSRVD0_MASK (0xF8U)

#define	LCDIF_CTRL1_RSRVD0_SHIFT (3U)

#define	LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK)

#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U)

#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U)

#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)

#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U)

#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U)

#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK)

#define	LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U)

#define	LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U)

#define	LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK)

#define	LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U)

#define	LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U)

#define	LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK)

#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)

#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U)

#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK)

#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)

#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)

#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK)

#define	LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U)

#define	LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U)

#define	LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK)

#define	LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U)

#define	LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U)

#define	LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK)

#define	LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U)

#define	LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U)

#define	LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)

#define	LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)

#define	LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)

#define	LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK)

#define	LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U)

#define	LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U)

#define	LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK)

#define	LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)

#define	LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)

#define	LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK)

#define	LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U)

#define	LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U)

#define	LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK)

#define	LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)

#define	LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U)

#define	LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK)

#define	LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U)

#define	LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U)

#define	LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK)

#define	LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U)

#define	LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U)

#define	LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK)

#define	LCDIF_CTRL1_CS_OUT_SELECT_MASK (0x40000000U)

#define	LCDIF_CTRL1_CS_OUT_SELECT_SHIFT (30U)

#define	LCDIF_CTRL1_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CS_OUT_SELECT_MASK)

#define	LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK (0x80000000U)

#define	LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT (31U)

#define	LCDIF_CTRL1_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK)

CTRL1_SET - LCDIF General Control1 Register
#define	LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U)

#define	LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U)

#define	LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK)

#define	LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U)

#define	LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U)

#define	LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK)

#define	LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U)

#define	LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U)

#define	LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK)

#define	LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U)

#define	LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U)

#define	LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK)

#define	LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U)

#define	LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U)

#define	LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK)

#define	LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)

#define	LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U)

#define	LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK)

#define	LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)

#define	LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)

#define	LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK)

#define	LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U)

#define	LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U)

#define	LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK)

#define	LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U)

#define	LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U)

#define	LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK)

#define	LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U)

#define	LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U)

#define	LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK)

#define	LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)

#define	LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)

#define	LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK)

#define	LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U)

#define	LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U)

#define	LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK)

#define	LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)

#define	LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)

#define	LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK)

#define	LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U)

#define	LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U)

#define	LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK)

#define	LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)

#define	LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U)

#define	LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK)

#define	LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U)

#define	LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U)

#define	LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK)

#define	LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U)

#define	LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U)

#define	LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK)

#define	LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK (0x40000000U)

#define	LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT (30U)

#define	LCDIF_CTRL1_SET_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK)

#define	LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK (0x80000000U)

#define	LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT (31U)

#define	LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK)

CTRL1_CLR - LCDIF General Control1 Register
#define	LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U)

#define	LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U)

#define	LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)

#define	LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U)

#define	LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U)

#define	LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK)

#define	LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U)

#define	LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U)

#define	LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK)

#define	LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U)

#define	LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U)

#define	LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK)

#define	LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U)

#define	LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U)

#define	LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK)

#define	LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)

#define	LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U)

#define	LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK)

#define	LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)

#define	LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)

#define	LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK)

#define	LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U)

#define	LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U)

#define	LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK)

#define	LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U)

#define	LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U)

#define	LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK)

#define	LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U)

#define	LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U)

#define	LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK)

#define	LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)

#define	LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)

#define	LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK)

#define	LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U)

#define	LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U)

#define	LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK)

#define	LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)

#define	LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)

#define	LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK)

#define	LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U)

#define	LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U)

#define	LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK)

#define	LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)

#define	LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U)

#define	LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK)

#define	LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U)

#define	LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U)

#define	LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK)

#define	LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U)

#define	LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U)

#define	LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK)

#define	LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK (0x40000000U)

#define	LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT (30U)

#define	LCDIF_CTRL1_CLR_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK)

#define	LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK (0x80000000U)

#define	LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT (31U)

#define	LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK)

CTRL1_TOG - LCDIF General Control1 Register
#define	LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U)

#define	LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U)

#define	LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK)

#define	LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U)

#define	LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U)

#define	LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK)

#define	LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U)

#define	LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U)

#define	LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK)

#define	LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U)

#define	LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U)

#define	LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK)

#define	LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U)

#define	LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U)

#define	LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK)

#define	LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)

#define	LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U)

#define	LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK)

#define	LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)

#define	LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)

#define	LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK)

#define	LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U)

#define	LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U)

#define	LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK)

#define	LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U)

#define	LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U)

#define	LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK)

#define	LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U)

#define	LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U)

#define	LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK)

#define	LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)

#define	LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)

#define	LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK)

#define	LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U)

#define	LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U)

#define	LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK)

#define	LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)

#define	LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)

#define	LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK)

#define	LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U)

#define	LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U)

#define	LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK)

#define	LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)

#define	LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U)

#define	LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK)

#define	LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U)

#define	LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U)

#define	LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK)

#define	LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U)

#define	LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U)

#define	LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK)

#define	LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK (0x40000000U)

#define	LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT (30U)

#define	LCDIF_CTRL1_TOG_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK)

#define	LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK (0x80000000U)

#define	LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT (31U)

#define	LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK)

CTRL2 - LCDIF General Control2 Register
#define	LCDIF_CTRL2_RSRVD0_MASK (0xFFFU)

#define	LCDIF_CTRL2_RSRVD0_SHIFT (0U)

#define	LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK)

#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U)

#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U)

#define	LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)

#define	LCDIF_CTRL2_RSRVD3_MASK (0x8000U)

#define	LCDIF_CTRL2_RSRVD3_SHIFT (15U)

#define	LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK)

#define	LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U)

#define	LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U)

#define	LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)

#define	LCDIF_CTRL2_RSRVD4_MASK (0x80000U)

#define	LCDIF_CTRL2_RSRVD4_SHIFT (19U)

#define	LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK)

#define	LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U)

#define	LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U)

#define	LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK)

#define	LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U)

#define	LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U)

#define	LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK)

#define	LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U)

#define	LCDIF_CTRL2_RSRVD5_SHIFT (24U)

#define	LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK)

CTRL2_SET - LCDIF General Control2 Register
#define	LCDIF_CTRL2_SET_RSRVD0_MASK (0xFFFU)

#define	LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U)

#define	LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK)

#define	LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U)

#define	LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U)

#define	LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)

#define	LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U)

#define	LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U)

#define	LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK)

#define	LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U)

#define	LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U)

#define	LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)

#define	LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U)

#define	LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U)

#define	LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK)

#define	LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U)

#define	LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U)

#define	LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK)

#define	LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U)

#define	LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U)

#define	LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)

#define	LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U)

#define	LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U)

#define	LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK)

CTRL2_CLR - LCDIF General Control2 Register
#define	LCDIF_CTRL2_CLR_RSRVD0_MASK (0xFFFU)

#define	LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U)

#define	LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK)

#define	LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U)

#define	LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U)

#define	LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)

#define	LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U)

#define	LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U)

#define	LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK)

#define	LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U)

#define	LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U)

#define	LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)

#define	LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U)

#define	LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U)

#define	LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK)

#define	LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U)

#define	LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U)

#define	LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK)

#define	LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U)

#define	LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U)

#define	LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)

#define	LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U)

#define	LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U)

#define	LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK)

CTRL2_TOG - LCDIF General Control2 Register
#define	LCDIF_CTRL2_TOG_RSRVD0_MASK (0xFFFU)

#define	LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U)

#define	LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK)

#define	LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U)

#define	LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U)

#define	LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)

#define	LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U)

#define	LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U)

#define	LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK)

#define	LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U)

#define	LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U)

#define	LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)

#define	LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U)

#define	LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U)

#define	LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK)

#define	LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U)

#define	LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U)

#define	LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK)

#define	LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U)

#define	LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U)

#define	LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)

#define	LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U)

#define	LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U)

#define	LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)

TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register
#define	LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU)

#define	LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U)

#define	LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK)

#define	LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U)

#define	LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U)

#define	LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK)

CUR_BUF - LCD Interface Current Buffer Address Register
#define	LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU)

#define	LCDIF_CUR_BUF_ADDR_SHIFT (0U)

#define	LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK)

NEXT_BUF - LCD Interface Next Buffer Address Register
#define	LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU)

#define	LCDIF_NEXT_BUF_ADDR_SHIFT (0U)

#define	LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK)

VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0
#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)

#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U)

#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)

#define	LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U)

#define	LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U)

#define	LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK)

#define	LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U)

#define	LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U)

#define	LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK)

#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)

#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)

#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK)

#define	LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U)

#define	LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U)

#define	LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK)

#define	LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U)

#define	LCDIF_VDCTRL0_RSRVD1_SHIFT (22U)

#define	LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK)

#define	LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U)

#define	LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U)

#define	LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK)

#define	LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U)

#define	LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U)

#define	LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK)

#define	LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U)

#define	LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U)

#define	LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK)

#define	LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U)

#define	LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U)

#define	LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK)

#define	LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U)

#define	LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U)

#define	LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK)

#define	LCDIF_VDCTRL0_RSRVD2_MASK (0xE0000000U)

#define	LCDIF_VDCTRL0_RSRVD2_SHIFT (29U)

#define	LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK)

VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0
#define	LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)

#define	LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U)

#define	LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK)

#define	LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U)

#define	LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U)

#define	LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK)

#define	LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U)

#define	LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U)

#define	LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK)

#define	LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)

#define	LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)

#define	LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK)

#define	LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U)

#define	LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U)

#define	LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK)

#define	LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U)

#define	LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U)

#define	LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK)

#define	LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U)

#define	LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U)

#define	LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK)

#define	LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U)

#define	LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U)

#define	LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK)

#define	LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U)

#define	LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U)

#define	LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK)

#define	LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U)

#define	LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U)

#define	LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK)

#define	LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U)

#define	LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U)

#define	LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK)

#define	LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xE0000000U)

#define	LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (29U)

#define	LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK)

VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0
#define	LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)

#define	LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U)

#define	LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK)

#define	LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U)

#define	LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U)

#define	LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK)

#define	LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U)

#define	LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U)

#define	LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK)

#define	LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)

#define	LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)

#define	LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK)

#define	LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U)

#define	LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U)

#define	LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK)

#define	LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U)

#define	LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U)

#define	LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK)

#define	LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U)

#define	LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U)

#define	LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK)

#define	LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U)

#define	LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U)

#define	LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK)

#define	LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U)

#define	LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U)

#define	LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK)

#define	LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U)

#define	LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U)

#define	LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK)

#define	LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U)

#define	LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U)

#define	LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK)

#define	LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xE0000000U)

#define	LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (29U)

#define	LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK)

VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0
#define	LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)

#define	LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U)

#define	LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK)

#define	LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U)

#define	LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U)

#define	LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK)

#define	LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U)

#define	LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U)

#define	LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK)

#define	LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)

#define	LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)

#define	LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK)

#define	LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U)

#define	LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U)

#define	LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK)

#define	LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U)

#define	LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U)

#define	LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK)

#define	LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U)

#define	LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U)

#define	LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK)

#define	LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U)

#define	LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U)

#define	LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK)

#define	LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U)

#define	LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U)

#define	LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK)

#define	LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U)

#define	LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U)

#define	LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK)

#define	LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U)

#define	LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U)

#define	LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK)

#define	LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xE0000000U)

#define	LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (29U)

#define	LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK)

VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1
#define	LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU)

#define	LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U)

#define	LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)

VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2
#define	LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU)

#define	LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U)

#define	LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)

#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U)

#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U)

#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)

VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3
#define	LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU)

#define	LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U)

#define	LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)

#define	LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U)

#define	LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U)

#define	LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)

#define	LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U)

#define	LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U)

#define	LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK)

#define	LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U)

#define	LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U)

#define	LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK)

#define	LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U)

#define	LCDIF_VDCTRL3_RSRVD0_SHIFT (30U)

#define	LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)

VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4
#define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU)

#define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U)

#define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)

#define	LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U)

#define	LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U)

#define	LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK)

#define	LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U)

#define	LCDIF_VDCTRL4_RSRVD0_SHIFT (19U)

#define	LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK)

#define	LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U)

#define	LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U)

#define	LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)

BM_ERROR_STAT - Bus Master Error Status Register
#define	LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU)

#define	LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U)

#define	LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK)

CRC_STAT - CRC Status Register
#define	LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU)

#define	LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U)

#define	LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK)

STAT - LCD Interface Status Register
#define	LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU)

#define	LCDIF_STAT_LFIFO_COUNT_SHIFT (0U)

#define	LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK)

#define	LCDIF_STAT_RSRVD0_MASK (0x1FFFE00U)

#define	LCDIF_STAT_RSRVD0_SHIFT (9U)

#define	LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK)

#define	LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U)

#define	LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U)

#define	LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK)

#define	LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U)

#define	LCDIF_STAT_TXFIFO_FULL_SHIFT (27U)

#define	LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK)

#define	LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U)

#define	LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U)

#define	LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK)

#define	LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U)

#define	LCDIF_STAT_LFIFO_FULL_SHIFT (29U)

#define	LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK)

#define	LCDIF_STAT_PRESENT_MASK (0x80000000U)

#define	LCDIF_STAT_PRESENT_SHIFT (31U)

#define	LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK)

RGB_ADJUST - RGB Color Range Adjust
#define	LCDIF_RGB_ADJUST_PIXEL_MASK (0xFFFFFFU)

#define	LCDIF_RGB_ADJUST_PIXEL_SHIFT (0U)

#define	LCDIF_RGB_ADJUST_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_PIXEL_SHIFT)) & LCDIF_RGB_ADJUST_PIXEL_MASK)

#define	LCDIF_RGB_ADJUST_RGB_ADJ_MODE_MASK (0xC0000000U)

#define	LCDIF_RGB_ADJUST_RGB_ADJ_MODE_SHIFT (30U)

#define	LCDIF_RGB_ADJUST_RGB_ADJ_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_RGB_ADJ_MODE_SHIFT)) & LCDIF_RGB_ADJUST_RGB_ADJ_MODE_MASK)

RGB_ADJUST_SET - RGB Color Range Adjust
#define	LCDIF_RGB_ADJUST_SET_PIXEL_MASK (0xFFFFFFU)

#define	LCDIF_RGB_ADJUST_SET_PIXEL_SHIFT (0U)

#define	LCDIF_RGB_ADJUST_SET_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_SET_PIXEL_SHIFT)) & LCDIF_RGB_ADJUST_SET_PIXEL_MASK)

#define	LCDIF_RGB_ADJUST_SET_RGB_ADJ_MODE_MASK (0xC0000000U)

#define	LCDIF_RGB_ADJUST_SET_RGB_ADJ_MODE_SHIFT (30U)

#define	LCDIF_RGB_ADJUST_SET_RGB_ADJ_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_SET_RGB_ADJ_MODE_SHIFT)) & LCDIF_RGB_ADJUST_SET_RGB_ADJ_MODE_MASK)

RGB_ADJUST_CLR - RGB Color Range Adjust
#define	LCDIF_RGB_ADJUST_CLR_PIXEL_MASK (0xFFFFFFU)

#define	LCDIF_RGB_ADJUST_CLR_PIXEL_SHIFT (0U)

#define	LCDIF_RGB_ADJUST_CLR_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_CLR_PIXEL_SHIFT)) & LCDIF_RGB_ADJUST_CLR_PIXEL_MASK)

#define	LCDIF_RGB_ADJUST_CLR_RGB_ADJ_MODE_MASK (0xC0000000U)

#define	LCDIF_RGB_ADJUST_CLR_RGB_ADJ_MODE_SHIFT (30U)

#define	LCDIF_RGB_ADJUST_CLR_RGB_ADJ_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_CLR_RGB_ADJ_MODE_SHIFT)) & LCDIF_RGB_ADJUST_CLR_RGB_ADJ_MODE_MASK)

RGB_ADJUST_TOG - RGB Color Range Adjust
#define	LCDIF_RGB_ADJUST_TOG_PIXEL_MASK (0xFFFFFFU)

#define	LCDIF_RGB_ADJUST_TOG_PIXEL_SHIFT (0U)

#define	LCDIF_RGB_ADJUST_TOG_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_TOG_PIXEL_SHIFT)) & LCDIF_RGB_ADJUST_TOG_PIXEL_MASK)

#define	LCDIF_RGB_ADJUST_TOG_RGB_ADJ_MODE_MASK (0xC0000000U)

#define	LCDIF_RGB_ADJUST_TOG_RGB_ADJ_MODE_SHIFT (30U)

#define	LCDIF_RGB_ADJUST_TOG_RGB_ADJ_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_TOG_RGB_ADJ_MODE_SHIFT)) & LCDIF_RGB_ADJUST_TOG_RGB_ADJ_MODE_MASK)

PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register
#define	LCDIF_PIGEONCTRL0_FD_PERIOD_MASK (0xFFFU)

#define	LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT (0U)

#define	LCDIF_PIGEONCTRL0_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK)

#define	LCDIF_PIGEONCTRL0_LD_PERIOD_MASK (0xFFF0000U)

#define	LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT (16U)

#define	LCDIF_PIGEONCTRL0_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK)

PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register
#define	LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK (0xFFFU)

#define	LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT (0U)

#define	LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK)

#define	LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK (0xFFF0000U)

#define	LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT (16U)

#define	LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK)

PIGEONCTRL0_CLR - LCDIF Pigeon Mode Control0 Register
#define	LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK (0xFFFU)

#define	LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT (0U)

#define	LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK)

#define	LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK (0xFFF0000U)

#define	LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT (16U)

#define	LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK)

PIGEONCTRL0_TOG - LCDIF Pigeon Mode Control0 Register
#define	LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK (0xFFFU)

#define	LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT (0U)

#define	LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK)

#define	LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK (0xFFF0000U)

#define	LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT (16U)

#define	LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK)

PIGEONCTRL1 - LCDIF Pigeon Mode Control1 Register
#define	LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK (0xFFFU)

#define	LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U)

#define	LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK)

#define	LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK (0xFFF0000U)

#define	LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U)

#define	LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK)

PIGEONCTRL1_SET - LCDIF Pigeon Mode Control1 Register
#define	LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU)

#define	LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U)

#define	LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK)

#define	LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U)

#define	LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U)

#define	LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK)

PIGEONCTRL1_CLR - LCDIF Pigeon Mode Control1 Register
#define	LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU)

#define	LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U)

#define	LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK)

#define	LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U)

#define	LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U)

#define	LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK)

PIGEONCTRL1_TOG - LCDIF Pigeon Mode Control1 Register
#define	LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU)

#define	LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U)

#define	LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK)

#define	LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U)

#define	LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U)

#define	LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK)

PIGEONCTRL2 - LCDIF Pigeon Mode Control2 Register
#define	LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK (0x1U)

#define	LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT (0U)

#define	LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK)

#define	LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK (0x2U)

#define	LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT (1U)

#define	LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK)

PIGEONCTRL2_SET - LCDIF Pigeon Mode Control2 Register
#define	LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U)

#define	LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U)

#define	LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK)

#define	LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U)

#define	LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U)

#define	LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK)

PIGEONCTRL2_CLR - LCDIF Pigeon Mode Control2 Register
#define	LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U)

#define	LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U)

#define	LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK)

#define	LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U)

#define	LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U)

#define	LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK)

PIGEONCTRL2_TOG - LCDIF Pigeon Mode Control2 Register
#define	LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U)

#define	LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U)

#define	LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK)

#define	LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U)

#define	LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U)

#define	LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK)

PIGEON_0 - Panel Interface Signal Generator Register
#define	LCDIF_PIGEON_0_EN_MASK (0x1U)

#define	LCDIF_PIGEON_0_EN_SHIFT (0U)

#define	LCDIF_PIGEON_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK)

#define	LCDIF_PIGEON_0_POL_MASK (0x2U)

#define	LCDIF_PIGEON_0_POL_SHIFT (1U)

#define	LCDIF_PIGEON_0_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK)

#define	LCDIF_PIGEON_0_INC_SEL_MASK (0xCU)

#define	LCDIF_PIGEON_0_INC_SEL_SHIFT (2U)

#define	LCDIF_PIGEON_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK)

#define	LCDIF_PIGEON_0_OFFSET_MASK (0xF0U)

#define	LCDIF_PIGEON_0_OFFSET_SHIFT (4U)

#define	LCDIF_PIGEON_0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK)

#define	LCDIF_PIGEON_0_MASK_CNT_SEL_MASK (0xF00U)

#define	LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT (8U)

#define	LCDIF_PIGEON_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK)

#define	LCDIF_PIGEON_0_MASK_CNT_MASK (0xFFF000U)

#define	LCDIF_PIGEON_0_MASK_CNT_SHIFT (12U)

#define	LCDIF_PIGEON_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK)

#define	LCDIF_PIGEON_0_STATE_MASK_MASK (0xFF000000U)

#define	LCDIF_PIGEON_0_STATE_MASK_SHIFT (24U)

#define	LCDIF_PIGEON_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK)

PIGEON_1 - Panel Interface Signal Generator Register
#define	LCDIF_PIGEON_1_SET_CNT_MASK (0xFFFFU)

#define	LCDIF_PIGEON_1_SET_CNT_SHIFT (0U)

#define	LCDIF_PIGEON_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK)

#define	LCDIF_PIGEON_1_CLR_CNT_MASK (0xFFFF0000U)

#define	LCDIF_PIGEON_1_CLR_CNT_SHIFT (16U)

#define	LCDIF_PIGEON_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK)

PIGEON_2 - Panel Interface Signal Generator Register
#define	LCDIF_PIGEON_2_SIG_LOGIC_MASK (0xFU)

#define	LCDIF_PIGEON_2_SIG_LOGIC_SHIFT (0U)

#define	LCDIF_PIGEON_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK)

#define	LCDIF_PIGEON_2_SIG_ANOTHER_MASK (0x1F0U)

#define	LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT (4U)

#define	LCDIF_PIGEON_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK)

#define	LCDIF_PIGEON_2_RSVD_MASK (0xFFFFFE00U)

#define	LCDIF_PIGEON_2_RSVD_SHIFT (9U)

#define	LCDIF_PIGEON_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK)

LUT_CTRL - Look Up Table Control Register
#define	LCDIF_LUT_CTRL_LUT_BYPASS_MASK (0x1U)

#define	LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT (0U)

#define	LCDIF_LUT_CTRL_LUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK)

LUT0_ADDR - Lookup Table 0 Index Register
#define	LCDIF_LUT0_ADDR_ADDR_MASK (0xFFU)

#define	LCDIF_LUT0_ADDR_ADDR_SHIFT (0U)

#define	LCDIF_LUT0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK)

LUT0_DATA - Lookup Table 0 Data Register
#define	LCDIF_LUT0_DATA_DATA_MASK (0xFFFFFFFFU)

#define	LCDIF_LUT0_DATA_DATA_SHIFT (0U)

#define	LCDIF_LUT0_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK)

LUT1_ADDR - Lookup Table 1 Index Register
#define	LCDIF_LUT1_ADDR_ADDR_MASK (0xFFU)

#define	LCDIF_LUT1_ADDR_ADDR_SHIFT (0U)

#define	LCDIF_LUT1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK)

LUT1_DATA - Lookup Table 1 Data Register
#define	LCDIF_LUT1_DATA_DATA_MASK (0xFFFFFFFFU)

#define	LCDIF_LUT1_DATA_DATA_SHIFT (0U)

#define	LCDIF_LUT1_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK)

CTRL - LCDIF General Control Register
#define	LCDIF_CTRL_RUN_MASK (0x1U)

#define	LCDIF_CTRL_RUN_SHIFT (0U)

#define	LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK)

#define	LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U)

#define	LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U)

#define	LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK)

#define	LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U)

#define	LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U)

#define	LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK)

#define	LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U)

#define	LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U)

#define	LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK)

#define	LCDIF_CTRL_RSRVD0_MASK (0x10U)

#define	LCDIF_CTRL_RSRVD0_SHIFT (4U)

#define	LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK)

#define	LCDIF_CTRL_MASTER_MASK (0x20U)

#define	LCDIF_CTRL_MASTER_SHIFT (5U)

#define	LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK)

#define	LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U)

#define	LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U)

#define	LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK)

#define	LCDIF_CTRL_WORD_LENGTH_MASK (0x300U)

#define	LCDIF_CTRL_WORD_LENGTH_SHIFT (8U)

#define	LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK)

#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U)

#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U)

#define	LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK)

#define	LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U)

#define	LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U)

#define	LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK)

#define	LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U)

#define	LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U)

#define	LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK)

#define	LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U)

#define	LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U)

#define	LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK)

#define	LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U)

#define	LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U)

#define	LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK)

#define	LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U)

#define	LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U)

#define	LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK)

#define	LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U)

#define	LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U)

#define	LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK)

#define	LCDIF_CTRL_CLKGATE_MASK (0x40000000U)

#define	LCDIF_CTRL_CLKGATE_SHIFT (30U)

#define	LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK)

#define	LCDIF_CTRL_SFTRST_MASK (0x80000000U)

#define	LCDIF_CTRL_SFTRST_SHIFT (31U)

#define	LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK)

CTRL_SET - LCDIF General Control Register
#define	LCDIF_CTRL_SET_RUN_MASK (0x1U)

#define	LCDIF_CTRL_SET_RUN_SHIFT (0U)

#define	LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK)

#define	LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U)

#define	LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U)

#define	LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK)

#define	LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U)

#define	LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U)

#define	LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK)

#define	LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U)

#define	LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U)

#define	LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK)

#define	LCDIF_CTRL_SET_RSRVD0_MASK (0x10U)

#define	LCDIF_CTRL_SET_RSRVD0_SHIFT (4U)

#define	LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK)

#define	LCDIF_CTRL_SET_MASTER_MASK (0x20U)

#define	LCDIF_CTRL_SET_MASTER_SHIFT (5U)

#define	LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK)

#define	LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U)

#define	LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U)

#define	LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK)

#define	LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U)

#define	LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U)

#define	LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK)

#define	LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U)

#define	LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U)

#define	LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK)

#define	LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U)

#define	LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U)

#define	LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK)

#define	LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U)

#define	LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U)

#define	LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK)

#define	LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U)

#define	LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U)

#define	LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK)

#define	LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U)

#define	LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U)

#define	LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK)

#define	LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U)

#define	LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U)

#define	LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK)

#define	LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U)

#define	LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U)

#define	LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK)

#define	LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U)

#define	LCDIF_CTRL_SET_CLKGATE_SHIFT (30U)

#define	LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK)

#define	LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U)

#define	LCDIF_CTRL_SET_SFTRST_SHIFT (31U)

#define	LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK)

CTRL_CLR - LCDIF General Control Register
#define	LCDIF_CTRL_CLR_RUN_MASK (0x1U)

#define	LCDIF_CTRL_CLR_RUN_SHIFT (0U)

#define	LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK)

#define	LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U)

#define	LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U)

#define	LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK)

#define	LCDIF_CTRL_CLR_MASTER_MASK (0x20U)

#define	LCDIF_CTRL_CLR_MASTER_SHIFT (5U)

#define	LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK)

#define	LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U)

#define	LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U)

#define	LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK)

#define	LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U)

#define	LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U)

#define	LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK)

#define	LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U)

#define	LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U)

#define	LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK)

#define	LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U)

#define	LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U)

#define	LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK)

#define	LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U)

#define	LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U)

#define	LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK)

#define	LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U)

#define	LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U)

#define	LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK)

#define	LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U)

#define	LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U)

#define	LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK)

#define	LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U)

#define	LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U)

#define	LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK)

#define	LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U)

#define	LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U)

#define	LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK)

#define	LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U)

#define	LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U)

#define	LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK)

#define	LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U)

#define	LCDIF_CTRL_CLR_SFTRST_SHIFT (31U)

#define	LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK)

CTRL_TOG - LCDIF General Control Register
#define	LCDIF_CTRL_TOG_RUN_MASK (0x1U)

#define	LCDIF_CTRL_TOG_RUN_SHIFT (0U)

#define	LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK)

#define	LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U)

#define	LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U)

#define	LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK)

#define	LCDIF_CTRL_TOG_MASTER_MASK (0x20U)

#define	LCDIF_CTRL_TOG_MASTER_SHIFT (5U)

#define	LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK)

#define	LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U)

#define	LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U)

#define	LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK)

#define	LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U)

#define	LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U)

#define	LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK)

#define	LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U)

#define	LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U)

#define	LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK)

#define	LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U)

#define	LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U)

#define	LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK)

#define	LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U)

#define	LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U)

#define	LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK)

#define	LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U)

#define	LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U)

#define	LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK)

#define	LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U)

#define	LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U)

#define	LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK)

#define	LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U)

#define	LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U)

#define	LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK)

#define	LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U)

#define	LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U)

#define	LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK)

#define	LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U)

#define	LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U)

#define	LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK)

#define	LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U)

#define	LCDIF_CTRL_TOG_SFTRST_SHIFT (31U)

#define	LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK)

CTRL1 - LCDIF General Control1 Register
#define	LCDIF_CTRL1_RSRVD0_MASK (0xF8U)

#define	LCDIF_CTRL1_RSRVD0_SHIFT (3U)

#define	LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK)

#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U)

#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U)

#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)

#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U)

#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U)

#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK)

#define	LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U)

#define	LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U)

#define	LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK)

#define	LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U)

#define	LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U)

#define	LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK)

#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)

#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U)

#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK)

#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)

#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)

#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK)

#define	LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U)

#define	LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U)

#define	LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK)

#define	LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U)

#define	LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U)

#define	LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK)

#define	LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U)

#define	LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U)

#define	LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)

#define	LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)

#define	LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)

#define	LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK)

#define	LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U)

#define	LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U)

#define	LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK)

#define	LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)

#define	LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)

#define	LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK)

#define	LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U)

#define	LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U)

#define	LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK)

#define	LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)

#define	LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U)

#define	LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK)

#define	LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U)

#define	LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U)

#define	LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK)

#define	LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U)

#define	LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U)

#define	LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK)

#define	LCDIF_CTRL1_CS_OUT_SELECT_MASK (0x40000000U)

#define	LCDIF_CTRL1_CS_OUT_SELECT_SHIFT (30U)

#define	LCDIF_CTRL1_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CS_OUT_SELECT_MASK)

#define	LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK (0x80000000U)

#define	LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT (31U)

#define	LCDIF_CTRL1_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK)

CTRL1_SET - LCDIF General Control1 Register
#define	LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U)

#define	LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U)

#define	LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK)

#define	LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U)

#define	LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U)

#define	LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK)

#define	LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U)

#define	LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U)

#define	LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK)

#define	LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U)

#define	LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U)

#define	LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK)

#define	LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U)

#define	LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U)

#define	LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK)

#define	LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)

#define	LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U)

#define	LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK)

#define	LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)

#define	LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)

#define	LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK)

#define	LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U)

#define	LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U)

#define	LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK)

#define	LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U)

#define	LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U)

#define	LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK)

#define	LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U)

#define	LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U)

#define	LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK)

#define	LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)

#define	LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)

#define	LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK)

#define	LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U)

#define	LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U)

#define	LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK)

#define	LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)

#define	LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)

#define	LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK)

#define	LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U)

#define	LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U)

#define	LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK)

#define	LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)

#define	LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U)

#define	LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK)

#define	LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U)

#define	LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U)

#define	LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK)

#define	LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U)

#define	LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U)

#define	LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK)

#define	LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK (0x40000000U)

#define	LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT (30U)

#define	LCDIF_CTRL1_SET_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK)

#define	LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK (0x80000000U)

#define	LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT (31U)

#define	LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK)

CTRL1_CLR - LCDIF General Control1 Register
#define	LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U)

#define	LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U)

#define	LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)

#define	LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U)

#define	LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U)

#define	LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK)

#define	LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U)

#define	LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U)

#define	LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK)

#define	LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U)

#define	LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U)

#define	LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK)

#define	LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U)

#define	LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U)

#define	LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK)

#define	LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)

#define	LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U)

#define	LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK)

#define	LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)

#define	LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)

#define	LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK)

#define	LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U)

#define	LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U)

#define	LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK)

#define	LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U)

#define	LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U)

#define	LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK)

#define	LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U)

#define	LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U)

#define	LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK)

#define	LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)

#define	LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)

#define	LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK)

#define	LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U)

#define	LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U)

#define	LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK)

#define	LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)

#define	LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)

#define	LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK)

#define	LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U)

#define	LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U)

#define	LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK)

#define	LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)

#define	LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U)

#define	LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK)

#define	LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U)

#define	LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U)

#define	LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK)

#define	LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U)

#define	LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U)

#define	LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK)

#define	LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK (0x40000000U)

#define	LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT (30U)

#define	LCDIF_CTRL1_CLR_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK)

#define	LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK (0x80000000U)

#define	LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT (31U)

#define	LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK)

CTRL1_TOG - LCDIF General Control1 Register
#define	LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U)

#define	LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U)

#define	LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK)

#define	LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U)

#define	LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U)

#define	LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK)

#define	LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U)

#define	LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U)

#define	LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK)

#define	LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U)

#define	LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U)

#define	LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK)

#define	LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U)

#define	LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U)

#define	LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK)

#define	LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)

#define	LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U)

#define	LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK)

#define	LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)

#define	LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)

#define	LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK)

#define	LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U)

#define	LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U)

#define	LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK)

#define	LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U)

#define	LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U)

#define	LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK)

#define	LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U)

#define	LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U)

#define	LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK)

#define	LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)

#define	LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)

#define	LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK)

#define	LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U)

#define	LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U)

#define	LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK)

#define	LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)

#define	LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)

#define	LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK)

#define	LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U)

#define	LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U)

#define	LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK)

#define	LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)

#define	LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U)

#define	LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK)

#define	LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U)

#define	LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U)

#define	LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK)

#define	LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U)

#define	LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U)

#define	LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK)

#define	LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK (0x40000000U)

#define	LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT (30U)

#define	LCDIF_CTRL1_TOG_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK)

#define	LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK (0x80000000U)

#define	LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT (31U)

#define	LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK)

CTRL2 - LCDIF General Control2 Register
#define	LCDIF_CTRL2_RSRVD0_MASK (0xFFFU)

#define	LCDIF_CTRL2_RSRVD0_SHIFT (0U)

#define	LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK)

#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U)

#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U)

#define	LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)

#define	LCDIF_CTRL2_RSRVD3_MASK (0x8000U)

#define	LCDIF_CTRL2_RSRVD3_SHIFT (15U)

#define	LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK)

#define	LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U)

#define	LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U)

#define	LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)

#define	LCDIF_CTRL2_RSRVD4_MASK (0x80000U)

#define	LCDIF_CTRL2_RSRVD4_SHIFT (19U)

#define	LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK)

#define	LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U)

#define	LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U)

#define	LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK)

#define	LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U)

#define	LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U)

#define	LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK)

#define	LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U)

#define	LCDIF_CTRL2_RSRVD5_SHIFT (24U)

#define	LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK)

CTRL2_SET - LCDIF General Control2 Register
#define	LCDIF_CTRL2_SET_RSRVD0_MASK (0xFFFU)

#define	LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U)

#define	LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK)

#define	LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U)

#define	LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U)

#define	LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)

#define	LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U)

#define	LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U)

#define	LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK)

#define	LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U)

#define	LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U)

#define	LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)

#define	LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U)

#define	LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U)

#define	LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK)

#define	LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U)

#define	LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U)

#define	LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK)

#define	LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U)

#define	LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U)

#define	LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)

#define	LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U)

#define	LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U)

#define	LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK)

CTRL2_CLR - LCDIF General Control2 Register
#define	LCDIF_CTRL2_CLR_RSRVD0_MASK (0xFFFU)

#define	LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U)

#define	LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK)

#define	LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U)

#define	LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U)

#define	LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)

#define	LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U)

#define	LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U)

#define	LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK)

#define	LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U)

#define	LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U)

#define	LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)

#define	LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U)

#define	LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U)

#define	LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK)

#define	LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U)

#define	LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U)

#define	LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK)

#define	LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U)

#define	LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U)

#define	LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)

#define	LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U)

#define	LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U)

#define	LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK)

CTRL2_TOG - LCDIF General Control2 Register
#define	LCDIF_CTRL2_TOG_RSRVD0_MASK (0xFFFU)

#define	LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U)

#define	LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK)

#define	LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U)

#define	LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U)

#define	LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)

#define	LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U)

#define	LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U)

#define	LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK)

#define	LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U)

#define	LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U)

#define	LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)

#define	LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U)

#define	LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U)

#define	LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK)

#define	LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U)

#define	LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U)

#define	LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK)

#define	LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U)

#define	LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U)

#define	LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)

#define	LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U)

#define	LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U)

#define	LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)

TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register
#define	LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU)

#define	LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U)

#define	LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK)

#define	LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U)

#define	LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U)

#define	LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK)

CUR_BUF - LCD Interface Current Buffer Address Register
#define	LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU)

#define	LCDIF_CUR_BUF_ADDR_SHIFT (0U)

#define	LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK)

NEXT_BUF - LCD Interface Next Buffer Address Register
#define	LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU)

#define	LCDIF_NEXT_BUF_ADDR_SHIFT (0U)

#define	LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK)

VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0
#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)

#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U)

#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)

#define	LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U)

#define	LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U)

#define	LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK)

#define	LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U)

#define	LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U)

#define	LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK)

#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)

#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)

#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK)

#define	LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U)

#define	LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U)

#define	LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK)

#define	LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U)

#define	LCDIF_VDCTRL0_RSRVD1_SHIFT (22U)

#define	LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK)

#define	LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U)

#define	LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U)

#define	LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK)

#define	LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U)

#define	LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U)

#define	LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK)

#define	LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U)

#define	LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U)

#define	LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK)

#define	LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U)

#define	LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U)

#define	LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK)

#define	LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U)

#define	LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U)

#define	LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK)

#define	LCDIF_VDCTRL0_VSYNC_OEB_MASK (0x20000000U)

#define	LCDIF_VDCTRL0_VSYNC_OEB_SHIFT (29U)

#define	LCDIF_VDCTRL0_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_VSYNC_OEB_MASK)

#define	LCDIF_VDCTRL0_RSRVD2_MASK (0xC0000000U)

#define	LCDIF_VDCTRL0_RSRVD2_SHIFT (30U)

#define	LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK)

VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0
#define	LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)

#define	LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U)

#define	LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK)

#define	LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U)

#define	LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U)

#define	LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK)

#define	LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U)

#define	LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U)

#define	LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK)

#define	LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)

#define	LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)

#define	LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK)

#define	LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U)

#define	LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U)

#define	LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK)

#define	LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U)

#define	LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U)

#define	LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK)

#define	LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U)

#define	LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U)

#define	LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK)

#define	LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U)

#define	LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U)

#define	LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK)

#define	LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U)

#define	LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U)

#define	LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK)

#define	LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U)

#define	LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U)

#define	LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK)

#define	LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U)

#define	LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U)

#define	LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK)

#define	LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK (0x20000000U)

#define	LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT (29U)

#define	LCDIF_VDCTRL0_SET_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK)

#define	LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xC0000000U)

#define	LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (30U)

#define	LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK)

VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0
#define	LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)

#define	LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U)

#define	LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK)

#define	LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U)

#define	LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U)

#define	LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK)

#define	LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U)

#define	LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U)

#define	LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK)

#define	LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)

#define	LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)

#define	LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK)

#define	LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U)

#define	LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U)

#define	LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK)

#define	LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U)

#define	LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U)

#define	LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK)

#define	LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U)

#define	LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U)

#define	LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK)

#define	LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U)

#define	LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U)

#define	LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK)

#define	LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U)

#define	LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U)

#define	LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK)

#define	LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U)

#define	LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U)

#define	LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK)

#define	LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U)

#define	LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U)

#define	LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK)

#define	LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK (0x20000000U)

#define	LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT (29U)

#define	LCDIF_VDCTRL0_CLR_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK)

#define	LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xC0000000U)

#define	LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (30U)

#define	LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK)

VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0
#define	LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)

#define	LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U)

#define	LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK)

#define	LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U)

#define	LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U)

#define	LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK)

#define	LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U)

#define	LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U)

#define	LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK)

#define	LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)

#define	LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)

#define	LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK)

#define	LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U)

#define	LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U)

#define	LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK)

#define	LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U)

#define	LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U)

#define	LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK)

#define	LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U)

#define	LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U)

#define	LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK)

#define	LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U)

#define	LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U)

#define	LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK)

#define	LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U)

#define	LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U)

#define	LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK)

#define	LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U)

#define	LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U)

#define	LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK)

#define	LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U)

#define	LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U)

#define	LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK)

#define	LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK (0x20000000U)

#define	LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT (29U)

#define	LCDIF_VDCTRL0_TOG_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK)

#define	LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xC0000000U)

#define	LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (30U)

#define	LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK)

VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1
#define	LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU)

#define	LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U)

#define	LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)

VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2
#define	LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU)

#define	LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U)

#define	LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)

#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U)

#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U)

#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)

VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3
#define	LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU)

#define	LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U)

#define	LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)

#define	LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U)

#define	LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U)

#define	LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)

#define	LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U)

#define	LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U)

#define	LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK)

#define	LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U)

#define	LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U)

#define	LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK)

#define	LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U)

#define	LCDIF_VDCTRL3_RSRVD0_SHIFT (30U)

#define	LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)

VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4
#define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU)

#define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U)

#define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)

#define	LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U)

#define	LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U)

#define	LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK)

#define	LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U)

#define	LCDIF_VDCTRL4_RSRVD0_SHIFT (19U)

#define	LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK)

#define	LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U)

#define	LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U)

#define	LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)

BM_ERROR_STAT - Bus Master Error Status Register
#define	LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU)

#define	LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U)

#define	LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK)

CRC_STAT - CRC Status Register
#define	LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU)

#define	LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U)

#define	LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK)

STAT - LCD Interface Status Register
#define	LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU)

#define	LCDIF_STAT_LFIFO_COUNT_SHIFT (0U)

#define	LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK)

#define	LCDIF_STAT_RSRVD0_MASK (0x1FFFE00U)

#define	LCDIF_STAT_RSRVD0_SHIFT (9U)

#define	LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK)

#define	LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U)

#define	LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U)

#define	LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK)

#define	LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U)

#define	LCDIF_STAT_TXFIFO_FULL_SHIFT (27U)

#define	LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK)

#define	LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U)

#define	LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U)

#define	LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK)

#define	LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U)

#define	LCDIF_STAT_LFIFO_FULL_SHIFT (29U)

#define	LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK)

#define	LCDIF_STAT_DMA_REQ_MASK (0x40000000U)

#define	LCDIF_STAT_DMA_REQ_SHIFT (30U)

#define	LCDIF_STAT_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DMA_REQ_SHIFT)) & LCDIF_STAT_DMA_REQ_MASK)

#define	LCDIF_STAT_PRESENT_MASK (0x80000000U)

#define	LCDIF_STAT_PRESENT_SHIFT (31U)

#define	LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK)

THRES - LCDIF Threshold Register
#define	LCDIF_THRES_RSRVD_MASK (0x1FFU)

#define	LCDIF_THRES_RSRVD_SHIFT (0U)

#define	LCDIF_THRES_RSRVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD_SHIFT)) & LCDIF_THRES_RSRVD_MASK)

#define	LCDIF_THRES_RSRVD1_MASK (0xFE00U)

#define	LCDIF_THRES_RSRVD1_SHIFT (9U)

#define	LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK)

#define	LCDIF_THRES_FASTCLOCK_MASK (0x1FF0000U)

#define	LCDIF_THRES_FASTCLOCK_SHIFT (16U)

#define	LCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK)

#define	LCDIF_THRES_RSRVD2_MASK (0xFE000000U)

#define	LCDIF_THRES_RSRVD2_SHIFT (25U)

#define	LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK)

PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register
#define	LCDIF_PIGEONCTRL0_FD_PERIOD_MASK (0xFFFU)

#define	LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT (0U)

#define	LCDIF_PIGEONCTRL0_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK)

#define	LCDIF_PIGEONCTRL0_LD_PERIOD_MASK (0xFFF0000U)

#define	LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT (16U)

#define	LCDIF_PIGEONCTRL0_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK)

PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register
#define	LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK (0xFFFU)

#define	LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT (0U)

#define	LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK)

#define	LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK (0xFFF0000U)

#define	LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT (16U)

#define	LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK)

PIGEONCTRL0_CLR - LCDIF Pigeon Mode Control0 Register
#define	LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK (0xFFFU)

#define	LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT (0U)

#define	LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK)

#define	LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK (0xFFF0000U)

#define	LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT (16U)

#define	LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK)

PIGEONCTRL0_TOG - LCDIF Pigeon Mode Control0 Register
#define	LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK (0xFFFU)

#define	LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT (0U)

#define	LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK)

#define	LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK (0xFFF0000U)

#define	LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT (16U)

#define	LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK)

PIGEONCTRL1 - LCDIF Pigeon Mode Control1 Register
#define	LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK (0xFFFU)

#define	LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U)

#define	LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK)

#define	LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK (0xFFF0000U)

#define	LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U)

#define	LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK)

PIGEONCTRL1_SET - LCDIF Pigeon Mode Control1 Register
#define	LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU)

#define	LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U)

#define	LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK)

#define	LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U)

#define	LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U)

#define	LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK)

PIGEONCTRL1_CLR - LCDIF Pigeon Mode Control1 Register
#define	LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU)

#define	LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U)

#define	LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK)

#define	LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U)

#define	LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U)

#define	LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK)

PIGEONCTRL1_TOG - LCDIF Pigeon Mode Control1 Register
#define	LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU)

#define	LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U)

#define	LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK)

#define	LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U)

#define	LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U)

#define	LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK)

PIGEONCTRL2 - LCDIF Pigeon Mode Control2 Register
#define	LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK (0x1U)

#define	LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT (0U)

#define	LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK)

#define	LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK (0x2U)

#define	LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT (1U)

#define	LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK)

PIGEONCTRL2_SET - LCDIF Pigeon Mode Control2 Register
#define	LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U)

#define	LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U)

#define	LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK)

#define	LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U)

#define	LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U)

#define	LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK)

PIGEONCTRL2_CLR - LCDIF Pigeon Mode Control2 Register
#define	LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U)

#define	LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U)

#define	LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK)

#define	LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U)

#define	LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U)

#define	LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK)

PIGEONCTRL2_TOG - LCDIF Pigeon Mode Control2 Register
#define	LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U)

#define	LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U)

#define	LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK)

#define	LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U)

#define	LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U)

#define	LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK)

PIGEON_0 - Panel Interface Signal Generator Register
#define	LCDIF_PIGEON_0_EN_MASK (0x1U)

#define	LCDIF_PIGEON_0_EN_SHIFT (0U)

#define	LCDIF_PIGEON_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK)

#define	LCDIF_PIGEON_0_POL_MASK (0x2U)

#define	LCDIF_PIGEON_0_POL_SHIFT (1U)

#define	LCDIF_PIGEON_0_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK)

#define	LCDIF_PIGEON_0_INC_SEL_MASK (0xCU)

#define	LCDIF_PIGEON_0_INC_SEL_SHIFT (2U)

#define	LCDIF_PIGEON_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK)

#define	LCDIF_PIGEON_0_OFFSET_MASK (0xF0U)

#define	LCDIF_PIGEON_0_OFFSET_SHIFT (4U)

#define	LCDIF_PIGEON_0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK)

#define	LCDIF_PIGEON_0_MASK_CNT_SEL_MASK (0xF00U)

#define	LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT (8U)

#define	LCDIF_PIGEON_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK)

#define	LCDIF_PIGEON_0_MASK_CNT_MASK (0xFFF000U)

#define	LCDIF_PIGEON_0_MASK_CNT_SHIFT (12U)

#define	LCDIF_PIGEON_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK)

#define	LCDIF_PIGEON_0_STATE_MASK_MASK (0xFF000000U)

#define	LCDIF_PIGEON_0_STATE_MASK_SHIFT (24U)

#define	LCDIF_PIGEON_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK)

PIGEON_1 - Panel Interface Signal Generator Register
#define	LCDIF_PIGEON_1_SET_CNT_MASK (0xFFFFU)

#define	LCDIF_PIGEON_1_SET_CNT_SHIFT (0U)

#define	LCDIF_PIGEON_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK)

#define	LCDIF_PIGEON_1_CLR_CNT_MASK (0xFFFF0000U)

#define	LCDIF_PIGEON_1_CLR_CNT_SHIFT (16U)

#define	LCDIF_PIGEON_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK)

PIGEON_2 - Panel Interface Signal Generator Register
#define	LCDIF_PIGEON_2_SIG_LOGIC_MASK (0xFU)

#define	LCDIF_PIGEON_2_SIG_LOGIC_SHIFT (0U)

#define	LCDIF_PIGEON_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK)

#define	LCDIF_PIGEON_2_SIG_ANOTHER_MASK (0x1F0U)

#define	LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT (4U)

#define	LCDIF_PIGEON_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK)

#define	LCDIF_PIGEON_2_RSVD_MASK (0xFFFFFE00U)

#define	LCDIF_PIGEON_2_RSVD_SHIFT (9U)

#define	LCDIF_PIGEON_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK)

LUT_CTRL - Look Up Table Control Register
#define	LCDIF_LUT_CTRL_LUT_BYPASS_MASK (0x1U)

#define	LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT (0U)

#define	LCDIF_LUT_CTRL_LUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK)

LUT0_ADDR - Lookup Table 0 Index Register
#define	LCDIF_LUT0_ADDR_ADDR_MASK (0xFFU)

#define	LCDIF_LUT0_ADDR_ADDR_SHIFT (0U)

#define	LCDIF_LUT0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK)

LUT0_DATA - Lookup Table 0 Data Register
#define	LCDIF_LUT0_DATA_DATA_MASK (0xFFFFFFFFU)

#define	LCDIF_LUT0_DATA_DATA_SHIFT (0U)

#define	LCDIF_LUT0_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK)

LUT1_ADDR - Lookup Table 1 Index Register
#define	LCDIF_LUT1_ADDR_ADDR_MASK (0xFFU)

#define	LCDIF_LUT1_ADDR_ADDR_SHIFT (0U)

#define	LCDIF_LUT1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK)

LUT1_DATA - Lookup Table 1 Data Register
#define	LCDIF_LUT1_DATA_DATA_MASK (0xFFFFFFFFU)

#define	LCDIF_LUT1_DATA_DATA_SHIFT (0U)

#define	LCDIF_LUT1_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK)

CTRL - LCDIF General Control Register
#define	LCDIF_CTRL_RUN_MASK (0x1U)

#define	LCDIF_CTRL_RUN_SHIFT (0U)

#define	LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK)

#define	LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U)

#define	LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U)

#define	LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK)

#define	LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U)

#define	LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U)

#define	LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK)

#define	LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U)

#define	LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U)

#define	LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK)

#define	LCDIF_CTRL_RSRVD0_MASK (0x10U)

#define	LCDIF_CTRL_RSRVD0_SHIFT (4U)

#define	LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK)

#define	LCDIF_CTRL_MASTER_MASK (0x20U)

#define	LCDIF_CTRL_MASTER_SHIFT (5U)

#define	LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK)

#define	LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U)

#define	LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U)

#define	LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK)

#define	LCDIF_CTRL_WORD_LENGTH_MASK (0x300U)

#define	LCDIF_CTRL_WORD_LENGTH_SHIFT (8U)

#define	LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK)

#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U)

#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U)

#define	LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK)

#define	LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U)

#define	LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U)

#define	LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK)

#define	LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U)

#define	LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U)

#define	LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK)

#define	LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U)

#define	LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U)

#define	LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK)

#define	LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U)

#define	LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U)

#define	LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK)

#define	LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U)

#define	LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U)

#define	LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK)

#define	LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U)

#define	LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U)

#define	LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK)

#define	LCDIF_CTRL_CLKGATE_MASK (0x40000000U)

#define	LCDIF_CTRL_CLKGATE_SHIFT (30U)

#define	LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK)

#define	LCDIF_CTRL_SFTRST_MASK (0x80000000U)

#define	LCDIF_CTRL_SFTRST_SHIFT (31U)

#define	LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK)

CTRL_SET - LCDIF General Control Register
#define	LCDIF_CTRL_SET_RUN_MASK (0x1U)

#define	LCDIF_CTRL_SET_RUN_SHIFT (0U)

#define	LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK)

#define	LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U)

#define	LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U)

#define	LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK)

#define	LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U)

#define	LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U)

#define	LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK)

#define	LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U)

#define	LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U)

#define	LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK)

#define	LCDIF_CTRL_SET_RSRVD0_MASK (0x10U)

#define	LCDIF_CTRL_SET_RSRVD0_SHIFT (4U)

#define	LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK)

#define	LCDIF_CTRL_SET_MASTER_MASK (0x20U)

#define	LCDIF_CTRL_SET_MASTER_SHIFT (5U)

#define	LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK)

#define	LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U)

#define	LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U)

#define	LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK)

#define	LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U)

#define	LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U)

#define	LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK)

#define	LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U)

#define	LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U)

#define	LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK)

#define	LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U)

#define	LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U)

#define	LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK)

#define	LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U)

#define	LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U)

#define	LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK)

#define	LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U)

#define	LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U)

#define	LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK)

#define	LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U)

#define	LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U)

#define	LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK)

#define	LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U)

#define	LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U)

#define	LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK)

#define	LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U)

#define	LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U)

#define	LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK)

#define	LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U)

#define	LCDIF_CTRL_SET_CLKGATE_SHIFT (30U)

#define	LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK)

#define	LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U)

#define	LCDIF_CTRL_SET_SFTRST_SHIFT (31U)

#define	LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK)

CTRL_CLR - LCDIF General Control Register
#define	LCDIF_CTRL_CLR_RUN_MASK (0x1U)

#define	LCDIF_CTRL_CLR_RUN_SHIFT (0U)

#define	LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U)

#define	LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK)

#define	LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U)

#define	LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U)

#define	LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK)

#define	LCDIF_CTRL_CLR_MASTER_MASK (0x20U)

#define	LCDIF_CTRL_CLR_MASTER_SHIFT (5U)

#define	LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK)

#define	LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U)

#define	LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U)

#define	LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK)

#define	LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U)

#define	LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U)

#define	LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK)

#define	LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U)

#define	LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U)

#define	LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK)

#define	LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U)

#define	LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U)

#define	LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK)

#define	LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U)

#define	LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U)

#define	LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK)

#define	LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U)

#define	LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U)

#define	LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK)

#define	LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U)

#define	LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U)

#define	LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK)

#define	LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U)

#define	LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U)

#define	LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK)

#define	LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U)

#define	LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U)

#define	LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK)

#define	LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U)

#define	LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U)

#define	LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK)

#define	LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U)

#define	LCDIF_CTRL_CLR_SFTRST_SHIFT (31U)

#define	LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK)

CTRL_TOG - LCDIF General Control Register
#define	LCDIF_CTRL_TOG_RUN_MASK (0x1U)

#define	LCDIF_CTRL_TOG_RUN_SHIFT (0U)

#define	LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U)

#define	LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK)

#define	LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U)

#define	LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U)

#define	LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK)

#define	LCDIF_CTRL_TOG_MASTER_MASK (0x20U)

#define	LCDIF_CTRL_TOG_MASTER_SHIFT (5U)

#define	LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK)

#define	LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U)

#define	LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U)

#define	LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK)

#define	LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U)

#define	LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U)

#define	LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK)

#define	LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U)

#define	LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U)

#define	LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK)

#define	LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U)

#define	LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U)

#define	LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK)

#define	LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U)

#define	LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U)

#define	LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK)

#define	LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U)

#define	LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U)

#define	LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK)

#define	LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U)

#define	LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U)

#define	LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK)

#define	LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U)

#define	LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U)

#define	LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK)

#define	LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U)

#define	LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U)

#define	LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK)

#define	LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U)

#define	LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U)

#define	LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK)

#define	LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U)

#define	LCDIF_CTRL_TOG_SFTRST_SHIFT (31U)

#define	LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK)

CTRL1 - LCDIF General Control1 Register
#define	LCDIF_CTRL1_RSRVD0_MASK (0xF8U)

#define	LCDIF_CTRL1_RSRVD0_SHIFT (3U)

#define	LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK)

#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U)

#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U)

#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)

#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U)

#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U)

#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK)

#define	LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U)

#define	LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U)

#define	LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK)

#define	LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U)

#define	LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U)

#define	LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK)

#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)

#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U)

#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK)

#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)

#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)

#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK)

#define	LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U)

#define	LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U)

#define	LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK)

#define	LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U)

#define	LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U)

#define	LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK)

#define	LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U)

#define	LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U)

#define	LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)

#define	LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)

#define	LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)

#define	LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK)

#define	LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U)

#define	LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U)

#define	LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK)

#define	LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)

#define	LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)

#define	LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK)

#define	LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U)

#define	LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U)

#define	LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK)

#define	LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)

#define	LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U)

#define	LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK)

#define	LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U)

#define	LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U)

#define	LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK)

#define	LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U)

#define	LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U)

#define	LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK)

#define	LCDIF_CTRL1_CS_OUT_SELECT_MASK (0x40000000U)

#define	LCDIF_CTRL1_CS_OUT_SELECT_SHIFT (30U)

#define	LCDIF_CTRL1_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CS_OUT_SELECT_MASK)

#define	LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK (0x80000000U)

#define	LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT (31U)

#define	LCDIF_CTRL1_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK)

CTRL1_SET - LCDIF General Control1 Register
#define	LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U)

#define	LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U)

#define	LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK)

#define	LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U)

#define	LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U)

#define	LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK)

#define	LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U)

#define	LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U)

#define	LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK)

#define	LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U)

#define	LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U)

#define	LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK)

#define	LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U)

#define	LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U)

#define	LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK)

#define	LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)

#define	LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U)

#define	LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK)

#define	LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)

#define	LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)

#define	LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK)

#define	LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U)

#define	LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U)

#define	LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK)

#define	LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U)

#define	LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U)

#define	LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK)

#define	LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U)

#define	LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U)

#define	LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK)

#define	LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)

#define	LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)

#define	LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK)

#define	LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U)

#define	LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U)

#define	LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK)

#define	LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)

#define	LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)

#define	LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK)

#define	LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U)

#define	LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U)

#define	LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK)

#define	LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)

#define	LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U)

#define	LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK)

#define	LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U)

#define	LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U)

#define	LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK)

#define	LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U)

#define	LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U)

#define	LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK)

#define	LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK (0x40000000U)

#define	LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT (30U)

#define	LCDIF_CTRL1_SET_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK)

#define	LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK (0x80000000U)

#define	LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT (31U)

#define	LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK)

CTRL1_CLR - LCDIF General Control1 Register
#define	LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U)

#define	LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U)

#define	LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)

#define	LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U)

#define	LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U)

#define	LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK)

#define	LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U)

#define	LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U)

#define	LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK)

#define	LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U)

#define	LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U)

#define	LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK)

#define	LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U)

#define	LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U)

#define	LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK)

#define	LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)

#define	LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U)

#define	LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK)

#define	LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)

#define	LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)

#define	LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK)

#define	LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U)

#define	LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U)

#define	LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK)

#define	LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U)

#define	LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U)

#define	LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK)

#define	LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U)

#define	LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U)

#define	LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK)

#define	LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)

#define	LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)

#define	LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK)

#define	LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U)

#define	LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U)

#define	LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK)

#define	LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)

#define	LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)

#define	LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK)

#define	LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U)

#define	LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U)

#define	LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK)

#define	LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)

#define	LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U)

#define	LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK)

#define	LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U)

#define	LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U)

#define	LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK)

#define	LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U)

#define	LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U)

#define	LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK)

#define	LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK (0x40000000U)

#define	LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT (30U)

#define	LCDIF_CTRL1_CLR_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK)

#define	LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK (0x80000000U)

#define	LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT (31U)

#define	LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK)

CTRL1_TOG - LCDIF General Control1 Register
#define	LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U)

#define	LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U)

#define	LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK)

#define	LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U)

#define	LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U)

#define	LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK)

#define	LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U)

#define	LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U)

#define	LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK)

#define	LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U)

#define	LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U)

#define	LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK)

#define	LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U)

#define	LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U)

#define	LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK)

#define	LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)

#define	LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U)

#define	LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK)

#define	LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)

#define	LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)

#define	LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK)

#define	LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U)

#define	LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U)

#define	LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK)

#define	LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U)

#define	LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U)

#define	LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK)

#define	LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U)

#define	LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U)

#define	LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK)

#define	LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)

#define	LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)

#define	LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK)

#define	LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U)

#define	LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U)

#define	LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK)

#define	LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)

#define	LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)

#define	LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK)

#define	LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U)

#define	LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U)

#define	LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK)

#define	LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)

#define	LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U)

#define	LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK)

#define	LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U)

#define	LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U)

#define	LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK)

#define	LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U)

#define	LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U)

#define	LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK)

#define	LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK (0x40000000U)

#define	LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT (30U)

#define	LCDIF_CTRL1_TOG_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK)

#define	LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK (0x80000000U)

#define	LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT (31U)

#define	LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK)

CTRL2 - LCDIF General Control2 Register
#define	LCDIF_CTRL2_RSRVD0_MASK (0xFFFU)

#define	LCDIF_CTRL2_RSRVD0_SHIFT (0U)

#define	LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK)

#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U)

#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U)

#define	LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)

#define	LCDIF_CTRL2_RSRVD3_MASK (0x8000U)

#define	LCDIF_CTRL2_RSRVD3_SHIFT (15U)

#define	LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK)

#define	LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U)

#define	LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U)

#define	LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)

#define	LCDIF_CTRL2_RSRVD4_MASK (0x80000U)

#define	LCDIF_CTRL2_RSRVD4_SHIFT (19U)

#define	LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK)

#define	LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U)

#define	LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U)

#define	LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK)

#define	LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U)

#define	LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U)

#define	LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK)

#define	LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U)

#define	LCDIF_CTRL2_RSRVD5_SHIFT (24U)

#define	LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK)

CTRL2_SET - LCDIF General Control2 Register
#define	LCDIF_CTRL2_SET_RSRVD0_MASK (0xFFFU)

#define	LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U)

#define	LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK)

#define	LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U)

#define	LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U)

#define	LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)

#define	LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U)

#define	LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U)

#define	LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK)

#define	LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U)

#define	LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U)

#define	LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)

#define	LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U)

#define	LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U)

#define	LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK)

#define	LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U)

#define	LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U)

#define	LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK)

#define	LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U)

#define	LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U)

#define	LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)

#define	LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U)

#define	LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U)

#define	LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK)

CTRL2_CLR - LCDIF General Control2 Register
#define	LCDIF_CTRL2_CLR_RSRVD0_MASK (0xFFFU)

#define	LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U)

#define	LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK)

#define	LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U)

#define	LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U)

#define	LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)

#define	LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U)

#define	LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U)

#define	LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK)

#define	LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U)

#define	LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U)

#define	LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)

#define	LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U)

#define	LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U)

#define	LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK)

#define	LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U)

#define	LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U)

#define	LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK)

#define	LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U)

#define	LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U)

#define	LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)

#define	LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U)

#define	LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U)

#define	LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK)

CTRL2_TOG - LCDIF General Control2 Register
#define	LCDIF_CTRL2_TOG_RSRVD0_MASK (0xFFFU)

#define	LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U)

#define	LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK)

#define	LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U)

#define	LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U)

#define	LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)

#define	LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U)

#define	LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U)

#define	LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK)

#define	LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U)

#define	LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U)

#define	LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)

#define	LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U)

#define	LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U)

#define	LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK)

#define	LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U)

#define	LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U)

#define	LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK)

#define	LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U)

#define	LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U)

#define	LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)

#define	LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U)

#define	LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U)

#define	LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)

TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register
#define	LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU)

#define	LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U)

#define	LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK)

#define	LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U)

#define	LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U)

#define	LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK)

CUR_BUF - LCD Interface Current Buffer Address Register
#define	LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU)

#define	LCDIF_CUR_BUF_ADDR_SHIFT (0U)

#define	LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK)

NEXT_BUF - LCD Interface Next Buffer Address Register
#define	LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU)

#define	LCDIF_NEXT_BUF_ADDR_SHIFT (0U)

#define	LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK)

VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0
#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)

#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U)

#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)

#define	LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U)

#define	LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U)

#define	LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK)

#define	LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U)

#define	LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U)

#define	LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK)

#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)

#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)

#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK)

#define	LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U)

#define	LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U)

#define	LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK)

#define	LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U)

#define	LCDIF_VDCTRL0_RSRVD1_SHIFT (22U)

#define	LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK)

#define	LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U)

#define	LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U)

#define	LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK)

#define	LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U)

#define	LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U)

#define	LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK)

#define	LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U)

#define	LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U)

#define	LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK)

#define	LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U)

#define	LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U)

#define	LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK)

#define	LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U)

#define	LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U)

#define	LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK)

#define	LCDIF_VDCTRL0_VSYNC_OEB_MASK (0x20000000U)

#define	LCDIF_VDCTRL0_VSYNC_OEB_SHIFT (29U)

#define	LCDIF_VDCTRL0_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_VSYNC_OEB_MASK)

#define	LCDIF_VDCTRL0_RSRVD2_MASK (0xC0000000U)

#define	LCDIF_VDCTRL0_RSRVD2_SHIFT (30U)

#define	LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK)

VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0
#define	LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)

#define	LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U)

#define	LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK)

#define	LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U)

#define	LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U)

#define	LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK)

#define	LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U)

#define	LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U)

#define	LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK)

#define	LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)

#define	LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)

#define	LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK)

#define	LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U)

#define	LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U)

#define	LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK)

#define	LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U)

#define	LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U)

#define	LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK)

#define	LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U)

#define	LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U)

#define	LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK)

#define	LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U)

#define	LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U)

#define	LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK)

#define	LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U)

#define	LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U)

#define	LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK)

#define	LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U)

#define	LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U)

#define	LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK)

#define	LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U)

#define	LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U)

#define	LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK)

#define	LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK (0x20000000U)

#define	LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT (29U)

#define	LCDIF_VDCTRL0_SET_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK)

#define	LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xC0000000U)

#define	LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (30U)

#define	LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK)

VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0
#define	LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)

#define	LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U)

#define	LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK)

#define	LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U)

#define	LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U)

#define	LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK)

#define	LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U)

#define	LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U)

#define	LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK)

#define	LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)

#define	LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)

#define	LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK)

#define	LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U)

#define	LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U)

#define	LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK)

#define	LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U)

#define	LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U)

#define	LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK)

#define	LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U)

#define	LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U)

#define	LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK)

#define	LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U)

#define	LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U)

#define	LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK)

#define	LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U)

#define	LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U)

#define	LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK)

#define	LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U)

#define	LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U)

#define	LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK)

#define	LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U)

#define	LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U)

#define	LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK)

#define	LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK (0x20000000U)

#define	LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT (29U)

#define	LCDIF_VDCTRL0_CLR_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK)

#define	LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xC0000000U)

#define	LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (30U)

#define	LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK)

VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0
#define	LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)

#define	LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U)

#define	LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK)

#define	LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U)

#define	LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U)

#define	LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK)

#define	LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U)

#define	LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U)

#define	LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK)

#define	LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)

#define	LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)

#define	LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK)

#define	LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U)

#define	LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U)

#define	LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK)

#define	LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U)

#define	LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U)

#define	LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK)

#define	LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U)

#define	LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U)

#define	LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK)

#define	LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U)

#define	LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U)

#define	LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK)

#define	LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U)

#define	LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U)

#define	LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK)

#define	LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U)

#define	LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U)

#define	LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK)

#define	LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U)

#define	LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U)

#define	LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK)

#define	LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK (0x20000000U)

#define	LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT (29U)

#define	LCDIF_VDCTRL0_TOG_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK)

#define	LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xC0000000U)

#define	LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (30U)

#define	LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK)

VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1
#define	LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU)

#define	LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U)

#define	LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)

VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2
#define	LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU)

#define	LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U)

#define	LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)

#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U)

#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U)

#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)

VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3
#define	LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU)

#define	LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U)

#define	LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)

#define	LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U)

#define	LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U)

#define	LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)

#define	LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U)

#define	LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U)

#define	LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK)

#define	LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U)

#define	LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U)

#define	LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK)

#define	LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U)

#define	LCDIF_VDCTRL3_RSRVD0_SHIFT (30U)

#define	LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)

VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4
#define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU)

#define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U)

#define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)

#define	LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U)

#define	LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U)

#define	LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK)

#define	LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U)

#define	LCDIF_VDCTRL4_RSRVD0_SHIFT (19U)

#define	LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK)

#define	LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U)

#define	LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U)

#define	LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)

BM_ERROR_STAT - Bus Master Error Status Register
#define	LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU)

#define	LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U)

#define	LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK)

CRC_STAT - CRC Status Register
#define	LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU)

#define	LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U)

#define	LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK)

STAT - LCD Interface Status Register
#define	LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU)

#define	LCDIF_STAT_LFIFO_COUNT_SHIFT (0U)

#define	LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK)

#define	LCDIF_STAT_RSRVD0_MASK (0x1FFFE00U)

#define	LCDIF_STAT_RSRVD0_SHIFT (9U)

#define	LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK)

#define	LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U)

#define	LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U)

#define	LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK)

#define	LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U)

#define	LCDIF_STAT_TXFIFO_FULL_SHIFT (27U)

#define	LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK)

#define	LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U)

#define	LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U)

#define	LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK)

#define	LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U)

#define	LCDIF_STAT_LFIFO_FULL_SHIFT (29U)

#define	LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK)

#define	LCDIF_STAT_DMA_REQ_MASK (0x40000000U)

#define	LCDIF_STAT_DMA_REQ_SHIFT (30U)

#define	LCDIF_STAT_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DMA_REQ_SHIFT)) & LCDIF_STAT_DMA_REQ_MASK)

#define	LCDIF_STAT_PRESENT_MASK (0x80000000U)

#define	LCDIF_STAT_PRESENT_SHIFT (31U)

#define	LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK)

THRES - LCDIF Threshold Register
#define	LCDIF_THRES_RSRVD_MASK (0x1FFU)

#define	LCDIF_THRES_RSRVD_SHIFT (0U)

#define	LCDIF_THRES_RSRVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD_SHIFT)) & LCDIF_THRES_RSRVD_MASK)

#define	LCDIF_THRES_RSRVD1_MASK (0xFE00U)

#define	LCDIF_THRES_RSRVD1_SHIFT (9U)

#define	LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK)

#define	LCDIF_THRES_FASTCLOCK_MASK (0x1FF0000U)

#define	LCDIF_THRES_FASTCLOCK_SHIFT (16U)

#define	LCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK)

#define	LCDIF_THRES_RSRVD2_MASK (0xFE000000U)

#define	LCDIF_THRES_RSRVD2_SHIFT (25U)

#define	LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK)

PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register
#define	LCDIF_PIGEONCTRL0_FD_PERIOD_MASK (0xFFFU)

#define	LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT (0U)

#define	LCDIF_PIGEONCTRL0_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK)

#define	LCDIF_PIGEONCTRL0_LD_PERIOD_MASK (0xFFF0000U)

#define	LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT (16U)

#define	LCDIF_PIGEONCTRL0_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK)

PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register
#define	LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK (0xFFFU)

#define	LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT (0U)

#define	LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK)

#define	LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK (0xFFF0000U)

#define	LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT (16U)

#define	LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK)

PIGEONCTRL0_CLR - LCDIF Pigeon Mode Control0 Register
#define	LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK (0xFFFU)

#define	LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT (0U)

#define	LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK)

#define	LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK (0xFFF0000U)

#define	LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT (16U)

#define	LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK)

PIGEONCTRL0_TOG - LCDIF Pigeon Mode Control0 Register
#define	LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK (0xFFFU)

#define	LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT (0U)

#define	LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK)

#define	LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK (0xFFF0000U)

#define	LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT (16U)

#define	LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK)

PIGEONCTRL1 - LCDIF Pigeon Mode Control1 Register
#define	LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK (0xFFFU)

#define	LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U)

#define	LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK)

#define	LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK (0xFFF0000U)

#define	LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U)

#define	LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK)

PIGEONCTRL1_SET - LCDIF Pigeon Mode Control1 Register
#define	LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU)

#define	LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U)

#define	LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK)

#define	LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U)

#define	LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U)

#define	LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK)

PIGEONCTRL1_CLR - LCDIF Pigeon Mode Control1 Register
#define	LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU)

#define	LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U)

#define	LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK)

#define	LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U)

#define	LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U)

#define	LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK)

PIGEONCTRL1_TOG - LCDIF Pigeon Mode Control1 Register
#define	LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU)

#define	LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U)

#define	LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK)

#define	LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U)

#define	LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U)

#define	LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK)

PIGEONCTRL2 - LCDIF Pigeon Mode Control2 Register
#define	LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK (0x1U)

#define	LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT (0U)

#define	LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK)

#define	LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK (0x2U)

#define	LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT (1U)

#define	LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK)

PIGEONCTRL2_SET - LCDIF Pigeon Mode Control2 Register
#define	LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U)

#define	LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U)

#define	LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK)

#define	LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U)

#define	LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U)

#define	LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK)

PIGEONCTRL2_CLR - LCDIF Pigeon Mode Control2 Register
#define	LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U)

#define	LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U)

#define	LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK)

#define	LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U)

#define	LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U)

#define	LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK)

PIGEONCTRL2_TOG - LCDIF Pigeon Mode Control2 Register
#define	LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U)

#define	LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U)

#define	LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK)

#define	LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U)

#define	LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U)

#define	LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK)

PIGEON_0 - Panel Interface Signal Generator Register
#define	LCDIF_PIGEON_0_EN_MASK (0x1U)

#define	LCDIF_PIGEON_0_EN_SHIFT (0U)

#define	LCDIF_PIGEON_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK)

#define	LCDIF_PIGEON_0_POL_MASK (0x2U)

#define	LCDIF_PIGEON_0_POL_SHIFT (1U)

#define	LCDIF_PIGEON_0_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK)

#define	LCDIF_PIGEON_0_INC_SEL_MASK (0xCU)

#define	LCDIF_PIGEON_0_INC_SEL_SHIFT (2U)

#define	LCDIF_PIGEON_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK)

#define	LCDIF_PIGEON_0_OFFSET_MASK (0xF0U)

#define	LCDIF_PIGEON_0_OFFSET_SHIFT (4U)

#define	LCDIF_PIGEON_0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK)

#define	LCDIF_PIGEON_0_MASK_CNT_SEL_MASK (0xF00U)

#define	LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT (8U)

#define	LCDIF_PIGEON_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK)

#define	LCDIF_PIGEON_0_MASK_CNT_MASK (0xFFF000U)

#define	LCDIF_PIGEON_0_MASK_CNT_SHIFT (12U)

#define	LCDIF_PIGEON_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK)

#define	LCDIF_PIGEON_0_STATE_MASK_MASK (0xFF000000U)

#define	LCDIF_PIGEON_0_STATE_MASK_SHIFT (24U)

#define	LCDIF_PIGEON_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK)

PIGEON_1 - Panel Interface Signal Generator Register
#define	LCDIF_PIGEON_1_SET_CNT_MASK (0xFFFFU)

#define	LCDIF_PIGEON_1_SET_CNT_SHIFT (0U)

#define	LCDIF_PIGEON_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK)

#define	LCDIF_PIGEON_1_CLR_CNT_MASK (0xFFFF0000U)

#define	LCDIF_PIGEON_1_CLR_CNT_SHIFT (16U)

#define	LCDIF_PIGEON_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK)

PIGEON_2 - Panel Interface Signal Generator Register
#define	LCDIF_PIGEON_2_SIG_LOGIC_MASK (0xFU)

#define	LCDIF_PIGEON_2_SIG_LOGIC_SHIFT (0U)

#define	LCDIF_PIGEON_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK)

#define	LCDIF_PIGEON_2_SIG_ANOTHER_MASK (0x1F0U)

#define	LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT (4U)

#define	LCDIF_PIGEON_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK)

#define	LCDIF_PIGEON_2_RSVD_MASK (0xFFFFFE00U)

#define	LCDIF_PIGEON_2_RSVD_SHIFT (9U)

#define	LCDIF_PIGEON_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK)

LUT_CTRL - Look Up Table Control Register
#define	LCDIF_LUT_CTRL_LUT_BYPASS_MASK (0x1U)

#define	LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT (0U)

#define	LCDIF_LUT_CTRL_LUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK)

LUT0_ADDR - Lookup Table 0 Index Register
#define	LCDIF_LUT0_ADDR_ADDR_MASK (0xFFU)

#define	LCDIF_LUT0_ADDR_ADDR_SHIFT (0U)

#define	LCDIF_LUT0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK)

LUT0_DATA - Lookup Table 0 Data Register
#define	LCDIF_LUT0_DATA_DATA_MASK (0xFFFFFFFFU)

#define	LCDIF_LUT0_DATA_DATA_SHIFT (0U)

#define	LCDIF_LUT0_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK)

LUT1_ADDR - Lookup Table 1 Index Register
#define	LCDIF_LUT1_ADDR_ADDR_MASK (0xFFU)

#define	LCDIF_LUT1_ADDR_ADDR_SHIFT (0U)

#define	LCDIF_LUT1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK)

LUT1_DATA - Lookup Table 1 Data Register
#define	LCDIF_LUT1_DATA_DATA_MASK (0xFFFFFFFFU)

#define	LCDIF_LUT1_DATA_DATA_SHIFT (0U)

#define	LCDIF_LUT1_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK)

Detailed Description

Macro Definition Documentation

◆ LCDIF_CTRL1_BM_ERROR_IRQ [1/3]

#define LCDIF_CTRL1_BM_ERROR_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK)

BM_ERROR_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_BM_ERROR_IRQ [2/3]

#define LCDIF_CTRL1_BM_ERROR_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK)

BM_ERROR_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_BM_ERROR_IRQ [3/3]

#define LCDIF_CTRL1_BM_ERROR_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK)

BM_ERROR_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_CLR_BM_ERROR_IRQ [1/3]

#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK)

BM_ERROR_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_CLR_BM_ERROR_IRQ [2/3]

#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK)

BM_ERROR_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_CLR_BM_ERROR_IRQ [3/3]

#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK)

BM_ERROR_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ [1/3]

#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK)

CUR_FRAME_DONE_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ [2/3]

#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK)

CUR_FRAME_DONE_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ [3/3]

#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK)

CUR_FRAME_DONE_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_CLR_OVERFLOW_IRQ [1/3]

#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK)

OVERFLOW_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_CLR_OVERFLOW_IRQ [2/3]

#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK)

OVERFLOW_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_CLR_OVERFLOW_IRQ [3/3]

#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK)

OVERFLOW_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_CLR_UNDERFLOW_IRQ [1/3]

#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK)

UNDERFLOW_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_CLR_UNDERFLOW_IRQ [2/3]

#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK)

UNDERFLOW_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_CLR_UNDERFLOW_IRQ [3/3]

#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK)

UNDERFLOW_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ [1/3]

#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK)

VSYNC_EDGE_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ [2/3]

#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK)

VSYNC_EDGE_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ [3/3]

#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK)

VSYNC_EDGE_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_CUR_FRAME_DONE_IRQ [1/3]

#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK)

CUR_FRAME_DONE_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_CUR_FRAME_DONE_IRQ [2/3]

#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK)

CUR_FRAME_DONE_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_CUR_FRAME_DONE_IRQ [3/3]

#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK)

CUR_FRAME_DONE_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_OVERFLOW_IRQ [1/3]

#define LCDIF_CTRL1_OVERFLOW_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK)

OVERFLOW_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_OVERFLOW_IRQ [2/3]

#define LCDIF_CTRL1_OVERFLOW_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK)

OVERFLOW_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_OVERFLOW_IRQ [3/3]

#define LCDIF_CTRL1_OVERFLOW_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK)

OVERFLOW_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_SET_BM_ERROR_IRQ [1/3]

#define LCDIF_CTRL1_SET_BM_ERROR_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK)

BM_ERROR_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_SET_BM_ERROR_IRQ [2/3]

#define LCDIF_CTRL1_SET_BM_ERROR_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK)

BM_ERROR_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_SET_BM_ERROR_IRQ [3/3]

#define LCDIF_CTRL1_SET_BM_ERROR_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK)

BM_ERROR_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ [1/3]

#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK)

CUR_FRAME_DONE_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ [2/3]

#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK)

CUR_FRAME_DONE_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ [3/3]

#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK)

CUR_FRAME_DONE_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_SET_OVERFLOW_IRQ [1/3]

#define LCDIF_CTRL1_SET_OVERFLOW_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK)

OVERFLOW_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_SET_OVERFLOW_IRQ [2/3]

#define LCDIF_CTRL1_SET_OVERFLOW_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK)

OVERFLOW_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_SET_OVERFLOW_IRQ [3/3]

#define LCDIF_CTRL1_SET_OVERFLOW_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK)

OVERFLOW_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_SET_UNDERFLOW_IRQ [1/3]

#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK)

UNDERFLOW_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_SET_UNDERFLOW_IRQ [2/3]

#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK)

UNDERFLOW_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_SET_UNDERFLOW_IRQ [3/3]

#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK)

UNDERFLOW_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ [1/3]

#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK)

VSYNC_EDGE_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ [2/3]

#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK)

VSYNC_EDGE_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ [3/3]

#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK)

VSYNC_EDGE_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_TOG_BM_ERROR_IRQ [1/3]

#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK)

BM_ERROR_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_TOG_BM_ERROR_IRQ [2/3]

#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK)

BM_ERROR_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_TOG_BM_ERROR_IRQ [3/3]

#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK)

BM_ERROR_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ [1/3]

#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK)

CUR_FRAME_DONE_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ [2/3]

#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK)

CUR_FRAME_DONE_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ [3/3]

#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK)

CUR_FRAME_DONE_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_TOG_OVERFLOW_IRQ [1/3]

#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK)

OVERFLOW_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_TOG_OVERFLOW_IRQ [2/3]

#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK)

OVERFLOW_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_TOG_OVERFLOW_IRQ [3/3]

#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK)

OVERFLOW_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_TOG_UNDERFLOW_IRQ [1/3]

#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK)

UNDERFLOW_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_TOG_UNDERFLOW_IRQ [2/3]

#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK)

UNDERFLOW_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_TOG_UNDERFLOW_IRQ [3/3]

#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK)

UNDERFLOW_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ [1/3]

#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK)

VSYNC_EDGE_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ [2/3]

#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK)

VSYNC_EDGE_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ [3/3]

#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK)

VSYNC_EDGE_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_UNDERFLOW_IRQ [1/3]

#define LCDIF_CTRL1_UNDERFLOW_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK)

UNDERFLOW_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_UNDERFLOW_IRQ [2/3]

#define LCDIF_CTRL1_UNDERFLOW_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK)

UNDERFLOW_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_UNDERFLOW_IRQ [3/3]

#define LCDIF_CTRL1_UNDERFLOW_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK)

UNDERFLOW_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_VSYNC_EDGE_IRQ [1/3]

#define LCDIF_CTRL1_VSYNC_EDGE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)

VSYNC_EDGE_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_VSYNC_EDGE_IRQ [2/3]

#define LCDIF_CTRL1_VSYNC_EDGE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)

VSYNC_EDGE_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL1_VSYNC_EDGE_IRQ [3/3]

#define LCDIF_CTRL1_VSYNC_EDGE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)

VSYNC_EDGE_IRQ 0b0..No Interrupt Request Pending. 0b1..Interrupt Request Pending.

◆ LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN [1/3]

#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)

EVEN_LINE_PATTERN 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

◆ LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN [2/3]

#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)

EVEN_LINE_PATTERN 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

◆ LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN [3/3]

#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)

EVEN_LINE_PATTERN 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

◆ LCDIF_CTRL2_CLR_ODD_LINE_PATTERN [1/3]

#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)

ODD_LINE_PATTERN 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

◆ LCDIF_CTRL2_CLR_ODD_LINE_PATTERN [2/3]

#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)

ODD_LINE_PATTERN 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

◆ LCDIF_CTRL2_CLR_ODD_LINE_PATTERN [3/3]

#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)

ODD_LINE_PATTERN 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

◆ LCDIF_CTRL2_CLR_OUTSTANDING_REQS [1/3]

#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)

OUTSTANDING_REQS 0b000..REQ_1 0b001..REQ_2 0b010..REQ_4 0b011..REQ_8 0b100..REQ_16

◆ LCDIF_CTRL2_CLR_OUTSTANDING_REQS [2/3]

#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)

OUTSTANDING_REQS 0b000..REQ_1 0b001..REQ_2 0b010..REQ_4 0b011..REQ_8 0b100..REQ_16

◆ LCDIF_CTRL2_CLR_OUTSTANDING_REQS [3/3]

#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)

OUTSTANDING_REQS 0b000..REQ_1 0b001..REQ_2 0b010..REQ_4 0b011..REQ_8 0b100..REQ_16

◆ LCDIF_CTRL2_EVEN_LINE_PATTERN [1/3]

#define LCDIF_CTRL2_EVEN_LINE_PATTERN ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)

EVEN_LINE_PATTERN 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

◆ LCDIF_CTRL2_EVEN_LINE_PATTERN [2/3]

#define LCDIF_CTRL2_EVEN_LINE_PATTERN ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)

EVEN_LINE_PATTERN 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

◆ LCDIF_CTRL2_EVEN_LINE_PATTERN [3/3]

#define LCDIF_CTRL2_EVEN_LINE_PATTERN ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)

EVEN_LINE_PATTERN 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

◆ LCDIF_CTRL2_ODD_LINE_PATTERN [1/3]

#define LCDIF_CTRL2_ODD_LINE_PATTERN ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)

ODD_LINE_PATTERN 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

◆ LCDIF_CTRL2_ODD_LINE_PATTERN [2/3]

#define LCDIF_CTRL2_ODD_LINE_PATTERN ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)

ODD_LINE_PATTERN 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

◆ LCDIF_CTRL2_ODD_LINE_PATTERN [3/3]

#define LCDIF_CTRL2_ODD_LINE_PATTERN ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)

ODD_LINE_PATTERN 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

◆ LCDIF_CTRL2_OUTSTANDING_REQS [1/3]

#define LCDIF_CTRL2_OUTSTANDING_REQS ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK)

OUTSTANDING_REQS 0b000..REQ_1 0b001..REQ_2 0b010..REQ_4 0b011..REQ_8 0b100..REQ_16

◆ LCDIF_CTRL2_OUTSTANDING_REQS [2/3]

#define LCDIF_CTRL2_OUTSTANDING_REQS ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK)

OUTSTANDING_REQS 0b000..REQ_1 0b001..REQ_2 0b010..REQ_4 0b011..REQ_8 0b100..REQ_16

◆ LCDIF_CTRL2_OUTSTANDING_REQS [3/3]

#define LCDIF_CTRL2_OUTSTANDING_REQS ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK)

OUTSTANDING_REQS 0b000..REQ_1 0b001..REQ_2 0b010..REQ_4 0b011..REQ_8 0b100..REQ_16

◆ LCDIF_CTRL2_SET_EVEN_LINE_PATTERN [1/3]

#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)

EVEN_LINE_PATTERN 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

◆ LCDIF_CTRL2_SET_EVEN_LINE_PATTERN [2/3]

#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)

EVEN_LINE_PATTERN 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

◆ LCDIF_CTRL2_SET_EVEN_LINE_PATTERN [3/3]

#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)

EVEN_LINE_PATTERN 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

◆ LCDIF_CTRL2_SET_ODD_LINE_PATTERN [1/3]

#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)

ODD_LINE_PATTERN 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

◆ LCDIF_CTRL2_SET_ODD_LINE_PATTERN [2/3]

#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)

ODD_LINE_PATTERN 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

◆ LCDIF_CTRL2_SET_ODD_LINE_PATTERN [3/3]

#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)

ODD_LINE_PATTERN 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

◆ LCDIF_CTRL2_SET_OUTSTANDING_REQS [1/3]

#define LCDIF_CTRL2_SET_OUTSTANDING_REQS ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)

OUTSTANDING_REQS 0b000..REQ_1 0b001..REQ_2 0b010..REQ_4 0b011..REQ_8 0b100..REQ_16

◆ LCDIF_CTRL2_SET_OUTSTANDING_REQS [2/3]

#define LCDIF_CTRL2_SET_OUTSTANDING_REQS ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)

OUTSTANDING_REQS 0b000..REQ_1 0b001..REQ_2 0b010..REQ_4 0b011..REQ_8 0b100..REQ_16

◆ LCDIF_CTRL2_SET_OUTSTANDING_REQS [3/3]

#define LCDIF_CTRL2_SET_OUTSTANDING_REQS ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)

OUTSTANDING_REQS 0b000..REQ_1 0b001..REQ_2 0b010..REQ_4 0b011..REQ_8 0b100..REQ_16

◆ LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN [1/3]

#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)

EVEN_LINE_PATTERN 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

◆ LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN [2/3]

#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)

EVEN_LINE_PATTERN 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

◆ LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN [3/3]

#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)

EVEN_LINE_PATTERN 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

◆ LCDIF_CTRL2_TOG_ODD_LINE_PATTERN [1/3]

#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)

ODD_LINE_PATTERN 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

◆ LCDIF_CTRL2_TOG_ODD_LINE_PATTERN [2/3]

#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)

ODD_LINE_PATTERN 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

◆ LCDIF_CTRL2_TOG_ODD_LINE_PATTERN [3/3]

#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)

ODD_LINE_PATTERN 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

◆ LCDIF_CTRL2_TOG_OUTSTANDING_REQS [1/3]

#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)

OUTSTANDING_REQS 0b000..REQ_1 0b001..REQ_2 0b010..REQ_4 0b011..REQ_8 0b100..REQ_16

◆ LCDIF_CTRL2_TOG_OUTSTANDING_REQS [2/3]

#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)

OUTSTANDING_REQS 0b000..REQ_1 0b001..REQ_2 0b010..REQ_4 0b011..REQ_8 0b100..REQ_16

◆ LCDIF_CTRL2_TOG_OUTSTANDING_REQS [3/3]

#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)

OUTSTANDING_REQS 0b000..REQ_1 0b001..REQ_2 0b010..REQ_4 0b011..REQ_8 0b100..REQ_16

◆ LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE [1/3]

#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK)

CSC_DATA_SWIZZLE 0b00..No byte swapping.(Little endian) 0b00..Little Endian byte ordering (same as NO_SWAP). 0b01..Big Endian swap (swap bytes 0,3 and 1,2). 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). 0b10..Swap half-words. 0b11..Swap bytes within each half-word.

◆ LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE [2/3]

#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK)

CSC_DATA_SWIZZLE 0b00..No byte swapping.(Little endian) 0b00..Little Endian byte ordering (same as NO_SWAP). 0b01..Big Endian swap (swap bytes 0,3 and 1,2). 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). 0b10..Swap half-words. 0b11..Swap bytes within each half-word.

◆ LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE [3/3]

#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK)

CSC_DATA_SWIZZLE 0b00..No byte swapping.(Little endian) 0b00..Little Endian byte ordering (same as NO_SWAP). 0b01..Big Endian swap (swap bytes 0,3 and 1,2). 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). 0b10..Swap half-words. 0b11..Swap bytes within each half-word.

◆ LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT [1/3]

#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK)

DATA_FORMAT_18_BIT 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.

◆ LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT [2/3]

#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK)

DATA_FORMAT_18_BIT 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.

◆ LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT [3/3]

#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK)

DATA_FORMAT_18_BIT 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.

◆ LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT [1/3]

#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK)

DATA_FORMAT_24_BIT 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped.

◆ LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT [2/3]

#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK)

DATA_FORMAT_24_BIT 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped.

◆ LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT [3/3]

#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK)

DATA_FORMAT_24_BIT 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped.

◆ LCDIF_CTRL_CLR_DATA_SHIFT_DIR [1/3]

#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK)

DATA_SHIFT_DIR 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.

◆ LCDIF_CTRL_CLR_DATA_SHIFT_DIR [2/3]

#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK)

DATA_SHIFT_DIR 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.

◆ LCDIF_CTRL_CLR_DATA_SHIFT_DIR [3/3]

#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK)

DATA_SHIFT_DIR 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.

◆ LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE [1/3]

#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK)

INPUT_DATA_SWIZZLE 0b00..No byte swapping.(Little endian) 0b00..Little Endian byte ordering (same as NO_SWAP). 0b01..Big Endian swap (swap bytes 0,3 and 1,2). 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). 0b10..Swap half-words. 0b11..Swap bytes within each half-word.

◆ LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE [2/3]

#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK)

INPUT_DATA_SWIZZLE 0b00..No byte swapping.(Little endian) 0b00..Little Endian byte ordering (same as NO_SWAP). 0b01..Big Endian swap (swap bytes 0,3 and 1,2). 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). 0b10..Swap half-words. 0b11..Swap bytes within each half-word.

◆ LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE [3/3]

#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK)

INPUT_DATA_SWIZZLE 0b00..No byte swapping.(Little endian) 0b00..Little Endian byte ordering (same as NO_SWAP). 0b01..Big Endian swap (swap bytes 0,3 and 1,2). 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). 0b10..Swap half-words. 0b11..Swap bytes within each half-word.

◆ LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH [1/3]

#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK)

LCD_DATABUS_WIDTH 0b00..16-bit data bus mode. 0b01..8-bit data bus mode. 0b10..18-bit data bus mode. 0b11..24-bit data bus mode.

◆ LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH [2/3]

#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK)

LCD_DATABUS_WIDTH 0b00..16-bit data bus mode. 0b01..8-bit data bus mode. 0b10..18-bit data bus mode. 0b11..24-bit data bus mode.

◆ LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH [3/3]

#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK)

LCD_DATABUS_WIDTH 0b00..16-bit data bus mode. 0b01..8-bit data bus mode. 0b10..18-bit data bus mode. 0b11..24-bit data bus mode.

◆ LCDIF_CTRL_CLR_WORD_LENGTH [1/3]

#define LCDIF_CTRL_CLR_WORD_LENGTH ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK)

WORD_LENGTH 0b00..Input data is 16 bits per pixel. 0b01..Input data is 8 bits wide. 0b10..Input data is 18 bits per pixel. 0b11..Input data is 24 bits per pixel.

◆ LCDIF_CTRL_CLR_WORD_LENGTH [2/3]

#define LCDIF_CTRL_CLR_WORD_LENGTH ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK)

WORD_LENGTH 0b00..Input data is 16 bits per pixel. 0b01..Input data is 8 bits wide. 0b10..Input data is 18 bits per pixel. 0b11..Input data is 24 bits per pixel.

◆ LCDIF_CTRL_CLR_WORD_LENGTH [3/3]

#define LCDIF_CTRL_CLR_WORD_LENGTH ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK)

WORD_LENGTH 0b00..Input data is 16 bits per pixel. 0b01..Input data is 8 bits wide. 0b10..Input data is 18 bits per pixel. 0b11..Input data is 24 bits per pixel.

◆ LCDIF_CTRL_CSC_DATA_SWIZZLE [1/3]

#define LCDIF_CTRL_CSC_DATA_SWIZZLE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK)

CSC_DATA_SWIZZLE 0b00..No byte swapping.(Little endian) 0b00..Little Endian byte ordering (same as NO_SWAP). 0b01..Big Endian swap (swap bytes 0,3 and 1,2). 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). 0b10..Swap half-words. 0b11..Swap bytes within each half-word.

◆ LCDIF_CTRL_CSC_DATA_SWIZZLE [2/3]

#define LCDIF_CTRL_CSC_DATA_SWIZZLE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK)

CSC_DATA_SWIZZLE 0b00..No byte swapping.(Little endian) 0b00..Little Endian byte ordering (same as NO_SWAP). 0b01..Big Endian swap (swap bytes 0,3 and 1,2). 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). 0b10..Swap half-words. 0b11..Swap bytes within each half-word.

◆ LCDIF_CTRL_CSC_DATA_SWIZZLE [3/3]

#define LCDIF_CTRL_CSC_DATA_SWIZZLE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK)

CSC_DATA_SWIZZLE 0b00..No byte swapping.(Little endian) 0b00..Little Endian byte ordering (same as NO_SWAP). 0b01..Big Endian swap (swap bytes 0,3 and 1,2). 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). 0b10..Swap half-words. 0b11..Swap bytes within each half-word.

◆ LCDIF_CTRL_DATA_FORMAT_18_BIT [1/3]

#define LCDIF_CTRL_DATA_FORMAT_18_BIT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK)

DATA_FORMAT_18_BIT 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.

◆ LCDIF_CTRL_DATA_FORMAT_18_BIT [2/3]

#define LCDIF_CTRL_DATA_FORMAT_18_BIT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK)

DATA_FORMAT_18_BIT 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.

◆ LCDIF_CTRL_DATA_FORMAT_18_BIT [3/3]

#define LCDIF_CTRL_DATA_FORMAT_18_BIT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK)

DATA_FORMAT_18_BIT 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.

◆ LCDIF_CTRL_DATA_FORMAT_24_BIT [1/3]

#define LCDIF_CTRL_DATA_FORMAT_24_BIT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK)

DATA_FORMAT_24_BIT 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped.

◆ LCDIF_CTRL_DATA_FORMAT_24_BIT [2/3]

#define LCDIF_CTRL_DATA_FORMAT_24_BIT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK)

DATA_FORMAT_24_BIT 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped.

◆ LCDIF_CTRL_DATA_FORMAT_24_BIT [3/3]

#define LCDIF_CTRL_DATA_FORMAT_24_BIT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK)

DATA_FORMAT_24_BIT 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped.

◆ LCDIF_CTRL_DATA_SHIFT_DIR [1/3]

#define LCDIF_CTRL_DATA_SHIFT_DIR ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK)

DATA_SHIFT_DIR 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.

◆ LCDIF_CTRL_DATA_SHIFT_DIR [2/3]

#define LCDIF_CTRL_DATA_SHIFT_DIR ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK)

DATA_SHIFT_DIR 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.

◆ LCDIF_CTRL_DATA_SHIFT_DIR [3/3]

#define LCDIF_CTRL_DATA_SHIFT_DIR ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK)

DATA_SHIFT_DIR 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.

◆ LCDIF_CTRL_INPUT_DATA_SWIZZLE [1/3]

#define LCDIF_CTRL_INPUT_DATA_SWIZZLE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK)

INPUT_DATA_SWIZZLE 0b00..No byte swapping.(Little endian) 0b00..Little Endian byte ordering (same as NO_SWAP). 0b01..Big Endian swap (swap bytes 0,3 and 1,2). 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). 0b10..Swap half-words. 0b11..Swap bytes within each half-word.

◆ LCDIF_CTRL_INPUT_DATA_SWIZZLE [2/3]

#define LCDIF_CTRL_INPUT_DATA_SWIZZLE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK)

INPUT_DATA_SWIZZLE 0b00..No byte swapping.(Little endian) 0b00..Little Endian byte ordering (same as NO_SWAP). 0b01..Big Endian swap (swap bytes 0,3 and 1,2). 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). 0b10..Swap half-words. 0b11..Swap bytes within each half-word.

◆ LCDIF_CTRL_INPUT_DATA_SWIZZLE [3/3]

#define LCDIF_CTRL_INPUT_DATA_SWIZZLE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK)

INPUT_DATA_SWIZZLE 0b00..No byte swapping.(Little endian) 0b00..Little Endian byte ordering (same as NO_SWAP). 0b01..Big Endian swap (swap bytes 0,3 and 1,2). 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). 0b10..Swap half-words. 0b11..Swap bytes within each half-word.

◆ LCDIF_CTRL_LCD_DATABUS_WIDTH [1/3]

#define LCDIF_CTRL_LCD_DATABUS_WIDTH ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK)

LCD_DATABUS_WIDTH 0b00..16-bit data bus mode. 0b01..8-bit data bus mode. 0b10..18-bit data bus mode. 0b11..24-bit data bus mode.

◆ LCDIF_CTRL_LCD_DATABUS_WIDTH [2/3]

#define LCDIF_CTRL_LCD_DATABUS_WIDTH ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK)

LCD_DATABUS_WIDTH 0b00..16-bit data bus mode. 0b01..8-bit data bus mode. 0b10..18-bit data bus mode. 0b11..24-bit data bus mode.

◆ LCDIF_CTRL_LCD_DATABUS_WIDTH [3/3]

#define LCDIF_CTRL_LCD_DATABUS_WIDTH ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK)

LCD_DATABUS_WIDTH 0b00..16-bit data bus mode. 0b01..8-bit data bus mode. 0b10..18-bit data bus mode. 0b11..24-bit data bus mode.

◆ LCDIF_CTRL_SET_CSC_DATA_SWIZZLE [1/3]

#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK)

CSC_DATA_SWIZZLE 0b00..No byte swapping.(Little endian) 0b00..Little Endian byte ordering (same as NO_SWAP). 0b01..Big Endian swap (swap bytes 0,3 and 1,2). 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). 0b10..Swap half-words. 0b11..Swap bytes within each half-word.

◆ LCDIF_CTRL_SET_CSC_DATA_SWIZZLE [2/3]

#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK)

CSC_DATA_SWIZZLE 0b00..No byte swapping.(Little endian) 0b00..Little Endian byte ordering (same as NO_SWAP). 0b01..Big Endian swap (swap bytes 0,3 and 1,2). 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). 0b10..Swap half-words. 0b11..Swap bytes within each half-word.

◆ LCDIF_CTRL_SET_CSC_DATA_SWIZZLE [3/3]

#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK)

CSC_DATA_SWIZZLE 0b00..No byte swapping.(Little endian) 0b00..Little Endian byte ordering (same as NO_SWAP). 0b01..Big Endian swap (swap bytes 0,3 and 1,2). 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). 0b10..Swap half-words. 0b11..Swap bytes within each half-word.

◆ LCDIF_CTRL_SET_DATA_FORMAT_18_BIT [1/3]

#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK)

DATA_FORMAT_18_BIT 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.

◆ LCDIF_CTRL_SET_DATA_FORMAT_18_BIT [2/3]

#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK)

DATA_FORMAT_18_BIT 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.

◆ LCDIF_CTRL_SET_DATA_FORMAT_18_BIT [3/3]

#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK)

DATA_FORMAT_18_BIT 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.

◆ LCDIF_CTRL_SET_DATA_FORMAT_24_BIT [1/3]

#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK)

DATA_FORMAT_24_BIT 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped.

◆ LCDIF_CTRL_SET_DATA_FORMAT_24_BIT [2/3]

#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK)

DATA_FORMAT_24_BIT 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped.

◆ LCDIF_CTRL_SET_DATA_FORMAT_24_BIT [3/3]

#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK)

DATA_FORMAT_24_BIT 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped.

◆ LCDIF_CTRL_SET_DATA_SHIFT_DIR [1/3]

#define LCDIF_CTRL_SET_DATA_SHIFT_DIR ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK)

DATA_SHIFT_DIR 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.

◆ LCDIF_CTRL_SET_DATA_SHIFT_DIR [2/3]

#define LCDIF_CTRL_SET_DATA_SHIFT_DIR ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK)

DATA_SHIFT_DIR 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.

◆ LCDIF_CTRL_SET_DATA_SHIFT_DIR [3/3]

#define LCDIF_CTRL_SET_DATA_SHIFT_DIR ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK)

DATA_SHIFT_DIR 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.

◆ LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE [1/3]

#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK)

INPUT_DATA_SWIZZLE 0b00..No byte swapping.(Little endian) 0b00..Little Endian byte ordering (same as NO_SWAP). 0b01..Big Endian swap (swap bytes 0,3 and 1,2). 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). 0b10..Swap half-words. 0b11..Swap bytes within each half-word.

◆ LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE [2/3]

#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK)

INPUT_DATA_SWIZZLE 0b00..No byte swapping.(Little endian) 0b00..Little Endian byte ordering (same as NO_SWAP). 0b01..Big Endian swap (swap bytes 0,3 and 1,2). 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). 0b10..Swap half-words. 0b11..Swap bytes within each half-word.

◆ LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE [3/3]

#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK)

INPUT_DATA_SWIZZLE 0b00..No byte swapping.(Little endian) 0b00..Little Endian byte ordering (same as NO_SWAP). 0b01..Big Endian swap (swap bytes 0,3 and 1,2). 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). 0b10..Swap half-words. 0b11..Swap bytes within each half-word.

◆ LCDIF_CTRL_SET_LCD_DATABUS_WIDTH [1/3]

#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK)

LCD_DATABUS_WIDTH 0b00..16-bit data bus mode. 0b01..8-bit data bus mode. 0b10..18-bit data bus mode. 0b11..24-bit data bus mode.

◆ LCDIF_CTRL_SET_LCD_DATABUS_WIDTH [2/3]

#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK)

LCD_DATABUS_WIDTH 0b00..16-bit data bus mode. 0b01..8-bit data bus mode. 0b10..18-bit data bus mode. 0b11..24-bit data bus mode.

◆ LCDIF_CTRL_SET_LCD_DATABUS_WIDTH [3/3]

#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK)

LCD_DATABUS_WIDTH 0b00..16-bit data bus mode. 0b01..8-bit data bus mode. 0b10..18-bit data bus mode. 0b11..24-bit data bus mode.

◆ LCDIF_CTRL_SET_WORD_LENGTH [1/3]

#define LCDIF_CTRL_SET_WORD_LENGTH ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK)

WORD_LENGTH 0b00..Input data is 16 bits per pixel. 0b01..Input data is 8 bits wide. 0b10..Input data is 18 bits per pixel. 0b11..Input data is 24 bits per pixel.

◆ LCDIF_CTRL_SET_WORD_LENGTH [2/3]

#define LCDIF_CTRL_SET_WORD_LENGTH ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK)

WORD_LENGTH 0b00..Input data is 16 bits per pixel. 0b01..Input data is 8 bits wide. 0b10..Input data is 18 bits per pixel. 0b11..Input data is 24 bits per pixel.

◆ LCDIF_CTRL_SET_WORD_LENGTH [3/3]

#define LCDIF_CTRL_SET_WORD_LENGTH ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK)

WORD_LENGTH 0b00..Input data is 16 bits per pixel. 0b01..Input data is 8 bits wide. 0b10..Input data is 18 bits per pixel. 0b11..Input data is 24 bits per pixel.

◆ LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE [1/3]

#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK)

CSC_DATA_SWIZZLE 0b00..No byte swapping.(Little endian) 0b00..Little Endian byte ordering (same as NO_SWAP). 0b01..Big Endian swap (swap bytes 0,3 and 1,2). 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). 0b10..Swap half-words. 0b11..Swap bytes within each half-word.

◆ LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE [2/3]

#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK)

CSC_DATA_SWIZZLE 0b00..No byte swapping.(Little endian) 0b00..Little Endian byte ordering (same as NO_SWAP). 0b01..Big Endian swap (swap bytes 0,3 and 1,2). 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). 0b10..Swap half-words. 0b11..Swap bytes within each half-word.

◆ LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE [3/3]

#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK)

CSC_DATA_SWIZZLE 0b00..No byte swapping.(Little endian) 0b00..Little Endian byte ordering (same as NO_SWAP). 0b01..Big Endian swap (swap bytes 0,3 and 1,2). 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). 0b10..Swap half-words. 0b11..Swap bytes within each half-word.

◆ LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT [1/3]

#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK)

DATA_FORMAT_18_BIT 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.

◆ LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT [2/3]

#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK)

DATA_FORMAT_18_BIT 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.

◆ LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT [3/3]

#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK)

DATA_FORMAT_18_BIT 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.

◆ LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT [1/3]

#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK)

DATA_FORMAT_24_BIT 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped.

◆ LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT [2/3]

#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK)

DATA_FORMAT_24_BIT 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped.

◆ LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT [3/3]

#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK)

DATA_FORMAT_24_BIT 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped.

◆ LCDIF_CTRL_TOG_DATA_SHIFT_DIR [1/3]

#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK)

DATA_SHIFT_DIR 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.

◆ LCDIF_CTRL_TOG_DATA_SHIFT_DIR [2/3]

#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK)

DATA_SHIFT_DIR 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.

◆ LCDIF_CTRL_TOG_DATA_SHIFT_DIR [3/3]

#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK)

DATA_SHIFT_DIR 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.

◆ LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE [1/3]

#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK)

INPUT_DATA_SWIZZLE 0b00..No byte swapping.(Little endian) 0b00..Little Endian byte ordering (same as NO_SWAP). 0b01..Big Endian swap (swap bytes 0,3 and 1,2). 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). 0b10..Swap half-words. 0b11..Swap bytes within each half-word.

◆ LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE [2/3]

#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK)

INPUT_DATA_SWIZZLE 0b00..No byte swapping.(Little endian) 0b00..Little Endian byte ordering (same as NO_SWAP). 0b01..Big Endian swap (swap bytes 0,3 and 1,2). 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). 0b10..Swap half-words. 0b11..Swap bytes within each half-word.

◆ LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE [3/3]

#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK)

INPUT_DATA_SWIZZLE 0b00..No byte swapping.(Little endian) 0b00..Little Endian byte ordering (same as NO_SWAP). 0b01..Big Endian swap (swap bytes 0,3 and 1,2). 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). 0b10..Swap half-words. 0b11..Swap bytes within each half-word.

◆ LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH [1/3]

#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK)

LCD_DATABUS_WIDTH 0b00..16-bit data bus mode. 0b01..8-bit data bus mode. 0b10..18-bit data bus mode. 0b11..24-bit data bus mode.

◆ LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH [2/3]

#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK)

LCD_DATABUS_WIDTH 0b00..16-bit data bus mode. 0b01..8-bit data bus mode. 0b10..18-bit data bus mode. 0b11..24-bit data bus mode.

◆ LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH [3/3]

#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK)

LCD_DATABUS_WIDTH 0b00..16-bit data bus mode. 0b01..8-bit data bus mode. 0b10..18-bit data bus mode. 0b11..24-bit data bus mode.

◆ LCDIF_CTRL_TOG_WORD_LENGTH [1/3]

#define LCDIF_CTRL_TOG_WORD_LENGTH ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK)

WORD_LENGTH 0b00..Input data is 16 bits per pixel. 0b01..Input data is 8 bits wide. 0b10..Input data is 18 bits per pixel. 0b11..Input data is 24 bits per pixel.

◆ LCDIF_CTRL_TOG_WORD_LENGTH [2/3]

#define LCDIF_CTRL_TOG_WORD_LENGTH ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK)

WORD_LENGTH 0b00..Input data is 16 bits per pixel. 0b01..Input data is 8 bits wide. 0b10..Input data is 18 bits per pixel. 0b11..Input data is 24 bits per pixel.

◆ LCDIF_CTRL_TOG_WORD_LENGTH [3/3]

#define LCDIF_CTRL_TOG_WORD_LENGTH ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK)

WORD_LENGTH 0b00..Input data is 16 bits per pixel. 0b01..Input data is 8 bits wide. 0b10..Input data is 18 bits per pixel. 0b11..Input data is 24 bits per pixel.

◆ LCDIF_CTRL_WORD_LENGTH [1/3]

#define LCDIF_CTRL_WORD_LENGTH ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK)

WORD_LENGTH 0b00..Input data is 16 bits per pixel. 0b01..Input data is 8 bits wide. 0b10..Input data is 18 bits per pixel. 0b11..Input data is 24 bits per pixel.

◆ LCDIF_CTRL_WORD_LENGTH [2/3]

#define LCDIF_CTRL_WORD_LENGTH ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK)

WORD_LENGTH 0b00..Input data is 16 bits per pixel. 0b01..Input data is 8 bits wide. 0b10..Input data is 18 bits per pixel. 0b11..Input data is 24 bits per pixel.

◆ LCDIF_CTRL_WORD_LENGTH [3/3]

#define LCDIF_CTRL_WORD_LENGTH ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK)

WORD_LENGTH 0b00..Input data is 16 bits per pixel. 0b01..Input data is 8 bits wide. 0b10..Input data is 18 bits per pixel. 0b11..Input data is 24 bits per pixel.

◆ LCDIF_PIGEON_0_INC_SEL [1/3]

#define LCDIF_PIGEON_0_INC_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK)

INC_SEL 0b00..pclk 0b01..Line start pulse 0b10..Frame start pulse 0b11..Use another signal as tick event

◆ LCDIF_PIGEON_0_INC_SEL [2/3]

#define LCDIF_PIGEON_0_INC_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK)

INC_SEL 0b00..pclk 0b01..Line start pulse 0b10..Frame start pulse 0b11..Use another signal as tick event

◆ LCDIF_PIGEON_0_INC_SEL [3/3]

#define LCDIF_PIGEON_0_INC_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK)

INC_SEL 0b00..pclk 0b01..Line start pulse 0b10..Frame start pulse 0b11..Use another signal as tick event

◆ LCDIF_PIGEON_0_MASK_CNT_SEL [1/3]

#define LCDIF_PIGEON_0_MASK_CNT_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK)

MASK_CNT_SEL 0b0000..pclk counter within one hscan state 0b0001..pclk cycle within one hscan state 0b0010..line counter within one vscan state 0b0011..line cycle within one vscan state 0b0100..frame counter 0b0101..frame cycle 0b0110..horizontal counter (pclk counter within one line ) 0b0111..vertical counter (line counter within one frame)

◆ LCDIF_PIGEON_0_MASK_CNT_SEL [2/3]

#define LCDIF_PIGEON_0_MASK_CNT_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK)

MASK_CNT_SEL 0b0000..pclk counter within one hscan state 0b0001..pclk cycle within one hscan state 0b0010..line counter within one vscan state 0b0011..line cycle within one vscan state 0b0100..frame counter 0b0101..frame cycle 0b0110..horizontal counter (pclk counter within one line ) 0b0111..vertical counter (line counter within one frame)

◆ LCDIF_PIGEON_0_MASK_CNT_SEL [3/3]

#define LCDIF_PIGEON_0_MASK_CNT_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK)

MASK_CNT_SEL 0b0000..pclk counter within one hscan state 0b0001..pclk cycle within one hscan state 0b0010..line counter within one vscan state 0b0011..line cycle within one vscan state 0b0100..frame counter 0b0101..frame cycle 0b0110..horizontal counter (pclk counter within one line ) 0b0111..vertical counter (line counter within one frame)

◆ LCDIF_PIGEON_0_POL [1/3]

#define LCDIF_PIGEON_0_POL ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK)

POL 0b0..Normal Signal (Active high) 0b1..Inverted signal (Active low)

◆ LCDIF_PIGEON_0_POL [2/3]

#define LCDIF_PIGEON_0_POL ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK)

POL 0b0..Normal Signal (Active high) 0b1..Inverted signal (Active low)

◆ LCDIF_PIGEON_0_POL [3/3]

#define LCDIF_PIGEON_0_POL ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK)

POL 0b0..Normal Signal (Active high) 0b1..Inverted signal (Active low)

◆ LCDIF_PIGEON_0_STATE_MASK [1/3]

#define LCDIF_PIGEON_0_STATE_MASK ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK)

STATE_MASK 0b00000001..FRAME SYNC 0b00000010..FRAME BEGIN 0b00000100..FRAME DATA 0b00001000..FRAME END 0b00010000..LINE SYNC 0b00100000..LINE BEGIN 0b01000000..LINE DATA 0b10000000..LINE END

◆ LCDIF_PIGEON_0_STATE_MASK [2/3]

#define LCDIF_PIGEON_0_STATE_MASK ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK)

STATE_MASK 0b00000001..FRAME SYNC 0b00000010..FRAME BEGIN 0b00000100..FRAME DATA 0b00001000..FRAME END 0b00010000..LINE SYNC 0b00100000..LINE BEGIN 0b01000000..LINE DATA 0b10000000..LINE END

◆ LCDIF_PIGEON_0_STATE_MASK [3/3]

#define LCDIF_PIGEON_0_STATE_MASK ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK)

STATE_MASK 0b00000001..FRAME SYNC 0b00000010..FRAME BEGIN 0b00000100..FRAME DATA 0b00001000..FRAME END 0b00010000..LINE SYNC 0b00100000..LINE BEGIN 0b01000000..LINE DATA 0b10000000..LINE END

◆ LCDIF_PIGEON_1_CLR_CNT [1/3]

#define LCDIF_PIGEON_1_CLR_CNT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK)

CLR_CNT 0b0000000000000000..Keep active until mask off

◆ LCDIF_PIGEON_1_CLR_CNT [2/3]

#define LCDIF_PIGEON_1_CLR_CNT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK)

CLR_CNT 0b0000000000000000..Keep active until mask off

◆ LCDIF_PIGEON_1_CLR_CNT [3/3]

#define LCDIF_PIGEON_1_CLR_CNT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK)

CLR_CNT 0b0000000000000000..Keep active until mask off

◆ LCDIF_PIGEON_1_SET_CNT [1/3]

#define LCDIF_PIGEON_1_SET_CNT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK)

SET_CNT 0b0000000000000000..Start as active

◆ LCDIF_PIGEON_1_SET_CNT [2/3]

#define LCDIF_PIGEON_1_SET_CNT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK)

SET_CNT 0b0000000000000000..Start as active

◆ LCDIF_PIGEON_1_SET_CNT [3/3]

#define LCDIF_PIGEON_1_SET_CNT ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK)

SET_CNT 0b0000000000000000..Start as active

◆ LCDIF_PIGEON_2_SIG_ANOTHER [1/3]

#define LCDIF_PIGEON_2_SIG_ANOTHER ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK)

SIG_ANOTHER 0b00000..Keep active until mask off

◆ LCDIF_PIGEON_2_SIG_ANOTHER [2/3]

#define LCDIF_PIGEON_2_SIG_ANOTHER ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK)

SIG_ANOTHER 0b00000..Keep active until mask off

◆ LCDIF_PIGEON_2_SIG_ANOTHER [3/3]

#define LCDIF_PIGEON_2_SIG_ANOTHER ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK)

SIG_ANOTHER 0b00000..Keep active until mask off

◆ LCDIF_PIGEON_2_SIG_LOGIC [1/3]

#define LCDIF_PIGEON_2_SIG_LOGIC ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK)

SIG_LOGIC 0b0000..No logic operation 0b0001..sigout = sig_another AND this_sig 0b0010..sigout = sig_another OR this_sig 0b0011..mask = sig_another AND other_masks

◆ LCDIF_PIGEON_2_SIG_LOGIC [2/3]

#define LCDIF_PIGEON_2_SIG_LOGIC ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK)

SIG_LOGIC 0b0000..No logic operation 0b0001..sigout = sig_another AND this_sig 0b0010..sigout = sig_another OR this_sig 0b0011..mask = sig_another AND other_masks

◆ LCDIF_PIGEON_2_SIG_LOGIC [3/3]

#define LCDIF_PIGEON_2_SIG_LOGIC ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK)

SIG_LOGIC 0b0000..No logic operation 0b0001..sigout = sig_another AND this_sig 0b0010..sigout = sig_another OR this_sig 0b0011..mask = sig_another AND other_masks

◆ LCDIF_RGB_ADJUST_CLR_RGB_ADJ_MODE

#define LCDIF_RGB_ADJUST_CLR_RGB_ADJ_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_CLR_RGB_ADJ_MODE_SHIFT)) & LCDIF_RGB_ADJUST_CLR_RGB_ADJ_MODE_MASK)

RGB_ADJ_MODE 0b00..No Adjust 0b01..Increment RGB 0b10..Decrement RGB 0b11..Multiply RGB

◆ LCDIF_RGB_ADJUST_RGB_ADJ_MODE

#define LCDIF_RGB_ADJUST_RGB_ADJ_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_RGB_ADJ_MODE_SHIFT)) & LCDIF_RGB_ADJUST_RGB_ADJ_MODE_MASK)

RGB_ADJ_MODE 0b00..No Adjust 0b01..Increment RGB 0b10..Decrement RGB 0b11..Multiply RGB

◆ LCDIF_RGB_ADJUST_SET_RGB_ADJ_MODE

#define LCDIF_RGB_ADJUST_SET_RGB_ADJ_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_SET_RGB_ADJ_MODE_SHIFT)) & LCDIF_RGB_ADJUST_SET_RGB_ADJ_MODE_MASK)

RGB_ADJ_MODE 0b00..No Adjust 0b01..Increment RGB 0b10..Decrement RGB 0b11..Multiply RGB

◆ LCDIF_RGB_ADJUST_TOG_RGB_ADJ_MODE

#define LCDIF_RGB_ADJUST_TOG_RGB_ADJ_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_TOG_RGB_ADJ_MODE_SHIFT)) & LCDIF_RGB_ADJUST_TOG_RGB_ADJ_MODE_MASK)

RGB_ADJ_MODE 0b00..No Adjust 0b01..Increment RGB 0b10..Decrement RGB 0b11..Multiply RGB

◆ LCDIF_VDCTRL0_CLR_VSYNC_OEB [1/2]

#define LCDIF_VDCTRL0_CLR_VSYNC_OEB ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK)

VSYNC_OEB 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.

◆ LCDIF_VDCTRL0_CLR_VSYNC_OEB [2/2]

#define LCDIF_VDCTRL0_CLR_VSYNC_OEB ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK)

VSYNC_OEB 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.

◆ LCDIF_VDCTRL0_SET_VSYNC_OEB [1/2]

#define LCDIF_VDCTRL0_SET_VSYNC_OEB ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK)

VSYNC_OEB 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.

◆ LCDIF_VDCTRL0_SET_VSYNC_OEB [2/2]

#define LCDIF_VDCTRL0_SET_VSYNC_OEB ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK)

VSYNC_OEB 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.

◆ LCDIF_VDCTRL0_TOG_VSYNC_OEB [1/2]

#define LCDIF_VDCTRL0_TOG_VSYNC_OEB ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK)

VSYNC_OEB 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.

◆ LCDIF_VDCTRL0_TOG_VSYNC_OEB [2/2]

#define LCDIF_VDCTRL0_TOG_VSYNC_OEB ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK)

VSYNC_OEB 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.

◆ LCDIF_VDCTRL0_VSYNC_OEB [1/2]

#define LCDIF_VDCTRL0_VSYNC_OEB ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_VSYNC_OEB_MASK)

VSYNC_OEB 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.

◆ LCDIF_VDCTRL0_VSYNC_OEB [2/2]

#define LCDIF_VDCTRL0_VSYNC_OEB ( x ) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_VSYNC_OEB_MASK)

VSYNC_OEB 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.

Macros

CTRL - LCDIF General Control Register

CTRL_SET - LCDIF General Control Register

CTRL_CLR - LCDIF General Control Register

CTRL_TOG - LCDIF General Control Register

CTRL1 - LCDIF General Control1 Register

CTRL1_SET - LCDIF General Control1 Register

CTRL1_CLR - LCDIF General Control1 Register

CTRL1_TOG - LCDIF General Control1 Register

CTRL2 - LCDIF General Control2 Register

CTRL2_SET - LCDIF General Control2 Register

CTRL2_CLR - LCDIF General Control2 Register

CTRL2_TOG - LCDIF General Control2 Register

TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register

CUR_BUF - LCD Interface Current Buffer Address Register

NEXT_BUF - LCD Interface Next Buffer Address Register

VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0

VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0

VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0

VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0

VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1

VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2

VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3

VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4

BM_ERROR_STAT - Bus Master Error Status Register

CRC_STAT - CRC Status Register

STAT - LCD Interface Status Register

RGB_ADJUST - RGB Color Range Adjust

RGB_ADJUST_SET - RGB Color Range Adjust

RGB_ADJUST_CLR - RGB Color Range Adjust

RGB_ADJUST_TOG - RGB Color Range Adjust

PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register

PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register

PIGEONCTRL0_CLR - LCDIF Pigeon Mode Control0 Register

PIGEONCTRL0_TOG - LCDIF Pigeon Mode Control0 Register

PIGEONCTRL1 - LCDIF Pigeon Mode Control1 Register

PIGEONCTRL1_SET - LCDIF Pigeon Mode Control1 Register

PIGEONCTRL1_CLR - LCDIF Pigeon Mode Control1 Register

PIGEONCTRL1_TOG - LCDIF Pigeon Mode Control1 Register

PIGEONCTRL2 - LCDIF Pigeon Mode Control2 Register

PIGEONCTRL2_SET - LCDIF Pigeon Mode Control2 Register

PIGEONCTRL2_CLR - LCDIF Pigeon Mode Control2 Register

PIGEONCTRL2_TOG - LCDIF Pigeon Mode Control2 Register

PIGEON_0 - Panel Interface Signal Generator Register

PIGEON_1 - Panel Interface Signal Generator Register

PIGEON_2 - Panel Interface Signal Generator Register

LUT_CTRL - Look Up Table Control Register

LUT0_ADDR - Lookup Table 0 Index Register

LUT0_DATA - Lookup Table 0 Data Register

LUT1_ADDR - Lookup Table 1 Index Register

LUT1_DATA - Lookup Table 1 Data Register

CTRL - LCDIF General Control Register

CTRL_SET - LCDIF General Control Register

CTRL_CLR - LCDIF General Control Register

CTRL_TOG - LCDIF General Control Register

CTRL1 - LCDIF General Control1 Register

CTRL1_SET - LCDIF General Control1 Register

CTRL1_CLR - LCDIF General Control1 Register

CTRL1_TOG - LCDIF General Control1 Register

CTRL2 - LCDIF General Control2 Register

CTRL2_SET - LCDIF General Control2 Register

CTRL2_CLR - LCDIF General Control2 Register

CTRL2_TOG - LCDIF General Control2 Register

TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register

CUR_BUF - LCD Interface Current Buffer Address Register

NEXT_BUF - LCD Interface Next Buffer Address Register

VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0

VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0

VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0

VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0

VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1

VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2

VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3

VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4

BM_ERROR_STAT - Bus Master Error Status Register

CRC_STAT - CRC Status Register

STAT - LCD Interface Status Register

THRES - LCDIF Threshold Register

PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register

PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register