RTEMS 6.1-rc2
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IOMUXC_GPR Register Masks
Mapping Information » Iomuxc_pads » Device Peripheral Access Layer » IOMUXC_GPR Peripheral Access Layer

GPR1 - GPR1 General Purpose Register

#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK   (0x7U)
 
#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK)
 
#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK   (0x38U)
 
#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK)
 
#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK   (0xC0U)
 
#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK)
 
#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK   (0x300U)
 
#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)
 
#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK   (0xC00U)
 
#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK)
 
#define IOMUXC_GPR_GPR1_GINT_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR1_GINT_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR1_GINT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK)
 
#define IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL_MASK)
 
#define IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
 
#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK   (0x80000U)
 
#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT   (19U)
 
#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK)
 
#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)
 
#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK   (0x200000U)
 
#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK)
 
#define IOMUXC_GPR_GPR1_EXC_MON_MASK   (0x400000U)
 
#define IOMUXC_GPR_GPR1_EXC_MON_SHIFT   (22U)
 
#define IOMUXC_GPR_GPR1_EXC_MON(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK)
 
#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK   (0x80000000U)
 
#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT   (31U)
 
#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK)
 

GPR2 - GPR2 General Purpose Register

#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK)
 
#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK)
 
#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK   (0xFF0000U)
 
#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR2_MQS_CLK_DIV(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK)
 
#define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK   (0x1000000U)
 
#define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT   (24U)
 
#define IOMUXC_GPR_GPR2_MQS_SW_RST(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK)
 
#define IOMUXC_GPR_GPR2_MQS_EN_MASK   (0x2000000U)
 
#define IOMUXC_GPR_GPR2_MQS_EN_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR2_MQS_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK)
 
#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK   (0x4000000U)
 
#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT   (26U)
 
#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK)
 
#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK   (0x10000000U)
 
#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK)
 
#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK   (0x20000000U)
 
#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT   (29U)
 
#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK)
 
#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK   (0x40000000U)
 
#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK)
 
#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK   (0x80000000U)
 
#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT   (31U)
 
#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK)
 

GPR3 - GPR3 General Purpose Register

#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR3_DCP_KEY_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK)
 
#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK   (0x1U)
 
#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT   (0U)
 
#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK   (0x2U)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT   (1U)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK)
 
#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK   (0xCU)
 
#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT   (2U)
 
#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK   (0x10000U)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT   (16U)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK   (0x20000U)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT   (17U)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK   (0x40000U)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT   (18U)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK   (0x80000U)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT   (19U)
 
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK)
 

GPR4 - GPR4 General Purpose Register

#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR4_ENET_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR4_PIT_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK   (0x40000U)
 
#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK   (0x80000U)
 
#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT   (19U)
 
#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR4_ENET_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK   (0x200000U)
 
#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK   (0x400000U)
 
#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT   (22U)
 
#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK   (0x800000U)
 
#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT   (23U)
 
#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK   (0x2000000U)
 
#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK   (0x4000000U)
 
#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT   (26U)
 
#define IOMUXC_GPR_GPR4_PIT_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK   (0x8000000U)
 
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT   (27U)
 
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK   (0x10000000U)
 
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK   (0x20000000U)
 
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT   (29U)
 
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK)
 

GPR5 - GPR5 General Purpose Register

#define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR5_WDOG1_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK)
 
#define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR5_WDOG2_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK)
 
#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK   (0x800000U)
 
#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT   (23U)
 
#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK)
 
#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK   (0x2000000U)
 
#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK)
 
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK   (0x10000000U)
 
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK)
 
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK   (0x20000000U)
 
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT   (29U)
 
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK)
 

GPR6 - GPR6 General Purpose Register

#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK   (0x8000U)
 
#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT   (15U)
 
#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK   (0x40000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK   (0x80000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT   (19U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK   (0x200000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK   (0x400000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT   (22U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK   (0x800000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT   (23U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK   (0x1000000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT   (24U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK   (0x2000000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK   (0x4000000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT   (26U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK   (0x8000000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT   (27U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK   (0x10000000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK   (0x20000000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT   (29U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK   (0x40000000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK   (0x80000000U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT   (31U)
 
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK)
 

GPR7 - GPR7 General Purpose Register

#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK   (0x8000U)
 
#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT   (15U)
 
#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK   (0x40000U)
 
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK   (0x80000U)
 
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT   (19U)
 
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK   (0x200000U)
 
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK   (0x400000U)
 
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT   (22U)
 
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK   (0x800000U)
 
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT   (23U)
 
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK   (0x1000000U)
 
#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT   (24U)
 
#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK   (0x2000000U)
 
#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK   (0x4000000U)
 
#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT   (26U)
 
#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK   (0x8000000U)
 
#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT   (27U)
 
#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK   (0x10000000U)
 
#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK   (0x20000000U)
 
#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT   (29U)
 
#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK   (0x40000000U)
 
#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK   (0x80000000U)
 
#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT   (31U)
 
#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK)
 

GPR8 - GPR8 General Purpose Register

#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK   (0x8000U)
 
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT   (15U)
 
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK   (0x40000U)
 
#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK   (0x80000U)
 
#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT   (19U)
 
#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK   (0x200000U)
 
#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK   (0x400000U)
 
#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT   (22U)
 
#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK   (0x800000U)
 
#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT   (23U)
 
#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK   (0x1000000U)
 
#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT   (24U)
 
#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK   (0x2000000U)
 
#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK   (0x4000000U)
 
#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT   (26U)
 
#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK   (0x8000000U)
 
#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT   (27U)
 
#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK   (0x10000000U)
 
#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK   (0x20000000U)
 
#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT   (29U)
 
#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK   (0x40000000U)
 
#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK   (0x80000000U)
 
#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT   (31U)
 
#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK)
 

GPR10 - GPR10 General Purpose Register

#define IOMUXC_GPR_GPR10_NIDEN_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR10_NIDEN_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR10_NIDEN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK)
 
#define IOMUXC_GPR_GPR10_DBG_EN_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR10_DBG_EN_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR10_DBG_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK)
 
#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR10_SEC_ERR_RESP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK)
 
#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK)
 
#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK)
 
#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK   (0xFE00U)
 
#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK)
 
#define IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR10_LOCK_NIDEN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK)
 
#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR10_LOCK_DBG_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK)
 
#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK   (0x40000U)
 
#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK)
 
#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK)
 
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK   (0x1000000U)
 
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT   (24U)
 
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK)
 
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK   (0xFE000000U)
 
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK)
 

GPR11 - GPR11 General Purpose Register

#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK   (0x3U)
 
#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK)
 
#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK   (0xCU)
 
#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK)
 
#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK   (0x30U)
 
#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK)
 
#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK   (0xC0U)
 
#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK)
 
#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK   (0xF00U)
 
#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK)
 
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK   (0x30000U)
 
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK)
 
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK   (0xC0000U)
 
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK)
 
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK   (0x300000U)
 
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK)
 
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK   (0xC00000U)
 
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT   (22U)
 
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK)
 
#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK   (0xF000000U)
 
#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT   (24U)
 
#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK)
 

GPR12 - GPR12 General Purpose Register

#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK)
 

GPR13 - GPR13 General Purpose Register

#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR13_ARCACHE_USDHC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK)
 
#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR13_AWCACHE_USDHC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK)
 
#define IOMUXC_GPR_GPR13_CACHE_ENET_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR13_CACHE_ENET(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK)
 
#define IOMUXC_GPR_GPR13_CACHE_USB_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR13_CACHE_USB_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR13_CACHE_USB(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK)
 

GPR14 - GPR14 General Purpose Register

#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK)
 
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK)
 
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK)
 
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK)
 
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK)
 
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK)
 
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK)
 
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK)
 
#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK)
 
#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK)
 
#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK)
 
#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK)
 

GPR16 - GPR16 General Purpose Register

#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)
 
#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK   (0xFFFFFF80U)
 
#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT)) & IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK)
 

GPR17 - GPR17 General Purpose Register

#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK   (0xFFFFFFFFU)
 
#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK)
 

GPR18 - GPR18 General Purpose Register

#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK)
 
#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK)
 

GPR19 - GPR19 General Purpose Register

#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK)
 
#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK)
 

GPR20 - GPR20 General Purpose Register

#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK)
 
#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK)
 

GPR21 - GPR21 General Purpose Register

#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK)
 
#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK)
 

GPR22 - GPR22 General Purpose Register

#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK)
 
#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK)
 

GPR23 - GPR23 General Purpose Register

#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK)
 
#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK)
 

GPR24 - GPR24 General Purpose Register

#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK)
 
#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK)
 

GPR25 - GPR25 General Purpose Register

#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK)
 
#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK)
 

GPR0 - GPR0 General Purpose Register

#define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK   (0x7U)
 
#define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK)
 
#define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_MASK   (0x38U)
 
#define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_MASK)
 
#define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_MASK   (0xC0U)
 
#define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_MASK)
 
#define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_MASK)
 
#define IOMUXC_GPR_GPR0_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR0_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR0_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DWP_SHIFT)) & IOMUXC_GPR_GPR0_DWP_MASK)
 
#define IOMUXC_GPR_GPR0_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR0_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR0_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR0_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK   (0xFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK)
 
#define IOMUXC_LPSR_GPR_GPR0_DWP_MASK   (0x30000000U)
 
#define IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT   (28U)
 
#define IOMUXC_LPSR_GPR_GPR0_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_MASK)
 
#define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK)
 

GPR1 - GPR1 General Purpose Register

#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK   (0x3U)
 
#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)
 
#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)
 
#define IOMUXC_GPR_GPR1_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR1_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR1_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_DWP_SHIFT)) & IOMUXC_GPR_GPR1_DWP_MASK)
 
#define IOMUXC_GPR_GPR1_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR1_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR1_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR1_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK   (0xFFFFU)
 
#define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK)
 
#define IOMUXC_LPSR_GPR_GPR1_DWP_MASK   (0x30000000U)
 
#define IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT   (28U)
 
#define IOMUXC_LPSR_GPR_GPR1_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_MASK)
 
#define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK)
 

GPR2 - GPR2 General Purpose Register

#define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_MASK   (0x3U)
 
#define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_MASK)
 
#define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_MASK)
 
#define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_MASK)
 
#define IOMUXC_GPR_GPR2_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR2_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR2_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DWP_SHIFT)) & IOMUXC_GPR_GPR2_DWP_MASK)
 
#define IOMUXC_GPR_GPR2_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR2_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR2_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR2_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR2_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR2_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK)
 

GPR3 - GPR3 General Purpose Register

#define IOMUXC_GPR_GPR3_MQS_CLK_DIV_MASK   (0xFFU)
 
#define IOMUXC_GPR_GPR3_MQS_CLK_DIV_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR3_MQS_CLK_DIV(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR3_MQS_CLK_DIV_MASK)
 
#define IOMUXC_GPR_GPR3_MQS_SW_RST_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR3_MQS_SW_RST_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR3_MQS_SW_RST(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR3_MQS_SW_RST_MASK)
 
#define IOMUXC_GPR_GPR3_MQS_EN_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR3_MQS_EN_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR3_MQS_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR3_MQS_EN_MASK)
 
#define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_MASK)
 
#define IOMUXC_GPR_GPR3_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR3_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR3_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DWP_SHIFT)) & IOMUXC_GPR_GPR3_DWP_MASK)
 
#define IOMUXC_GPR_GPR3_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR3_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR3_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR3_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR3_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR3_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK)
 

GPR4 - GPR4 General Purpose Register

#define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK)
 
#define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK)
 
#define IOMUXC_GPR_GPR4_ENET_TIME_SEL_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR4_ENET_TIME_SEL_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR4_ENET_TIME_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_TIME_SEL_MASK)
 
#define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_MASK)
 
#define IOMUXC_GPR_GPR4_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR4_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR4_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_DWP_SHIFT)) & IOMUXC_GPR_GPR4_DWP_MASK)
 
#define IOMUXC_GPR_GPR4_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR4_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR4_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR4_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR4_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR4_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK)
 

GPR5 - GPR5 General Purpose Register

#define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK)
 
#define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK)
 
#define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK)
 
#define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_MASK)
 
#define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_MASK)
 
#define IOMUXC_GPR_GPR5_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR5_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR5_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_DWP_SHIFT)) & IOMUXC_GPR_GPR5_DWP_MASK)
 
#define IOMUXC_GPR_GPR5_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR5_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR5_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR5_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR5_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR5_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK)
 

GPR7 - GPR7 General Purpose Register

#define IOMUXC_GPR_GPR7_GINT_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR7_GINT_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR7_GINT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_GINT_SHIFT)) & IOMUXC_GPR_GPR7_GINT_MASK)
 
#define IOMUXC_GPR_GPR7_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR7_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR7_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_DWP_SHIFT)) & IOMUXC_GPR_GPR7_DWP_MASK)
 
#define IOMUXC_GPR_GPR7_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR7_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR7_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR7_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR7_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR7_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK)
 

GPR8 - GPR8 General Purpose Register

#define IOMUXC_GPR_GPR8_WDOG1_MASK_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR8_WDOG1_MASK_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR8_WDOG1_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR8_WDOG1_MASK_MASK)
 
#define IOMUXC_GPR_GPR8_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR8_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR8_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_DWP_SHIFT)) & IOMUXC_GPR_GPR8_DWP_MASK)
 
#define IOMUXC_GPR_GPR8_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR8_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR8_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR8_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR8_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR8_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK)
 

GPR9 - GPR9 General Purpose Register

#define IOMUXC_GPR_GPR9_WDOG2_MASK_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR9_WDOG2_MASK_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR9_WDOG2_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR9_WDOG2_MASK_MASK)
 
#define IOMUXC_GPR_GPR9_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR9_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR9_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_DWP_SHIFT)) & IOMUXC_GPR_GPR9_DWP_MASK)
 
#define IOMUXC_GPR_GPR9_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR9_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR9_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR9_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR9_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR9_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK)
 

GPR10 - GPR10 General Purpose Register

#define IOMUXC_GPR_GPR10_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR10_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR10_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DWP_SHIFT)) & IOMUXC_GPR_GPR10_DWP_MASK)
 
#define IOMUXC_GPR_GPR10_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR10_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR10_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR10_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR10_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR10_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK)
 

GPR11 - GPR11 General Purpose Register

#define IOMUXC_GPR_GPR11_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR11_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR11_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_DWP_SHIFT)) & IOMUXC_GPR_GPR11_DWP_MASK)
 
#define IOMUXC_GPR_GPR11_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR11_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR11_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR11_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR11_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR11_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK)
 

GPR12 - GPR12 General Purpose Register

#define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_MASK)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR12_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR12_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR12_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_DWP_SHIFT)) & IOMUXC_GPR_GPR12_DWP_MASK)
 
#define IOMUXC_GPR_GPR12_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR12_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR12_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR12_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR12_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR12_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK)
 

GPR13 - GPR13 General Purpose Register

#define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_MASK)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR13_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR13_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR13_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_DWP_SHIFT)) & IOMUXC_GPR_GPR13_DWP_MASK)
 
#define IOMUXC_GPR_GPR13_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR13_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR13_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR13_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR13_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR13_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK)
 

GPR14 - GPR14 General Purpose Register

#define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_MASK)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR14_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR14_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR14_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_DWP_SHIFT)) & IOMUXC_GPR_GPR14_DWP_MASK)
 
#define IOMUXC_GPR_GPR14_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR14_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR14_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR14_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR14_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR14_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK)
 

GPR15 - GPR15 General Purpose Register

#define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_MASK)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR15_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR15_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR15_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_DWP_SHIFT)) & IOMUXC_GPR_GPR15_DWP_MASK)
 
#define IOMUXC_GPR_GPR15_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR15_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR15_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR15_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR15_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR15_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK)
 

GPR16 - GPR16 General Purpose Register

#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)
 
#define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK)
 
#define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_MASK)
 
#define IOMUXC_GPR_GPR16_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR16_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR16_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_DWP_SHIFT)) & IOMUXC_GPR_GPR16_DWP_MASK)
 
#define IOMUXC_GPR_GPR16_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR16_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR16_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR16_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR16_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR16_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK)
 

GPR17 - GPR17 General Purpose Register

#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK   (0xFFFFU)
 
#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK)
 
#define IOMUXC_GPR_GPR17_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR17_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR17_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_DWP_SHIFT)) & IOMUXC_GPR_GPR17_DWP_MASK)
 
#define IOMUXC_GPR_GPR17_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR17_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR17_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR17_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR17_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR17_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK)
 

GPR18 - GPR18 General Purpose Register

#define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK   (0xFFFFU)
 
#define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_SHIFT)) & IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK)
 
#define IOMUXC_GPR_GPR18_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR18_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR18_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_DWP_SHIFT)) & IOMUXC_GPR_GPR18_DWP_MASK)
 
#define IOMUXC_GPR_GPR18_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR18_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR18_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR18_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR18_LOCK_MASK   (0xFFFF0000U)
 
#define IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR18_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_LOCK_MASK)
 

GPR20 - GPR20 General Purpose Register

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_MASK   (0x8000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_SHIFT   (15U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_MASK   (0x40000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_MASK   (0x80000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_SHIFT   (19U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_MASK   (0x200000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_MASK   (0x400000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_SHIFT   (22U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_MASK   (0x800000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_SHIFT   (23U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_MASK   (0x1000000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_SHIFT   (24U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_MASK   (0x2000000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_MASK   (0x4000000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_SHIFT   (26U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_MASK   (0x8000000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_SHIFT   (27U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_MASK)
 
#define IOMUXC_GPR_GPR20_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR20_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR20_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_DWP_SHIFT)) & IOMUXC_GPR_GPR20_DWP_MASK)
 
#define IOMUXC_GPR_GPR20_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR20_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR20_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR20_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR20_LOCK_MASK   (0xFFFF0000U)
 
#define IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR20_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_LOCK_MASK)
 

GPR21 - GPR21 General Purpose Register

#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_MASK)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_MASK)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_MASK)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_MASK)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_MASK)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_MASK)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_MASK)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_MASK)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_MASK)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_MASK)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_MASK)
 
#define IOMUXC_GPR_GPR21_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR21_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR21_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_DWP_SHIFT)) & IOMUXC_GPR_GPR21_DWP_MASK)
 
#define IOMUXC_GPR_GPR21_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR21_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR21_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR21_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR21_LOCK_MASK   (0xFFFF0000U)
 
#define IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR21_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_LOCK_MASK)
 

GPR22 - GPR22 General Purpose Register

#define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK)
 
#define IOMUXC_GPR_GPR22_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR22_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR22_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_DWP_SHIFT)) & IOMUXC_GPR_GPR22_DWP_MASK)
 
#define IOMUXC_GPR_GPR22_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR22_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR22_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR22_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR22_LOCK_MASK   (0xFFFF0000U)
 
#define IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR22_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_LOCK_MASK)
 

GPR23 - GPR23 General Purpose Register

#define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK)
 
#define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_MASK)
 
#define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_MASK)
 
#define IOMUXC_GPR_GPR23_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR23_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR23_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_DWP_SHIFT)) & IOMUXC_GPR_GPR23_DWP_MASK)
 
#define IOMUXC_GPR_GPR23_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR23_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR23_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR23_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR23_LOCK_MASK   (0xFFFF0000U)
 
#define IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR23_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_LOCK_MASK)
 

GPR24 - GPR24 General Purpose Register

#define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_SHIFT)) & IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK)
 
#define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_MASK)
 
#define IOMUXC_GPR_GPR24_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR24_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR24_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_DWP_SHIFT)) & IOMUXC_GPR_GPR24_DWP_MASK)
 
#define IOMUXC_GPR_GPR24_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR24_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR24_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR24_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR24_LOCK_MASK   (0xFFFF0000U)
 
#define IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR24_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_LOCK_MASK)
 

GPR25 - GPR25 General Purpose Register

#define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_SHIFT)) & IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK)
 
#define IOMUXC_GPR_GPR25_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR25_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR25_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_DWP_SHIFT)) & IOMUXC_GPR_GPR25_DWP_MASK)
 
#define IOMUXC_GPR_GPR25_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR25_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR25_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR25_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK   (0x20U)
 
#define IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT   (5U)
 
#define IOMUXC_LPSR_GPR_GPR25_APC_VALID(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK)
 
#define IOMUXC_LPSR_GPR_GPR25_LOCK_MASK   (0xFFFF0000U)
 
#define IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR25_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_LOCK_MASK)
 

GPR26 - GPR26 General Purpose Register

#define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_SHIFT)) & IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK)
 
#define IOMUXC_GPR_GPR26_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR26_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR26_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_DWP_SHIFT)) & IOMUXC_GPR_GPR26_DWP_MASK)
 
#define IOMUXC_GPR_GPR26_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR26_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR26_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR26_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK   (0x1FFFFFFU)
 
#define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK)
 
#define IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK   (0xE000000U)
 
#define IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT   (25U)
 
#define IOMUXC_LPSR_GPR_GPR26_FIELD_0(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK)
 
#define IOMUXC_LPSR_GPR_GPR26_DWP_MASK   (0x30000000U)
 
#define IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT   (28U)
 
#define IOMUXC_LPSR_GPR_GPR26_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_MASK)
 
#define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK)
 

GPR27 - GPR27 General Purpose Register

#define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_SHIFT)) & IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK)
 
#define IOMUXC_GPR_GPR27_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR27_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR27_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_DWP_SHIFT)) & IOMUXC_GPR_GPR27_DWP_MASK)
 
#define IOMUXC_GPR_GPR27_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR27_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR27_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR27_DWP_LOCK_MASK)
 

GPR28 - GPR28 General Purpose Register

#define IOMUXC_GPR_GPR28_ARCACHE_USDHC_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR28_ARCACHE_USDHC_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR28_ARCACHE_USDHC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR28_ARCACHE_USDHC_MASK)
 
#define IOMUXC_GPR_GPR28_AWCACHE_USDHC_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR28_AWCACHE_USDHC_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR28_AWCACHE_USDHC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR28_AWCACHE_USDHC_MASK)
 
#define IOMUXC_GPR_GPR28_CACHE_ENET1G_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR28_CACHE_ENET1G_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR28_CACHE_ENET1G(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_ENET1G_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_ENET1G_MASK)
 
#define IOMUXC_GPR_GPR28_CACHE_ENET_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR28_CACHE_ENET_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR28_CACHE_ENET(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_ENET_MASK)
 
#define IOMUXC_GPR_GPR28_CACHE_USB_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR28_CACHE_USB_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR28_CACHE_USB(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_USB_MASK)
 
#define IOMUXC_GPR_GPR28_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR28_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR28_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_DWP_SHIFT)) & IOMUXC_GPR_GPR28_DWP_MASK)
 
#define IOMUXC_GPR_GPR28_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR28_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR28_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR28_DWP_LOCK_MASK)
 

GPR29 - GPR29 General Purpose Register

#define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_MASK)
 
#define IOMUXC_GPR_GPR29_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR29_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR29_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_DWP_SHIFT)) & IOMUXC_GPR_GPR29_DWP_MASK)
 
#define IOMUXC_GPR_GPR29_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR29_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR29_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR29_DWP_LOCK_MASK)
 

GPR30 - GPR30 General Purpose Register

#define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_MASK)
 
#define IOMUXC_GPR_GPR30_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR30_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR30_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_DWP_SHIFT)) & IOMUXC_GPR_GPR30_DWP_MASK)
 
#define IOMUXC_GPR_GPR30_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR30_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR30_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR30_DWP_LOCK_MASK)
 

GPR31 - GPR31 General Purpose Register

#define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_MASK)
 
#define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_SHIFT)) & IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_MASK)
 
#define IOMUXC_GPR_GPR31_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR31_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR31_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_DWP_SHIFT)) & IOMUXC_GPR_GPR31_DWP_MASK)
 
#define IOMUXC_GPR_GPR31_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR31_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR31_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR31_DWP_LOCK_MASK)
 

GPR32 - GPR32 General Purpose Register

#define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_MASK)
 
#define IOMUXC_GPR_GPR32_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR32_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR32_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_DWP_SHIFT)) & IOMUXC_GPR_GPR32_DWP_MASK)
 
#define IOMUXC_GPR_GPR32_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR32_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR32_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR32_DWP_LOCK_MASK)
 
#define IOMUXC_SNVS_GPR_GPR32_GPR_MASK   (0xFFFEU)
 
#define IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT   (1U)
 
#define IOMUXC_SNVS_GPR_GPR32_GPR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_GPR_MASK)
 
#define IOMUXC_SNVS_GPR_GPR32_LOCK_MASK   (0xFFFF0000U)
 
#define IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT   (16U)
 
#define IOMUXC_SNVS_GPR_GPR32_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK)
 

GPR33 - GPR33 General Purpose Register

#define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_MASK)
 
#define IOMUXC_GPR_GPR33_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR33_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR33_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_DWP_SHIFT)) & IOMUXC_GPR_GPR33_DWP_MASK)
 
#define IOMUXC_GPR_GPR33_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR33_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR33_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR33_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK)
 
#define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK   (0x100U)
 
#define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT   (8U)
 
#define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK)
 
#define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK   (0x200U)
 
#define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT   (9U)
 
#define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK)
 
#define IOMUXC_LPSR_GPR_GPR33_DWP_MASK   (0x30000000U)
 
#define IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT   (28U)
 
#define IOMUXC_LPSR_GPR_GPR33_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_MASK)
 
#define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK   (0x2U)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT   (1U)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK)
 
#define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK   (0x4U)
 
#define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT   (2U)
 
#define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK   (0x10000U)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT   (16U)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK   (0x20000U)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT   (17U)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK   (0x40000U)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT   (18U)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK   (0x80000U)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT   (19U)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK)
 
#define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK   (0x100000U)
 
#define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT   (20U)
 
#define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK)
 

GPR34 - GPR34 General Purpose Register

#define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_MASK)
 
#define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_SHIFT)) & IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_MASK)
 
#define IOMUXC_GPR_GPR34_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR34_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR34_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_DWP_SHIFT)) & IOMUXC_GPR_GPR34_DWP_MASK)
 
#define IOMUXC_GPR_GPR34_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR34_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR34_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR34_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK   (0x2U)
 
#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT   (1U)
 
#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK   (0x4U)
 
#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT   (2U)
 
#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK   (0x8U)
 
#define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK   (0x20U)
 
#define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT   (5U)
 
#define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK)
 
#define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK   (0x800U)
 
#define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT   (11U)
 
#define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK)
 
#define IOMUXC_LPSR_GPR_GPR34_DWP_MASK   (0x30000000U)
 
#define IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT   (28U)
 
#define IOMUXC_LPSR_GPR_GPR34_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_MASK)
 
#define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK)
 
#define IOMUXC_SNVS_GPR_GPR34_LOCK_MASK   (0x1U)
 
#define IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT   (0U)
 
#define IOMUXC_SNVS_GPR_GPR34_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_LOCK_MASK)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK   (0x2U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT   (1U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK   (0xCU)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT   (2U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK   (0x80U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT   (7U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK   (0xFF00U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT   (8U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK   (0x30000U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT   (16U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK   (0xC0000U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT   (18U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK   (0x800000U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT   (23U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK   (0xF000000U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT   (24U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK)
 

GPR35 - GPR35 General Purpose Register

#define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_MASK)
 
#define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_SHIFT)) & IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_MASK)
 
#define IOMUXC_GPR_GPR35_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR35_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR35_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_DWP_SHIFT)) & IOMUXC_GPR_GPR35_DWP_MASK)
 
#define IOMUXC_GPR_GPR35_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR35_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR35_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR35_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK   (0x2U)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT   (1U)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK   (0x4U)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT   (2U)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK   (0x8U)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK   (0x20U)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT   (5U)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK   (0x40U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT   (6U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK   (0x80U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT   (7U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK   (0x100U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT   (8U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK   (0x200U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT   (9U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK   (0x400U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT   (10U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK   (0x800U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT   (11U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK   (0x1000U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT   (12U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK   (0x2000U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT   (13U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK   (0x8000U)
 
#define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT   (15U)
 
#define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK   (0x10000U)
 
#define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK   (0x20000U)
 
#define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT   (17U)
 
#define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK   (0x40000U)
 
#define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT   (18U)
 
#define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK   (0x80000U)
 
#define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT   (19U)
 
#define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK   (0x100000U)
 
#define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT   (20U)
 
#define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK   (0x200000U)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT   (21U)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK   (0x400000U)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT   (22U)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK   (0x800000U)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT   (23U)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK   (0x1000000U)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT   (24U)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK   (0x2000000U)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT   (25U)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK   (0x4000000U)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT   (26U)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_DWP_MASK   (0x30000000U)
 
#define IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT   (28U)
 
#define IOMUXC_LPSR_GPR_GPR35_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK)
 
#define IOMUXC_SNVS_GPR_GPR35_LOCK_MASK   (0x1U)
 
#define IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT   (0U)
 
#define IOMUXC_SNVS_GPR_GPR35_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_LOCK_MASK)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK   (0x8U)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT   (3U)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK   (0xFF0U)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT   (4U)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK   (0x8000U)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT   (15U)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK   (0xFFF0000U)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT   (16U)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK   (0x30000000U)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT   (28U)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK   (0xC0000000U)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT   (30U)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK)
 

GPR36 - GPR36 General Purpose Register

#define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_MASK)
 
#define IOMUXC_GPR_GPR36_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR36_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR36_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_DWP_SHIFT)) & IOMUXC_GPR_GPR36_DWP_MASK)
 
#define IOMUXC_GPR_GPR36_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR36_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR36_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR36_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK   (0x2U)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT   (1U)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK   (0x4U)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT   (2U)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK   (0x8U)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK   (0x20U)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT   (5U)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK   (0x40U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT   (6U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK   (0x80U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT   (7U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK   (0x100U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT   (8U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK   (0x200U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT   (9U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK   (0x400U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT   (10U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK   (0x800U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT   (11U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK   (0x1000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT   (12U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK   (0x2000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT   (13U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK   (0x4000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT   (14U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK   (0x8000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT   (15U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK   (0x10000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK   (0x20000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT   (17U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK   (0x40000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT   (18U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK   (0x80000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT   (19U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK   (0x100000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT   (20U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK   (0x200000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT   (21U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK   (0x400000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT   (22U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK   (0x800000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT   (23U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK   (0x1000000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT   (24U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK   (0x2000000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT   (25U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK   (0x4000000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT   (26U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_DWP_MASK   (0x30000000U)
 
#define IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT   (28U)
 
#define IOMUXC_LPSR_GPR_GPR36_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK   (0x800000U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT   (23U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK   (0x4000000U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT   (26U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK   (0x8000000U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT   (27U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK   (0x10000000U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT   (28U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK   (0x20000000U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT   (29U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK   (0x40000000U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT   (30U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK   (0x80000000U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT   (31U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK)
 

GPR37 - GPR37 General Purpose Register

#define IOMUXC_GPR_GPR37_NIDEN_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR37_NIDEN_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR37_NIDEN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_NIDEN_SHIFT)) & IOMUXC_GPR_GPR37_NIDEN_MASK)
 
#define IOMUXC_GPR_GPR37_DBG_EN_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR37_DBG_EN_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR37_DBG_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR37_DBG_EN_MASK)
 
#define IOMUXC_GPR_GPR37_EXC_MON_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR37_EXC_MON_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR37_EXC_MON(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR37_EXC_MON_MASK)
 
#define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_SHIFT)) & IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_MASK)
 
#define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_SHIFT)) & IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_MASK)
 
#define IOMUXC_GPR_GPR37_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR37_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR37_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DWP_SHIFT)) & IOMUXC_GPR_GPR37_DWP_MASK)
 
#define IOMUXC_GPR_GPR37_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR37_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR37_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR37_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK   (0x2U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT   (1U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK   (0x4U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT   (2U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK   (0x8U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK   (0x20U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT   (5U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK   (0x40U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT   (6U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK   (0x80U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT   (7U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK   (0x100U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT   (8U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK   (0x200U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT   (9U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK   (0x400U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT   (10U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK   (0x800U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT   (11U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK   (0x1000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT   (12U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK   (0x2000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT   (13U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK   (0x4000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT   (14U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK   (0x8000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT   (15U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK   (0x10000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK   (0x20000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT   (17U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK   (0x40000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT   (18U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK   (0x80000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT   (19U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK   (0x100000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT   (20U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK   (0x200000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT   (21U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK   (0x400000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT   (22U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK   (0x800000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT   (23U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK   (0x1000000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT   (24U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK   (0x2000000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT   (25U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK   (0x4000000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT   (26U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_DWP_MASK   (0x30000000U)
 
#define IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT   (28U)
 
#define IOMUXC_LPSR_GPR_GPR37_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK)
 
#define IOMUXC_SNVS_GPR_GPR37_LOCK_MASK   (0x1U)
 
#define IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT   (0U)
 
#define IOMUXC_SNVS_GPR_GPR37_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_LOCK_MASK)
 
#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK   (0x7FEU)
 
#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT   (1U)
 
#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK)
 
#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK   (0x1FF800U)
 
#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT   (11U)
 
#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK)
 

GPR38 - GPR38 General Purpose Register

#define IOMUXC_GPR_GPR38_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR38_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR38_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR38_DWP_SHIFT)) & IOMUXC_GPR_GPR38_DWP_MASK)
 
#define IOMUXC_GPR_GPR38_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR38_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR38_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR38_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR38_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK   (0x2U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT   (1U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK   (0x4U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT   (2U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK   (0x8U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK   (0x20U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT   (5U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK   (0x40U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT   (6U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK   (0x80U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT   (7U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK   (0x100U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT   (8U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK   (0x200U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT   (9U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK   (0x400U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT   (10U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK   (0x800U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT   (11U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK   (0x1000U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT   (12U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK   (0x2000U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT   (13U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK   (0x4000U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT   (14U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK   (0x8000U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT   (15U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK   (0x10000U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK   (0x20000U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT   (17U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK   (0x40000U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT   (18U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK   (0x80000U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT   (19U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK   (0x100000U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT   (20U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK   (0x200000U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT   (21U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK   (0x400000U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT   (22U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK   (0x800000U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT   (23U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK   (0x1000000U)
 
#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT   (24U)
 
#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK   (0x2000000U)
 
#define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT   (25U)
 
#define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK   (0x4000000U)
 
#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT   (26U)
 
#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_DWP_MASK   (0x30000000U)
 
#define IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT   (28U)
 
#define IOMUXC_LPSR_GPR_GPR38_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK)
 

GPR39 - GPR39 General Purpose Register

#define IOMUXC_GPR_GPR39_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR39_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR39_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR39_DWP_SHIFT)) & IOMUXC_GPR_GPR39_DWP_MASK)
 
#define IOMUXC_GPR_GPR39_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR39_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR39_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR39_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR39_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK   (0x2U)
 
#define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT   (1U)
 
#define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK   (0x4U)
 
#define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT   (2U)
 
#define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK   (0x8U)
 
#define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK   (0x20U)
 
#define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT   (5U)
 
#define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK   (0x40U)
 
#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT   (6U)
 
#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK   (0x80U)
 
#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT   (7U)
 
#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK   (0x100U)
 
#define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT   (8U)
 
#define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK   (0x200U)
 
#define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT   (9U)
 
#define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK   (0x400U)
 
#define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT   (10U)
 
#define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK   (0x800U)
 
#define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT   (11U)
 
#define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK   (0x1000U)
 
#define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT   (12U)
 
#define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK   (0x2000U)
 
#define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT   (13U)
 
#define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK   (0x4000U)
 
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT   (14U)
 
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK   (0x8000U)
 
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT   (15U)
 
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK   (0x10000U)
 
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK   (0x20000U)
 
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT   (17U)
 
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_DWP_MASK   (0x30000000U)
 
#define IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT   (28U)
 
#define IOMUXC_LPSR_GPR_GPR39_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK)
 

GPR40 - GPR40 General Purpose Register

#define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_MASK   (0xFFFFU)
 
#define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_SHIFT)) & IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_MASK)
 
#define IOMUXC_GPR_GPR40_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR40_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR40_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_DWP_SHIFT)) & IOMUXC_GPR_GPR40_DWP_MASK)
 
#define IOMUXC_GPR_GPR40_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR40_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR40_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR40_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK   (0x2U)
 
#define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT   (1U)
 
#define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK   (0x4U)
 
#define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT   (2U)
 
#define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK   (0x8U)
 
#define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK   (0x20U)
 
#define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT   (5U)
 
#define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK   (0x40U)
 
#define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT   (6U)
 
#define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK   (0x80U)
 
#define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT   (7U)
 
#define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK   (0x100U)
 
#define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT   (8U)
 
#define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK   (0x200U)
 
#define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT   (9U)
 
#define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK   (0x400U)
 
#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT   (10U)
 
#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK   (0x800U)
 
#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT   (11U)
 
#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK   (0x1000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT   (12U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK   (0x2000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT   (13U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK   (0x4000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT   (14U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK   (0x8000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT   (15U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK   (0x10000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK   (0x20000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT   (17U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK   (0x40000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT   (18U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK   (0x80000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT   (19U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK   (0x100000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT   (20U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK   (0x200000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT   (21U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK   (0x400000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT   (22U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK   (0x800000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT   (23U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK   (0x1000000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT   (24U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK   (0x2000000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT   (25U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK   (0x4000000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT   (26U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK   (0x8000000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT   (27U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK   (0x10000000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT   (28U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK   (0x20000000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT   (29U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK   (0x40000000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT   (30U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK   (0x80000000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT   (31U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK)
 

GPR41 - GPR41 General Purpose Register

#define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_MASK   (0xFFFFU)
 
#define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_SHIFT)) & IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_MASK)
 
#define IOMUXC_GPR_GPR41_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR41_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR41_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_DWP_SHIFT)) & IOMUXC_GPR_GPR41_DWP_MASK)
 
#define IOMUXC_GPR_GPR41_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR41_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR41_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR41_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK   (0x2U)
 
#define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT   (1U)
 
#define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK   (0x4U)
 
#define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT   (2U)
 
#define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK   (0x8U)
 
#define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK   (0x20U)
 
#define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT   (5U)
 
#define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK   (0x40U)
 
#define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT   (6U)
 
#define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK   (0x80U)
 
#define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT   (7U)
 
#define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK   (0x100U)
 
#define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT   (8U)
 
#define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK   (0x200U)
 
#define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT   (9U)
 
#define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK   (0x400U)
 
#define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT   (10U)
 
#define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK   (0x800U)
 
#define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT   (11U)
 
#define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK   (0x1000U)
 
#define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT   (12U)
 
#define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK   (0x2000U)
 
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT   (13U)
 
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK   (0x4000U)
 
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT   (14U)
 
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK   (0x8000U)
 
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT   (15U)
 
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK   (0x10000U)
 
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK   (0x1000000U)
 
#define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT   (24U)
 
#define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK)
 

GPR42 - GPR42 General Purpose Register

#define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_MASK   (0xFFFFU)
 
#define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_SHIFT)) & IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_MASK)
 
#define IOMUXC_GPR_GPR42_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR42_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR42_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_DWP_SHIFT)) & IOMUXC_GPR_GPR42_DWP_MASK)
 
#define IOMUXC_GPR_GPR42_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR42_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR42_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR42_DWP_LOCK_MASK)
 

GPR43 - GPR43 General Purpose Register

#define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK   (0xFFFFU)
 
#define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_SHIFT)) & IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK)
 
#define IOMUXC_GPR_GPR43_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR43_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR43_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_DWP_SHIFT)) & IOMUXC_GPR_GPR43_DWP_MASK)
 
#define IOMUXC_GPR_GPR43_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR43_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR43_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR43_DWP_LOCK_MASK)
 

GPR44 - GPR44 General Purpose Register

#define IOMUXC_GPR_GPR44_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR44_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR44_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR44_DWP_SHIFT)) & IOMUXC_GPR_GPR44_DWP_MASK)
 
#define IOMUXC_GPR_GPR44_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR44_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR44_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR44_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR44_DWP_LOCK_MASK)
 

GPR45 - GPR45 General Purpose Register

#define IOMUXC_GPR_GPR45_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR45_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR45_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR45_DWP_SHIFT)) & IOMUXC_GPR_GPR45_DWP_MASK)
 
#define IOMUXC_GPR_GPR45_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR45_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR45_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR45_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR45_DWP_LOCK_MASK)
 

GPR46 - GPR46 General Purpose Register

#define IOMUXC_GPR_GPR46_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR46_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR46_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR46_DWP_SHIFT)) & IOMUXC_GPR_GPR46_DWP_MASK)
 
#define IOMUXC_GPR_GPR46_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR46_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR46_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR46_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR46_DWP_LOCK_MASK)
 

GPR47 - GPR47 General Purpose Register

#define IOMUXC_GPR_GPR47_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR47_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR47_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR47_DWP_SHIFT)) & IOMUXC_GPR_GPR47_DWP_MASK)
 
#define IOMUXC_GPR_GPR47_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR47_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR47_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR47_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR47_DWP_LOCK_MASK)
 

GPR48 - GPR48 General Purpose Register

#define IOMUXC_GPR_GPR48_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR48_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR48_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR48_DWP_SHIFT)) & IOMUXC_GPR_GPR48_DWP_MASK)
 
#define IOMUXC_GPR_GPR48_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR48_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR48_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR48_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR48_DWP_LOCK_MASK)
 

GPR49 - GPR49 General Purpose Register

#define IOMUXC_GPR_GPR49_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR49_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR49_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR49_DWP_SHIFT)) & IOMUXC_GPR_GPR49_DWP_MASK)
 
#define IOMUXC_GPR_GPR49_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR49_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR49_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR49_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR49_DWP_LOCK_MASK)
 

GPR50 - GPR50 General Purpose Register

#define IOMUXC_GPR_GPR50_CAAM_IPS_MGR_MASK   (0x1FU)
 
#define IOMUXC_GPR_GPR50_CAAM_IPS_MGR_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR50_CAAM_IPS_MGR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_CAAM_IPS_MGR_SHIFT)) & IOMUXC_GPR_GPR50_CAAM_IPS_MGR_MASK)
 
#define IOMUXC_GPR_GPR50_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR50_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR50_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_DWP_SHIFT)) & IOMUXC_GPR_GPR50_DWP_MASK)
 
#define IOMUXC_GPR_GPR50_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR50_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR50_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR50_DWP_LOCK_MASK)
 

GPR51 - GPR51 General Purpose Register

#define IOMUXC_GPR_GPR51_M7_NMI_CLEAR_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR51_M7_NMI_CLEAR_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR51_M7_NMI_CLEAR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_M7_NMI_CLEAR_SHIFT)) & IOMUXC_GPR_GPR51_M7_NMI_CLEAR_MASK)
 
#define IOMUXC_GPR_GPR51_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR51_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR51_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_DWP_SHIFT)) & IOMUXC_GPR_GPR51_DWP_MASK)
 
#define IOMUXC_GPR_GPR51_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR51_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR51_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR51_DWP_LOCK_MASK)
 

GPR52 - GPR52 General Purpose Register

#define IOMUXC_GPR_GPR52_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR52_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR52_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR52_DWP_SHIFT)) & IOMUXC_GPR_GPR52_DWP_MASK)
 
#define IOMUXC_GPR_GPR52_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR52_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR52_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR52_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR52_DWP_LOCK_MASK)
 

GPR53 - GPR53 General Purpose Register

#define IOMUXC_GPR_GPR53_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR53_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR53_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR53_DWP_SHIFT)) & IOMUXC_GPR_GPR53_DWP_MASK)
 
#define IOMUXC_GPR_GPR53_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR53_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR53_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR53_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR53_DWP_LOCK_MASK)
 

GPR54 - GPR54 General Purpose Register

#define IOMUXC_GPR_GPR54_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR54_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR54_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR54_DWP_SHIFT)) & IOMUXC_GPR_GPR54_DWP_MASK)
 
#define IOMUXC_GPR_GPR54_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR54_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR54_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR54_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR54_DWP_LOCK_MASK)
 

GPR55 - GPR55 General Purpose Register

#define IOMUXC_GPR_GPR55_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR55_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR55_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR55_DWP_SHIFT)) & IOMUXC_GPR_GPR55_DWP_MASK)
 
#define IOMUXC_GPR_GPR55_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR55_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR55_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR55_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR55_DWP_LOCK_MASK)
 

GPR59 - GPR59 General Purpose Register

#define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_MASK)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_MASK)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_MASK)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_MASK   (0xC0U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_MASK)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_MASK   (0x300U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_MASK)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_MASK   (0xC00U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_MASK)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK   (0x3F000U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK)
 
#define IOMUXC_GPR_GPR59_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR59_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR59_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_DWP_SHIFT)) & IOMUXC_GPR_GPR59_DWP_MASK)
 
#define IOMUXC_GPR_GPR59_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR59_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR59_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR59_DWP_LOCK_MASK)
 

GPR62 - GPR62 General Purpose Register

#define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_MASK   (0x7U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_MASK)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_MASK   (0x38U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_MASK)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_MASK   (0x1C0U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_MASK)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_MASK   (0x600U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_MASK)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_MASK   (0x3800U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_MASK)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK   (0x40000U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK   (0x80000U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_SHIFT   (19U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK)
 
#define IOMUXC_GPR_GPR62_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR62_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR62_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_DWP_SHIFT)) & IOMUXC_GPR_GPR62_DWP_MASK)
 
#define IOMUXC_GPR_GPR62_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR62_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR62_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR62_DWP_LOCK_MASK)
 

GPR63 - GPR63 General Purpose Register

#define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_MASK   (0x7U)
 
#define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_MASK)
 

GPR64 - GPR64 General Purpose Register

#define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_MASK)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_MASK)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_MASK)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_MASK)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_MASK   (0xF0U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_MASK)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_MASK   (0xF00U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_MASK)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_MASK)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_MASK)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_MASK)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_MASK)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_MASK   (0x1E00000U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_MASK)
 
#define IOMUXC_GPR_GPR64_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR64_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR64_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_DWP_SHIFT)) & IOMUXC_GPR_GPR64_DWP_MASK)
 
#define IOMUXC_GPR_GPR64_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR64_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR64_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR64_DWP_LOCK_MASK)
 

GPR65 - GPR65 General Purpose Register

#define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_MASK)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_MASK)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_MASK)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_MASK)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_MASK   (0xF0U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_MASK)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_MASK   (0xF00U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_MASK)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_MASK)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_MASK)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_MASK)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_MASK)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_MASK   (0x1E00000U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_MASK)
 
#define IOMUXC_GPR_GPR65_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR65_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR65_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_DWP_SHIFT)) & IOMUXC_GPR_GPR65_DWP_MASK)
 
#define IOMUXC_GPR_GPR65_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR65_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR65_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR65_DWP_LOCK_MASK)
 

GPR66 - GPR66 General Purpose Register

#define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_MASK)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_MASK)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_MASK)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_MASK)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_MASK   (0xF0U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_MASK)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_MASK   (0xF00U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_MASK)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_MASK)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_MASK)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_MASK)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_MASK)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_MASK   (0x1E00000U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_MASK)
 
#define IOMUXC_GPR_GPR66_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR66_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR66_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_DWP_SHIFT)) & IOMUXC_GPR_GPR66_DWP_MASK)
 
#define IOMUXC_GPR_GPR66_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR66_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR66_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR66_DWP_LOCK_MASK)
 

GPR67 - GPR67 General Purpose Register

#define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_MASK)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_MASK)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_MASK)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_MASK)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_MASK   (0xF0U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_MASK)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_MASK   (0xF00U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_MASK)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_MASK)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_MASK)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_MASK)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_MASK)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_MASK   (0x1E00000U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_MASK)
 
#define IOMUXC_GPR_GPR67_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR67_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR67_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_DWP_SHIFT)) & IOMUXC_GPR_GPR67_DWP_MASK)
 
#define IOMUXC_GPR_GPR67_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR67_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR67_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR67_DWP_LOCK_MASK)
 

GPR68 - GPR68 General Purpose Register

#define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_MASK)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_MASK)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_MASK)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_MASK)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_MASK   (0xF0U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_MASK)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_MASK   (0xF00U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_MASK)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_MASK)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_MASK)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_MASK)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_MASK)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_MASK   (0x1E00000U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_MASK)
 
#define IOMUXC_GPR_GPR68_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR68_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR68_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_DWP_SHIFT)) & IOMUXC_GPR_GPR68_DWP_MASK)
 
#define IOMUXC_GPR_GPR68_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR68_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR68_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR68_DWP_LOCK_MASK)
 

GPR69 - GPR69 General Purpose Register

#define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_MASK)
 
#define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_MASK)
 
#define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_MASK)
 
#define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_MASK)
 
#define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_MASK)
 
#define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_MASK)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_MASK)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_MASK)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_MASK)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_MASK)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_MASK)
 
#define IOMUXC_GPR_GPR69_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR69_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR69_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_DWP_SHIFT)) & IOMUXC_GPR_GPR69_DWP_MASK)
 
#define IOMUXC_GPR_GPR69_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR69_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR69_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR69_DWP_LOCK_MASK)
 

GPR70 - GPR70 General Purpose Register

#define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR70_ADC1_STOP_REQ_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR70_ADC1_STOP_REQ_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR70_ADC1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR70_ADC2_STOP_REQ_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR70_ADC2_STOP_REQ_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR70_ADC2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR70_CAAM_STOP_REQ_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR70_CAAM_STOP_REQ_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR70_CAAM_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAAM_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAAM_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR70_CAN1_STOP_REQ_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR70_CAN1_STOP_REQ_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR70_CAN1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR70_CAN2_STOP_REQ_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR70_CAN2_STOP_REQ_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR70_CAN2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR70_CAN3_STOP_REQ_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR70_CAN3_STOP_REQ_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR70_CAN3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN3_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR70_EDMA_STOP_REQ_MASK   (0x8000U)
 
#define IOMUXC_GPR_GPR70_EDMA_STOP_REQ_SHIFT   (15U)
 
#define IOMUXC_GPR_GPR70_EDMA_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_EDMA_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR70_ENET_IPG_DOZE_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR70_ENET_IPG_DOZE_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR70_ENET_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ENET_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR70_ENET_STOP_REQ_MASK   (0x40000U)
 
#define IOMUXC_GPR_GPR70_ENET_STOP_REQ_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR70_ENET_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ENET_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_MASK   (0x80000U)
 
#define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_SHIFT   (19U)
 
#define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_MASK   (0x200000U)
 
#define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_MASK   (0x400000U)
 
#define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_SHIFT   (22U)
 
#define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_MASK   (0x800000U)
 
#define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_SHIFT   (23U)
 
#define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_MASK   (0x1000000U)
 
#define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_SHIFT   (24U)
 
#define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_MASK   (0x2000000U)
 
#define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_MASK   (0x4000000U)
 
#define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_SHIFT   (26U)
 
#define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR70_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR70_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR70_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_DWP_SHIFT)) & IOMUXC_GPR_GPR70_DWP_MASK)
 
#define IOMUXC_GPR_GPR70_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR70_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR70_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR70_DWP_LOCK_MASK)
 

GPR71 - GPR71 General Purpose Register

#define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_MASK   (0x8000U)
 
#define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_SHIFT   (15U)
 
#define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_MASK   (0x40000U)
 
#define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_MASK   (0x80000U)
 
#define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_SHIFT   (19U)
 
#define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_MASK   (0x200000U)
 
#define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_MASK   (0x400000U)
 
#define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_SHIFT   (22U)
 
#define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_MASK   (0x800000U)
 
#define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_SHIFT   (23U)
 
#define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_MASK   (0x1000000U)
 
#define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_SHIFT   (24U)
 
#define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_MASK   (0x2000000U)
 
#define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_MASK   (0x4000000U)
 
#define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_SHIFT   (26U)
 
#define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR71_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR71_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR71_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_DWP_SHIFT)) & IOMUXC_GPR_GPR71_DWP_MASK)
 
#define IOMUXC_GPR_GPR71_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR71_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR71_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR71_DWP_LOCK_MASK)
 

GPR72 - GPR72 General Purpose Register

#define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_MASK   (0x8000U)
 
#define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_SHIFT   (15U)
 
#define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_MASK   (0x40000U)
 
#define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_MASK   (0x80000U)
 
#define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_SHIFT   (19U)
 
#define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_MASK   (0x200000U)
 
#define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_MASK   (0x400000U)
 
#define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_SHIFT   (22U)
 
#define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_MASK   (0x800000U)
 
#define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_SHIFT   (23U)
 
#define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_MASK   (0x1000000U)
 
#define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_SHIFT   (24U)
 
#define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_MASK   (0x2000000U)
 
#define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_MASK   (0x4000000U)
 
#define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_SHIFT   (26U)
 
#define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR72_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR72_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR72_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_DWP_SHIFT)) & IOMUXC_GPR_GPR72_DWP_MASK)
 
#define IOMUXC_GPR_GPR72_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR72_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR72_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR72_DWP_LOCK_MASK)
 

GPR73 - GPR73 General Purpose Register

#define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_MASK   (0x8000U)
 
#define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_SHIFT   (15U)
 
#define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_MASK   (0x40000U)
 
#define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_MASK   (0x80000U)
 
#define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_SHIFT   (19U)
 
#define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_MASK   (0x200000U)
 
#define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_MASK   (0x400000U)
 
#define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_SHIFT   (22U)
 
#define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_MASK   (0x800000U)
 
#define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_SHIFT   (23U)
 
#define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR73_MIC_IPG_DOZE_MASK   (0x1000000U)
 
#define IOMUXC_GPR_GPR73_MIC_IPG_DOZE_SHIFT   (24U)
 
#define IOMUXC_GPR_GPR73_MIC_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_MIC_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR73_MIC_STOP_REQ_MASK   (0x2000000U)
 
#define IOMUXC_GPR_GPR73_MIC_STOP_REQ_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR73_MIC_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_MIC_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_MASK   (0x4000000U)
 
#define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_SHIFT   (26U)
 
#define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR73_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR73_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR73_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_DWP_SHIFT)) & IOMUXC_GPR_GPR73_DWP_MASK)
 
#define IOMUXC_GPR_GPR73_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR73_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR73_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR73_DWP_LOCK_MASK)
 

GPR74 - GPR74 General Purpose Register

#define IOMUXC_GPR_GPR74_PIT1_STOP_REQ_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR74_PIT1_STOP_REQ_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR74_PIT1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_PIT1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_PIT1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR74_PIT2_STOP_REQ_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR74_PIT2_STOP_REQ_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR74_PIT2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_PIT2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_PIT2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR74_SEMC_STOP_REQ_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR74_SEMC_STOP_REQ_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR74_SEMC_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SEMC_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR74_SAI1_STOP_REQ_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR74_SAI1_STOP_REQ_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR74_SAI1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR74_SAI2_STOP_REQ_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR74_SAI2_STOP_REQ_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR74_SAI2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR74_SAI3_STOP_REQ_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR74_SAI3_STOP_REQ_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR74_SAI3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI3_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR74_SAI4_STOP_REQ_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR74_SAI4_STOP_REQ_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR74_SAI4_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI4_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_MASK)
 
#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_MASK   (0x8000U)
 
#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_SHIFT   (15U)
 
#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_MASK)
 
#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_MASK)
 
#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_MASK)
 
#define IOMUXC_GPR_GPR74_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR74_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR74_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_DWP_SHIFT)) & IOMUXC_GPR_GPR74_DWP_MASK)
 
#define IOMUXC_GPR_GPR74_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR74_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR74_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR74_DWP_LOCK_MASK)
 

GPR75 - GPR75 General Purpose Register

#define IOMUXC_GPR_GPR75_ADC1_STOP_ACK_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR75_ADC1_STOP_ACK_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR75_ADC1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ADC1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ADC1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_ADC2_STOP_ACK_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR75_ADC2_STOP_ACK_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR75_ADC2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ADC2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ADC2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_CAAM_STOP_ACK_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR75_CAAM_STOP_ACK_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR75_CAAM_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAAM_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAAM_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_CAN1_STOP_ACK_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR75_CAN1_STOP_ACK_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR75_CAN1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_CAN2_STOP_ACK_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR75_CAN2_STOP_ACK_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR75_CAN2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_CAN3_STOP_ACK_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR75_CAN3_STOP_ACK_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR75_CAN3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN3_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_EDMA_STOP_ACK_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR75_EDMA_STOP_ACK_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR75_EDMA_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_EDMA_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_ENET_STOP_ACK_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR75_ENET_STOP_ACK_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR75_ENET_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ENET_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_MASK   (0x8000U)
 
#define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_SHIFT   (15U)
 
#define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_MASK   (0x40000U)
 
#define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_MASK   (0x80000U)
 
#define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_SHIFT   (19U)
 
#define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_MASK   (0x200000U)
 
#define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_MASK   (0x400000U)
 
#define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_SHIFT   (22U)
 
#define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_MASK   (0x800000U)
 
#define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_SHIFT   (23U)
 
#define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_MASK   (0x1000000U)
 
#define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_SHIFT   (24U)
 
#define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_MASK   (0x2000000U)
 
#define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_MASK   (0x4000000U)
 
#define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_SHIFT   (26U)
 
#define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_MASK   (0x8000000U)
 
#define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_SHIFT   (27U)
 
#define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_MASK   (0x10000000U)
 
#define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_MASK   (0x20000000U)
 
#define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_SHIFT   (29U)
 
#define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_MASK   (0x40000000U)
 
#define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_MASK   (0x80000000U)
 
#define IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_SHIFT   (31U)
 
#define IOMUXC_GPR_GPR75_LPUART8_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_MASK)
 

GPR76 - GPR76 General Purpose Register

#define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_MIC_STOP_ACK_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR76_MIC_STOP_ACK_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR76_MIC_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_MIC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_MIC_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_PIT1_STOP_ACK_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR76_PIT1_STOP_ACK_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR76_PIT1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_PIT1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_PIT1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_PIT2_STOP_ACK_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR76_PIT2_STOP_ACK_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR76_PIT2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_PIT2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_PIT2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_SEMC_STOP_ACK_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR76_SEMC_STOP_ACK_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR76_SEMC_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SEMC_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_SAI1_STOP_ACK_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR76_SAI1_STOP_ACK_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR76_SAI1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_SAI2_STOP_ACK_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR76_SAI2_STOP_ACK_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR76_SAI2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_SAI3_STOP_ACK_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR76_SAI3_STOP_ACK_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR76_SAI3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI3_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_SAI4_STOP_ACK_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR76_SAI4_STOP_ACK_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR76_SAI4_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI4_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_MASK)
 
#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_MASK)
 
#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_MASK   (0x8000U)
 
#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_SHIFT   (15U)
 
#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_MASK)
 
#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_MASK)
 

GPR0 - GPR0 General Purpose Register

#define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK   (0x7U)
 
#define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK)
 
#define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_MASK   (0x38U)
 
#define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_MASK)
 
#define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_MASK   (0xC0U)
 
#define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_MASK)
 
#define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_MASK)
 
#define IOMUXC_GPR_GPR0_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR0_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR0_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DWP_SHIFT)) & IOMUXC_GPR_GPR0_DWP_MASK)
 
#define IOMUXC_GPR_GPR0_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR0_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR0_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR0_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK   (0xFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK)
 
#define IOMUXC_LPSR_GPR_GPR0_DWP_MASK   (0x30000000U)
 
#define IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT   (28U)
 
#define IOMUXC_LPSR_GPR_GPR0_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_MASK)
 
#define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK)
 

GPR1 - GPR1 General Purpose Register

#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK   (0x3U)
 
#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)
 
#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)
 
#define IOMUXC_GPR_GPR1_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR1_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR1_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_DWP_SHIFT)) & IOMUXC_GPR_GPR1_DWP_MASK)
 
#define IOMUXC_GPR_GPR1_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR1_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR1_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR1_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK   (0xFFFFU)
 
#define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK)
 
#define IOMUXC_LPSR_GPR_GPR1_DWP_MASK   (0x30000000U)
 
#define IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT   (28U)
 
#define IOMUXC_LPSR_GPR_GPR1_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_MASK)
 
#define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK)
 

GPR2 - GPR2 General Purpose Register

#define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_MASK   (0x3U)
 
#define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_MASK)
 
#define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_MASK)
 
#define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_MASK)
 
#define IOMUXC_GPR_GPR2_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR2_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR2_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DWP_SHIFT)) & IOMUXC_GPR_GPR2_DWP_MASK)
 
#define IOMUXC_GPR_GPR2_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR2_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR2_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR2_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR2_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR2_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK)
 

GPR3 - GPR3 General Purpose Register

#define IOMUXC_GPR_GPR3_MQS_CLK_DIV_MASK   (0xFFU)
 
#define IOMUXC_GPR_GPR3_MQS_CLK_DIV_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR3_MQS_CLK_DIV(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR3_MQS_CLK_DIV_MASK)
 
#define IOMUXC_GPR_GPR3_MQS_SW_RST_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR3_MQS_SW_RST_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR3_MQS_SW_RST(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR3_MQS_SW_RST_MASK)
 
#define IOMUXC_GPR_GPR3_MQS_EN_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR3_MQS_EN_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR3_MQS_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR3_MQS_EN_MASK)
 
#define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_MASK)
 
#define IOMUXC_GPR_GPR3_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR3_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR3_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DWP_SHIFT)) & IOMUXC_GPR_GPR3_DWP_MASK)
 
#define IOMUXC_GPR_GPR3_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR3_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR3_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR3_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR3_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR3_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK)
 

GPR4 - GPR4 General Purpose Register

#define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK)
 
#define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK)
 
#define IOMUXC_GPR_GPR4_ENET_TIME_SEL_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR4_ENET_TIME_SEL_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR4_ENET_TIME_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_TIME_SEL_MASK)
 
#define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_MASK)
 
#define IOMUXC_GPR_GPR4_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR4_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR4_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_DWP_SHIFT)) & IOMUXC_GPR_GPR4_DWP_MASK)
 
#define IOMUXC_GPR_GPR4_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR4_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR4_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR4_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR4_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR4_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK)
 

GPR5 - GPR5 General Purpose Register

#define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK)
 
#define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK)
 
#define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK)
 
#define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_MASK)
 
#define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_MASK)
 
#define IOMUXC_GPR_GPR5_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR5_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR5_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_DWP_SHIFT)) & IOMUXC_GPR_GPR5_DWP_MASK)
 
#define IOMUXC_GPR_GPR5_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR5_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR5_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR5_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR5_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR5_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK)
 

GPR7 - GPR7 General Purpose Register

#define IOMUXC_GPR_GPR7_GINT_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR7_GINT_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR7_GINT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_GINT_SHIFT)) & IOMUXC_GPR_GPR7_GINT_MASK)
 
#define IOMUXC_GPR_GPR7_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR7_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR7_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_DWP_SHIFT)) & IOMUXC_GPR_GPR7_DWP_MASK)
 
#define IOMUXC_GPR_GPR7_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR7_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR7_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR7_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR7_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR7_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK)
 

GPR8 - GPR8 General Purpose Register

#define IOMUXC_GPR_GPR8_WDOG1_MASK_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR8_WDOG1_MASK_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR8_WDOG1_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR8_WDOG1_MASK_MASK)
 
#define IOMUXC_GPR_GPR8_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR8_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR8_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_DWP_SHIFT)) & IOMUXC_GPR_GPR8_DWP_MASK)
 
#define IOMUXC_GPR_GPR8_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR8_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR8_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR8_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR8_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR8_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK)
 

GPR9 - GPR9 General Purpose Register

#define IOMUXC_GPR_GPR9_WDOG2_MASK_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR9_WDOG2_MASK_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR9_WDOG2_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR9_WDOG2_MASK_MASK)
 
#define IOMUXC_GPR_GPR9_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR9_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR9_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_DWP_SHIFT)) & IOMUXC_GPR_GPR9_DWP_MASK)
 
#define IOMUXC_GPR_GPR9_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR9_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR9_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR9_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR9_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR9_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK)
 

GPR10 - GPR10 General Purpose Register

#define IOMUXC_GPR_GPR10_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR10_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR10_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DWP_SHIFT)) & IOMUXC_GPR_GPR10_DWP_MASK)
 
#define IOMUXC_GPR_GPR10_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR10_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR10_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR10_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR10_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR10_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK)
 

GPR11 - GPR11 General Purpose Register

#define IOMUXC_GPR_GPR11_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR11_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR11_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_DWP_SHIFT)) & IOMUXC_GPR_GPR11_DWP_MASK)
 
#define IOMUXC_GPR_GPR11_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR11_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR11_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR11_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR11_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR11_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK)
 

GPR12 - GPR12 General Purpose Register

#define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_MASK)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR12_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR12_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR12_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_DWP_SHIFT)) & IOMUXC_GPR_GPR12_DWP_MASK)
 
#define IOMUXC_GPR_GPR12_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR12_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR12_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR12_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR12_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR12_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK)
 

GPR13 - GPR13 General Purpose Register

#define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_MASK)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR13_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR13_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR13_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_DWP_SHIFT)) & IOMUXC_GPR_GPR13_DWP_MASK)
 
#define IOMUXC_GPR_GPR13_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR13_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR13_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR13_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR13_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR13_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK)
 

GPR14 - GPR14 General Purpose Register

#define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_MASK)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR14_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR14_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR14_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_DWP_SHIFT)) & IOMUXC_GPR_GPR14_DWP_MASK)
 
#define IOMUXC_GPR_GPR14_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR14_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR14_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR14_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR14_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR14_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK)
 

GPR15 - GPR15 General Purpose Register

#define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_MASK)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_MASK)
 
#define IOMUXC_GPR_GPR15_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR15_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR15_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_DWP_SHIFT)) & IOMUXC_GPR_GPR15_DWP_MASK)
 
#define IOMUXC_GPR_GPR15_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR15_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR15_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR15_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR15_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR15_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK)
 

GPR16 - GPR16 General Purpose Register

#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)
 
#define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK)
 
#define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_MASK)
 
#define IOMUXC_GPR_GPR16_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR16_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR16_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_DWP_SHIFT)) & IOMUXC_GPR_GPR16_DWP_MASK)
 
#define IOMUXC_GPR_GPR16_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR16_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR16_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR16_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR16_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR16_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK)
 

GPR17 - GPR17 General Purpose Register

#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK   (0xFFFFU)
 
#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK)
 
#define IOMUXC_GPR_GPR17_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR17_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR17_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_DWP_SHIFT)) & IOMUXC_GPR_GPR17_DWP_MASK)
 
#define IOMUXC_GPR_GPR17_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR17_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR17_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR17_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR17_LOCK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR17_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK   (0xFFFFFFF8U)
 
#define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK)
 

GPR18 - GPR18 General Purpose Register

#define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK   (0xFFFFU)
 
#define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_SHIFT)) & IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK)
 
#define IOMUXC_GPR_GPR18_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR18_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR18_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_DWP_SHIFT)) & IOMUXC_GPR_GPR18_DWP_MASK)
 
#define IOMUXC_GPR_GPR18_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR18_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR18_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR18_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR18_LOCK_MASK   (0xFFFF0000U)
 
#define IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR18_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_LOCK_MASK)
 

GPR20 - GPR20 General Purpose Register

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_MASK   (0x8000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_SHIFT   (15U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_MASK   (0x40000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_MASK   (0x80000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_SHIFT   (19U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_MASK   (0x200000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_MASK   (0x400000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_SHIFT   (22U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_MASK   (0x800000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_SHIFT   (23U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_MASK   (0x1000000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_SHIFT   (24U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_MASK   (0x2000000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_MASK   (0x4000000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_SHIFT   (26U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_MASK)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_MASK   (0x8000000U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_SHIFT   (27U)
 
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_MASK)
 
#define IOMUXC_GPR_GPR20_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR20_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR20_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_DWP_SHIFT)) & IOMUXC_GPR_GPR20_DWP_MASK)
 
#define IOMUXC_GPR_GPR20_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR20_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR20_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR20_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR20_LOCK_MASK   (0xFFFF0000U)
 
#define IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR20_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_LOCK_MASK)
 

GPR21 - GPR21 General Purpose Register

#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_MASK)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_MASK)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_MASK)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_MASK)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_MASK)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_MASK)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_MASK)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_MASK)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_MASK)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_MASK)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_MASK)
 
#define IOMUXC_GPR_GPR21_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR21_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR21_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_DWP_SHIFT)) & IOMUXC_GPR_GPR21_DWP_MASK)
 
#define IOMUXC_GPR_GPR21_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR21_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR21_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR21_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR21_LOCK_MASK   (0xFFFF0000U)
 
#define IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR21_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_LOCK_MASK)
 

GPR22 - GPR22 General Purpose Register

#define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK)
 
#define IOMUXC_GPR_GPR22_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR22_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR22_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_DWP_SHIFT)) & IOMUXC_GPR_GPR22_DWP_MASK)
 
#define IOMUXC_GPR_GPR22_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR22_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR22_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR22_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR22_LOCK_MASK   (0xFFFF0000U)
 
#define IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR22_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_LOCK_MASK)
 

GPR23 - GPR23 General Purpose Register

#define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK)
 
#define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_MASK)
 
#define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_MASK)
 
#define IOMUXC_GPR_GPR23_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR23_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR23_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_DWP_SHIFT)) & IOMUXC_GPR_GPR23_DWP_MASK)
 
#define IOMUXC_GPR_GPR23_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR23_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR23_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR23_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR23_LOCK_MASK   (0xFFFF0000U)
 
#define IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR23_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_LOCK_MASK)
 

GPR24 - GPR24 General Purpose Register

#define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_SHIFT)) & IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK)
 
#define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_MASK)
 
#define IOMUXC_GPR_GPR24_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR24_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR24_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_DWP_SHIFT)) & IOMUXC_GPR_GPR24_DWP_MASK)
 
#define IOMUXC_GPR_GPR24_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR24_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR24_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR24_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR24_LOCK_MASK   (0xFFFF0000U)
 
#define IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR24_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_LOCK_MASK)
 

GPR25 - GPR25 General Purpose Register

#define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_SHIFT)) & IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK)
 
#define IOMUXC_GPR_GPR25_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR25_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR25_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_DWP_SHIFT)) & IOMUXC_GPR_GPR25_DWP_MASK)
 
#define IOMUXC_GPR_GPR25_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR25_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR25_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR25_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK   (0x20U)
 
#define IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT   (5U)
 
#define IOMUXC_LPSR_GPR_GPR25_APC_VALID(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK)
 
#define IOMUXC_LPSR_GPR_GPR25_LOCK_MASK   (0xFFFF0000U)
 
#define IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR25_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_LOCK_MASK)
 

GPR26 - GPR26 General Purpose Register

#define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_SHIFT)) & IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK)
 
#define IOMUXC_GPR_GPR26_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR26_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR26_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_DWP_SHIFT)) & IOMUXC_GPR_GPR26_DWP_MASK)
 
#define IOMUXC_GPR_GPR26_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR26_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR26_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR26_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK   (0x1FFFFFFU)
 
#define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK)
 
#define IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK   (0xE000000U)
 
#define IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT   (25U)
 
#define IOMUXC_LPSR_GPR_GPR26_FIELD_0(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK)
 
#define IOMUXC_LPSR_GPR_GPR26_DWP_MASK   (0x30000000U)
 
#define IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT   (28U)
 
#define IOMUXC_LPSR_GPR_GPR26_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_MASK)
 
#define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK)
 

GPR27 - GPR27 General Purpose Register

#define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_SHIFT)) & IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK)
 
#define IOMUXC_GPR_GPR27_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR27_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR27_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_DWP_SHIFT)) & IOMUXC_GPR_GPR27_DWP_MASK)
 
#define IOMUXC_GPR_GPR27_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR27_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR27_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR27_DWP_LOCK_MASK)
 

GPR28 - GPR28 General Purpose Register

#define IOMUXC_GPR_GPR28_ARCACHE_USDHC_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR28_ARCACHE_USDHC_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR28_ARCACHE_USDHC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR28_ARCACHE_USDHC_MASK)
 
#define IOMUXC_GPR_GPR28_AWCACHE_USDHC_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR28_AWCACHE_USDHC_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR28_AWCACHE_USDHC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR28_AWCACHE_USDHC_MASK)
 
#define IOMUXC_GPR_GPR28_CACHE_ENET1G_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR28_CACHE_ENET1G_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR28_CACHE_ENET1G(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_ENET1G_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_ENET1G_MASK)
 
#define IOMUXC_GPR_GPR28_CACHE_ENET_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR28_CACHE_ENET_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR28_CACHE_ENET(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_ENET_MASK)
 
#define IOMUXC_GPR_GPR28_CACHE_USB_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR28_CACHE_USB_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR28_CACHE_USB(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_USB_MASK)
 
#define IOMUXC_GPR_GPR28_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR28_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR28_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_DWP_SHIFT)) & IOMUXC_GPR_GPR28_DWP_MASK)
 
#define IOMUXC_GPR_GPR28_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR28_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR28_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR28_DWP_LOCK_MASK)
 

GPR29 - GPR29 General Purpose Register

#define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_MASK)
 
#define IOMUXC_GPR_GPR29_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR29_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR29_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_DWP_SHIFT)) & IOMUXC_GPR_GPR29_DWP_MASK)
 
#define IOMUXC_GPR_GPR29_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR29_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR29_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR29_DWP_LOCK_MASK)
 

GPR30 - GPR30 General Purpose Register

#define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_MASK)
 
#define IOMUXC_GPR_GPR30_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR30_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR30_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_DWP_SHIFT)) & IOMUXC_GPR_GPR30_DWP_MASK)
 
#define IOMUXC_GPR_GPR30_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR30_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR30_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR30_DWP_LOCK_MASK)
 

GPR31 - GPR31 General Purpose Register

#define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_MASK)
 
#define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_SHIFT)) & IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_MASK)
 
#define IOMUXC_GPR_GPR31_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR31_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR31_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_DWP_SHIFT)) & IOMUXC_GPR_GPR31_DWP_MASK)
 
#define IOMUXC_GPR_GPR31_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR31_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR31_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR31_DWP_LOCK_MASK)
 

GPR32 - GPR32 General Purpose Register

#define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_MASK)
 
#define IOMUXC_GPR_GPR32_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR32_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR32_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_DWP_SHIFT)) & IOMUXC_GPR_GPR32_DWP_MASK)
 
#define IOMUXC_GPR_GPR32_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR32_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR32_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR32_DWP_LOCK_MASK)
 
#define IOMUXC_SNVS_GPR_GPR32_GPR_MASK   (0xFFFEU)
 
#define IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT   (1U)
 
#define IOMUXC_SNVS_GPR_GPR32_GPR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_GPR_MASK)
 
#define IOMUXC_SNVS_GPR_GPR32_LOCK_MASK   (0xFFFF0000U)
 
#define IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT   (16U)
 
#define IOMUXC_SNVS_GPR_GPR32_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK)
 

GPR33 - GPR33 General Purpose Register

#define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_MASK)
 
#define IOMUXC_GPR_GPR33_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR33_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR33_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_DWP_SHIFT)) & IOMUXC_GPR_GPR33_DWP_MASK)
 
#define IOMUXC_GPR_GPR33_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR33_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR33_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR33_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK)
 
#define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK   (0x100U)
 
#define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT   (8U)
 
#define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK)
 
#define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK   (0x200U)
 
#define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT   (9U)
 
#define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK)
 
#define IOMUXC_LPSR_GPR_GPR33_DWP_MASK   (0x30000000U)
 
#define IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT   (28U)
 
#define IOMUXC_LPSR_GPR_GPR33_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_MASK)
 
#define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK   (0x2U)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT   (1U)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK)
 
#define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK   (0x4U)
 
#define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT   (2U)
 
#define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK   (0x10000U)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT   (16U)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK   (0x20000U)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT   (17U)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK   (0x40000U)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT   (18U)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK   (0x80000U)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT   (19U)
 
#define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK)
 
#define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK   (0x100000U)
 
#define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT   (20U)
 
#define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK)
 

GPR34 - GPR34 General Purpose Register

#define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_MASK)
 
#define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_SHIFT)) & IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_MASK)
 
#define IOMUXC_GPR_GPR34_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR34_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR34_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_DWP_SHIFT)) & IOMUXC_GPR_GPR34_DWP_MASK)
 
#define IOMUXC_GPR_GPR34_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR34_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR34_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR34_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK   (0x2U)
 
#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT   (1U)
 
#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK   (0x4U)
 
#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT   (2U)
 
#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK   (0x8U)
 
#define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK   (0x20U)
 
#define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT   (5U)
 
#define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK)
 
#define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK   (0x800U)
 
#define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT   (11U)
 
#define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK)
 
#define IOMUXC_LPSR_GPR_GPR34_DWP_MASK   (0x30000000U)
 
#define IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT   (28U)
 
#define IOMUXC_LPSR_GPR_GPR34_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_MASK)
 
#define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK)
 
#define IOMUXC_SNVS_GPR_GPR34_LOCK_MASK   (0x1U)
 
#define IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT   (0U)
 
#define IOMUXC_SNVS_GPR_GPR34_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_LOCK_MASK)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK   (0x2U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT   (1U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK   (0xCU)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT   (2U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK   (0x80U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT   (7U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK   (0xFF00U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT   (8U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK   (0x30000U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT   (16U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK   (0xC0000U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT   (18U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK   (0x800000U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT   (23U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK   (0xF000000U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT   (24U)
 
#define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK)
 

GPR35 - GPR35 General Purpose Register

#define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_MASK)
 
#define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_SHIFT)) & IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_MASK)
 
#define IOMUXC_GPR_GPR35_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR35_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR35_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_DWP_SHIFT)) & IOMUXC_GPR_GPR35_DWP_MASK)
 
#define IOMUXC_GPR_GPR35_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR35_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR35_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR35_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK   (0x2U)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT   (1U)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK   (0x4U)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT   (2U)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK   (0x8U)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK   (0x20U)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT   (5U)
 
#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK   (0x40U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT   (6U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK   (0x80U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT   (7U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK   (0x100U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT   (8U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK   (0x200U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT   (9U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK   (0x400U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT   (10U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK   (0x800U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT   (11U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK   (0x1000U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT   (12U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK   (0x2000U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT   (13U)
 
#define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK   (0x8000U)
 
#define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT   (15U)
 
#define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK   (0x10000U)
 
#define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK   (0x20000U)
 
#define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT   (17U)
 
#define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK   (0x40000U)
 
#define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT   (18U)
 
#define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK   (0x80000U)
 
#define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT   (19U)
 
#define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK   (0x100000U)
 
#define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT   (20U)
 
#define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK   (0x200000U)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT   (21U)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK   (0x400000U)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT   (22U)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK   (0x800000U)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT   (23U)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK   (0x1000000U)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT   (24U)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK   (0x2000000U)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT   (25U)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK   (0x4000000U)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT   (26U)
 
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_DWP_MASK   (0x30000000U)
 
#define IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT   (28U)
 
#define IOMUXC_LPSR_GPR_GPR35_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_MASK)
 
#define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK)
 
#define IOMUXC_SNVS_GPR_GPR35_LOCK_MASK   (0x1U)
 
#define IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT   (0U)
 
#define IOMUXC_SNVS_GPR_GPR35_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_LOCK_MASK)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK   (0x8U)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT   (3U)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK   (0xFF0U)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT   (4U)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK   (0x8000U)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT   (15U)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK   (0xFFF0000U)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT   (16U)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK   (0x30000000U)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT   (28U)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK   (0xC0000000U)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT   (30U)
 
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK)
 

GPR36 - GPR36 General Purpose Register

#define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_MASK)
 
#define IOMUXC_GPR_GPR36_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR36_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR36_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_DWP_SHIFT)) & IOMUXC_GPR_GPR36_DWP_MASK)
 
#define IOMUXC_GPR_GPR36_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR36_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR36_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR36_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK   (0x2U)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT   (1U)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK   (0x4U)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT   (2U)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK   (0x8U)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK   (0x20U)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT   (5U)
 
#define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK   (0x40U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT   (6U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK   (0x80U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT   (7U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK   (0x100U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT   (8U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK   (0x200U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT   (9U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK   (0x400U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT   (10U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK   (0x800U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT   (11U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK   (0x1000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT   (12U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK   (0x2000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT   (13U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK   (0x4000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT   (14U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK   (0x8000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT   (15U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK   (0x10000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK   (0x20000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT   (17U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK   (0x40000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT   (18U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK   (0x80000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT   (19U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK   (0x100000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT   (20U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK   (0x200000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT   (21U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK   (0x400000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT   (22U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK   (0x800000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT   (23U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK   (0x1000000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT   (24U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK   (0x2000000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT   (25U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK   (0x4000000U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT   (26U)
 
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_DWP_MASK   (0x30000000U)
 
#define IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT   (28U)
 
#define IOMUXC_LPSR_GPR_GPR36_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_MASK)
 
#define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK   (0x800000U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT   (23U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK   (0x4000000U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT   (26U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK   (0x8000000U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT   (27U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK   (0x10000000U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT   (28U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK   (0x20000000U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT   (29U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK   (0x40000000U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT   (30U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK   (0x80000000U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT   (31U)
 
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK)
 

GPR37 - GPR37 General Purpose Register

#define IOMUXC_GPR_GPR37_NIDEN_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR37_NIDEN_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR37_NIDEN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_NIDEN_SHIFT)) & IOMUXC_GPR_GPR37_NIDEN_MASK)
 
#define IOMUXC_GPR_GPR37_DBG_EN_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR37_DBG_EN_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR37_DBG_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR37_DBG_EN_MASK)
 
#define IOMUXC_GPR_GPR37_EXC_MON_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR37_EXC_MON_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR37_EXC_MON(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR37_EXC_MON_MASK)
 
#define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_SHIFT)) & IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_MASK)
 
#define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_SHIFT)) & IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_MASK)
 
#define IOMUXC_GPR_GPR37_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR37_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR37_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DWP_SHIFT)) & IOMUXC_GPR_GPR37_DWP_MASK)
 
#define IOMUXC_GPR_GPR37_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR37_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR37_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR37_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK   (0x2U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT   (1U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK   (0x4U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT   (2U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK   (0x8U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK   (0x20U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT   (5U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK   (0x40U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT   (6U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK   (0x80U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT   (7U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK   (0x100U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT   (8U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK   (0x200U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT   (9U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK   (0x400U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT   (10U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK   (0x800U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT   (11U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK   (0x1000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT   (12U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK   (0x2000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT   (13U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK   (0x4000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT   (14U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK   (0x8000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT   (15U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK   (0x10000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK   (0x20000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT   (17U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK   (0x40000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT   (18U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK   (0x80000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT   (19U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK   (0x100000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT   (20U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK   (0x200000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT   (21U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK   (0x400000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT   (22U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK   (0x800000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT   (23U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK   (0x1000000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT   (24U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK   (0x2000000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT   (25U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK   (0x4000000U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT   (26U)
 
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_DWP_MASK   (0x30000000U)
 
#define IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT   (28U)
 
#define IOMUXC_LPSR_GPR_GPR37_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_MASK)
 
#define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK)
 
#define IOMUXC_SNVS_GPR_GPR37_LOCK_MASK   (0x1U)
 
#define IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT   (0U)
 
#define IOMUXC_SNVS_GPR_GPR37_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_LOCK_MASK)
 
#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK   (0x7FEU)
 
#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT   (1U)
 
#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK)
 
#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK   (0x1FF800U)
 
#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT   (11U)
 
#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK)
 

GPR38 - GPR38 General Purpose Register

#define IOMUXC_GPR_GPR38_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR38_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR38_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR38_DWP_SHIFT)) & IOMUXC_GPR_GPR38_DWP_MASK)
 
#define IOMUXC_GPR_GPR38_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR38_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR38_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR38_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR38_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK   (0x2U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT   (1U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK   (0x4U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT   (2U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK   (0x8U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK   (0x20U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT   (5U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK   (0x40U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT   (6U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK   (0x80U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT   (7U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK   (0x100U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT   (8U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK   (0x200U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT   (9U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK   (0x400U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT   (10U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK   (0x800U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT   (11U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK   (0x1000U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT   (12U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK   (0x2000U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT   (13U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK   (0x4000U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT   (14U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK   (0x8000U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT   (15U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK   (0x10000U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK   (0x20000U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT   (17U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK   (0x40000U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT   (18U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK   (0x80000U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT   (19U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK   (0x100000U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT   (20U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK   (0x200000U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT   (21U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK   (0x400000U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT   (22U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK   (0x800000U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT   (23U)
 
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK   (0x1000000U)
 
#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT   (24U)
 
#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK   (0x2000000U)
 
#define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT   (25U)
 
#define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK   (0x4000000U)
 
#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT   (26U)
 
#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_DWP_MASK   (0x30000000U)
 
#define IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT   (28U)
 
#define IOMUXC_LPSR_GPR_GPR38_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_MASK)
 
#define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK)
 

GPR39 - GPR39 General Purpose Register

#define IOMUXC_GPR_GPR39_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR39_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR39_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR39_DWP_SHIFT)) & IOMUXC_GPR_GPR39_DWP_MASK)
 
#define IOMUXC_GPR_GPR39_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR39_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR39_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR39_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR39_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK   (0x2U)
 
#define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT   (1U)
 
#define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK   (0x4U)
 
#define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT   (2U)
 
#define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK   (0x8U)
 
#define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK   (0x20U)
 
#define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT   (5U)
 
#define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK   (0x40U)
 
#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT   (6U)
 
#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK   (0x80U)
 
#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT   (7U)
 
#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK   (0x100U)
 
#define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT   (8U)
 
#define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK   (0x200U)
 
#define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT   (9U)
 
#define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK   (0x400U)
 
#define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT   (10U)
 
#define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK   (0x800U)
 
#define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT   (11U)
 
#define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK   (0x1000U)
 
#define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT   (12U)
 
#define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK   (0x2000U)
 
#define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT   (13U)
 
#define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK   (0x4000U)
 
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT   (14U)
 
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK   (0x8000U)
 
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT   (15U)
 
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK   (0x10000U)
 
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK   (0x20000U)
 
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT   (17U)
 
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_DWP_MASK   (0x30000000U)
 
#define IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT   (28U)
 
#define IOMUXC_LPSR_GPR_GPR39_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_MASK)
 
#define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK)
 

GPR40 - GPR40 General Purpose Register

#define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_MASK   (0xFFFFU)
 
#define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_SHIFT)) & IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_MASK)
 
#define IOMUXC_GPR_GPR40_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR40_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR40_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_DWP_SHIFT)) & IOMUXC_GPR_GPR40_DWP_MASK)
 
#define IOMUXC_GPR_GPR40_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR40_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR40_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR40_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK   (0x2U)
 
#define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT   (1U)
 
#define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK   (0x4U)
 
#define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT   (2U)
 
#define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK   (0x8U)
 
#define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK   (0x20U)
 
#define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT   (5U)
 
#define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK   (0x40U)
 
#define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT   (6U)
 
#define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK   (0x80U)
 
#define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT   (7U)
 
#define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK   (0x100U)
 
#define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT   (8U)
 
#define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK   (0x200U)
 
#define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT   (9U)
 
#define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK   (0x400U)
 
#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT   (10U)
 
#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK   (0x800U)
 
#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT   (11U)
 
#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK   (0x1000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT   (12U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK   (0x2000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT   (13U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK   (0x4000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT   (14U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK   (0x8000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT   (15U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK   (0x10000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK   (0x20000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT   (17U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK   (0x40000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT   (18U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK   (0x80000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT   (19U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK   (0x100000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT   (20U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK   (0x200000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT   (21U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK   (0x400000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT   (22U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK   (0x800000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT   (23U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK   (0x1000000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT   (24U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK   (0x2000000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT   (25U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK   (0x4000000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT   (26U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK   (0x8000000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT   (27U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK   (0x10000000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT   (28U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK   (0x20000000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT   (29U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK   (0x40000000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT   (30U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK   (0x80000000U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT   (31U)
 
#define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK)
 

GPR41 - GPR41 General Purpose Register

#define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_MASK   (0xFFFFU)
 
#define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_SHIFT)) & IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_MASK)
 
#define IOMUXC_GPR_GPR41_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR41_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR41_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_DWP_SHIFT)) & IOMUXC_GPR_GPR41_DWP_MASK)
 
#define IOMUXC_GPR_GPR41_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR41_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR41_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR41_DWP_LOCK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK   (0x1U)
 
#define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT   (0U)
 
#define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK   (0x2U)
 
#define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT   (1U)
 
#define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK   (0x4U)
 
#define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT   (2U)
 
#define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK   (0x8U)
 
#define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT   (3U)
 
#define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK   (0x10U)
 
#define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT   (4U)
 
#define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK   (0x20U)
 
#define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT   (5U)
 
#define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK   (0x40U)
 
#define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT   (6U)
 
#define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK   (0x80U)
 
#define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT   (7U)
 
#define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK   (0x100U)
 
#define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT   (8U)
 
#define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK   (0x200U)
 
#define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT   (9U)
 
#define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK   (0x400U)
 
#define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT   (10U)
 
#define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK   (0x800U)
 
#define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT   (11U)
 
#define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK   (0x1000U)
 
#define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT   (12U)
 
#define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK   (0x2000U)
 
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT   (13U)
 
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK   (0x4000U)
 
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT   (14U)
 
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK   (0x8000U)
 
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT   (15U)
 
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK   (0x10000U)
 
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT   (16U)
 
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK)
 
#define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK   (0x1000000U)
 
#define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT   (24U)
 
#define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK)
 

GPR42 - GPR42 General Purpose Register

#define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_MASK   (0xFFFFU)
 
#define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_SHIFT)) & IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_MASK)
 
#define IOMUXC_GPR_GPR42_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR42_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR42_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_DWP_SHIFT)) & IOMUXC_GPR_GPR42_DWP_MASK)
 
#define IOMUXC_GPR_GPR42_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR42_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR42_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR42_DWP_LOCK_MASK)
 

GPR43 - GPR43 General Purpose Register

#define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK   (0xFFFFU)
 
#define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_SHIFT)) & IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK)
 
#define IOMUXC_GPR_GPR43_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR43_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR43_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_DWP_SHIFT)) & IOMUXC_GPR_GPR43_DWP_MASK)
 
#define IOMUXC_GPR_GPR43_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR43_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR43_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR43_DWP_LOCK_MASK)
 

GPR44 - GPR44 General Purpose Register

#define IOMUXC_GPR_GPR44_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR44_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR44_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR44_DWP_SHIFT)) & IOMUXC_GPR_GPR44_DWP_MASK)
 
#define IOMUXC_GPR_GPR44_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR44_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR44_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR44_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR44_DWP_LOCK_MASK)
 

GPR45 - GPR45 General Purpose Register

#define IOMUXC_GPR_GPR45_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR45_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR45_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR45_DWP_SHIFT)) & IOMUXC_GPR_GPR45_DWP_MASK)
 
#define IOMUXC_GPR_GPR45_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR45_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR45_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR45_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR45_DWP_LOCK_MASK)
 

GPR46 - GPR46 General Purpose Register

#define IOMUXC_GPR_GPR46_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR46_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR46_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR46_DWP_SHIFT)) & IOMUXC_GPR_GPR46_DWP_MASK)
 
#define IOMUXC_GPR_GPR46_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR46_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR46_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR46_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR46_DWP_LOCK_MASK)
 

GPR47 - GPR47 General Purpose Register

#define IOMUXC_GPR_GPR47_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR47_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR47_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR47_DWP_SHIFT)) & IOMUXC_GPR_GPR47_DWP_MASK)
 
#define IOMUXC_GPR_GPR47_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR47_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR47_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR47_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR47_DWP_LOCK_MASK)
 

GPR48 - GPR48 General Purpose Register

#define IOMUXC_GPR_GPR48_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR48_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR48_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR48_DWP_SHIFT)) & IOMUXC_GPR_GPR48_DWP_MASK)
 
#define IOMUXC_GPR_GPR48_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR48_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR48_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR48_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR48_DWP_LOCK_MASK)
 

GPR49 - GPR49 General Purpose Register

#define IOMUXC_GPR_GPR49_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR49_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR49_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR49_DWP_SHIFT)) & IOMUXC_GPR_GPR49_DWP_MASK)
 
#define IOMUXC_GPR_GPR49_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR49_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR49_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR49_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR49_DWP_LOCK_MASK)
 

GPR50 - GPR50 General Purpose Register

#define IOMUXC_GPR_GPR50_CAAM_IPS_MGR_MASK   (0x1FU)
 
#define IOMUXC_GPR_GPR50_CAAM_IPS_MGR_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR50_CAAM_IPS_MGR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_CAAM_IPS_MGR_SHIFT)) & IOMUXC_GPR_GPR50_CAAM_IPS_MGR_MASK)
 
#define IOMUXC_GPR_GPR50_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR50_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR50_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_DWP_SHIFT)) & IOMUXC_GPR_GPR50_DWP_MASK)
 
#define IOMUXC_GPR_GPR50_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR50_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR50_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR50_DWP_LOCK_MASK)
 

GPR51 - GPR51 General Purpose Register

#define IOMUXC_GPR_GPR51_M7_NMI_CLEAR_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR51_M7_NMI_CLEAR_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR51_M7_NMI_CLEAR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_M7_NMI_CLEAR_SHIFT)) & IOMUXC_GPR_GPR51_M7_NMI_CLEAR_MASK)
 
#define IOMUXC_GPR_GPR51_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR51_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR51_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_DWP_SHIFT)) & IOMUXC_GPR_GPR51_DWP_MASK)
 
#define IOMUXC_GPR_GPR51_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR51_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR51_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR51_DWP_LOCK_MASK)
 

GPR52 - GPR52 General Purpose Register

#define IOMUXC_GPR_GPR52_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR52_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR52_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR52_DWP_SHIFT)) & IOMUXC_GPR_GPR52_DWP_MASK)
 
#define IOMUXC_GPR_GPR52_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR52_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR52_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR52_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR52_DWP_LOCK_MASK)
 

GPR53 - GPR53 General Purpose Register

#define IOMUXC_GPR_GPR53_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR53_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR53_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR53_DWP_SHIFT)) & IOMUXC_GPR_GPR53_DWP_MASK)
 
#define IOMUXC_GPR_GPR53_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR53_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR53_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR53_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR53_DWP_LOCK_MASK)
 

GPR54 - GPR54 General Purpose Register

#define IOMUXC_GPR_GPR54_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR54_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR54_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR54_DWP_SHIFT)) & IOMUXC_GPR_GPR54_DWP_MASK)
 
#define IOMUXC_GPR_GPR54_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR54_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR54_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR54_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR54_DWP_LOCK_MASK)
 

GPR55 - GPR55 General Purpose Register

#define IOMUXC_GPR_GPR55_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR55_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR55_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR55_DWP_SHIFT)) & IOMUXC_GPR_GPR55_DWP_MASK)
 
#define IOMUXC_GPR_GPR55_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR55_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR55_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR55_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR55_DWP_LOCK_MASK)
 

GPR59 - GPR59 General Purpose Register

#define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_MASK)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_MASK)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_MASK)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_MASK   (0xC0U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_MASK)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_MASK   (0x300U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_MASK)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_MASK   (0xC00U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_MASK)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK   (0x3F000U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK)
 
#define IOMUXC_GPR_GPR59_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR59_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR59_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_DWP_SHIFT)) & IOMUXC_GPR_GPR59_DWP_MASK)
 
#define IOMUXC_GPR_GPR59_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR59_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR59_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR59_DWP_LOCK_MASK)
 

GPR62 - GPR62 General Purpose Register

#define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_MASK   (0x7U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_MASK)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_MASK   (0x38U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_MASK)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_MASK   (0x1C0U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_MASK)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_MASK   (0x600U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_MASK)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_MASK   (0x3800U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_MASK)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK   (0x40000U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK   (0x80000U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_SHIFT   (19U)
 
#define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK)
 
#define IOMUXC_GPR_GPR62_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR62_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR62_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_DWP_SHIFT)) & IOMUXC_GPR_GPR62_DWP_MASK)
 
#define IOMUXC_GPR_GPR62_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR62_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR62_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR62_DWP_LOCK_MASK)
 

GPR63 - GPR63 General Purpose Register

#define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_MASK   (0x7U)
 
#define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_MASK)
 

GPR64 - GPR64 General Purpose Register

#define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_MASK)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_MASK)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_MASK)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_MASK)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_MASK   (0xF0U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_MASK)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_MASK   (0xF00U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_MASK)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_MASK)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_MASK)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_MASK)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_MASK)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_MASK   (0x1E00000U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_MASK)
 
#define IOMUXC_GPR_GPR64_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR64_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR64_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_DWP_SHIFT)) & IOMUXC_GPR_GPR64_DWP_MASK)
 
#define IOMUXC_GPR_GPR64_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR64_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR64_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR64_DWP_LOCK_MASK)
 

GPR65 - GPR65 General Purpose Register

#define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_MASK)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_MASK)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_MASK)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_MASK)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_MASK   (0xF0U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_MASK)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_MASK   (0xF00U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_MASK)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_MASK)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_MASK)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_MASK)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_MASK)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_MASK   (0x1E00000U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_MASK)
 
#define IOMUXC_GPR_GPR65_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR65_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR65_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_DWP_SHIFT)) & IOMUXC_GPR_GPR65_DWP_MASK)
 
#define IOMUXC_GPR_GPR65_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR65_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR65_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR65_DWP_LOCK_MASK)
 

GPR66 - GPR66 General Purpose Register

#define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_MASK)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_MASK)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_MASK)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_MASK)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_MASK   (0xF0U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_MASK)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_MASK   (0xF00U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_MASK)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_MASK)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_MASK)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_MASK)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_MASK)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_MASK   (0x1E00000U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_MASK)
 
#define IOMUXC_GPR_GPR66_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR66_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR66_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_DWP_SHIFT)) & IOMUXC_GPR_GPR66_DWP_MASK)
 
#define IOMUXC_GPR_GPR66_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR66_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR66_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR66_DWP_LOCK_MASK)
 

GPR67 - GPR67 General Purpose Register

#define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_MASK)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_MASK)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_MASK)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_MASK)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_MASK   (0xF0U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_MASK)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_MASK   (0xF00U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_MASK)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_MASK)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_MASK)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_MASK)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_MASK)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_MASK   (0x1E00000U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_MASK)
 
#define IOMUXC_GPR_GPR67_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR67_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR67_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_DWP_SHIFT)) & IOMUXC_GPR_GPR67_DWP_MASK)
 
#define IOMUXC_GPR_GPR67_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR67_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR67_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR67_DWP_LOCK_MASK)
 

GPR68 - GPR68 General Purpose Register

#define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_MASK)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_MASK)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_MASK)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_MASK)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_MASK   (0xF0U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_MASK)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_MASK   (0xF00U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_MASK)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_MASK)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_MASK)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_MASK)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_MASK)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_MASK   (0x1E00000U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_MASK)
 
#define IOMUXC_GPR_GPR68_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR68_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR68_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_DWP_SHIFT)) & IOMUXC_GPR_GPR68_DWP_MASK)
 
#define IOMUXC_GPR_GPR68_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR68_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR68_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR68_DWP_LOCK_MASK)
 

GPR69 - GPR69 General Purpose Register

#define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_MASK)
 
#define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_MASK)
 
#define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_MASK)
 
#define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_MASK)
 
#define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_MASK)
 
#define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_MASK)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_MASK)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_MASK)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_MASK)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_MASK)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_MASK)
 
#define IOMUXC_GPR_GPR69_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR69_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR69_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_DWP_SHIFT)) & IOMUXC_GPR_GPR69_DWP_MASK)
 
#define IOMUXC_GPR_GPR69_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR69_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR69_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR69_DWP_LOCK_MASK)
 

GPR70 - GPR70 General Purpose Register

#define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR70_ADC1_STOP_REQ_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR70_ADC1_STOP_REQ_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR70_ADC1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR70_ADC2_STOP_REQ_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR70_ADC2_STOP_REQ_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR70_ADC2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR70_CAAM_STOP_REQ_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR70_CAAM_STOP_REQ_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR70_CAAM_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAAM_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAAM_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR70_CAN1_STOP_REQ_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR70_CAN1_STOP_REQ_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR70_CAN1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR70_CAN2_STOP_REQ_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR70_CAN2_STOP_REQ_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR70_CAN2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR70_CAN3_STOP_REQ_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR70_CAN3_STOP_REQ_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR70_CAN3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN3_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR70_EDMA_STOP_REQ_MASK   (0x8000U)
 
#define IOMUXC_GPR_GPR70_EDMA_STOP_REQ_SHIFT   (15U)
 
#define IOMUXC_GPR_GPR70_EDMA_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_EDMA_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR70_ENET_IPG_DOZE_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR70_ENET_IPG_DOZE_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR70_ENET_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ENET_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR70_ENET_STOP_REQ_MASK   (0x40000U)
 
#define IOMUXC_GPR_GPR70_ENET_STOP_REQ_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR70_ENET_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ENET_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_MASK   (0x80000U)
 
#define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_SHIFT   (19U)
 
#define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_MASK   (0x200000U)
 
#define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_MASK   (0x400000U)
 
#define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_SHIFT   (22U)
 
#define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_MASK   (0x800000U)
 
#define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_SHIFT   (23U)
 
#define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_MASK   (0x1000000U)
 
#define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_SHIFT   (24U)
 
#define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_MASK   (0x2000000U)
 
#define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_MASK   (0x4000000U)
 
#define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_SHIFT   (26U)
 
#define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR70_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR70_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR70_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_DWP_SHIFT)) & IOMUXC_GPR_GPR70_DWP_MASK)
 
#define IOMUXC_GPR_GPR70_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR70_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR70_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR70_DWP_LOCK_MASK)
 

GPR71 - GPR71 General Purpose Register

#define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_MASK   (0x8000U)
 
#define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_SHIFT   (15U)
 
#define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_MASK   (0x40000U)
 
#define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_MASK   (0x80000U)
 
#define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_SHIFT   (19U)
 
#define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_MASK   (0x200000U)
 
#define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_MASK   (0x400000U)
 
#define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_SHIFT   (22U)
 
#define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_MASK   (0x800000U)
 
#define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_SHIFT   (23U)
 
#define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_MASK   (0x1000000U)
 
#define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_SHIFT   (24U)
 
#define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_MASK   (0x2000000U)
 
#define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_MASK   (0x4000000U)
 
#define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_SHIFT   (26U)
 
#define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR71_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR71_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR71_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_DWP_SHIFT)) & IOMUXC_GPR_GPR71_DWP_MASK)
 
#define IOMUXC_GPR_GPR71_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR71_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR71_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR71_DWP_LOCK_MASK)
 

GPR72 - GPR72 General Purpose Register

#define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_MASK   (0x8000U)
 
#define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_SHIFT   (15U)
 
#define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_MASK   (0x40000U)
 
#define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_MASK   (0x80000U)
 
#define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_SHIFT   (19U)
 
#define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_MASK   (0x200000U)
 
#define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_MASK   (0x400000U)
 
#define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_SHIFT   (22U)
 
#define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_MASK   (0x800000U)
 
#define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_SHIFT   (23U)
 
#define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_MASK   (0x1000000U)
 
#define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_SHIFT   (24U)
 
#define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_MASK   (0x2000000U)
 
#define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_MASK   (0x4000000U)
 
#define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_SHIFT   (26U)
 
#define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR72_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR72_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR72_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_DWP_SHIFT)) & IOMUXC_GPR_GPR72_DWP_MASK)
 
#define IOMUXC_GPR_GPR72_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR72_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR72_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR72_DWP_LOCK_MASK)
 

GPR73 - GPR73 General Purpose Register

#define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_MASK   (0x8000U)
 
#define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_SHIFT   (15U)
 
#define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_MASK   (0x40000U)
 
#define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_MASK   (0x80000U)
 
#define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_SHIFT   (19U)
 
#define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_MASK   (0x200000U)
 
#define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_MASK   (0x400000U)
 
#define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_SHIFT   (22U)
 
#define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_MASK   (0x800000U)
 
#define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_SHIFT   (23U)
 
#define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR73_MIC_IPG_DOZE_MASK   (0x1000000U)
 
#define IOMUXC_GPR_GPR73_MIC_IPG_DOZE_SHIFT   (24U)
 
#define IOMUXC_GPR_GPR73_MIC_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_MIC_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR73_MIC_STOP_REQ_MASK   (0x2000000U)
 
#define IOMUXC_GPR_GPR73_MIC_STOP_REQ_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR73_MIC_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_MIC_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_MASK   (0x4000000U)
 
#define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_SHIFT   (26U)
 
#define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_MASK)
 
#define IOMUXC_GPR_GPR73_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR73_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR73_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_DWP_SHIFT)) & IOMUXC_GPR_GPR73_DWP_MASK)
 
#define IOMUXC_GPR_GPR73_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR73_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR73_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR73_DWP_LOCK_MASK)
 

GPR74 - GPR74 General Purpose Register

#define IOMUXC_GPR_GPR74_PIT1_STOP_REQ_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR74_PIT1_STOP_REQ_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR74_PIT1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_PIT1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_PIT1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR74_PIT2_STOP_REQ_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR74_PIT2_STOP_REQ_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR74_PIT2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_PIT2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_PIT2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR74_SEMC_STOP_REQ_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR74_SEMC_STOP_REQ_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR74_SEMC_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SEMC_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_MASK)
 
#define IOMUXC_GPR_GPR74_SAI1_STOP_REQ_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR74_SAI1_STOP_REQ_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR74_SAI1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI1_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR74_SAI2_STOP_REQ_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR74_SAI2_STOP_REQ_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR74_SAI2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI2_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR74_SAI3_STOP_REQ_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR74_SAI3_STOP_REQ_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR74_SAI3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI3_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR74_SAI4_STOP_REQ_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR74_SAI4_STOP_REQ_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR74_SAI4_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI4_STOP_REQ_MASK)
 
#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_MASK)
 
#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_MASK   (0x8000U)
 
#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_SHIFT   (15U)
 
#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_MASK)
 
#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_MASK)
 
#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_MASK)
 
#define IOMUXC_GPR_GPR74_DWP_MASK   (0x30000000U)
 
#define IOMUXC_GPR_GPR74_DWP_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR74_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_DWP_SHIFT)) & IOMUXC_GPR_GPR74_DWP_MASK)
 
#define IOMUXC_GPR_GPR74_DWP_LOCK_MASK   (0xC0000000U)
 
#define IOMUXC_GPR_GPR74_DWP_LOCK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR74_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR74_DWP_LOCK_MASK)
 

GPR75 - GPR75 General Purpose Register

#define IOMUXC_GPR_GPR75_ADC1_STOP_ACK_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR75_ADC1_STOP_ACK_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR75_ADC1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ADC1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ADC1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_ADC2_STOP_ACK_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR75_ADC2_STOP_ACK_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR75_ADC2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ADC2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ADC2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_CAAM_STOP_ACK_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR75_CAAM_STOP_ACK_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR75_CAAM_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAAM_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAAM_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_CAN1_STOP_ACK_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR75_CAN1_STOP_ACK_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR75_CAN1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_CAN2_STOP_ACK_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR75_CAN2_STOP_ACK_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR75_CAN2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_CAN3_STOP_ACK_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR75_CAN3_STOP_ACK_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR75_CAN3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN3_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_EDMA_STOP_ACK_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR75_EDMA_STOP_ACK_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR75_EDMA_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_EDMA_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_ENET_STOP_ACK_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR75_ENET_STOP_ACK_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR75_ENET_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ENET_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_MASK   (0x8000U)
 
#define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_SHIFT   (15U)
 
#define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_MASK   (0x20000U)
 
#define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_SHIFT   (17U)
 
#define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_MASK   (0x40000U)
 
#define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_SHIFT   (18U)
 
#define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_MASK   (0x80000U)
 
#define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_SHIFT   (19U)
 
#define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_MASK   (0x100000U)
 
#define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_SHIFT   (20U)
 
#define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_MASK   (0x200000U)
 
#define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_SHIFT   (21U)
 
#define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_MASK   (0x400000U)
 
#define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_SHIFT   (22U)
 
#define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_MASK   (0x800000U)
 
#define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_SHIFT   (23U)
 
#define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_MASK   (0x1000000U)
 
#define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_SHIFT   (24U)
 
#define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_MASK   (0x2000000U)
 
#define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_SHIFT   (25U)
 
#define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_MASK   (0x4000000U)
 
#define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_SHIFT   (26U)
 
#define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_MASK   (0x8000000U)
 
#define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_SHIFT   (27U)
 
#define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_MASK   (0x10000000U)
 
#define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_SHIFT   (28U)
 
#define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_MASK   (0x20000000U)
 
#define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_SHIFT   (29U)
 
#define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_MASK   (0x40000000U)
 
#define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_SHIFT   (30U)
 
#define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_MASK   (0x80000000U)
 
#define IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_SHIFT   (31U)
 
#define IOMUXC_GPR_GPR75_LPUART8_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_MASK)
 

GPR76 - GPR76 General Purpose Register

#define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_MASK   (0x1U)
 
#define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_SHIFT   (0U)
 
#define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_MASK   (0x2U)
 
#define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_SHIFT   (1U)
 
#define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_MASK   (0x4U)
 
#define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_SHIFT   (2U)
 
#define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_MASK   (0x8U)
 
#define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_SHIFT   (3U)
 
#define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_MIC_STOP_ACK_MASK   (0x10U)
 
#define IOMUXC_GPR_GPR76_MIC_STOP_ACK_SHIFT   (4U)
 
#define IOMUXC_GPR_GPR76_MIC_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_MIC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_MIC_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_PIT1_STOP_ACK_MASK   (0x20U)
 
#define IOMUXC_GPR_GPR76_PIT1_STOP_ACK_SHIFT   (5U)
 
#define IOMUXC_GPR_GPR76_PIT1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_PIT1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_PIT1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_PIT2_STOP_ACK_MASK   (0x40U)
 
#define IOMUXC_GPR_GPR76_PIT2_STOP_ACK_SHIFT   (6U)
 
#define IOMUXC_GPR_GPR76_PIT2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_PIT2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_PIT2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_SEMC_STOP_ACK_MASK   (0x80U)
 
#define IOMUXC_GPR_GPR76_SEMC_STOP_ACK_SHIFT   (7U)
 
#define IOMUXC_GPR_GPR76_SEMC_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SEMC_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_MASK   (0x100U)
 
#define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_SHIFT   (8U)
 
#define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_SAI1_STOP_ACK_MASK   (0x200U)
 
#define IOMUXC_GPR_GPR76_SAI1_STOP_ACK_SHIFT   (9U)
 
#define IOMUXC_GPR_GPR76_SAI1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI1_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_SAI2_STOP_ACK_MASK   (0x400U)
 
#define IOMUXC_GPR_GPR76_SAI2_STOP_ACK_SHIFT   (10U)
 
#define IOMUXC_GPR_GPR76_SAI2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI2_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_SAI3_STOP_ACK_MASK   (0x800U)
 
#define IOMUXC_GPR_GPR76_SAI3_STOP_ACK_SHIFT   (11U)
 
#define IOMUXC_GPR_GPR76_SAI3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI3_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_SAI4_STOP_ACK_MASK   (0x1000U)
 
#define IOMUXC_GPR_GPR76_SAI4_STOP_ACK_SHIFT   (12U)
 
#define IOMUXC_GPR_GPR76_SAI4_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI4_STOP_ACK_MASK)
 
#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_MASK   (0x2000U)
 
#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_SHIFT   (13U)
 
#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_MASK)
 
#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_MASK   (0x4000U)
 
#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_SHIFT   (14U)
 
#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_MASK)
 
#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_MASK   (0x8000U)
 
#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_SHIFT   (15U)
 
#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_MASK)
 
#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_MASK   (0x10000U)
 
#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_SHIFT   (16U)
 
#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_MASK)
 

Detailed Description

Macro Definition Documentation

◆ IOMUXC_GPR_GPR0_DWP [1/2]

#define IOMUXC_GPR_GPR0_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DWP_SHIFT)) & IOMUXC_GPR_GPR0_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR0_DWP [2/2]

#define IOMUXC_GPR_GPR0_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DWP_SHIFT)) & IOMUXC_GPR_GPR0_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR0_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR0_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR0_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR0_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR0_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR0_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL [1/2]

#define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK)

SAI1_MCLK1_SEL - SAI1 MCLK1 source select

◆ IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL [2/2]

#define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK)

SAI1_MCLK1_SEL - SAI1 MCLK1 source select

◆ IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL [1/2]

#define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_MASK)

SAI1_MCLK2_SEL - SAI1 MCLK2 source select

◆ IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL [2/2]

#define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_MASK)

SAI1_MCLK2_SEL - SAI1 MCLK2 source select

◆ IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL [1/2]

#define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_MASK)

SAI1_MCLK3_SEL - SAI1 MCLK3 source select

◆ IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL [2/2]

#define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_MASK)

SAI1_MCLK3_SEL - SAI1 MCLK3 source select

◆ IOMUXC_GPR_GPR0_SAI1_MCLK_DIR [1/2]

#define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_MASK)

SAI1_MCLK_DIR - SAI1_MCLK signal direction control

◆ IOMUXC_GPR_GPR0_SAI1_MCLK_DIR [2/2]

#define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_MASK)

SAI1_MCLK_DIR - SAI1_MCLK signal direction control

◆ IOMUXC_GPR_GPR10_DBG_EN

#define IOMUXC_GPR_GPR10_DBG_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK)

DBG_EN - Arm invasive debug enable 0b0..Debug turned off 0b1..Debug enabled (default)

◆ IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX

#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK)

DCPKEY_OCOTP_OR_KEYMUX 0b0..Select key from SNVS Master Key 0b1..Select key from OCOTP (SW_GP2)

◆ IOMUXC_GPR_GPR10_DWP [1/2]

#define IOMUXC_GPR_GPR10_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DWP_SHIFT)) & IOMUXC_GPR_GPR10_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR10_DWP [2/2]

#define IOMUXC_GPR_GPR10_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DWP_SHIFT)) & IOMUXC_GPR_GPR10_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR10_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR10_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR10_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR10_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR10_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR10_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR10_LOCK_DBG_EN

#define IOMUXC_GPR_GPR10_LOCK_DBG_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK)

LOCK_DBG_EN 0b0..Field is not locked 0b1..Field is locked (read access only)

◆ IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX

#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK)

LOCK_DCPKEY_OCOTP_OR_KEYMUX 0b0..Field is not locked 0b1..Field is locked (read access only)

◆ IOMUXC_GPR_GPR10_LOCK_NIDEN

#define IOMUXC_GPR_GPR10_LOCK_NIDEN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK)

LOCK_NIDEN 0b0..Field is not locked 0b1..Field is locked (read access only)

◆ IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR

#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK)

LOCK_OCRAM_TZ_ADDR 0b0000000..Field is not locked 0b0000001..Field is locked (read access only)

◆ IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN

#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK)

LOCK_OCRAM_TZ_EN 0b0..Field is not locked 0b1..Field is locked (read access only)

◆ IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP

#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK)

LOCK_SEC_ERR_RESP 0b0..Field is not locked 0b1..Field is locked (read access only)

◆ IOMUXC_GPR_GPR10_NIDEN

#define IOMUXC_GPR_GPR10_NIDEN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK)

NIDEN - Arm non-secure (non-invasive) debug enable 0b0..Debug turned off 0b1..Debug enabled (default)

◆ IOMUXC_GPR_GPR10_OCRAM_TZ_EN

#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK)

OCRAM_TZ_EN 0b0..The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor) 0b1..The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter

◆ IOMUXC_GPR_GPR10_SEC_ERR_RESP

#define IOMUXC_GPR_GPR10_SEC_ERR_RESP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK)

SEC_ERR_RESP - Security error response enable 0b0..OKEY response 0b1..SLVError (default)

◆ IOMUXC_GPR_GPR11_BEE_DE_RX_EN

#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK)

BEE_DE_RX_EN 0b0000..FlexSPI data decryption disabled 0b0001..FlexSPI data decryption enabled

◆ IOMUXC_GPR_GPR11_DWP [1/2]

#define IOMUXC_GPR_GPR11_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_DWP_SHIFT)) & IOMUXC_GPR_GPR11_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR11_DWP [2/2]

#define IOMUXC_GPR_GPR11_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_DWP_SHIFT)) & IOMUXC_GPR_GPR11_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR11_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR11_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR11_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR11_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR11_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR11_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN

#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK)

LOCK_BEE_DE_RX_EN 0b0000..Field is not locked 0b0001..Field is locked (read access only)

◆ IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL

#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK)

LOCK_M7_APC_AC_R0_CTRL 0b00..Field is not locked 0b01..Field is locked (read access only)

◆ IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL

#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK)

LOCK_M7_APC_AC_R1_CTRL 0b00..Field is not locked 0b01..Field is locked (read access only)

◆ IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL

#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK)

LOCK_M7_APC_AC_R2_CTRL 0b00..Field is not locked 0b01..Field is locked (read access only)

◆ IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL

#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK)

LOCK_M7_APC_AC_R3_CTRL 0b00..Field is not locked 0b01..Field is locked (read access only)

◆ IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL

#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK)

M7_APC_AC_R0_CTRL 0b00..No access protection - All accesses are allowed 0b01..M7 debug protection enabled - The APC block will block CM7 breakpoints, watchpoints and trace to the GPR_M7_APC_AC_R0_TOP/BOT specified region (IOMUXC_GPR_GPR18 - IOMUXC_GPR_GPR19) 0b10..Reserved 0b11..Reserved

◆ IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL

#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK)

M7_APC_AC_R1_CTRL 0b00..No access protection - All accesses are allowed 0b01..M7 debug protection enabled - The APC block will block CM7 breakpoints, watchpoints and trace to the GPR_M7_APC_AC_R1_TOP/BOT specified region (IOMUXC_GPR_GPR20 - IOMUXC_GPR_GPR21) 0b10..Reserved 0b11..Reserved

◆ IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL

#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK)

M7_APC_AC_R2_CTRL 0b00..No access protection - All accesses are allowed 0b01..M7 debug protection enabled - The APC block will block CM7 breakpoints, watchpoints and trace to the GPR_M7_APC_AC_R2_TOP/BOT specified region (IOMUXC_GPR_GPR22 - IOMUXC_GPR_GPR23) 0b10..Reserved 0b11..Reserved

◆ IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL

#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK)

M7_APC_AC_R3_CTRL 0b00..No access protection - All accesses are allowed 0b01..M7 debug protection enabled - The APC block will block CM7 breakpoints, watchpoints and trace to the GPR_M7_APC_AC_R3_TOP/BOT specified region (IOMUXC_GPR_GPR24 - IOMUXC_GPR_GPR25) 0b10..Reserved 0b11..Reserved

◆ IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE

#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK)

ACMP_IPG_STOP_MODE 0b0..ACMP is functional in Stop mode 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, ACMP is not functional in Stop mode

◆ IOMUXC_GPR_GPR12_DWP [1/2]

#define IOMUXC_GPR_GPR12_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_DWP_SHIFT)) & IOMUXC_GPR_GPR12_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR12_DWP [2/2]

#define IOMUXC_GPR_GPR12_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_DWP_SHIFT)) & IOMUXC_GPR_GPR12_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR12_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR12_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR12_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR12_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR12_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR12_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE

#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK)

FLEXIO1_IPG_DOZE 0b0..FLEXIO1 is not in doze mode 0b1..FLEXIO1 is in doze mode

◆ IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE

#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK)

FLEXIO1_IPG_STOP_MODE 0b0..FlexIO1 is functional in Stop mode 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO1 is not functional in Stop mode

◆ IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE

#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK)

FLEXIO2_IPG_DOZE 0b0..FLEXIO2 is not in doze mode 0b1..FLEXIO2 is in doze mode

◆ IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE

#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK)

FLEXIO2_IPG_STOP_MODE 0b0..FlexIO2 is functional in Stop mode 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO2 is not functional in Stop mode

◆ IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE [1/2]

#define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_MASK)

QTIMER1_TMR_CNTS_FREEZE - QTIMER1 timer counter freeze

◆ IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE [2/2]

#define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_MASK)

QTIMER1_TMR_CNTS_FREEZE - QTIMER1 timer counter freeze

◆ IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL [1/2]

#define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_MASK)

QTIMER1_TRM0_INPUT_SEL - QTIMER1 TMR0 input select

◆ IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL [2/2]

#define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_MASK)

QTIMER1_TRM0_INPUT_SEL - QTIMER1 TMR0 input select

◆ IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL [1/2]

#define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_MASK)

QTIMER1_TRM1_INPUT_SEL - QTIMER1 TMR1 input select

◆ IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL [2/2]

#define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_MASK)

QTIMER1_TRM1_INPUT_SEL - QTIMER1 TMR1 input select

◆ IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL [1/2]

#define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_MASK)

QTIMER1_TRM2_INPUT_SEL - QTIMER1 TMR2 input select

◆ IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL [2/2]

#define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_MASK)

QTIMER1_TRM2_INPUT_SEL - QTIMER1 TMR2 input select

◆ IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL [1/2]

#define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_MASK)

QTIMER1_TRM3_INPUT_SEL - QTIMER1 TMR3 input select

◆ IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL [2/2]

#define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_MASK)

QTIMER1_TRM3_INPUT_SEL - QTIMER1 TMR3 input select

◆ IOMUXC_GPR_GPR13_ARCACHE_USDHC

#define IOMUXC_GPR_GPR13_ARCACHE_USDHC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK)

ARCACHE_USDHC - uSDHC block cacheable attribute value of AXI read transactions 0b0..Cacheable attribute is off for read transactions 0b1..Cacheable attribute is on for read transactions

◆ IOMUXC_GPR_GPR13_AWCACHE_USDHC

#define IOMUXC_GPR_GPR13_AWCACHE_USDHC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK)

AWCACHE_USDHC - uSDHC block cacheable attribute value of AXI write transactions 0b0..Cacheable attribute is off for write transactions 0b1..Cacheable attribute is on for write transactions

◆ IOMUXC_GPR_GPR13_CACHE_ENET

#define IOMUXC_GPR_GPR13_CACHE_ENET (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK)

CACHE_ENET - ENET block cacheable attribute value of AXI transactions 0b0..Cacheable attribute is off for read/write transactions 0b1..Cacheable attribute is on for read/write transactions

◆ IOMUXC_GPR_GPR13_CACHE_USB

#define IOMUXC_GPR_GPR13_CACHE_USB (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK)

CACHE_USB - USB block cacheable attribute value of AXI transactions 0b0..Cacheable attribute is off for read/write transactions 0b1..Cacheable attribute is on for read/write transactions

◆ IOMUXC_GPR_GPR13_DWP [1/2]

#define IOMUXC_GPR_GPR13_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_DWP_SHIFT)) & IOMUXC_GPR_GPR13_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR13_DWP [2/2]

#define IOMUXC_GPR_GPR13_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_DWP_SHIFT)) & IOMUXC_GPR_GPR13_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR13_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR13_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR13_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR13_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR13_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR13_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE [1/2]

#define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_MASK)

QTIMER2_TMR_CNTS_FREEZE - QTIMER2 timer counter freeze

◆ IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE [2/2]

#define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_MASK)

QTIMER2_TMR_CNTS_FREEZE - QTIMER2 timer counter freeze

◆ IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL [1/2]

#define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_MASK)

QTIMER2_TRM0_INPUT_SEL - QTIMER2 TMR0 input select

◆ IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL [2/2]

#define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_MASK)

QTIMER2_TRM0_INPUT_SEL - QTIMER2 TMR0 input select

◆ IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL [1/2]

#define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_MASK)

QTIMER2_TRM1_INPUT_SEL - QTIMER2 TMR1 input select

◆ IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL [2/2]

#define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_MASK)

QTIMER2_TRM1_INPUT_SEL - QTIMER2 TMR1 input select

◆ IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL [1/2]

#define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_MASK)

QTIMER2_TRM2_INPUT_SEL - QTIMER2 TMR2 input select

◆ IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL [2/2]

#define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_MASK)

QTIMER2_TRM2_INPUT_SEL - QTIMER2 TMR2 input select

◆ IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL [1/2]

#define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_MASK)

QTIMER2_TRM3_INPUT_SEL - QTIMER2 TMR3 input select

◆ IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL [2/2]

#define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_MASK)

QTIMER2_TRM3_INPUT_SEL - QTIMER2 TMR3 input select

◆ IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN

#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK)

ACMP1_CMP_IGEN_TRIM_DN 0b0..no reduce 0b1..reduces

◆ IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP

#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK)

ACMP1_CMP_IGEN_TRIM_UP 0b0..no increase 0b1..increases

◆ IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN

#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK)

ACMP1_SAMPLE_SYNC_EN 0b0..select XBAR output 0b1..select synced sample_lv

◆ IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN

#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK)

ACMP2_CMP_IGEN_TRIM_DN 0b0..no reduce 0b1..reduces

◆ IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP

#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK)

ACMP2_CMP_IGEN_TRIM_UP 0b0..no increase 0b1..increases

◆ IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN

#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK)

ACMP2_SAMPLE_SYNC_EN 0b0..select XBAR output 0b1..select synced sample_lv

◆ IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN

#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK)

ACMP3_CMP_IGEN_TRIM_DN 0b0..no reduce 0b1..reduces

◆ IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP

#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK)

ACMP3_CMP_IGEN_TRIM_UP 0b0..no increase 0b1..increases

◆ IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN

#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK)

ACMP3_SAMPLE_SYNC_EN 0b0..select XBAR output 0b1..select synced sample_lv

◆ IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN

#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK)

ACMP4_CMP_IGEN_TRIM_DN 0b0..no reduce 0b1..reduces

◆ IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP

#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK)

ACMP4_CMP_IGEN_TRIM_UP 0b0..no increase 0b1..increases

◆ IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN

#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK)

ACMP4_SAMPLE_SYNC_EN 0b0..select XBAR output 0b1..select synced sample_lv

◆ IOMUXC_GPR_GPR14_DWP [1/2]

#define IOMUXC_GPR_GPR14_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_DWP_SHIFT)) & IOMUXC_GPR_GPR14_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR14_DWP [2/2]

#define IOMUXC_GPR_GPR14_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_DWP_SHIFT)) & IOMUXC_GPR_GPR14_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR14_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR14_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR14_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR14_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR14_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR14_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE [1/2]

#define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_MASK)

QTIMER3_TMR_CNTS_FREEZE - QTIMER3 timer counter freeze

◆ IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE [2/2]

#define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_MASK)

QTIMER3_TMR_CNTS_FREEZE - QTIMER3 timer counter freeze

◆ IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL [1/2]

#define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_MASK)

QTIMER3_TRM0_INPUT_SEL - QTIMER3 TMR0 input select

◆ IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL [2/2]

#define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_MASK)

QTIMER3_TRM0_INPUT_SEL - QTIMER3 TMR0 input select

◆ IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL [1/2]

#define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_MASK)

QTIMER3_TRM1_INPUT_SEL - QTIMER3 TMR1 input select

◆ IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL [2/2]

#define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_MASK)

QTIMER3_TRM1_INPUT_SEL - QTIMER3 TMR1 input select

◆ IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL [1/2]

#define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_MASK)

QTIMER3_TRM2_INPUT_SEL - QTIMER3 TMR2 input select

◆ IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL [2/2]

#define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_MASK)

QTIMER3_TRM2_INPUT_SEL - QTIMER3 TMR2 input select

◆ IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL [1/2]

#define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_MASK)

QTIMER3_TRM3_INPUT_SEL - QTIMER3 TMR3 input select

◆ IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL [2/2]

#define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_MASK)

QTIMER3_TRM3_INPUT_SEL - QTIMER3 TMR3 input select

◆ IOMUXC_GPR_GPR15_DWP [1/2]

#define IOMUXC_GPR_GPR15_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_DWP_SHIFT)) & IOMUXC_GPR_GPR15_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR15_DWP [2/2]

#define IOMUXC_GPR_GPR15_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_DWP_SHIFT)) & IOMUXC_GPR_GPR15_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR15_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR15_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR15_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR15_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR15_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR15_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE [1/2]

#define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_MASK)

QTIMER4_TMR_CNTS_FREEZE - QTIMER4 timer counter freeze

◆ IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE [2/2]

#define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_MASK)

QTIMER4_TMR_CNTS_FREEZE - QTIMER4 timer counter freeze

◆ IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL [1/2]

#define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_MASK)

QTIMER4_TRM0_INPUT_SEL - QTIMER4 TMR0 input select

◆ IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL [2/2]

#define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_MASK)

QTIMER4_TRM0_INPUT_SEL - QTIMER4 TMR0 input select

◆ IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL [1/2]

#define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_MASK)

QTIMER4_TRM1_INPUT_SEL - QTIMER4 TMR1 input select

◆ IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL [2/2]

#define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_MASK)

QTIMER4_TRM1_INPUT_SEL - QTIMER4 TMR1 input select

◆ IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL [1/2]

#define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_MASK)

QTIMER4_TRM2_INPUT_SEL - QTIMER4 TMR2 input select

◆ IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL [2/2]

#define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_MASK)

QTIMER4_TRM2_INPUT_SEL - QTIMER4 TMR2 input select

◆ IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL [1/2]

#define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_MASK)

QTIMER4_TRM3_INPUT_SEL - QTIMER4 TMR3 input select

◆ IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL [2/2]

#define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_MASK)

QTIMER4_TRM3_INPUT_SEL - QTIMER4 TMR3 input select

◆ IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN [1/2]

#define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK)

CM7_FORCE_HCLK_EN - CM7 platform AHB clock enable

◆ IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN [2/2]

#define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK)

CM7_FORCE_HCLK_EN - CM7 platform AHB clock enable

◆ IOMUXC_GPR_GPR16_DWP [1/2]

#define IOMUXC_GPR_GPR16_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_DWP_SHIFT)) & IOMUXC_GPR_GPR16_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR16_DWP [2/2]

#define IOMUXC_GPR_GPR16_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_DWP_SHIFT)) & IOMUXC_GPR_GPR16_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR16_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR16_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR16_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR16_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR16_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR16_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL [1/3]

#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)

FLEXRAM_BANK_CFG_SEL 0b0..use fuse value to config 0b1..use FLEXRAM_BANK_CFG to config

◆ IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL [2/3]

#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)

FLEXRAM_BANK_CFG_SEL - FlexRAM bank config source select

◆ IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL [3/3]

#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)

FLEXRAM_BANK_CFG_SEL - FlexRAM bank config source select

◆ IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL [1/2]

#define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_MASK)

M7_GPC_SLEEP_SEL - CM7 sleep request selection

◆ IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL [2/2]

#define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_MASK)

M7_GPC_SLEEP_SEL - CM7 sleep request selection

◆ IOMUXC_GPR_GPR17_DWP [1/2]

#define IOMUXC_GPR_GPR17_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_DWP_SHIFT)) & IOMUXC_GPR_GPR17_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR17_DWP [2/2]

#define IOMUXC_GPR_GPR17_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_DWP_SHIFT)) & IOMUXC_GPR_GPR17_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR17_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR17_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR17_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR17_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR17_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR17_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG

#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK)

FLEXRAM_BANK_CFG - FlexRAM bank config value

◆ IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW [1/2]

#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK)

FLEXRAM_BANK_CFG_LOW - FlexRAM bank config value

◆ IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW [2/2]

#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK)

FLEXRAM_BANK_CFG_LOW - FlexRAM bank config value

◆ IOMUXC_GPR_GPR18_DWP [1/2]

#define IOMUXC_GPR_GPR18_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_DWP_SHIFT)) & IOMUXC_GPR_GPR18_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR18_DWP [2/2]

#define IOMUXC_GPR_GPR18_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_DWP_SHIFT)) & IOMUXC_GPR_GPR18_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR18_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR18_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR18_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR18_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR18_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR18_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH [1/2]

#define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_SHIFT)) & IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK)

FLEXRAM_BANK_CFG_HIGH - FlexRAM bank config value

◆ IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH [2/2]

#define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_SHIFT)) & IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK)

FLEXRAM_BANK_CFG_HIGH - FlexRAM bank config value

◆ IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT

#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK)

LOCK_M7_APC_AC_R0_BOT 0b0..M7_APC_AC_R0_BOT is not locked 0b1..M7_APC_AC_R0_BOT is locked (read access only)

◆ IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT

#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK)

M7_APC_AC_R0_BOT - Access Permission Controller (APC) end address of memory region-0

◆ IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP

#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK)

LOCK_M7_APC_AC_R0_TOP 0b0..M7_APC_AC_R0_TOP is not locked 0b1..M7_APC_AC_R0_TOP is locked (read access only)

◆ IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP

#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK)

M7_APC_AC_R0_TOP - Access Permission Controller (APC) start address of memory region-0

◆ IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN

#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK)

CM7_FORCE_HCLK_EN - Arm CM7 platform AHB clock enable 0b0..AHB clock is not running (gated) when CM7 is sleeping and TCM is not accessible 0b1..AHB clock is running (enabled) when CM7 is sleeping and TCM is accessible

◆ IOMUXC_GPR_GPR1_DWP [1/2]

#define IOMUXC_GPR_GPR1_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_DWP_SHIFT)) & IOMUXC_GPR_GPR1_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR1_DWP [2/2]

#define IOMUXC_GPR_GPR1_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_DWP_SHIFT)) & IOMUXC_GPR_GPR1_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR1_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR1_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR1_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR1_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR1_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR1_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR

#define IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)

ENET_REF_CLK_DIR - ENET_REF_CLK direction control 0b0..ENET_REF_CLK is input 0b1..ENET_REF_CLK is output driven by ref_enetpll0

◆ IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL

#define IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL_MASK)

ENET_TX_CLK_SEL - ENET_TX_CLK select 0b0..Do not use 0b1..ENET_TX_CLK is the 25MHz MII clock

◆ IOMUXC_GPR_GPR1_EXC_MON

#define IOMUXC_GPR_GPR1_EXC_MON (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK)

EXC_MON - Exclusive monitor response select of illegal command 0b0..OKAY response 0b1..SLVError response

◆ IOMUXC_GPR_GPR1_GINT

#define IOMUXC_GPR_GPR1_GINT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK)

GINT - Global Interrupt 0b0..Global interrupt request is not asserted 0b1..Global interrupt request is asserted. Interrupt is issued to Arm M7 IRQ#41 and GPC

◆ IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL

#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK)

SAI1_MCLK1_SEL - SAI1 MCLK1 source select 0b000..SAI1_CLK_ROOT 0b001..SAI2_CLK_ROOT 0b010..SAI3_CLK_ROOT 0b011..iomux.sai1_ipg_clk_sai_mclk 0b100..iomux.sai2_ipg_clk_sai_mclk 0b101..iomux.sai3_ipg_clk_sai_mclk 0b110..Reserved 0b111..Reserved

◆ IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL

#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK)

SAI1_MCLK2_SEL - SAI1 MCLK2 source select 0b000..SAI1_CLK_ROOT 0b001..SAI2_CLK_ROOT 0b010..SAI3_CLK_ROOT 0b011..iomux.sai1_ipg_clk_sai_mclk 0b100..iomux.sai2_ipg_clk_sai_mclk 0b101..iomux.sai3_ipg_clk_sai_mclk 0b110..Reserved 0b111..Reserved

◆ IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL

#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK)

SAI1_MCLK3_SEL - SAI1 MCLK3 source select 0b00..ccm.spdif0_clk_root 0b01..iomux.spdif_tx_clk2 0b10..spdif.spdif_srclk 0b11..spdif.spdif_outclock

◆ IOMUXC_GPR_GPR1_SAI1_MCLK_DIR

#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK)

SAI1_MCLK_DIR - SAI1_MCLK signal direction control. Sets the direction for the SAI1_MCLK pin function. 0b0..SAI1_MCLK is input signal 0b1..SAI1_MCLK is output signal

◆ IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL [1/3]

#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)

SAI2_MCLK3_SEL - SAI2 MCLK3 source select 0b00..ccm.spdif0_clk_root 0b01..iomux.spdif_tx_clk2 0b10..spdif.spdif_srclk 0b11..spdif.spdif_outclock

◆ IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL [2/3]

#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)

SAI2_MCLK3_SEL - SAI2 MCLK3 source select

◆ IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL [3/3]

#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)

SAI2_MCLK3_SEL - SAI2 MCLK3 source select

◆ IOMUXC_GPR_GPR1_SAI2_MCLK_DIR [1/3]

#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)

SAI2_MCLK_DIR - SAI2_MCLK signal direction control. Sets the direction for the SAI2_MCLK pin function. 0b0..SAI2_MCLK is input signal 0b1..SAI2_MCLK is output signal

◆ IOMUXC_GPR_GPR1_SAI2_MCLK_DIR [2/3]

#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)

SAI2_MCLK_DIR - SAI2_MCLK signal direction control

◆ IOMUXC_GPR_GPR1_SAI2_MCLK_DIR [3/3]

#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)

SAI2_MCLK_DIR - SAI2_MCLK signal direction control

◆ IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL

#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK)

SAI3_MCLK3_SEL - SAI3 MCLK3 source select 0b00..ccm.spdif0_clk_root 0b01..iomux.spdif_tx_clk2 0b10..spdif.spdif_srclk 0b11..spdif.spdif_outclock

◆ IOMUXC_GPR_GPR1_SAI3_MCLK_DIR

#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK)

SAI3_MCLK_DIR - SAI3_MCLK signal direction control. Sets the direction for the SAI3_MCLK pin function. 0b0..SAI3_MCLK is input signal 0b1..SAI3_MCLK is output signal

◆ IOMUXC_GPR_GPR20_DWP [1/2]

#define IOMUXC_GPR_GPR20_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_DWP_SHIFT)) & IOMUXC_GPR_GPR20_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR20_DWP [2/2]

#define IOMUXC_GPR_GPR20_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_DWP_SHIFT)) & IOMUXC_GPR_GPR20_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR20_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR20_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR20_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR20_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR20_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR20_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_MASK)

IOMUXC_XBAR_DIR_SEL_10 - IOMUXC XBAR_INOUT10 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_MASK)

IOMUXC_XBAR_DIR_SEL_10 - IOMUXC XBAR_INOUT10 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_MASK)

IOMUXC_XBAR_DIR_SEL_11 - IOMUXC XBAR_INOUT11 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_MASK)

IOMUXC_XBAR_DIR_SEL_11 - IOMUXC XBAR_INOUT11 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_MASK)

IOMUXC_XBAR_DIR_SEL_12 - IOMUXC XBAR_INOUT12 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_MASK)

IOMUXC_XBAR_DIR_SEL_12 - IOMUXC XBAR_INOUT12 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_MASK)

IOMUXC_XBAR_DIR_SEL_13 - IOMUXC XBAR_INOUT13 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_MASK)

IOMUXC_XBAR_DIR_SEL_13 - IOMUXC XBAR_INOUT13 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_MASK)

IOMUXC_XBAR_DIR_SEL_14 - IOMUXC XBAR_INOUT14 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_MASK)

IOMUXC_XBAR_DIR_SEL_14 - IOMUXC XBAR_INOUT14 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_MASK)

IOMUXC_XBAR_DIR_SEL_15 - IOMUXC XBAR_INOUT15 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_MASK)

IOMUXC_XBAR_DIR_SEL_15 - IOMUXC XBAR_INOUT15 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_MASK)

IOMUXC_XBAR_DIR_SEL_16 - IOMUXC XBAR_INOUT16 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_MASK)

IOMUXC_XBAR_DIR_SEL_16 - IOMUXC XBAR_INOUT16 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_MASK)

IOMUXC_XBAR_DIR_SEL_17 - IOMUXC XBAR_INOUT17 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_MASK)

IOMUXC_XBAR_DIR_SEL_17 - IOMUXC XBAR_INOUT17 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_MASK)

IOMUXC_XBAR_DIR_SEL_18 - IOMUXC XBAR_INOUT18 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_MASK)

IOMUXC_XBAR_DIR_SEL_18 - IOMUXC XBAR_INOUT18 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_MASK)

IOMUXC_XBAR_DIR_SEL_19 - IOMUXC XBAR_INOUT19 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_MASK)

IOMUXC_XBAR_DIR_SEL_19 - IOMUXC XBAR_INOUT19 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_MASK)

IOMUXC_XBAR_DIR_SEL_20 - IOMUXC XBAR_INOUT20 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_MASK)

IOMUXC_XBAR_DIR_SEL_20 - IOMUXC XBAR_INOUT20 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_MASK)

IOMUXC_XBAR_DIR_SEL_21 - IOMUXC XBAR_INOUT21 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_MASK)

IOMUXC_XBAR_DIR_SEL_21 - IOMUXC XBAR_INOUT21 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_MASK)

IOMUXC_XBAR_DIR_SEL_22 - IOMUXC XBAR_INOUT22 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_MASK)

IOMUXC_XBAR_DIR_SEL_22 - IOMUXC XBAR_INOUT22 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_MASK)

IOMUXC_XBAR_DIR_SEL_23 - IOMUXC XBAR_INOUT23 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_MASK)

IOMUXC_XBAR_DIR_SEL_23 - IOMUXC XBAR_INOUT23 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_MASK)

IOMUXC_XBAR_DIR_SEL_24 - IOMUXC XBAR_INOUT24 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_MASK)

IOMUXC_XBAR_DIR_SEL_24 - IOMUXC XBAR_INOUT24 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_MASK)

IOMUXC_XBAR_DIR_SEL_25 - IOMUXC XBAR_INOUT25 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_MASK)

IOMUXC_XBAR_DIR_SEL_25 - IOMUXC XBAR_INOUT25 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_MASK)

IOMUXC_XBAR_DIR_SEL_26 - IOMUXC XBAR_INOUT26 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_MASK)

IOMUXC_XBAR_DIR_SEL_26 - IOMUXC XBAR_INOUT26 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_MASK)

IOMUXC_XBAR_DIR_SEL_27 - IOMUXC XBAR_INOUT27 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_MASK)

IOMUXC_XBAR_DIR_SEL_27 - IOMUXC XBAR_INOUT27 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_MASK)

IOMUXC_XBAR_DIR_SEL_28 - IOMUXC XBAR_INOUT28 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_MASK)

IOMUXC_XBAR_DIR_SEL_28 - IOMUXC XBAR_INOUT28 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_MASK)

IOMUXC_XBAR_DIR_SEL_29 - IOMUXC XBAR_INOUT29 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_MASK)

IOMUXC_XBAR_DIR_SEL_29 - IOMUXC XBAR_INOUT29 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_MASK)

IOMUXC_XBAR_DIR_SEL_30 - IOMUXC XBAR_INOUT30 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_MASK)

IOMUXC_XBAR_DIR_SEL_30 - IOMUXC XBAR_INOUT30 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_MASK)

IOMUXC_XBAR_DIR_SEL_31 - IOMUXC XBAR_INOUT31 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_MASK)

IOMUXC_XBAR_DIR_SEL_31 - IOMUXC XBAR_INOUT31 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_MASK)

IOMUXC_XBAR_DIR_SEL_4 - IOMUXC XBAR_INOUT4 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_MASK)

IOMUXC_XBAR_DIR_SEL_4 - IOMUXC XBAR_INOUT4 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_MASK)

IOMUXC_XBAR_DIR_SEL_5 - IOMUXC XBAR_INOUT5 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_MASK)

IOMUXC_XBAR_DIR_SEL_5 - IOMUXC XBAR_INOUT5 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_MASK)

IOMUXC_XBAR_DIR_SEL_6 - IOMUXC XBAR_INOUT6 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_MASK)

IOMUXC_XBAR_DIR_SEL_6 - IOMUXC XBAR_INOUT6 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_MASK)

IOMUXC_XBAR_DIR_SEL_7 - IOMUXC XBAR_INOUT7 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_MASK)

IOMUXC_XBAR_DIR_SEL_7 - IOMUXC XBAR_INOUT7 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_MASK)

IOMUXC_XBAR_DIR_SEL_8 - IOMUXC XBAR_INOUT8 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_MASK)

IOMUXC_XBAR_DIR_SEL_8 - IOMUXC XBAR_INOUT8 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9 [1/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_MASK)

IOMUXC_XBAR_DIR_SEL_9 - IOMUXC XBAR_INOUT9 function direction select

◆ IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9 [2/2]

#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_MASK)

IOMUXC_XBAR_DIR_SEL_9 - IOMUXC XBAR_INOUT9 function direction select

◆ IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT

#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK)

LOCK_M7_APC_AC_R1_BOT 0b0..M7_APC_AC_R1_BOT is not locked 0b1..M7_APC_AC_R1_BOT is locked (read access only)

◆ IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT

#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK)

M7_APC_AC_R1_BOT - Access Permission Controller (APC) end address of memory region-1

◆ IOMUXC_GPR_GPR21_DWP [1/2]

#define IOMUXC_GPR_GPR21_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_DWP_SHIFT)) & IOMUXC_GPR_GPR21_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR21_DWP [2/2]

#define IOMUXC_GPR_GPR21_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_DWP_SHIFT)) & IOMUXC_GPR_GPR21_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR21_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR21_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR21_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR21_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR21_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR21_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32 [1/2]

#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_MASK)

IOMUXC_XBAR_DIR_SEL_32 - IOMUXC XBAR_INOUT32 function direction select

◆ IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32 [2/2]

#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_MASK)

IOMUXC_XBAR_DIR_SEL_32 - IOMUXC XBAR_INOUT32 function direction select

◆ IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33 [1/2]

#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_MASK)

IOMUXC_XBAR_DIR_SEL_33 - IOMUXC XBAR_INOUT33 function direction select

◆ IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33 [2/2]

#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_MASK)

IOMUXC_XBAR_DIR_SEL_33 - IOMUXC XBAR_INOUT33 function direction select

◆ IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34 [1/2]

#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_MASK)

IOMUXC_XBAR_DIR_SEL_34 - IOMUXC XBAR_INOUT34 function direction select

◆ IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34 [2/2]

#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_MASK)

IOMUXC_XBAR_DIR_SEL_34 - IOMUXC XBAR_INOUT34 function direction select

◆ IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35 [1/2]

#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_MASK)

IOMUXC_XBAR_DIR_SEL_35 - IOMUXC XBAR_INOUT35 function direction select

◆ IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35 [2/2]

#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_MASK)

IOMUXC_XBAR_DIR_SEL_35 - IOMUXC XBAR_INOUT35 function direction select

◆ IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36 [1/2]

#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_MASK)

IOMUXC_XBAR_DIR_SEL_36 - IOMUXC XBAR_INOUT36 function direction select

◆ IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36 [2/2]

#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_MASK)

IOMUXC_XBAR_DIR_SEL_36 - IOMUXC XBAR_INOUT36 function direction select

◆ IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37 [1/2]

#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_MASK)

IOMUXC_XBAR_DIR_SEL_37 - IOMUXC XBAR_INOUT37 function direction select

◆ IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37 [2/2]

#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_MASK)

IOMUXC_XBAR_DIR_SEL_37 - IOMUXC XBAR_INOUT37 function direction select

◆ IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38 [1/2]

#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_MASK)

IOMUXC_XBAR_DIR_SEL_38 - IOMUXC XBAR_INOUT38 function direction select

◆ IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38 [2/2]

#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_MASK)

IOMUXC_XBAR_DIR_SEL_38 - IOMUXC XBAR_INOUT38 function direction select

◆ IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39 [1/2]

#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_MASK)

IOMUXC_XBAR_DIR_SEL_39 - IOMUXC XBAR_INOUT39 function direction select

◆ IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39 [2/2]

#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_MASK)

IOMUXC_XBAR_DIR_SEL_39 - IOMUXC XBAR_INOUT39 function direction select

◆ IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40 [1/2]

#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_MASK)

IOMUXC_XBAR_DIR_SEL_40 - IOMUXC XBAR_INOUT40 function direction select

◆ IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40 [2/2]

#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_MASK)

IOMUXC_XBAR_DIR_SEL_40 - IOMUXC XBAR_INOUT40 function direction select

◆ IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41 [1/2]

#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_MASK)

IOMUXC_XBAR_DIR_SEL_41 - IOMUXC XBAR_INOUT41 function direction select

◆ IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41 [2/2]

#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_MASK)

IOMUXC_XBAR_DIR_SEL_41 - IOMUXC XBAR_INOUT41 function direction select

◆ IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42 [1/2]

#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_MASK)

IOMUXC_XBAR_DIR_SEL_42 - IOMUXC XBAR_INOUT42 function direction select

◆ IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42 [2/2]

#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_MASK)

IOMUXC_XBAR_DIR_SEL_42 - IOMUXC XBAR_INOUT42 function direction select

◆ IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP

#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK)

LOCK_M7_APC_AC_R1_TOP 0b0..M7_APC_AC_R1_TOP is not locked 0b1..M7_APC_AC_R1_TOP is locked (read access only)

◆ IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP

#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK)

M7_APC_AC_R1_TOP - Access Permission Controller (APC) start address of memory region-1

◆ IOMUXC_GPR_GPR22_DWP [1/2]

#define IOMUXC_GPR_GPR22_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_DWP_SHIFT)) & IOMUXC_GPR_GPR22_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR22_DWP [2/2]

#define IOMUXC_GPR_GPR22_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_DWP_SHIFT)) & IOMUXC_GPR_GPR22_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR22_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR22_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR22_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR22_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR22_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR22_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT

#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK)

LOCK_M7_APC_AC_R2_BOT 0b0..M7_APC_AC_R2_BOT is not locked 0b1..M7_APC_AC_R2_BOT is locked (read access only)

◆ IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT

#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK)

M7_APC_AC_R2_BOT - Access Permission Controller (APC) end address of memory region-2

◆ IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1 [1/2]

#define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK)

REF_1M_CLK_GPT1 - GPT1 1 MHz clock source select

◆ IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1 [2/2]

#define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK)

REF_1M_CLK_GPT1 - GPT1 1 MHz clock source select

◆ IOMUXC_GPR_GPR23_DWP [1/2]

#define IOMUXC_GPR_GPR23_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_DWP_SHIFT)) & IOMUXC_GPR_GPR23_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR23_DWP [2/2]

#define IOMUXC_GPR_GPR23_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_DWP_SHIFT)) & IOMUXC_GPR_GPR23_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR23_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR23_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR23_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR23_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR23_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR23_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL [1/2]

#define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_MASK)

GPT2_CAPIN1_SEL - GPT2 input capture channel 1 source select

◆ IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL [2/2]

#define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_MASK)

GPT2_CAPIN1_SEL - GPT2 input capture channel 1 source select

◆ IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL [1/2]

#define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_MASK)

GPT2_CAPIN2_SEL - GPT2 input capture channel 2 source select

◆ IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL [2/2]

#define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_MASK)

GPT2_CAPIN2_SEL - GPT2 input capture channel 2 source select

◆ IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP

#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK)

LOCK_M7_APC_AC_R2_TOP 0b0..M7_APC_AC_R2_TOP is not locked 0b1..M7_APC_AC_R2_TOP is locked (read access only)

◆ IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP

#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK)

M7_APC_AC_R2_TOP - Access Permission Controller (APC) start address of memory region-2

◆ IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2 [1/2]

#define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK)

REF_1M_CLK_GPT2 - GPT2 1 MHz clock source select

◆ IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2 [2/2]

#define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK)

REF_1M_CLK_GPT2 - GPT2 1 MHz clock source select

◆ IOMUXC_GPR_GPR24_DWP [1/2]

#define IOMUXC_GPR_GPR24_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_DWP_SHIFT)) & IOMUXC_GPR_GPR24_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR24_DWP [2/2]

#define IOMUXC_GPR_GPR24_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_DWP_SHIFT)) & IOMUXC_GPR_GPR24_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR24_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR24_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR24_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR24_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR24_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR24_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL [1/2]

#define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_MASK)

GPT3_CAPIN1_SEL - GPT3 input capture channel 1 source select

◆ IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL [2/2]

#define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_MASK)

GPT3_CAPIN1_SEL - GPT3 input capture channel 1 source select

◆ IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT

#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK)

LOCK_M7_APC_AC_R3_BOT 0b0..M7_APC_AC_R3_BOT is not locked 0b1..M7_APC_AC_R3_BOT is locked (read access only)

◆ IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT

#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK)

M7_APC_AC_R3_BOT - Access Permission Controller (APC) end address of memory region-3

◆ IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3 [1/2]

#define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_SHIFT)) & IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK)

REF_1M_CLK_GPT3 - GPT3 1 MHz clock source select

◆ IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3 [2/2]

#define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_SHIFT)) & IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK)

REF_1M_CLK_GPT3 - GPT3 1 MHz clock source select

◆ IOMUXC_GPR_GPR25_DWP [1/2]

#define IOMUXC_GPR_GPR25_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_DWP_SHIFT)) & IOMUXC_GPR_GPR25_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR25_DWP [2/2]

#define IOMUXC_GPR_GPR25_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_DWP_SHIFT)) & IOMUXC_GPR_GPR25_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR25_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR25_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR25_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR25_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR25_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR25_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP

#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK)

LOCK_M7_APC_AC_R3_TOP 0b0..M7_APC_AC_R3_TOP is not locked 0b1..M7_APC_AC_R3_TOP is locked (read access only)

◆ IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP

#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK)

M7_APC_AC_R3_TOP - Access Permission Controller (APC) start address of memory region-3

◆ IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4 [1/2]

#define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_SHIFT)) & IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK)

REF_1M_CLK_GPT4 - GPT4 1 MHz clock source select

◆ IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4 [2/2]

#define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_SHIFT)) & IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK)

REF_1M_CLK_GPT4 - GPT4 1 MHz clock source select

◆ IOMUXC_GPR_GPR26_DWP [1/2]

#define IOMUXC_GPR_GPR26_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_DWP_SHIFT)) & IOMUXC_GPR_GPR26_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR26_DWP [2/2]

#define IOMUXC_GPR_GPR26_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_DWP_SHIFT)) & IOMUXC_GPR_GPR26_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR26_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR26_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR26_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR26_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR26_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR26_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5 [1/2]

#define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_SHIFT)) & IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK)

REF_1M_CLK_GPT5 - GPT5 1 MHz clock source select

◆ IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5 [2/2]

#define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_SHIFT)) & IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK)

REF_1M_CLK_GPT5 - GPT5 1 MHz clock source select

◆ IOMUXC_GPR_GPR27_DWP [1/2]

#define IOMUXC_GPR_GPR27_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_DWP_SHIFT)) & IOMUXC_GPR_GPR27_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR27_DWP [2/2]

#define IOMUXC_GPR_GPR27_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_DWP_SHIFT)) & IOMUXC_GPR_GPR27_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR27_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR27_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR27_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR27_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR27_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR27_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6 [1/2]

#define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_SHIFT)) & IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK)

REF_1M_CLK_GPT6 - GPT6 1 MHz clock source select

◆ IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6 [2/2]

#define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_SHIFT)) & IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK)

REF_1M_CLK_GPT6 - GPT6 1 MHz clock source select

◆ IOMUXC_GPR_GPR28_ARCACHE_USDHC [1/2]

#define IOMUXC_GPR_GPR28_ARCACHE_USDHC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR28_ARCACHE_USDHC_MASK)

ARCACHE_USDHC - uSDHC block cacheable attribute value of AXI read transactions

◆ IOMUXC_GPR_GPR28_ARCACHE_USDHC [2/2]

#define IOMUXC_GPR_GPR28_ARCACHE_USDHC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR28_ARCACHE_USDHC_MASK)

ARCACHE_USDHC - uSDHC block cacheable attribute value of AXI read transactions

◆ IOMUXC_GPR_GPR28_AWCACHE_USDHC [1/2]

#define IOMUXC_GPR_GPR28_AWCACHE_USDHC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR28_AWCACHE_USDHC_MASK)

AWCACHE_USDHC - uSDHC block cacheable attribute value of AXI write transactions

◆ IOMUXC_GPR_GPR28_AWCACHE_USDHC [2/2]

#define IOMUXC_GPR_GPR28_AWCACHE_USDHC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR28_AWCACHE_USDHC_MASK)

AWCACHE_USDHC - uSDHC block cacheable attribute value of AXI write transactions

◆ IOMUXC_GPR_GPR28_CACHE_ENET [1/2]

#define IOMUXC_GPR_GPR28_CACHE_ENET (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_ENET_MASK)

CACHE_ENET - ENET block cacheable attribute value of AXI transactions

◆ IOMUXC_GPR_GPR28_CACHE_ENET [2/2]

#define IOMUXC_GPR_GPR28_CACHE_ENET (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_ENET_MASK)

CACHE_ENET - ENET block cacheable attribute value of AXI transactions

◆ IOMUXC_GPR_GPR28_CACHE_USB [1/2]

#define IOMUXC_GPR_GPR28_CACHE_USB (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_USB_MASK)

CACHE_USB - USB block cacheable attribute value of AXI transactions

◆ IOMUXC_GPR_GPR28_CACHE_USB [2/2]

#define IOMUXC_GPR_GPR28_CACHE_USB (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_USB_MASK)

CACHE_USB - USB block cacheable attribute value of AXI transactions

◆ IOMUXC_GPR_GPR28_DWP [1/2]

#define IOMUXC_GPR_GPR28_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_DWP_SHIFT)) & IOMUXC_GPR_GPR28_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR28_DWP [2/2]

#define IOMUXC_GPR_GPR28_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_DWP_SHIFT)) & IOMUXC_GPR_GPR28_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR28_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR28_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR28_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR28_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR28_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR28_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR29_DWP [1/2]

#define IOMUXC_GPR_GPR29_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_DWP_SHIFT)) & IOMUXC_GPR_GPR29_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR29_DWP [2/2]

#define IOMUXC_GPR_GPR29_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_DWP_SHIFT)) & IOMUXC_GPR_GPR29_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR29_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR29_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR29_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR29_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR29_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR29_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE [1/2]

#define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_MASK)

USBPHY1_IPG_CLK_ACTIVE - USBPHY1 register access clock enable

◆ IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE [2/2]

#define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_MASK)

USBPHY1_IPG_CLK_ACTIVE - USBPHY1 register access clock enable

◆ IOMUXC_GPR_GPR2_DWP [1/2]

#define IOMUXC_GPR_GPR2_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DWP_SHIFT)) & IOMUXC_GPR_GPR2_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR2_DWP [2/2]

#define IOMUXC_GPR_GPR2_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DWP_SHIFT)) & IOMUXC_GPR_GPR2_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR2_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR2_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR2_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR2_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR2_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR2_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP

#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK)

L2_MEM_DEEPSLEEP 0b0..No force sleep control supported, memory deep sleep mode only entered when whole system in stop mode (OCRAM in normal mode) 0b1..Force memory into deep sleep mode (OCRAM in power saving mode)

◆ IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING

#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK)

L2_MEM_EN_POWERSAVING - Enable power saving features on memory 0b0..Enters power saving mode only when chip is in SUSPEND mode 0b1..Controlled by L2_MEM_DEEPSLEEP bitfield

◆ IOMUXC_GPR_GPR2_MQS_CLK_DIV

#define IOMUXC_GPR_GPR2_MQS_CLK_DIV (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK)

MQS_CLK_DIV - Divider ratio control for mclk from hmclk. mclk frequency = 1/(n+1) * hmclk frequency. 0b00000000..mclk frequency = 1/1 * hmclk frequency 0b00000001..mclk frequency = 1/2 * hmclk frequency 0b00000010..mclk frequency = 1/3 * hmclk frequency 0b00000011..mclk frequency = 1/4 * hmclk frequency 0b00000100..mclk frequency = 1/5 * hmclk frequency 0b00000101..mclk frequency = 1/6 * hmclk frequency 0b00000110..mclk frequency = 1/7 * hmclk frequency 0b00000111..mclk frequency = 1/8 * hmclk frequency 0b00001000..mclk frequency = 1/9 * hmclk frequency 0b00001001..mclk frequency = 1/10 * hmclk frequency 0b00001010..mclk frequency = 1/11 * hmclk frequency 0b00001011..mclk frequency = 1/12 * hmclk frequency 0b00001100..mclk frequency = 1/13 * hmclk frequency 0b00001101..mclk frequency = 1/14 * hmclk frequency 0b00001110..mclk frequency = 1/15 * hmclk frequency 0b00001111..mclk frequency = 1/16 * hmclk frequency 0b00010000..mclk frequency = 1/17 * hmclk frequency 0b00010001..mclk frequency = 1/18 * hmclk frequency 0b00010010..mclk frequency = 1/19 * hmclk frequency 0b00010011..mclk frequency = 1/20 * hmclk frequency 0b00010100..mclk frequency = 1/21 * hmclk frequency 0b00010101..mclk frequency = 1/22 * hmclk frequency 0b00010110..mclk frequency = 1/23 * hmclk frequency 0b00010111..mclk frequency = 1/24 * hmclk frequency 0b00011000..mclk frequency = 1/25 * hmclk frequency 0b00011001..mclk frequency = 1/26 * hmclk frequency 0b00011010..mclk frequency = 1/27 * hmclk frequency 0b00011011..mclk frequency = 1/28 * hmclk frequency 0b00011100..mclk frequency = 1/29 * hmclk frequency 0b00011101..mclk frequency = 1/30 * hmclk frequency 0b00011110..mclk frequency = 1/31 * hmclk frequency 0b00011111..mclk frequency = 1/32 * hmclk frequency 0b00100000..mclk frequency = 1/33 * hmclk frequency 0b00100001..mclk frequency = 1/34 * hmclk frequency 0b00100010..mclk frequency = 1/35 * hmclk frequency 0b00100011..mclk frequency = 1/36 * hmclk frequency 0b00100100..mclk frequency = 1/37 * hmclk frequency 0b00100101..mclk frequency = 1/38 * hmclk frequency 0b00100110..mclk frequency = 1/39 * hmclk frequency 0b00100111..mclk frequency = 1/40 * hmclk frequency 0b00101000..mclk frequency = 1/41 * hmclk frequency 0b00101001..mclk frequency = 1/42 * hmclk frequency 0b00101010..mclk frequency = 1/43 * hmclk frequency 0b00101011..mclk frequency = 1/44 * hmclk frequency 0b00101100..mclk frequency = 1/45 * hmclk frequency 0b00101101..mclk frequency = 1/46 * hmclk frequency 0b00101110..mclk frequency = 1/47 * hmclk frequency 0b00101111..mclk frequency = 1/48 * hmclk frequency 0b00110000..mclk frequency = 1/49 * hmclk frequency 0b00110001..mclk frequency = 1/50 * hmclk frequency 0b00110010..mclk frequency = 1/51 * hmclk frequency 0b00110011..mclk frequency = 1/52 * hmclk frequency 0b00110100..mclk frequency = 1/53 * hmclk frequency 0b00110101..mclk frequency = 1/54 * hmclk frequency 0b00110110..mclk frequency = 1/55 * hmclk frequency 0b00110111..mclk frequency = 1/56 * hmclk frequency 0b00111000..mclk frequency = 1/57 * hmclk frequency 0b00111001..mclk frequency = 1/58 * hmclk frequency 0b00111010..mclk frequency = 1/59 * hmclk frequency 0b00111011..mclk frequency = 1/60 * hmclk frequency 0b00111100..mclk frequency = 1/61 * hmclk frequency 0b00111101..mclk frequency = 1/62 * hmclk frequency 0b00111110..mclk frequency = 1/63 * hmclk frequency 0b00111111..mclk frequency = 1/64 * hmclk frequency 0b01000000..mclk frequency = 1/65 * hmclk frequency 0b01000001..mclk frequency = 1/66 * hmclk frequency 0b01000010..mclk frequency = 1/67 * hmclk frequency 0b01000011..mclk frequency = 1/68 * hmclk frequency 0b01000100..mclk frequency = 1/69 * hmclk frequency 0b01000101..mclk frequency = 1/70 * hmclk frequency 0b01000110..mclk frequency = 1/71 * hmclk frequency 0b01000111..mclk frequency = 1/72 * hmclk frequency 0b01001000..mclk frequency = 1/73 * hmclk frequency 0b01001001..mclk frequency = 1/74 * hmclk frequency 0b01001010..mclk frequency = 1/75 * hmclk frequency 0b01001011..mclk frequency = 1/76 * hmclk frequency 0b01001100..mclk frequency = 1/77 * hmclk frequency 0b01001101..mclk frequency = 1/78 * hmclk frequency 0b01001110..mclk frequency = 1/79 * hmclk frequency 0b01001111..mclk frequency = 1/80 * hmclk frequency 0b01010000..mclk frequency = 1/81 * hmclk frequency 0b01010001..mclk frequency = 1/82 * hmclk frequency 0b01010010..mclk frequency = 1/83 * hmclk frequency 0b01010011..mclk frequency = 1/84 * hmclk frequency 0b01010100..mclk frequency = 1/85 * hmclk frequency 0b01010101..mclk frequency = 1/86 * hmclk frequency 0b01010110..mclk frequency = 1/87 * hmclk frequency 0b01010111..mclk frequency = 1/88 * hmclk frequency 0b01011000..mclk frequency = 1/89 * hmclk frequency 0b01011001..mclk frequency = 1/90 * hmclk frequency 0b01011010..mclk frequency = 1/91 * hmclk frequency 0b01011011..mclk frequency = 1/92 * hmclk frequency 0b01011100..mclk frequency = 1/93 * hmclk frequency 0b01011101..mclk frequency = 1/94 * hmclk frequency 0b01011110..mclk frequency = 1/95 * hmclk frequency 0b01011111..mclk frequency = 1/96 * hmclk frequency 0b01100000..mclk frequency = 1/97 * hmclk frequency 0b01100001..mclk frequency = 1/98 * hmclk frequency 0b01100010..mclk frequency = 1/99 * hmclk frequency 0b01100011..mclk frequency = 1/100 * hmclk frequency 0b01100100..mclk frequency = 1/101 * hmclk frequency 0b01100101..mclk frequency = 1/102 * hmclk frequency 0b01100110..mclk frequency = 1/103 * hmclk frequency 0b01100111..mclk frequency = 1/104 * hmclk frequency 0b01101000..mclk frequency = 1/105 * hmclk frequency 0b01101001..mclk frequency = 1/106 * hmclk frequency 0b01101010..mclk frequency = 1/107 * hmclk frequency 0b01101011..mclk frequency = 1/108 * hmclk frequency 0b01101100..mclk frequency = 1/109 * hmclk frequency 0b01101101..mclk frequency = 1/110 * hmclk frequency 0b01101110..mclk frequency = 1/111 * hmclk frequency 0b01101111..mclk frequency = 1/112 * hmclk frequency 0b01110000..mclk frequency = 1/113 * hmclk frequency 0b01110001..mclk frequency = 1/114 * hmclk frequency 0b01110010..mclk frequency = 1/115 * hmclk frequency 0b01110011..mclk frequency = 1/116 * hmclk frequency 0b01110100..mclk frequency = 1/117 * hmclk frequency 0b01110101..mclk frequency = 1/118 * hmclk frequency 0b01110110..mclk frequency = 1/119 * hmclk frequency 0b01110111..mclk frequency = 1/120 * hmclk frequency 0b01111000..mclk frequency = 1/121 * hmclk frequency 0b01111001..mclk frequency = 1/122 * hmclk frequency 0b01111010..mclk frequency = 1/123 * hmclk frequency 0b01111011..mclk frequency = 1/124 * hmclk frequency 0b01111100..mclk frequency = 1/125 * hmclk frequency 0b01111101..mclk frequency = 1/126 * hmclk frequency 0b01111110..mclk frequency = 1/127 * hmclk frequency 0b01111111..mclk frequency = 1/128 * hmclk frequency 0b10000000..mclk frequency = 1/129 * hmclk frequency 0b10000001..mclk frequency = 1/130 * hmclk frequency 0b10000010..mclk frequency = 1/131 * hmclk frequency 0b10000011..mclk frequency = 1/132 * hmclk frequency 0b10000100..mclk frequency = 1/133 * hmclk frequency 0b10000101..mclk frequency = 1/134 * hmclk frequency 0b10000110..mclk frequency = 1/135 * hmclk frequency 0b10000111..mclk frequency = 1/136 * hmclk frequency 0b10001000..mclk frequency = 1/137 * hmclk frequency 0b10001001..mclk frequency = 1/138 * hmclk frequency 0b10001010..mclk frequency = 1/139 * hmclk frequency 0b10001011..mclk frequency = 1/140 * hmclk frequency 0b10001100..mclk frequency = 1/141 * hmclk frequency 0b10001101..mclk frequency = 1/142 * hmclk frequency 0b10001110..mclk frequency = 1/143 * hmclk frequency 0b10001111..mclk frequency = 1/144 * hmclk frequency 0b10010000..mclk frequency = 1/145 * hmclk frequency 0b10010001..mclk frequency = 1/146 * hmclk frequency 0b10010010..mclk frequency = 1/147 * hmclk frequency 0b10010011..mclk frequency = 1/148 * hmclk frequency 0b10010100..mclk frequency = 1/149 * hmclk frequency 0b10010101..mclk frequency = 1/150 * hmclk frequency 0b10010110..mclk frequency = 1/151 * hmclk frequency 0b10010111..mclk frequency = 1/152 * hmclk frequency 0b10011000..mclk frequency = 1/153 * hmclk frequency 0b10011001..mclk frequency = 1/154 * hmclk frequency 0b10011010..mclk frequency = 1/155 * hmclk frequency 0b10011011..mclk frequency = 1/156 * hmclk frequency 0b10011100..mclk frequency = 1/157 * hmclk frequency 0b10011101..mclk frequency = 1/158 * hmclk frequency 0b10011110..mclk frequency = 1/159 * hmclk frequency 0b10011111..mclk frequency = 1/160 * hmclk frequency 0b10100000..mclk frequency = 1/161 * hmclk frequency 0b10100001..mclk frequency = 1/162 * hmclk frequency 0b10100010..mclk frequency = 1/163 * hmclk frequency 0b10100011..mclk frequency = 1/164 * hmclk frequency 0b10100100..mclk frequency = 1/165 * hmclk frequency 0b10100101..mclk frequency = 1/166 * hmclk frequency 0b10100110..mclk frequency = 1/167 * hmclk frequency 0b10100111..mclk frequency = 1/168 * hmclk frequency 0b10101000..mclk frequency = 1/169 * hmclk frequency 0b10101001..mclk frequency = 1/170 * hmclk frequency 0b10101010..mclk frequency = 1/171 * hmclk frequency 0b10101011..mclk frequency = 1/172 * hmclk frequency 0b10101100..mclk frequency = 1/173 * hmclk frequency 0b10101101..mclk frequency = 1/174 * hmclk frequency 0b10101110..mclk frequency = 1/175 * hmclk frequency 0b10101111..mclk frequency = 1/176 * hmclk frequency 0b10110000..mclk frequency = 1/177 * hmclk frequency 0b10110001..mclk frequency = 1/178 * hmclk frequency 0b10110010..mclk frequency = 1/179 * hmclk frequency 0b10110011..mclk frequency = 1/180 * hmclk frequency 0b10110100..mclk frequency = 1/181 * hmclk frequency 0b10110101..mclk frequency = 1/182 * hmclk frequency 0b10110110..mclk frequency = 1/183 * hmclk frequency 0b10110111..mclk frequency = 1/184 * hmclk frequency 0b10111000..mclk frequency = 1/185 * hmclk frequency 0b10111001..mclk frequency = 1/186 * hmclk frequency 0b10111010..mclk frequency = 1/187 * hmclk frequency 0b10111011..mclk frequency = 1/188 * hmclk frequency 0b10111100..mclk frequency = 1/189 * hmclk frequency 0b10111101..mclk frequency = 1/190 * hmclk frequency 0b10111110..mclk frequency = 1/191 * hmclk frequency 0b10111111..mclk frequency = 1/192 * hmclk frequency 0b11000000..mclk frequency = 1/193 * hmclk frequency 0b11000001..mclk frequency = 1/194 * hmclk frequency 0b11000010..mclk frequency = 1/195 * hmclk frequency 0b11000011..mclk frequency = 1/196 * hmclk frequency 0b11000100..mclk frequency = 1/197 * hmclk frequency 0b11000101..mclk frequency = 1/198 * hmclk frequency 0b11000110..mclk frequency = 1/199 * hmclk frequency 0b11000111..mclk frequency = 1/200 * hmclk frequency 0b11001000..mclk frequency = 1/201 * hmclk frequency 0b11001001..mclk frequency = 1/202 * hmclk frequency 0b11001010..mclk frequency = 1/203 * hmclk frequency 0b11001011..mclk frequency = 1/204 * hmclk frequency 0b11001100..mclk frequency = 1/205 * hmclk frequency 0b11001101..mclk frequency = 1/206 * hmclk frequency 0b11001110..mclk frequency = 1/207 * hmclk frequency 0b11001111..mclk frequency = 1/208 * hmclk frequency 0b11010000..mclk frequency = 1/209 * hmclk frequency 0b11010001..mclk frequency = 1/210 * hmclk frequency 0b11010010..mclk frequency = 1/211 * hmclk frequency 0b11010011..mclk frequency = 1/212 * hmclk frequency 0b11010100..mclk frequency = 1/213 * hmclk frequency 0b11010101..mclk frequency = 1/214 * hmclk frequency 0b11010110..mclk frequency = 1/215 * hmclk frequency 0b11010111..mclk frequency = 1/216 * hmclk frequency 0b11011000..mclk frequency = 1/217 * hmclk frequency 0b11011001..mclk frequency = 1/218 * hmclk frequency 0b11011010..mclk frequency = 1/219 * hmclk frequency 0b11011011..mclk frequency = 1/220 * hmclk frequency 0b11011100..mclk frequency = 1/221 * hmclk frequency 0b11011101..mclk frequency = 1/222 * hmclk frequency 0b11011110..mclk frequency = 1/223 * hmclk frequency 0b11011111..mclk frequency = 1/224 * hmclk frequency 0b11100000..mclk frequency = 1/225 * hmclk frequency 0b11100001..mclk frequency = 1/226 * hmclk frequency 0b11100010..mclk frequency = 1/227 * hmclk frequency 0b11100011..mclk frequency = 1/228 * hmclk frequency 0b11100100..mclk frequency = 1/229 * hmclk frequency 0b11100101..mclk frequency = 1/230 * hmclk frequency 0b11100110..mclk frequency = 1/231 * hmclk frequency 0b11100111..mclk frequency = 1/232 * hmclk frequency 0b11101000..mclk frequency = 1/233 * hmclk frequency 0b11101001..mclk frequency = 1/234 * hmclk frequency 0b11101010..mclk frequency = 1/235 * hmclk frequency 0b11101011..mclk frequency = 1/236 * hmclk frequency 0b11101100..mclk frequency = 1/237 * hmclk frequency 0b11101101..mclk frequency = 1/238 * hmclk frequency 0b11101110..mclk frequency = 1/239 * hmclk frequency 0b11101111..mclk frequency = 1/240 * hmclk frequency 0b11110000..mclk frequency = 1/241 * hmclk frequency 0b11110001..mclk frequency = 1/242 * hmclk frequency 0b11110010..mclk frequency = 1/243 * hmclk frequency 0b11110011..mclk frequency = 1/244 * hmclk frequency 0b11110100..mclk frequency = 1/245 * hmclk frequency 0b11110101..mclk frequency = 1/246 * hmclk frequency 0b11110110..mclk frequency = 1/247 * hmclk frequency 0b11110111..mclk frequency = 1/248 * hmclk frequency 0b11111000..mclk frequency = 1/249 * hmclk frequency 0b11111001..mclk frequency = 1/250 * hmclk frequency 0b11111010..mclk frequency = 1/251 * hmclk frequency 0b11111011..mclk frequency = 1/252 * hmclk frequency 0b11111100..mclk frequency = 1/253 * hmclk frequency 0b11111101..mclk frequency = 1/254 * hmclk frequency 0b11111110..mclk frequency = 1/255 * hmclk frequency 0b11111111..mclk frequency = 1/256 * hmclk frequency

◆ IOMUXC_GPR_GPR2_MQS_EN

#define IOMUXC_GPR_GPR2_MQS_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK)

MQS_EN 0b0..Disable MQS 0b1..Enable MQS

◆ IOMUXC_GPR_GPR2_MQS_OVERSAMPLE

#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK)

MQS_OVERSAMPLE - Medium Quality Sound (MQS) Oversample 0b0..32 0b1..64

◆ IOMUXC_GPR_GPR2_MQS_SW_RST

#define IOMUXC_GPR_GPR2_MQS_SW_RST (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK)

MQS_SW_RST 0b0..Exit software reset for MQS 0b1..Enable software reset for MQS

◆ IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE

#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK)

QTIMER1_TMR_CNTS_FREEZE - QTIMER1 timer counter freeze 0b0..Timer counter works normally 0b1..Reset counter and ouput flags

◆ IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE

#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK)

QTIMER2_TMR_CNTS_FREEZE - QTIMER2 timer counter freeze 0b0..Timer counter works normally 0b1..Reset counter and ouput flags

◆ IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE

#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK)

QTIMER3_TMR_CNTS_FREEZE - QTIMER3 timer counter freeze 0b0..Timer counter works normally 0b1..Reset counter and ouput flags

◆ IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE

#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK)

QTIMER4_TMR_CNTS_FREEZE - QTIMER4 timer counter freeze 0b0..Timer counter works normally 0b1..Reset counter and ouput flags

◆ IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL [1/2]

#define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_MASK)

SAI3_MCLK3_SEL - SAI3 MCLK3 source select

◆ IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL [2/2]

#define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_MASK)

SAI3_MCLK3_SEL - SAI3 MCLK3 source select

◆ IOMUXC_GPR_GPR2_SAI3_MCLK_DIR [1/2]

#define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_MASK)

SAI3_MCLK_DIR - SAI3_MCLK signal direction control

◆ IOMUXC_GPR_GPR2_SAI3_MCLK_DIR [2/2]

#define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_MASK)

SAI3_MCLK_DIR - SAI3_MCLK signal direction control

◆ IOMUXC_GPR_GPR2_SAI4_MCLK_DIR [1/2]

#define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_MASK)

SAI4_MCLK_DIR - SAI4_MCLK signal direction control

◆ IOMUXC_GPR_GPR2_SAI4_MCLK_DIR [2/2]

#define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_MASK)

SAI4_MCLK_DIR - SAI4_MCLK signal direction control

◆ IOMUXC_GPR_GPR30_DWP [1/2]

#define IOMUXC_GPR_GPR30_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_DWP_SHIFT)) & IOMUXC_GPR_GPR30_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR30_DWP [2/2]

#define IOMUXC_GPR_GPR30_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_DWP_SHIFT)) & IOMUXC_GPR_GPR30_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR30_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR30_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR30_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR30_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR30_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR30_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE [1/2]

#define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_MASK)

USBPHY2_IPG_CLK_ACTIVE - USBPHY2 register access clock enable

◆ IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE [2/2]

#define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_MASK)

USBPHY2_IPG_CLK_ACTIVE - USBPHY2 register access clock enable

◆ IOMUXC_GPR_GPR31_DWP [1/2]

#define IOMUXC_GPR_GPR31_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_DWP_SHIFT)) & IOMUXC_GPR_GPR31_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR31_DWP [2/2]

#define IOMUXC_GPR_GPR31_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_DWP_SHIFT)) & IOMUXC_GPR_GPR31_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR31_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR31_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR31_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR31_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR31_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR31_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING [1/2]

#define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_SHIFT)) & IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_MASK)

OCRAM_M7_CLK_GATING - OCRAM M7 clock gating enable

◆ IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING [2/2]

#define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_SHIFT)) & IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_MASK)

OCRAM_M7_CLK_GATING - OCRAM M7 clock gating enable

◆ IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL [1/2]

#define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_MASK)

RMW2_WAIT_BVALID_CPL - OCRAM M7 RMW wait enable

◆ IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL [2/2]

#define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_MASK)

RMW2_WAIT_BVALID_CPL - OCRAM M7 RMW wait enable

◆ IOMUXC_GPR_GPR32_DWP [1/2]

#define IOMUXC_GPR_GPR32_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_DWP_SHIFT)) & IOMUXC_GPR_GPR32_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR32_DWP [2/2]

#define IOMUXC_GPR_GPR32_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_DWP_SHIFT)) & IOMUXC_GPR_GPR32_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR32_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR32_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR32_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR32_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR32_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR32_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL [1/2]

#define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_MASK)

RMW1_WAIT_BVALID_CPL - OCRAM1 RMW wait enable

◆ IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL [2/2]

#define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_MASK)

RMW1_WAIT_BVALID_CPL - OCRAM1 RMW wait enable

◆ IOMUXC_GPR_GPR33_DWP [1/2]

#define IOMUXC_GPR_GPR33_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_DWP_SHIFT)) & IOMUXC_GPR_GPR33_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR33_DWP [2/2]

#define IOMUXC_GPR_GPR33_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_DWP_SHIFT)) & IOMUXC_GPR_GPR33_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR33_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR33_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR33_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR33_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR33_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR33_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL [1/2]

#define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_MASK)

RMW2_WAIT_BVALID_CPL - OCRAM2 RMW wait enable

◆ IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL [2/2]

#define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_MASK)

RMW2_WAIT_BVALID_CPL - OCRAM2 RMW wait enable

◆ IOMUXC_GPR_GPR34_DWP [1/2]

#define IOMUXC_GPR_GPR34_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_DWP_SHIFT)) & IOMUXC_GPR_GPR34_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR34_DWP [2/2]

#define IOMUXC_GPR_GPR34_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_DWP_SHIFT)) & IOMUXC_GPR_GPR34_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR34_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR34_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR34_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR34_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR34_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR34_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN [1/2]

#define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_SHIFT)) & IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_MASK)

FLEXSPI1_OTFAD_EN - FlexSPI1 OTFAD enable

◆ IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN [2/2]

#define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_SHIFT)) & IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_MASK)

FLEXSPI1_OTFAD_EN - FlexSPI1 OTFAD enable

◆ IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL [1/2]

#define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_MASK)

XECC_FLEXSPI1_WAIT_BVALID_CPL - XECC_FLEXSPI1 RMW wait enable

◆ IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL [2/2]

#define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_MASK)

XECC_FLEXSPI1_WAIT_BVALID_CPL - XECC_FLEXSPI1 RMW wait enable

◆ IOMUXC_GPR_GPR35_DWP [1/2]

#define IOMUXC_GPR_GPR35_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_DWP_SHIFT)) & IOMUXC_GPR_GPR35_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR35_DWP [2/2]

#define IOMUXC_GPR_GPR35_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_DWP_SHIFT)) & IOMUXC_GPR_GPR35_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR35_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR35_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR35_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR35_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR35_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR35_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN [1/2]

#define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_SHIFT)) & IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_MASK)

FLEXSPI2_OTFAD_EN - FlexSPI2 OTFAD enable

◆ IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN [2/2]

#define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_SHIFT)) & IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_MASK)

FLEXSPI2_OTFAD_EN - FlexSPI2 OTFAD enable

◆ IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL [1/2]

#define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_MASK)

XECC_FLEXSPI2_WAIT_BVALID_CPL - XECC_FLEXSPI2 RMW wait enable

◆ IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL [2/2]

#define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_MASK)

XECC_FLEXSPI2_WAIT_BVALID_CPL - XECC_FLEXSPI2 RMW wait enable

◆ IOMUXC_GPR_GPR36_DWP [1/2]

#define IOMUXC_GPR_GPR36_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_DWP_SHIFT)) & IOMUXC_GPR_GPR36_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR36_DWP [2/2]

#define IOMUXC_GPR_GPR36_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_DWP_SHIFT)) & IOMUXC_GPR_GPR36_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR36_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR36_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR36_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR36_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR36_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR36_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL [1/2]

#define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_MASK)

XECC_SEMC_WAIT_BVALID_CPL - XECC_SEMC RMW wait enable

◆ IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL [2/2]

#define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_MASK)

XECC_SEMC_WAIT_BVALID_CPL - XECC_SEMC RMW wait enable

◆ IOMUXC_GPR_GPR37_DBG_EN [1/2]

#define IOMUXC_GPR_GPR37_DBG_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR37_DBG_EN_MASK)

DBG_EN - ARM invasive debug enable

◆ IOMUXC_GPR_GPR37_DBG_EN [2/2]

#define IOMUXC_GPR_GPR37_DBG_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR37_DBG_EN_MASK)

DBG_EN - ARM invasive debug enable

◆ IOMUXC_GPR_GPR37_DWP [1/2]

#define IOMUXC_GPR_GPR37_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DWP_SHIFT)) & IOMUXC_GPR_GPR37_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR37_DWP [2/2]

#define IOMUXC_GPR_GPR37_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DWP_SHIFT)) & IOMUXC_GPR_GPR37_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR37_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR37_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR37_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR37_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR37_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR37_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR37_EXC_MON [1/2]

#define IOMUXC_GPR_GPR37_EXC_MON (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR37_EXC_MON_MASK)

EXC_MON - Exclusive monitor response select of illegal command

◆ IOMUXC_GPR_GPR37_EXC_MON [2/2]

#define IOMUXC_GPR_GPR37_EXC_MON (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR37_EXC_MON_MASK)

EXC_MON - Exclusive monitor response select of illegal command

◆ IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK [1/2]

#define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_SHIFT)) & IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_MASK)

M4_DBG_ACK_MASK - CM4 debug halt mask

◆ IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK [2/2]

#define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_SHIFT)) & IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_MASK)

M4_DBG_ACK_MASK - CM4 debug halt mask

◆ IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK [1/2]

#define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_SHIFT)) & IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_MASK)

M7_DBG_ACK_MASK - CM7 debug halt mask

◆ IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK [2/2]

#define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_SHIFT)) & IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_MASK)

M7_DBG_ACK_MASK - CM7 debug halt mask

◆ IOMUXC_GPR_GPR37_NIDEN [1/2]

#define IOMUXC_GPR_GPR37_NIDEN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_NIDEN_SHIFT)) & IOMUXC_GPR_GPR37_NIDEN_MASK)

NIDEN - ARM non-secure (non-invasive) debug enable

◆ IOMUXC_GPR_GPR37_NIDEN [2/2]

#define IOMUXC_GPR_GPR37_NIDEN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_NIDEN_SHIFT)) & IOMUXC_GPR_GPR37_NIDEN_MASK)

NIDEN - ARM non-secure (non-invasive) debug enable

◆ IOMUXC_GPR_GPR38_DWP [1/2]

#define IOMUXC_GPR_GPR38_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR38_DWP_SHIFT)) & IOMUXC_GPR_GPR38_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR38_DWP [2/2]

#define IOMUXC_GPR_GPR38_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR38_DWP_SHIFT)) & IOMUXC_GPR_GPR38_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR38_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR38_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR38_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR38_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR38_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR38_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR38_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR38_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR39_DWP [1/2]

#define IOMUXC_GPR_GPR39_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR39_DWP_SHIFT)) & IOMUXC_GPR_GPR39_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR39_DWP [2/2]

#define IOMUXC_GPR_GPR39_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR39_DWP_SHIFT)) & IOMUXC_GPR_GPR39_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR39_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR39_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR39_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR39_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR39_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR39_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR39_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR39_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR3_DCP_KEY_SEL

#define IOMUXC_GPR_GPR3_DCP_KEY_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK)

DCP_KEY_SEL - Select 128-bit DCP key from 256-bit key from SNVS Master Key 0b0..Select [127:0] from SNVS Master Key as DCP key 0b1..Select [255:128] from SNVS Master Key as DCP key

◆ IOMUXC_GPR_GPR3_DWP [1/2]

#define IOMUXC_GPR_GPR3_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DWP_SHIFT)) & IOMUXC_GPR_GPR3_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR3_DWP [2/2]

#define IOMUXC_GPR_GPR3_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DWP_SHIFT)) & IOMUXC_GPR_GPR3_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR3_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR3_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR3_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR3_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR3_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR3_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR3_MQS_CLK_DIV [1/2]

#define IOMUXC_GPR_GPR3_MQS_CLK_DIV (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR3_MQS_CLK_DIV_MASK)

MQS_CLK_DIV - Divider ratio control for mclk from hmclk.

◆ IOMUXC_GPR_GPR3_MQS_CLK_DIV [2/2]

#define IOMUXC_GPR_GPR3_MQS_CLK_DIV (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR3_MQS_CLK_DIV_MASK)

MQS_CLK_DIV - Divider ratio control for mclk from hmclk.

◆ IOMUXC_GPR_GPR3_MQS_EN [1/2]

#define IOMUXC_GPR_GPR3_MQS_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR3_MQS_EN_MASK)

MQS_EN - MQS enable

◆ IOMUXC_GPR_GPR3_MQS_EN [2/2]

#define IOMUXC_GPR_GPR3_MQS_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR3_MQS_EN_MASK)

MQS_EN - MQS enable

◆ IOMUXC_GPR_GPR3_MQS_OVERSAMPLE [1/2]

#define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_MASK)

MQS_OVERSAMPLE - Medium Quality Sound (MQS) Oversample

◆ IOMUXC_GPR_GPR3_MQS_OVERSAMPLE [2/2]

#define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_MASK)

MQS_OVERSAMPLE - Medium Quality Sound (MQS) Oversample

◆ IOMUXC_GPR_GPR3_MQS_SW_RST [1/2]

#define IOMUXC_GPR_GPR3_MQS_SW_RST (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR3_MQS_SW_RST_MASK)

MQS_SW_RST - MQS software reset

◆ IOMUXC_GPR_GPR3_MQS_SW_RST [2/2]

#define IOMUXC_GPR_GPR3_MQS_SW_RST (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR3_MQS_SW_RST_MASK)

MQS_SW_RST - MQS software reset

◆ IOMUXC_GPR_GPR40_DWP [1/2]

#define IOMUXC_GPR_GPR40_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_DWP_SHIFT)) & IOMUXC_GPR_GPR40_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR40_DWP [2/2]

#define IOMUXC_GPR_GPR40_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_DWP_SHIFT)) & IOMUXC_GPR_GPR40_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR40_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR40_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR40_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR40_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR40_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR40_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW [1/2]

#define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_SHIFT)) & IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_MASK)

GPIO_MUX2_GPIO_SEL_LOW - GPIO2 and CM7_GPIO2 share same IO MUX function, GPIO_MUX2 selects one GPIO function.

◆ IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW [2/2]

#define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_SHIFT)) & IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_MASK)

GPIO_MUX2_GPIO_SEL_LOW - GPIO2 and CM7_GPIO2 share same IO MUX function, GPIO_MUX2 selects one GPIO function.

◆ IOMUXC_GPR_GPR41_DWP [1/2]

#define IOMUXC_GPR_GPR41_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_DWP_SHIFT)) & IOMUXC_GPR_GPR41_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR41_DWP [2/2]

#define IOMUXC_GPR_GPR41_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_DWP_SHIFT)) & IOMUXC_GPR_GPR41_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR41_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR41_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR41_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR41_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR41_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR41_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH [1/2]

#define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_SHIFT)) & IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_MASK)

GPIO_MUX2_GPIO_SEL_HIGH - GPIO2 and CM7_GPIO2 share same IO MUX function, GPIO_MUX2 selects one GPIO function.

◆ IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH [2/2]

#define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_SHIFT)) & IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_MASK)

GPIO_MUX2_GPIO_SEL_HIGH - GPIO2 and CM7_GPIO2 share same IO MUX function, GPIO_MUX2 selects one GPIO function.

◆ IOMUXC_GPR_GPR42_DWP [1/2]

#define IOMUXC_GPR_GPR42_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_DWP_SHIFT)) & IOMUXC_GPR_GPR42_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR42_DWP [2/2]

#define IOMUXC_GPR_GPR42_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_DWP_SHIFT)) & IOMUXC_GPR_GPR42_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR42_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR42_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR42_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR42_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR42_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR42_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW [1/2]

#define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_SHIFT)) & IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_MASK)

GPIO_MUX3_GPIO_SEL_LOW - GPIO3 and CM7_GPIO3 share same IO MUX function, GPIO_MUX3 selects one GPIO function.

◆ IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW [2/2]

#define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_SHIFT)) & IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_MASK)

GPIO_MUX3_GPIO_SEL_LOW - GPIO3 and CM7_GPIO3 share same IO MUX function, GPIO_MUX3 selects one GPIO function.

◆ IOMUXC_GPR_GPR43_DWP [1/2]

#define IOMUXC_GPR_GPR43_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_DWP_SHIFT)) & IOMUXC_GPR_GPR43_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR43_DWP [2/2]

#define IOMUXC_GPR_GPR43_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_DWP_SHIFT)) & IOMUXC_GPR_GPR43_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR43_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR43_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR43_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR43_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR43_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR43_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH [1/2]

#define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_SHIFT)) & IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK)

GPIO_MUX3_GPIO_SEL_HIGH - GPIO3 and CM7_GPIO3 share same IO MUX function, GPIO_MUX3 selects one GPIO function.

◆ IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH [2/2]

#define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_SHIFT)) & IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK)

GPIO_MUX3_GPIO_SEL_HIGH - GPIO3 and CM7_GPIO3 share same IO MUX function, GPIO_MUX3 selects one GPIO function.

◆ IOMUXC_GPR_GPR44_DWP [1/2]

#define IOMUXC_GPR_GPR44_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR44_DWP_SHIFT)) & IOMUXC_GPR_GPR44_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR44_DWP [2/2]

#define IOMUXC_GPR_GPR44_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR44_DWP_SHIFT)) & IOMUXC_GPR_GPR44_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR44_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR44_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR44_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR44_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR44_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR44_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR44_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR44_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR45_DWP [1/2]

#define IOMUXC_GPR_GPR45_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR45_DWP_SHIFT)) & IOMUXC_GPR_GPR45_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR45_DWP [2/2]

#define IOMUXC_GPR_GPR45_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR45_DWP_SHIFT)) & IOMUXC_GPR_GPR45_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR45_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR45_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR45_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR45_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR45_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR45_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR45_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR45_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR46_DWP [1/2]

#define IOMUXC_GPR_GPR46_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR46_DWP_SHIFT)) & IOMUXC_GPR_GPR46_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR46_DWP [2/2]

#define IOMUXC_GPR_GPR46_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR46_DWP_SHIFT)) & IOMUXC_GPR_GPR46_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR46_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR46_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR46_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR46_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR46_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR46_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR46_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR46_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR47_DWP [1/2]

#define IOMUXC_GPR_GPR47_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR47_DWP_SHIFT)) & IOMUXC_GPR_GPR47_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR47_DWP [2/2]

#define IOMUXC_GPR_GPR47_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR47_DWP_SHIFT)) & IOMUXC_GPR_GPR47_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR47_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR47_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR47_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR47_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR47_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR47_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR47_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR47_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR48_DWP [1/2]

#define IOMUXC_GPR_GPR48_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR48_DWP_SHIFT)) & IOMUXC_GPR_GPR48_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR48_DWP [2/2]

#define IOMUXC_GPR_GPR48_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR48_DWP_SHIFT)) & IOMUXC_GPR_GPR48_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR48_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR48_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR48_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR48_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR48_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR48_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR48_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR48_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR49_DWP [1/2]

#define IOMUXC_GPR_GPR49_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR49_DWP_SHIFT)) & IOMUXC_GPR_GPR49_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR49_DWP [2/2]

#define IOMUXC_GPR_GPR49_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR49_DWP_SHIFT)) & IOMUXC_GPR_GPR49_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR49_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR49_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR49_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR49_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR49_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR49_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR49_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR49_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR4_CAN1_STOP_ACK

#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK)

CAN1_STOP_ACK - CAN1 stop acknowledge 0b0..CAN1 stop acknowledge is not asserted 0b1..CAN1 stop acknowledge is asserted

◆ IOMUXC_GPR_GPR4_CAN1_STOP_REQ

#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK)

CAN1_STOP_REQ - CAN1 stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR4_CAN2_STOP_ACK

#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK)

CAN2_STOP_ACK - CAN2 stop acknowledge 0b0..CAN2 stop acknowledge is not asserted 0b1..CAN2 stop acknowledge is asserted

◆ IOMUXC_GPR_GPR4_CAN2_STOP_REQ

#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK)

CAN2_STOP_REQ - CAN2 stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR4_DWP [1/2]

#define IOMUXC_GPR_GPR4_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_DWP_SHIFT)) & IOMUXC_GPR_GPR4_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR4_DWP [2/2]

#define IOMUXC_GPR_GPR4_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_DWP_SHIFT)) & IOMUXC_GPR_GPR4_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR4_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR4_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR4_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR4_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR4_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR4_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR4_EDMA_STOP_ACK

#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK)

EDMA_STOP_ACK - EDMA stop acknowledge 0b0..EDMA stop acknowledge is not asserted 0b1..EDMA stop acknowledge is asserted (EDMA is in STOP mode)

◆ IOMUXC_GPR_GPR4_EDMA_STOP_REQ

#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK)

EDMA_STOP_REQ - EDMA stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL [1/2]

#define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_MASK)

ENET_EVENT0IN_SEL - ENET ENET_1588_EVENT0_IN source select

◆ IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL [2/2]

#define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_MASK)

ENET_EVENT0IN_SEL - ENET ENET_1588_EVENT0_IN source select

◆ IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR [1/2]

#define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK)

ENET_REF_CLK_DIR - ENET_REF_CLK direction control

◆ IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR [2/2]

#define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK)

ENET_REF_CLK_DIR - ENET_REF_CLK direction control

◆ IOMUXC_GPR_GPR4_ENET_STOP_ACK

#define IOMUXC_GPR_GPR4_ENET_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK)

ENET_STOP_ACK - ENET stop acknowledge 0b0..ENET stop acknowledge is not asserted 0b1..ENET stop acknowledge is asserted

◆ IOMUXC_GPR_GPR4_ENET_STOP_REQ

#define IOMUXC_GPR_GPR4_ENET_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK)

ENET_STOP_REQ - ENET stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR4_ENET_TIME_SEL [1/2]

#define IOMUXC_GPR_GPR4_ENET_TIME_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_TIME_SEL_MASK)

ENET_TIME_SEL - ENET master timer source select

◆ IOMUXC_GPR_GPR4_ENET_TIME_SEL [2/2]

#define IOMUXC_GPR_GPR4_ENET_TIME_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_TIME_SEL_MASK)

ENET_TIME_SEL - ENET master timer source select

◆ IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL [1/2]

#define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK)

ENET_TX_CLK_SEL - ENET TX_CLK select

◆ IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL [2/2]

#define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK)

ENET_TX_CLK_SEL - ENET TX_CLK select

◆ IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK

#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK)

FLEXIO1_STOP_ACK - FLEXIO1 stop acknowledge 0b0..FLEXIO1 stop acknowledge is not asserted 0b1..FLEXIO1 stop acknowledge is asserted

◆ IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ

#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK)

FLEXIO1_STOP_REQ - FlexIO1 stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK

#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK)

FLEXIO2_STOP_ACK - FLEXIO2 stop acknowledge 0b0..FLEXIO2 stop acknowledge is not asserted 0b1..FLEXIO2 stop acknowledge is asserted (FLEXIO2 is in STOP mode)

◆ IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ

#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK)

FLEXIO2_STOP_REQ - FlexIO2 stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK

#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK)

FLEXSPI_STOP_ACK - FLEXSPI stop acknowledge 0b0..FLEXSPI stop acknowledge is not asserted 0b1..FLEXSPI stop acknowledge is asserted

◆ IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ

#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK)

FLEXSPI_STOP_REQ - FlexSPI stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR4_PIT_STOP_ACK

#define IOMUXC_GPR_GPR4_PIT_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK)

PIT_STOP_ACK - PIT stop acknowledge 0b0..PIT stop acknowledge is not asserted 0b1..PIT stop acknowledge is asserted

◆ IOMUXC_GPR_GPR4_PIT_STOP_REQ

#define IOMUXC_GPR_GPR4_PIT_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK)

PIT_STOP_REQ - PIT stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR4_SAI1_STOP_ACK

#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK)

SAI1_STOP_ACK - SAI1 stop acknowledge 0b0..SAI1 stop acknowledge is not asserted 0b1..SAI1 stop acknowledge is asserted

◆ IOMUXC_GPR_GPR4_SAI1_STOP_REQ

#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK)

SAI1_STOP_REQ - SAI1 stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR4_SAI2_STOP_ACK

#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK)

SAI2_STOP_ACK - SAI2 stop acknowledge 0b0..SAI2 stop acknowledge is not asserted 0b1..SAI2 stop acknowledge is asserted

◆ IOMUXC_GPR_GPR4_SAI2_STOP_REQ

#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK)

SAI2_STOP_REQ - SAI2 stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR4_SAI3_STOP_ACK

#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK)

SAI3_STOP_ACK - SAI3 stop acknowledge 0b0..SAI3 stop acknowledge is not asserted 0b1..SAI3 stop acknowledge is asserted

◆ IOMUXC_GPR_GPR4_SAI3_STOP_REQ

#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK)

SAI3_STOP_REQ - SAI3 stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR4_SEMC_STOP_ACK

#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK)

SEMC_STOP_ACK - SEMC stop acknowledge 0b0..SEMC stop acknowledge is not asserted 0b1..SEMC stop acknowledge is asserted

◆ IOMUXC_GPR_GPR4_SEMC_STOP_REQ

#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK)

SEMC_STOP_REQ - SEMC stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR4_TRNG_STOP_ACK

#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK)

TRNG_STOP_ACK - TRNG stop acknowledge 0b0..TRNG stop acknowledge is not asserted 0b1..TRNG stop acknowledge is asserted

◆ IOMUXC_GPR_GPR4_TRNG_STOP_REQ

#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK)

TRNG_STOP_REQ - TRNG stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR50_CAAM_IPS_MGR [1/2]

#define IOMUXC_GPR_GPR50_CAAM_IPS_MGR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_CAAM_IPS_MGR_SHIFT)) & IOMUXC_GPR_GPR50_CAAM_IPS_MGR_MASK)

CAAM_IPS_MGR - CAAM manager processor identifier

◆ IOMUXC_GPR_GPR50_CAAM_IPS_MGR [2/2]

#define IOMUXC_GPR_GPR50_CAAM_IPS_MGR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_CAAM_IPS_MGR_SHIFT)) & IOMUXC_GPR_GPR50_CAAM_IPS_MGR_MASK)

CAAM_IPS_MGR - CAAM manager processor identifier

◆ IOMUXC_GPR_GPR50_DWP [1/2]

#define IOMUXC_GPR_GPR50_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_DWP_SHIFT)) & IOMUXC_GPR_GPR50_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR50_DWP [2/2]

#define IOMUXC_GPR_GPR50_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_DWP_SHIFT)) & IOMUXC_GPR_GPR50_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR50_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR50_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR50_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR50_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR50_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR50_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR51_DWP [1/2]

#define IOMUXC_GPR_GPR51_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_DWP_SHIFT)) & IOMUXC_GPR_GPR51_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR51_DWP [2/2]

#define IOMUXC_GPR_GPR51_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_DWP_SHIFT)) & IOMUXC_GPR_GPR51_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR51_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR51_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR51_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR51_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR51_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR51_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR51_M7_NMI_CLEAR [1/2]

#define IOMUXC_GPR_GPR51_M7_NMI_CLEAR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_M7_NMI_CLEAR_SHIFT)) & IOMUXC_GPR_GPR51_M7_NMI_CLEAR_MASK)

M7_NMI_CLEAR - Clear CM7 NMI holding register

◆ IOMUXC_GPR_GPR51_M7_NMI_CLEAR [2/2]

#define IOMUXC_GPR_GPR51_M7_NMI_CLEAR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_M7_NMI_CLEAR_SHIFT)) & IOMUXC_GPR_GPR51_M7_NMI_CLEAR_MASK)

M7_NMI_CLEAR - Clear CM7 NMI holding register

◆ IOMUXC_GPR_GPR52_DWP [1/2]

#define IOMUXC_GPR_GPR52_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR52_DWP_SHIFT)) & IOMUXC_GPR_GPR52_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR52_DWP [2/2]

#define IOMUXC_GPR_GPR52_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR52_DWP_SHIFT)) & IOMUXC_GPR_GPR52_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR52_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR52_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR52_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR52_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR52_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR52_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR52_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR52_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR53_DWP [1/2]

#define IOMUXC_GPR_GPR53_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR53_DWP_SHIFT)) & IOMUXC_GPR_GPR53_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR53_DWP [2/2]

#define IOMUXC_GPR_GPR53_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR53_DWP_SHIFT)) & IOMUXC_GPR_GPR53_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR53_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR53_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR53_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR53_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR53_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR53_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR53_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR53_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR54_DWP [1/2]

#define IOMUXC_GPR_GPR54_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR54_DWP_SHIFT)) & IOMUXC_GPR_GPR54_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR54_DWP [2/2]

#define IOMUXC_GPR_GPR54_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR54_DWP_SHIFT)) & IOMUXC_GPR_GPR54_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR54_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR54_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR54_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR54_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR54_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR54_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR54_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR54_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR55_DWP [1/2]

#define IOMUXC_GPR_GPR55_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR55_DWP_SHIFT)) & IOMUXC_GPR_GPR55_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR55_DWP [2/2]

#define IOMUXC_GPR_GPR55_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR55_DWP_SHIFT)) & IOMUXC_GPR_GPR55_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR55_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR55_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR55_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR55_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR55_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR55_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR55_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR55_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR59_DWP [1/2]

#define IOMUXC_GPR_GPR59_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_DWP_SHIFT)) & IOMUXC_GPR_GPR59_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR59_DWP [2/2]

#define IOMUXC_GPR_GPR59_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_DWP_SHIFT)) & IOMUXC_GPR_GPR59_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR59_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR59_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR59_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR59_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR59_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR59_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN [1/2]

#define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_MASK)

MIPI_CSI_AUTO_PD_EN - Powers down inactive lanes reported by CSI2X_CFG_NUM_LANES.

◆ IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN [2/2]

#define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_MASK)

MIPI_CSI_AUTO_PD_EN - Powers down inactive lanes reported by CSI2X_CFG_NUM_LANES.

◆ IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE [1/2]

#define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_MASK)

MIPI_CSI_CONT_CLK_MODE - Enables the slave clock lane feature to maintain HS reception state during continuous clock mode operation, despite line glitches.

◆ IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE [2/2]

#define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_MASK)

MIPI_CSI_CONT_CLK_MODE - Enables the slave clock lane feature to maintain HS reception state during continuous clock mode operation, despite line glitches.

◆ IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN [1/2]

#define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_MASK)

MIPI_CSI_DDRCLK_EN - When high, enables received DDR clock on CLK_DRXHS

◆ IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN [2/2]

#define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_MASK)

MIPI_CSI_DDRCLK_EN - When high, enables received DDR clock on CLK_DRXHS

◆ IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX [1/2]

#define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK)

MIPI_CSI_PD_RX - Power Down input for MIPI CSI PHY.

◆ IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX [2/2]

#define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK)

MIPI_CSI_PD_RX - Power Down input for MIPI CSI PHY.

◆ IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE [1/2]

#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK)

MIPI_CSI_RX_ENABLE - Assert to enable MIPI CSI Receive Enable

◆ IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE [2/2]

#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK)

MIPI_CSI_RX_ENABLE - Assert to enable MIPI CSI Receive Enable

◆ IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL [1/2]

#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_MASK)

MIPI_CSI_RX_RCAL - MIPI CSI PHY on-chip termination control bits

◆ IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL [2/2]

#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_MASK)

MIPI_CSI_RX_RCAL - MIPI CSI PHY on-chip termination control bits

◆ IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP [1/2]

#define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_MASK)

MIPI_CSI_RXCDRP - Programming bits that adjust the threshold voltage of LP-CD, default setting 2'b01 0b00..344mV 0b01..325mV (Default) 0b10..307mV 0b11..Invalid

◆ IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP [2/2]

#define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_MASK)

MIPI_CSI_RXCDRP - Programming bits that adjust the threshold voltage of LP-CD, default setting 2'b01 0b00..344mV 0b01..325mV (Default) 0b10..307mV 0b11..Invalid

◆ IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP [1/2]

#define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_MASK)

MIPI_CSI_RXLPRP - Programming bits that adjust the threshold voltage of LP-RX, default setting 2'b01

◆ IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP [2/2]

#define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_MASK)

MIPI_CSI_RXLPRP - Programming bits that adjust the threshold voltage of LP-RX, default setting 2'b01

◆ IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE [1/2]

#define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK)

MIPI_CSI_S_PRG_RXHS_SETTLE - Bits used to program T_HS_SETTLE.

◆ IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE [2/2]

#define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK)

MIPI_CSI_S_PRG_RXHS_SETTLE - Bits used to program T_HS_SETTLE.

◆ IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N [1/2]

#define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK)

MIPI_CSI_SOFT_RST_N - MIPI CSI APB clock domain and User interface clock domain software reset bit 0b0..Assert reset 0b1..De-assert reset

◆ IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N [2/2]

#define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK)

MIPI_CSI_SOFT_RST_N - MIPI CSI APB clock domain and User interface clock domain software reset bit 0b0..Assert reset 0b1..De-assert reset

◆ IOMUXC_GPR_GPR5_DWP [1/2]

#define IOMUXC_GPR_GPR5_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_DWP_SHIFT)) & IOMUXC_GPR_GPR5_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR5_DWP [2/2]

#define IOMUXC_GPR_GPR5_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_DWP_SHIFT)) & IOMUXC_GPR_GPR5_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR5_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR5_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR5_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR5_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR5_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR5_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL [1/2]

#define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_MASK)

ENET1G_EVENT0IN_SEL - ENET1G ENET_1588_EVENT0_IN source select

◆ IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL [2/2]

#define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_MASK)

ENET1G_EVENT0IN_SEL - ENET1G ENET_1588_EVENT0_IN source select

◆ IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR [1/2]

#define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK)

ENET1G_REF_CLK_DIR - ENET1G_REF_CLK direction control

◆ IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR [2/2]

#define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK)

ENET1G_REF_CLK_DIR - ENET1G_REF_CLK direction control

◆ IOMUXC_GPR_GPR5_ENET1G_RGMII_EN [1/2]

#define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK)

ENET1G_RGMII_EN - ENET1G RGMII TX clock output enable

◆ IOMUXC_GPR_GPR5_ENET1G_RGMII_EN [2/2]

#define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK)

ENET1G_RGMII_EN - ENET1G RGMII TX clock output enable

◆ IOMUXC_GPR_GPR5_ENET1G_TIME_SEL [1/2]

#define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_MASK)

ENET1G_TIME_SEL - ENET1G master timer source select

◆ IOMUXC_GPR_GPR5_ENET1G_TIME_SEL [2/2]

#define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_MASK)

ENET1G_TIME_SEL - ENET1G master timer source select

◆ IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL [1/2]

#define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK)

ENET1G_TX_CLK_SEL - ENET1G TX_CLK select

◆ IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL [2/2]

#define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK)

ENET1G_TX_CLK_SEL - ENET1G TX_CLK select

◆ IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL

#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK)

ENET_EVENT3IN_SEL 0b0..event3 source input from pad 0b1..event3 source input from gpt2.ipp_do_cmpout1

◆ IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL

#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK)

GPT2_CAPIN1_SEL 0b0..source from pad 0b1..source from enet1.ipp_do_mac0_timer[3]

◆ IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1

#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK)

VREF_1M_CLK_GPT1 0b0..GPT1 ipg_clk_highfreq driven by IPG_PERCLK. IPG_PERCLK is derived from either BUS clock or OSC_24M clock. See CCM chapter for more information 0b1..GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock. Anatop 1M clock is derived from the OSC_RC_24M clock. It has two versions: corrected by 32k clock or un-corrected. See the XTALOSC24M_OSC_CONFIG2 register for more details

◆ IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2

#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK)

VREF_1M_CLK_GPT2 0b0..GPT2 ipg_clk_highfreq driven by IPG_PERCLK. IPG_PERCLK is derived from either BUS clock or OSC_24M clock. See CCM chapter for more information 0b1..GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock. Anatop 1M clock is derived from the OSC_RC_24M clock. It has two versions: corrected by 32k clock or un-corrected. See the XTALOSC24M_OSC_CONFIG2 register for more details

◆ IOMUXC_GPR_GPR5_WDOG1_MASK

#define IOMUXC_GPR_GPR5_WDOG1_MASK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK)

WDOG1_MASK 0b0..WDOG1 Timeout behaves normally 0b1..WDOG1 Timeout is masked

◆ IOMUXC_GPR_GPR5_WDOG2_MASK

#define IOMUXC_GPR_GPR5_WDOG2_MASK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK)

WDOG2_MASK 0b0..WDOG2 Timeout behaves normally 0b1..WDOG2 Timeout is masked

◆ IOMUXC_GPR_GPR62_DWP [1/2]

#define IOMUXC_GPR_GPR62_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_DWP_SHIFT)) & IOMUXC_GPR_GPR62_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR62_DWP [2/2]

#define IOMUXC_GPR_GPR62_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_DWP_SHIFT)) & IOMUXC_GPR_GPR62_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR62_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR62_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR62_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR62_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR62_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR62_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N [1/2]

#define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK)

MIPI_DSI_BYTE_SOFT_RESET_N - MIPI DSI Byte clock domain software reset bit 0b0..Assert reset 0b1..De-assert reset

◆ IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N [2/2]

#define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK)

MIPI_DSI_BYTE_SOFT_RESET_N - MIPI DSI Byte clock domain software reset bit 0b0..Assert reset 0b1..De-assert reset

◆ IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM [1/2]

#define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_MASK)

MIPI_DSI_CLK_TM - MIPI DSI Clock Lane triming bits

◆ IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM [2/2]

#define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_MASK)

MIPI_DSI_CLK_TM - MIPI DSI Clock Lane triming bits

◆ IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM [1/2]

#define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_MASK)

MIPI_DSI_D0_TM - MIPI DSI Data Lane 0 triming bits

◆ IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM [2/2]

#define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_MASK)

MIPI_DSI_D0_TM - MIPI DSI Data Lane 0 triming bits

◆ IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM [1/2]

#define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_MASK)

MIPI_DSI_D1_TM - MIPI DSI Data Lane 1 triming bits

◆ IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM [2/2]

#define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_MASK)

MIPI_DSI_D1_TM - MIPI DSI Data Lane 1 triming bits

◆ IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N [1/2]

#define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK)

MIPI_DSI_DPI_SOFT_RESET_N - MIPI DSI Pixel clock domain software reset bit 0b0..Assert reset 0b1..De-assert reset

◆ IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N [2/2]

#define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK)

MIPI_DSI_DPI_SOFT_RESET_N - MIPI DSI Pixel clock domain software reset bit 0b0..Assert reset 0b1..De-assert reset

◆ IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N [1/2]

#define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK)

MIPI_DSI_ESC_SOFT_RESET_N - MIPI DSI Escape clock domain software reset bit 0b0..Assert reset 0b1..De-assert reset

◆ IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N [2/2]

#define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK)

MIPI_DSI_ESC_SOFT_RESET_N - MIPI DSI Escape clock domain software reset bit 0b0..Assert reset 0b1..De-assert reset

◆ IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N [1/2]

#define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK)

MIPI_DSI_PCLK_SOFT_RESET_N - MIPI DSI APB clock domain software reset bit 0b0..Assert reset 0b1..De-assert reset

◆ IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N [2/2]

#define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK)

MIPI_DSI_PCLK_SOFT_RESET_N - MIPI DSI APB clock domain software reset bit 0b0..Assert reset 0b1..De-assert reset

◆ IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL [1/2]

#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_MASK)

MIPI_DSI_TX_RCAL - MIPI DSI PHY on-chip termination control bits

◆ IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL [2/2]

#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_MASK)

MIPI_DSI_TX_RCAL - MIPI DSI PHY on-chip termination control bits

◆ IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE [1/2]

#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_MASK)

MIPI_DSI_TX_ULPS_ENABLE - DSI transmit ULPS mode enable

◆ IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE [2/2]

#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_MASK)

MIPI_DSI_TX_ULPS_ENABLE - DSI transmit ULPS mode enable

◆ IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE [1/2]

#define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_MASK)

MIPI_DSI_TX_ULPS_ACTIVE - DSI transmit ULPS mode active flag

◆ IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE [2/2]

#define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_MASK)

MIPI_DSI_TX_ULPS_ACTIVE - DSI transmit ULPS mode active flag

◆ IOMUXC_GPR_GPR64_DWP [1/2]

#define IOMUXC_GPR_GPR64_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_DWP_SHIFT)) & IOMUXC_GPR_GPR64_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR64_DWP [2/2]

#define IOMUXC_GPR_GPR64_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_DWP_SHIFT)) & IOMUXC_GPR_GPR64_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR64_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR64_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR64_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR64_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR64_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR64_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN [1/2]

#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_MASK)

GPIO_DISP1_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell

◆ IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN [2/2]

#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_MASK)

GPIO_DISP1_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell

◆ IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK [1/2]

#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_MASK)

GPIO_DISP1_COMPOK - GPIO_DISP_B1 IO bank compensation OK flag

◆ IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK [2/2]

#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_MASK)

GPIO_DISP1_COMPOK - GPIO_DISP_B1 IO bank compensation OK flag

◆ IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ [1/2]

#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_MASK)

GPIO_DISP1_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell

◆ IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ [2/2]

#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_MASK)

GPIO_DISP1_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell

◆ IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN [1/2]

#define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_MASK)

GPIO_DISP1_FASTFRZ_EN - Compensation code fast freeze

◆ IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN [2/2]

#define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_MASK)

GPIO_DISP1_FASTFRZ_EN - Compensation code fast freeze

◆ IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE [1/2]

#define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_MASK)

GPIO_DISP1_FREEZE - Compensation code freeze

◆ IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE [2/2]

#define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_MASK)

GPIO_DISP1_FREEZE - Compensation code freeze

◆ IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC [1/2]

#define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_MASK)

GPIO_DISP1_NASRC - GPIO_DISP_B1 IO bank compensation codes

◆ IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC [2/2]

#define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_MASK)

GPIO_DISP1_NASRC - GPIO_DISP_B1 IO bank compensation codes

◆ IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN [1/2]

#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_MASK)

GPIO_DISP1_RASRCN - GPIO_DISP_B1 IO bank's 4-bit NMOS compensation codes from core

◆ IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN [2/2]

#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_MASK)

GPIO_DISP1_RASRCN - GPIO_DISP_B1 IO bank's 4-bit NMOS compensation codes from core

◆ IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP [1/2]

#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_MASK)

GPIO_DISP1_RASRCP - GPIO_DISP_B1 IO bank's 4-bit PMOS compensation codes from core

◆ IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP [2/2]

#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_MASK)

GPIO_DISP1_RASRCP - GPIO_DISP_B1 IO bank's 4-bit PMOS compensation codes from core

◆ IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP [1/2]

#define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_MASK)

GPIO_DISP1_REFGEN_SLEEP - GPIO_DISP_B1 IO bank reference voltage generator cell sleep enable

◆ IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP [2/2]

#define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_MASK)

GPIO_DISP1_REFGEN_SLEEP - GPIO_DISP_B1 IO bank reference voltage generator cell sleep enable

◆ IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC [1/2]

#define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_MASK)

GPIO_DISP1_SELECT_NASRC - GPIO_DISP1_NASRC selection

◆ IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC [2/2]

#define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_MASK)

GPIO_DISP1_SELECT_NASRC - GPIO_DISP1_NASRC selection

◆ IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH [1/2]

#define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_MASK)

GPIO_DISP1_SUPLYDET_LATCH - GPIO_DISP_B1 IO bank power supply mode latch enable

◆ IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH [2/2]

#define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_MASK)

GPIO_DISP1_SUPLYDET_LATCH - GPIO_DISP_B1 IO bank power supply mode latch enable

◆ IOMUXC_GPR_GPR65_DWP [1/2]

#define IOMUXC_GPR_GPR65_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_DWP_SHIFT)) & IOMUXC_GPR_GPR65_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR65_DWP [2/2]

#define IOMUXC_GPR_GPR65_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_DWP_SHIFT)) & IOMUXC_GPR_GPR65_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR65_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR65_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR65_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR65_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR65_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR65_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN [1/2]

#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_MASK)

GPIO_EMC1_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell

◆ IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN [2/2]

#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_MASK)

GPIO_EMC1_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell

◆ IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK [1/2]

#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_MASK)

GPIO_EMC1_COMPOK - GPIO_EMC_B1 IO bank compensation OK flag

◆ IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK [2/2]

#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_MASK)

GPIO_EMC1_COMPOK - GPIO_EMC_B1 IO bank compensation OK flag

◆ IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ [1/2]

#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_MASK)

GPIO_EMC1_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell

◆ IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ [2/2]

#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_MASK)

GPIO_EMC1_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell

◆ IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN [1/2]

#define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_MASK)

GPIO_EMC1_FASTFRZ_EN - Compensation code fast freeze

◆ IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN [2/2]

#define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_MASK)

GPIO_EMC1_FASTFRZ_EN - Compensation code fast freeze

◆ IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE [1/2]

#define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_MASK)

GPIO_EMC1_FREEZE - Compensation code freeze

◆ IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE [2/2]

#define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_MASK)

GPIO_EMC1_FREEZE - Compensation code freeze

◆ IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC [1/2]

#define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_MASK)

GPIO_EMC1_NASRC - GPIO_EMC_B1 IO bank compensation codes

◆ IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC [2/2]

#define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_MASK)

GPIO_EMC1_NASRC - GPIO_EMC_B1 IO bank compensation codes

◆ IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN [1/2]

#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_MASK)

GPIO_EMC1_RASRCN - GPIO_EMC_B1 IO bank's 4-bit NMOS compensation codes from core

◆ IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN [2/2]

#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_MASK)

GPIO_EMC1_RASRCN - GPIO_EMC_B1 IO bank's 4-bit NMOS compensation codes from core

◆ IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP [1/2]

#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_MASK)

GPIO_EMC1_RASRCP - GPIO_EMC_B1 IO bank's 4-bit PMOS compensation codes from core

◆ IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP [2/2]

#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_MASK)

GPIO_EMC1_RASRCP - GPIO_EMC_B1 IO bank's 4-bit PMOS compensation codes from core

◆ IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP [1/2]

#define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_MASK)

GPIO_EMC1_REFGEN_SLEEP - GPIO_EMC_B1 IO bank reference voltage generator cell sleep enable

◆ IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP [2/2]

#define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_MASK)

GPIO_EMC1_REFGEN_SLEEP - GPIO_EMC_B1 IO bank reference voltage generator cell sleep enable

◆ IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC [1/2]

#define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_MASK)

GPIO_EMC1_SELECT_NASRC - GPIO_EMC1_NASRC selection

◆ IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC [2/2]

#define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_MASK)

GPIO_EMC1_SELECT_NASRC - GPIO_EMC1_NASRC selection

◆ IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH [1/2]

#define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_MASK)

GPIO_EMC1_SUPLYDET_LATCH - GPIO_EMC_B1 IO bank power supply mode latch enable

◆ IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH [2/2]

#define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_MASK)

GPIO_EMC1_SUPLYDET_LATCH - GPIO_EMC_B1 IO bank power supply mode latch enable

◆ IOMUXC_GPR_GPR66_DWP [1/2]

#define IOMUXC_GPR_GPR66_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_DWP_SHIFT)) & IOMUXC_GPR_GPR66_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR66_DWP [2/2]

#define IOMUXC_GPR_GPR66_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_DWP_SHIFT)) & IOMUXC_GPR_GPR66_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR66_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR66_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR66_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR66_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR66_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR66_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN [1/2]

#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_MASK)

GPIO_EMC2_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell

◆ IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN [2/2]

#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_MASK)

GPIO_EMC2_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell

◆ IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK [1/2]

#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_MASK)

GPIO_EMC2_COMPOK - GPIO_EMC_B2 IO bank compensation OK flag

◆ IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK [2/2]

#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_MASK)

GPIO_EMC2_COMPOK - GPIO_EMC_B2 IO bank compensation OK flag

◆ IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ [1/2]

#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_MASK)

GPIO_EMC2_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell

◆ IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ [2/2]

#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_MASK)

GPIO_EMC2_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell

◆ IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN [1/2]

#define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_MASK)

GPIO_EMC2_FASTFRZ_EN - Compensation code fast freeze

◆ IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN [2/2]

#define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_MASK)

GPIO_EMC2_FASTFRZ_EN - Compensation code fast freeze

◆ IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE [1/2]

#define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_MASK)

GPIO_EMC2_FREEZE - Compensation code freeze

◆ IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE [2/2]

#define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_MASK)

GPIO_EMC2_FREEZE - Compensation code freeze

◆ IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC [1/2]

#define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_MASK)

GPIO_EMC2_NASRC - GPIO_EMC_B2 IO bank compensation codes

◆ IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC [2/2]

#define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_MASK)

GPIO_EMC2_NASRC - GPIO_EMC_B2 IO bank compensation codes

◆ IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN [1/2]

#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_MASK)

GPIO_EMC2_RASRCN - GPIO_EMC_B2 IO bank's 4-bit NMOS compensation codes from core

◆ IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN [2/2]

#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_MASK)

GPIO_EMC2_RASRCN - GPIO_EMC_B2 IO bank's 4-bit NMOS compensation codes from core

◆ IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP [1/2]

#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_MASK)

GPIO_EMC2_RASRCP - GPIO_EMC_B2 IO bank's 4-bit PMOS compensation codes from core

◆ IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP [2/2]

#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_MASK)

GPIO_EMC2_RASRCP - GPIO_EMC_B2 IO bank's 4-bit PMOS compensation codes from core

◆ IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP [1/2]

#define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_MASK)

GPIO_EMC2_REFGEN_SLEEP - GPIO_EMC_B2 IO bank reference voltage generator cell sleep enable

◆ IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP [2/2]

#define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_MASK)

GPIO_EMC2_REFGEN_SLEEP - GPIO_EMC_B2 IO bank reference voltage generator cell sleep enable

◆ IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC [1/2]

#define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_MASK)

GPIO_EMC2_SELECT_NASRC - GPIO_EMC2_NASRC selection

◆ IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC [2/2]

#define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_MASK)

GPIO_EMC2_SELECT_NASRC - GPIO_EMC2_NASRC selection

◆ IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH [1/2]

#define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_MASK)

GPIO_EMC2_SUPLYDET_LATCH - GPIO_EMC_B2 IO bank power supply mode latch enable

◆ IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH [2/2]

#define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_MASK)

GPIO_EMC2_SUPLYDET_LATCH - GPIO_EMC_B2 IO bank power supply mode latch enable

◆ IOMUXC_GPR_GPR67_DWP [1/2]

#define IOMUXC_GPR_GPR67_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_DWP_SHIFT)) & IOMUXC_GPR_GPR67_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR67_DWP [2/2]

#define IOMUXC_GPR_GPR67_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_DWP_SHIFT)) & IOMUXC_GPR_GPR67_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR67_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR67_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR67_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR67_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR67_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR67_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN [1/2]

#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_MASK)

GPIO_SD1_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell

◆ IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN [2/2]

#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_MASK)

GPIO_SD1_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell

◆ IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK [1/2]

#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_MASK)

GPIO_SD1_COMPOK - GPIO_SD_B1 IO bank compensation OK flag

◆ IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK [2/2]

#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_MASK)

GPIO_SD1_COMPOK - GPIO_SD_B1 IO bank compensation OK flag

◆ IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ [1/2]

#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_MASK)

GPIO_SD1_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell

◆ IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ [2/2]

#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_MASK)

GPIO_SD1_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell

◆ IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN [1/2]

#define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_MASK)

GPIO_SD1_FASTFRZ_EN - Compensation code fast freeze

◆ IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN [2/2]

#define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_MASK)

GPIO_SD1_FASTFRZ_EN - Compensation code fast freeze

◆ IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE [1/2]

#define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_MASK)

GPIO_SD1_FREEZE - Compensation code freeze

◆ IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE [2/2]

#define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_MASK)

GPIO_SD1_FREEZE - Compensation code freeze

◆ IOMUXC_GPR_GPR67_GPIO_SD1_NASRC [1/2]

#define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_MASK)

GPIO_SD1_NASRC - GPIO_SD_B1 IO bank compensation codes

◆ IOMUXC_GPR_GPR67_GPIO_SD1_NASRC [2/2]

#define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_MASK)

GPIO_SD1_NASRC - GPIO_SD_B1 IO bank compensation codes

◆ IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN [1/2]

#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_MASK)

GPIO_SD1_RASRCN - GPIO_SD_B1 IO bank's 4-bit NMOS compensation codes from core

◆ IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN [2/2]

#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_MASK)

GPIO_SD1_RASRCN - GPIO_SD_B1 IO bank's 4-bit NMOS compensation codes from core

◆ IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP [1/2]

#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_MASK)

GPIO_SD1_RASRCP - GPIO_SD_B1 IO bank's 4-bit PMOS compensation codes from core

◆ IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP [2/2]

#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_MASK)

GPIO_SD1_RASRCP - GPIO_SD_B1 IO bank's 4-bit PMOS compensation codes from core

◆ IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP [1/2]

#define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_MASK)

GPIO_SD1_REFGEN_SLEEP - GPIO_SD_B1 IO bank reference voltage generator cell sleep enable

◆ IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP [2/2]

#define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_MASK)

GPIO_SD1_REFGEN_SLEEP - GPIO_SD_B1 IO bank reference voltage generator cell sleep enable

◆ IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC [1/2]

#define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_MASK)

GPIO_SD1_SELECT_NASRC - GPIO_SD1_NASRC selection

◆ IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC [2/2]

#define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_MASK)

GPIO_SD1_SELECT_NASRC - GPIO_SD1_NASRC selection

◆ IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH [1/2]

#define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_MASK)

GPIO_SD1_SUPLYDET_LATCH - GPIO_SD_B1 IO bank power supply mode latch enable

◆ IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH [2/2]

#define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_MASK)

GPIO_SD1_SUPLYDET_LATCH - GPIO_SD_B1 IO bank power supply mode latch enable

◆ IOMUXC_GPR_GPR68_DWP [1/2]

#define IOMUXC_GPR_GPR68_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_DWP_SHIFT)) & IOMUXC_GPR_GPR68_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR68_DWP [2/2]

#define IOMUXC_GPR_GPR68_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_DWP_SHIFT)) & IOMUXC_GPR_GPR68_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR68_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR68_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR68_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR68_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR68_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR68_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN [1/2]

#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_MASK)

GPIO_SD2_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell

◆ IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN [2/2]

#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_MASK)

GPIO_SD2_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell

◆ IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK [1/2]

#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_MASK)

GPIO_SD2_COMPOK - GPIO_SD_B2 IO bank compensation OK flag

◆ IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK [2/2]

#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_MASK)

GPIO_SD2_COMPOK - GPIO_SD_B2 IO bank compensation OK flag

◆ IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ [1/2]

#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_MASK)

GPIO_SD2_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell

◆ IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ [2/2]

#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_MASK)

GPIO_SD2_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell

◆ IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN [1/2]

#define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_MASK)

GPIO_SD2_FASTFRZ_EN - Compensation code fast freeze

◆ IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN [2/2]

#define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_MASK)

GPIO_SD2_FASTFRZ_EN - Compensation code fast freeze

◆ IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE [1/2]

#define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_MASK)

GPIO_SD2_FREEZE - Compensation code freeze

◆ IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE [2/2]

#define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_MASK)

GPIO_SD2_FREEZE - Compensation code freeze

◆ IOMUXC_GPR_GPR68_GPIO_SD2_NASRC [1/2]

#define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_MASK)

GPIO_SD2_NASRC - GPIO_SD_B2 IO bank compensation codes

◆ IOMUXC_GPR_GPR68_GPIO_SD2_NASRC [2/2]

#define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_MASK)

GPIO_SD2_NASRC - GPIO_SD_B2 IO bank compensation codes

◆ IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN [1/2]

#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_MASK)

GPIO_SD2_RASRCN - GPIO_SD_B2 IO bank's 4-bit NMOS compensation codes from core

◆ IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN [2/2]

#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_MASK)

GPIO_SD2_RASRCN - GPIO_SD_B2 IO bank's 4-bit NMOS compensation codes from core

◆ IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP [1/2]

#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_MASK)

GPIO_SD2_RASRCP - GPIO_SD_B2 IO bank's 4-bit PMOS compensation codes from core

◆ IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP [2/2]

#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_MASK)

GPIO_SD2_RASRCP - GPIO_SD_B2 IO bank's 4-bit PMOS compensation codes from core

◆ IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP [1/2]

#define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_MASK)

GPIO_SD2_REFGEN_SLEEP - GPIO_SD_B2 IO bank reference voltage generator cell sleep enable

◆ IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP [2/2]

#define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_MASK)

GPIO_SD2_REFGEN_SLEEP - GPIO_SD_B2 IO bank reference voltage generator cell sleep enable

◆ IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC [1/2]

#define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_MASK)

GPIO_SD2_SELECT_NASRC - GPIO_SD2_NASRC selection

◆ IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC [2/2]

#define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_MASK)

GPIO_SD2_SELECT_NASRC - GPIO_SD2_NASRC selection

◆ IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH [1/2]

#define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_MASK)

GPIO_SD2_SUPLYDET_LATCH - GPIO_SD_B2 IO bank power supply mode latch enable

◆ IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH [2/2]

#define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_MASK)

GPIO_SD2_SUPLYDET_LATCH - GPIO_SD_B2 IO bank power supply mode latch enable

◆ IOMUXC_GPR_GPR69_DWP [1/2]

#define IOMUXC_GPR_GPR69_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_DWP_SHIFT)) & IOMUXC_GPR_GPR69_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR69_DWP [2/2]

#define IOMUXC_GPR_GPR69_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_DWP_SHIFT)) & IOMUXC_GPR_GPR69_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR69_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR69_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR69_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR69_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR69_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR69_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE [1/2]

#define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_MASK)

GPIO_AD0_HIGH_RANGE - GPIO_AD IO bank supply voltage range selection for GPIO_AD_00 to GPIO_AD_17

◆ IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE [2/2]

#define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_MASK)

GPIO_AD0_HIGH_RANGE - GPIO_AD IO bank supply voltage range selection for GPIO_AD_00 to GPIO_AD_17

◆ IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE [1/2]

#define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_MASK)

GPIO_AD0_LOW_RANGE - GPIO_AD IO bank supply voltage range selection for GPIO_AD_00 to GPIO_AD_17

◆ IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE [2/2]

#define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_MASK)

GPIO_AD0_LOW_RANGE - GPIO_AD IO bank supply voltage range selection for GPIO_AD_00 to GPIO_AD_17

◆ IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE [1/2]

#define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_MASK)

GPIO_AD1_HIGH_RANGE - GPIO_LPSR IO bank supply voltage range selection for GPIO_AD_18 to GPIO_AD_35

◆ IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE [2/2]

#define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_MASK)

GPIO_AD1_HIGH_RANGE - GPIO_LPSR IO bank supply voltage range selection for GPIO_AD_18 to GPIO_AD_35

◆ IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE [1/2]

#define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_MASK)

GPIO_AD1_LOW_RANGE - GPIO_LPSR IO bank supply voltage range selection for GPIO_AD_18 to GPIO_AD_35

◆ IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE [2/2]

#define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_MASK)

GPIO_AD1_LOW_RANGE - GPIO_LPSR IO bank supply voltage range selection for GPIO_AD_18 to GPIO_AD_35

◆ IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE [1/2]

#define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_MASK)

GPIO_DISP2_HIGH_RANGE - GPIO_DISP_B2 IO bank supply voltage range selection

◆ IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE [2/2]

#define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_MASK)

GPIO_DISP2_HIGH_RANGE - GPIO_DISP_B2 IO bank supply voltage range selection

◆ IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE [1/2]

#define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_MASK)

GPIO_DISP2_LOW_RANGE - GPIO_DISP_B2 IO bank supply voltage range selection

◆ IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE [2/2]

#define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_MASK)

GPIO_DISP2_LOW_RANGE - GPIO_DISP_B2 IO bank supply voltage range selection

◆ IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP [1/2]

#define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_MASK)

SUPLYDET_DISP1_SLEEP - GPIO_DISP_B1 IO bank supply voltage detector sleep mode enable

◆ IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP [2/2]

#define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_MASK)

SUPLYDET_DISP1_SLEEP - GPIO_DISP_B1 IO bank supply voltage detector sleep mode enable

◆ IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP [1/2]

#define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_MASK)

SUPLYDET_EMC1_SLEEP - GPIO_EMC_B1 IO bank supply voltage detector sleep mode enable

◆ IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP [2/2]

#define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_MASK)

SUPLYDET_EMC1_SLEEP - GPIO_EMC_B1 IO bank supply voltage detector sleep mode enable

◆ IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP [1/2]

#define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_MASK)

SUPLYDET_EMC2_SLEEP - GPIO_EMC_B2 IO bank supply voltage detector sleep mode enable

◆ IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP [2/2]

#define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_MASK)

SUPLYDET_EMC2_SLEEP - GPIO_EMC_B2 IO bank supply voltage detector sleep mode enable

◆ IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP [1/2]

#define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_MASK)

SUPLYDET_SD1_SLEEP - GPIO_SD_B1 IO bank supply voltage detector sleep mode enable

◆ IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP [2/2]

#define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_MASK)

SUPLYDET_SD1_SLEEP - GPIO_SD_B1 IO bank supply voltage detector sleep mode enable

◆ IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP [1/2]

#define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_MASK)

SUPLYDET_SD2_SLEEP - GPIO_SD_B2 IO bank supply voltage detector sleep mode enable

◆ IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP [2/2]

#define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_MASK)

SUPLYDET_SD2_SLEEP - GPIO_SD_B2 IO bank supply voltage detector sleep mode enable

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK)

IOMUXC_XBAR_DIR_SEL_10 0b0..XBAR1_INOUT as input 0b1..XBAR1_INOUT as output

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK)

IOMUXC_XBAR_DIR_SEL_11 0b0..XBAR1_INOUT as input 0b1..XBAR1_INOUT as output

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK)

IOMUXC_XBAR_DIR_SEL_12 0b0..XBAR1_INOUT as input 0b1..XBAR1_INOUT as output

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK)

IOMUXC_XBAR_DIR_SEL_13 0b0..XBAR1_INOUT as input 0b1..XBAR1_INOUT as output

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK)

IOMUXC_XBAR_DIR_SEL_14 0b0..XBAR1_INOUT as input 0b1..XBAR1_INOUT as output

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK)

IOMUXC_XBAR_DIR_SEL_15 0b0..XBAR1_INOUT as input 0b1..XBAR1_INOUT as output

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK)

IOMUXC_XBAR_DIR_SEL_16 0b0..XBAR1_INOUT as input 0b1..XBAR1_INOUT as output

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK)

IOMUXC_XBAR_DIR_SEL_17 0b0..XBAR1_INOUT as input 0b1..XBAR1_INOUT as output

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK)

IOMUXC_XBAR_DIR_SEL_18 0b0..XBAR1_INOUT as input 0b1..XBAR1_INOUT as output

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK)

IOMUXC_XBAR_DIR_SEL_19 0b0..XBAR1_INOUT as input 0b1..XBAR1_INOUT as output

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK)

IOMUXC_XBAR_DIR_SEL_4 0b0..XBAR1_INOUT as input 0b1..XBAR1_INOUT as output

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK)

IOMUXC_XBAR_DIR_SEL_5 0b0..XBAR1_INOUT as input 0b1..XBAR1_INOUT as output

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK)

IOMUXC_XBAR_DIR_SEL_6 0b0..XBAR1_INOUT as input 0b1..XBAR1_INOUT as output

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK)

IOMUXC_XBAR_DIR_SEL_7 0b0..XBAR1_INOUT as input 0b1..XBAR1_INOUT as output

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK)

IOMUXC_XBAR_DIR_SEL_8 0b0..XBAR1_INOUT as input 0b1..XBAR1_INOUT as output

◆ IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9

#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK)

IOMUXC_XBAR_DIR_SEL_9 0b0..XBAR1_INOUT as input 0b1..XBAR1_INOUT as output

◆ IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK)

QTIMER1_TRM0_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

◆ IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK)

QTIMER1_TRM1_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

◆ IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK)

QTIMER1_TRM2_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

◆ IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK)

QTIMER1_TRM3_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

◆ IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK)

QTIMER2_TRM0_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

◆ IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK)

QTIMER2_TRM1_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

◆ IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK)

QTIMER2_TRM2_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

◆ IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK)

QTIMER2_TRM3_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

◆ IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK)

QTIMER3_TRM0_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

◆ IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK)

QTIMER3_TRM1_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

◆ IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK)

QTIMER3_TRM2_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

◆ IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK)

QTIMER3_TRM3_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

◆ IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK)

QTIMER4_TRM0_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

◆ IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK)

QTIMER4_TRM1_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

◆ IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK)

QTIMER4_TRM2_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

◆ IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL

#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK)

QTIMER4_TRM3_INPUT_SEL 0b0..input from IOMUX 0b1..input from XBAR

◆ IOMUXC_GPR_GPR70_ADC1_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_MASK)

ADC1_IPG_DOZE - ADC1 doze mode

◆ IOMUXC_GPR_GPR70_ADC1_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_MASK)

ADC1_IPG_DOZE - ADC1 doze mode

◆ IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_MASK)

ADC1_IPG_STOP_MODE - ADC1 stop mode selection, cannot change when ADC1_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_MASK)

ADC1_IPG_STOP_MODE - ADC1 stop mode selection, cannot change when ADC1_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR70_ADC1_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR70_ADC1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_STOP_REQ_MASK)

ADC1_STOP_REQ - ADC1 stop request

◆ IOMUXC_GPR_GPR70_ADC1_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR70_ADC1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_STOP_REQ_MASK)

ADC1_STOP_REQ - ADC1 stop request

◆ IOMUXC_GPR_GPR70_ADC2_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_MASK)

ADC2_IPG_DOZE - ADC2 doze mode

◆ IOMUXC_GPR_GPR70_ADC2_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_MASK)

ADC2_IPG_DOZE - ADC2 doze mode

◆ IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_MASK)

ADC2_IPG_STOP_MODE - ADC2 stop mode selection, cannot change when ADC2_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_MASK)

ADC2_IPG_STOP_MODE - ADC2 stop mode selection, cannot change when ADC2_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR70_ADC2_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR70_ADC2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_STOP_REQ_MASK)

ADC2_STOP_REQ - ADC2 stop request

◆ IOMUXC_GPR_GPR70_ADC2_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR70_ADC2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_STOP_REQ_MASK)

ADC2_STOP_REQ - ADC2 stop request

◆ IOMUXC_GPR_GPR70_CAAM_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_MASK)

CAAM_IPG_DOZE - CAN3 doze mode

◆ IOMUXC_GPR_GPR70_CAAM_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_MASK)

CAAM_IPG_DOZE - CAN3 doze mode

◆ IOMUXC_GPR_GPR70_CAAM_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR70_CAAM_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAAM_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAAM_STOP_REQ_MASK)

CAAM_STOP_REQ - CAAM stop request

◆ IOMUXC_GPR_GPR70_CAAM_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR70_CAAM_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAAM_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAAM_STOP_REQ_MASK)

CAAM_STOP_REQ - CAAM stop request

◆ IOMUXC_GPR_GPR70_CAN1_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_MASK)

CAN1_IPG_DOZE - CAN1 doze mode

◆ IOMUXC_GPR_GPR70_CAN1_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_MASK)

CAN1_IPG_DOZE - CAN1 doze mode

◆ IOMUXC_GPR_GPR70_CAN1_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR70_CAN1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN1_STOP_REQ_MASK)

CAN1_STOP_REQ - CAN1 stop request

◆ IOMUXC_GPR_GPR70_CAN1_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR70_CAN1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN1_STOP_REQ_MASK)

CAN1_STOP_REQ - CAN1 stop request

◆ IOMUXC_GPR_GPR70_CAN2_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_MASK)

CAN2_IPG_DOZE - CAN2 doze mode

◆ IOMUXC_GPR_GPR70_CAN2_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_MASK)

CAN2_IPG_DOZE - CAN2 doze mode

◆ IOMUXC_GPR_GPR70_CAN2_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR70_CAN2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN2_STOP_REQ_MASK)

CAN2_STOP_REQ - CAN2 stop request

◆ IOMUXC_GPR_GPR70_CAN2_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR70_CAN2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN2_STOP_REQ_MASK)

CAN2_STOP_REQ - CAN2 stop request

◆ IOMUXC_GPR_GPR70_CAN3_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_MASK)

CAN3_IPG_DOZE - CAN3 doze mode

◆ IOMUXC_GPR_GPR70_CAN3_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_MASK)

CAN3_IPG_DOZE - CAN3 doze mode

◆ IOMUXC_GPR_GPR70_CAN3_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR70_CAN3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN3_STOP_REQ_MASK)

CAN3_STOP_REQ - CAN3 stop request

◆ IOMUXC_GPR_GPR70_CAN3_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR70_CAN3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN3_STOP_REQ_MASK)

CAN3_STOP_REQ - CAN3 stop request

◆ IOMUXC_GPR_GPR70_DWP [1/2]

#define IOMUXC_GPR_GPR70_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_DWP_SHIFT)) & IOMUXC_GPR_GPR70_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR70_DWP [2/2]

#define IOMUXC_GPR_GPR70_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_DWP_SHIFT)) & IOMUXC_GPR_GPR70_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR70_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR70_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR70_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR70_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR70_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR70_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_MASK)

EDMA_LPSR_STOP_REQ - EDMA_LPSR stop request

◆ IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_MASK)

EDMA_LPSR_STOP_REQ - EDMA_LPSR stop request

◆ IOMUXC_GPR_GPR70_EDMA_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR70_EDMA_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_EDMA_STOP_REQ_MASK)

EDMA_STOP_REQ - EDMA stop request

◆ IOMUXC_GPR_GPR70_EDMA_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR70_EDMA_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_EDMA_STOP_REQ_MASK)

EDMA_STOP_REQ - EDMA stop request

◆ IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_MASK)

ENET1G_IPG_DOZE - ENET1G doze mode

◆ IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_MASK)

ENET1G_IPG_DOZE - ENET1G doze mode

◆ IOMUXC_GPR_GPR70_ENET1G_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_MASK)

ENET1G_STOP_REQ - ENET1G stop request

◆ IOMUXC_GPR_GPR70_ENET1G_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_MASK)

ENET1G_STOP_REQ - ENET1G stop request

◆ IOMUXC_GPR_GPR70_ENET_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR70_ENET_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ENET_IPG_DOZE_MASK)

ENET_IPG_DOZE - ENET doze mode

◆ IOMUXC_GPR_GPR70_ENET_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR70_ENET_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ENET_IPG_DOZE_MASK)

ENET_IPG_DOZE - ENET doze mode

◆ IOMUXC_GPR_GPR70_ENET_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR70_ENET_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ENET_STOP_REQ_MASK)

ENET_STOP_REQ - ENET stop request

◆ IOMUXC_GPR_GPR70_ENET_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR70_ENET_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ENET_STOP_REQ_MASK)

ENET_STOP_REQ - ENET stop request

◆ IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_MASK)

FLEXIO1_IPG_DOZE - FLEXIO2 doze mode

◆ IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_MASK)

FLEXIO1_IPG_DOZE - FLEXIO2 doze mode

◆ IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_MASK)

FLEXIO2_IPG_DOZE - FLEXIO2 doze mode

◆ IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_MASK)

FLEXIO2_IPG_DOZE - FLEXIO2 doze mode

◆ IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_MASK)

FLEXSPI1_IPG_DOZE - FLEXSPI1 doze mode

◆ IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_MASK)

FLEXSPI1_IPG_DOZE - FLEXSPI1 doze mode

◆ IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_MASK)

FLEXSPI1_STOP_REQ - FLEXSPI1 stop request

◆ IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_MASK)

FLEXSPI1_STOP_REQ - FLEXSPI1 stop request

◆ IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_MASK)

FLEXSPI2_IPG_DOZE - FLEXSPI2 doze mode

◆ IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_MASK)

FLEXSPI2_IPG_DOZE - FLEXSPI2 doze mode

◆ IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_MASK)

FLEXSPI2_STOP_REQ - FLEXSPI2 stop request

◆ IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_MASK)

FLEXSPI2_STOP_REQ - FLEXSPI2 stop request

◆ IOMUXC_GPR_GPR71_DWP [1/2]

#define IOMUXC_GPR_GPR71_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_DWP_SHIFT)) & IOMUXC_GPR_GPR71_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR71_DWP [2/2]

#define IOMUXC_GPR_GPR71_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_DWP_SHIFT)) & IOMUXC_GPR_GPR71_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR71_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR71_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR71_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR71_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR71_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR71_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR71_GPT1_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_MASK)

GPT1_IPG_DOZE - GPT1 doze mode

◆ IOMUXC_GPR_GPR71_GPT1_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_MASK)

GPT1_IPG_DOZE - GPT1 doze mode

◆ IOMUXC_GPR_GPR71_GPT2_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_MASK)

GPT2_IPG_DOZE - GPT2 doze mode

◆ IOMUXC_GPR_GPR71_GPT2_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_MASK)

GPT2_IPG_DOZE - GPT2 doze mode

◆ IOMUXC_GPR_GPR71_GPT3_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_MASK)

GPT3_IPG_DOZE - GPT3 doze mode

◆ IOMUXC_GPR_GPR71_GPT3_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_MASK)

GPT3_IPG_DOZE - GPT3 doze mode

◆ IOMUXC_GPR_GPR71_GPT4_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_MASK)

GPT4_IPG_DOZE - GPT4 doze mode

◆ IOMUXC_GPR_GPR71_GPT4_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_MASK)

GPT4_IPG_DOZE - GPT4 doze mode

◆ IOMUXC_GPR_GPR71_GPT5_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_MASK)

GPT5_IPG_DOZE - GPT5 doze mode

◆ IOMUXC_GPR_GPR71_GPT5_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_MASK)

GPT5_IPG_DOZE - GPT5 doze mode

◆ IOMUXC_GPR_GPR71_GPT6_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_MASK)

GPT6_IPG_DOZE - GPT6 doze mode

◆ IOMUXC_GPR_GPR71_GPT6_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_MASK)

GPT6_IPG_DOZE - GPT6 doze mode

◆ IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_MASK)

LPI2C1_IPG_DOZE - LPI2C1 doze mode

◆ IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_MASK)

LPI2C1_IPG_DOZE - LPI2C1 doze mode

◆ IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_MASK)

LPI2C1_IPG_STOP_MODE - LPI2C1 stop mode selection, cannot change when LPI2C1_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_MASK)

LPI2C1_IPG_STOP_MODE - LPI2C1 stop mode selection, cannot change when LPI2C1_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_MASK)

LPI2C1_STOP_REQ - LPI2C1 stop request

◆ IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_MASK)

LPI2C1_STOP_REQ - LPI2C1 stop request

◆ IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_MASK)

LPI2C2_IPG_DOZE - LPI2C2 doze mode

◆ IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_MASK)

LPI2C2_IPG_DOZE - LPI2C2 doze mode

◆ IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_MASK)

LPI2C2_IPG_STOP_MODE - LPI2C2 stop mode selection, cannot change when LPI2C2_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_MASK)

LPI2C2_IPG_STOP_MODE - LPI2C2 stop mode selection, cannot change when LPI2C2_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_MASK)

LPI2C2_STOP_REQ - LPI2C2 stop request

◆ IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_MASK)

LPI2C2_STOP_REQ - LPI2C2 stop request

◆ IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_MASK)

LPI2C3_IPG_DOZE - LPI2C3 doze mode

◆ IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_MASK)

LPI2C3_IPG_DOZE - LPI2C3 doze mode

◆ IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_MASK)

LPI2C3_IPG_STOP_MODE - LPI2C3 stop mode selection, cannot change when LPI2C3_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_MASK)

LPI2C3_IPG_STOP_MODE - LPI2C3 stop mode selection, cannot change when LPI2C3_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_MASK)

LPI2C3_STOP_REQ - LPI2C3 stop request

◆ IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_MASK)

LPI2C3_STOP_REQ - LPI2C3 stop request

◆ IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_MASK)

LPI2C4_IPG_DOZE - LPI2C4 doze mode

◆ IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_MASK)

LPI2C4_IPG_DOZE - LPI2C4 doze mode

◆ IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_MASK)

LPI2C4_IPG_STOP_MODE - LPI2C4 stop mode selection, cannot change when LPI2C4_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_MASK)

LPI2C4_IPG_STOP_MODE - LPI2C4 stop mode selection, cannot change when LPI2C4_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_MASK)

LPI2C4_STOP_REQ - LPI2C4 stop request

◆ IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_MASK)

LPI2C4_STOP_REQ - LPI2C4 stop request

◆ IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_MASK)

LPI2C5_IPG_DOZE - LPI2C5 doze mode

◆ IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_MASK)

LPI2C5_IPG_DOZE - LPI2C5 doze mode

◆ IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_MASK)

LPI2C5_IPG_STOP_MODE - LPI2C5 stop mode selection, cannot change when LPI2C5_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_MASK)

LPI2C5_IPG_STOP_MODE - LPI2C5 stop mode selection, cannot change when LPI2C5_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_MASK)

LPI2C5_STOP_REQ - LPI2C5 stop request

◆ IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_MASK)

LPI2C5_STOP_REQ - LPI2C5 stop request

◆ IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_MASK)

LPI2C6_IPG_DOZE - LPI2C6 doze mode

◆ IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_MASK)

LPI2C6_IPG_DOZE - LPI2C6 doze mode

◆ IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_MASK)

LPI2C6_IPG_STOP_MODE - LPI2C6 stop mode selection, cannot change when LPI2C6_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_MASK)

LPI2C6_IPG_STOP_MODE - LPI2C6 stop mode selection, cannot change when LPI2C6_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_MASK)

LPI2C6_STOP_REQ - LPI2C6 stop request

◆ IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_MASK)

LPI2C6_STOP_REQ - LPI2C6 stop request

◆ IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_MASK)

LPSPI1_IPG_DOZE - LPSPI1 doze mode

◆ IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_MASK)

LPSPI1_IPG_DOZE - LPSPI1 doze mode

◆ IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_MASK)

LPSPI1_IPG_STOP_MODE - LPSPI1 stop mode selection, cannot change when LPSPI1_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_MASK)

LPSPI1_IPG_STOP_MODE - LPSPI1 stop mode selection, cannot change when LPSPI1_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_MASK)

LPSPI1_STOP_REQ - LPSPI1 stop request

◆ IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_MASK)

LPSPI1_STOP_REQ - LPSPI1 stop request

◆ IOMUXC_GPR_GPR72_DWP [1/2]

#define IOMUXC_GPR_GPR72_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_DWP_SHIFT)) & IOMUXC_GPR_GPR72_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR72_DWP [2/2]

#define IOMUXC_GPR_GPR72_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_DWP_SHIFT)) & IOMUXC_GPR_GPR72_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR72_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR72_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR72_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR72_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR72_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR72_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_MASK)

LPSPI2_IPG_DOZE - LPSPI2 doze mode

◆ IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_MASK)

LPSPI2_IPG_DOZE - LPSPI2 doze mode

◆ IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_MASK)

LPSPI2_IPG_STOP_MODE - LPSPI2 stop mode selection, cannot change when LPSPI2_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_MASK)

LPSPI2_IPG_STOP_MODE - LPSPI2 stop mode selection, cannot change when LPSPI2_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_MASK)

LPSPI2_STOP_REQ - LPSPI2 stop request

◆ IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_MASK)

LPSPI2_STOP_REQ - LPSPI2 stop request

◆ IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_MASK)

LPSPI3_IPG_DOZE - LPSPI3 doze mode

◆ IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_MASK)

LPSPI3_IPG_DOZE - LPSPI3 doze mode

◆ IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_MASK)

LPSPI3_IPG_STOP_MODE - LPSPI3 stop mode selection, cannot change when LPSPI3_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_MASK)

LPSPI3_IPG_STOP_MODE - LPSPI3 stop mode selection, cannot change when LPSPI3_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_MASK)

LPSPI3_STOP_REQ - LPSPI3 stop request

◆ IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_MASK)

LPSPI3_STOP_REQ - LPSPI3 stop request

◆ IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_MASK)

LPSPI4_IPG_DOZE - LPSPI4 doze mode

◆ IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_MASK)

LPSPI4_IPG_DOZE - LPSPI4 doze mode

◆ IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_MASK)

LPSPI4_IPG_STOP_MODE - LPSPI4 stop mode selection, cannot change when LPSPI4_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_MASK)

LPSPI4_IPG_STOP_MODE - LPSPI4 stop mode selection, cannot change when LPSPI4_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_MASK)

LPSPI4_STOP_REQ - LPSPI4 stop request

◆ IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_MASK)

LPSPI4_STOP_REQ - LPSPI4 stop request

◆ IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_MASK)

LPSPI5_IPG_DOZE - LPSPI5 doze mode

◆ IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_MASK)

LPSPI5_IPG_DOZE - LPSPI5 doze mode

◆ IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_MASK)

LPSPI5_IPG_STOP_MODE - LPSPI5 stop mode selection, cannot change when LPSPI5_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_MASK)

LPSPI5_IPG_STOP_MODE - LPSPI5 stop mode selection, cannot change when LPSPI5_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_MASK)

LPSPI5_STOP_REQ - LPSPI5 stop request

◆ IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_MASK)

LPSPI5_STOP_REQ - LPSPI5 stop request

◆ IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_MASK)

LPSPI6_IPG_DOZE - LPSPI6 doze mode

◆ IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_MASK)

LPSPI6_IPG_DOZE - LPSPI6 doze mode

◆ IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_MASK)

LPSPI6_IPG_STOP_MODE - LPSPI6 stop mode selection, cannot change when LPSPI6_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_MASK)

LPSPI6_IPG_STOP_MODE - LPSPI6 stop mode selection, cannot change when LPSPI6_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_MASK)

LPSPI6_STOP_REQ - LPSPI6 stop request

◆ IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_MASK)

LPSPI6_STOP_REQ - LPSPI6 stop request

◆ IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_MASK)

LPUART1_IPG_DOZE - LPUART1 doze mode

◆ IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_MASK)

LPUART1_IPG_DOZE - LPUART1 doze mode

◆ IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_MASK)

LPUART1_IPG_STOP_MODE - LPUART1 stop mode selection, cannot change when LPUART1_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_MASK)

LPUART1_IPG_STOP_MODE - LPUART1 stop mode selection, cannot change when LPUART1_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR72_LPUART1_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_MASK)

LPUART1_STOP_REQ - LPUART1 stop request

◆ IOMUXC_GPR_GPR72_LPUART1_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_MASK)

LPUART1_STOP_REQ - LPUART1 stop request

◆ IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_MASK)

LPUART2_IPG_DOZE - LPUART2 doze mode

◆ IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_MASK)

LPUART2_IPG_DOZE - LPUART2 doze mode

◆ IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_MASK)

LPUART2_IPG_STOP_MODE - LPUART2 stop mode selection, cannot change when LPUART2_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_MASK)

LPUART2_IPG_STOP_MODE - LPUART2 stop mode selection, cannot change when LPUART2_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR72_LPUART2_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_MASK)

LPUART2_STOP_REQ - LPUART2 stop request

◆ IOMUXC_GPR_GPR72_LPUART2_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_MASK)

LPUART2_STOP_REQ - LPUART2 stop request

◆ IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_MASK)

LPUART3_IPG_DOZE - LPUART3 doze mode

◆ IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_MASK)

LPUART3_IPG_DOZE - LPUART3 doze mode

◆ IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_MASK)

LPUART3_IPG_STOP_MODE - LPUART3 stop mode selection, cannot change when LPUART3_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_MASK)

LPUART3_IPG_STOP_MODE - LPUART3 stop mode selection, cannot change when LPUART3_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR72_LPUART3_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_MASK)

LPUART3_STOP_REQ - LPUART3 stop request

◆ IOMUXC_GPR_GPR72_LPUART3_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_MASK)

LPUART3_STOP_REQ - LPUART3 stop request

◆ IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_MASK)

LPUART4_IPG_DOZE - LPUART4 doze mode

◆ IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_MASK)

LPUART4_IPG_DOZE - LPUART4 doze mode

◆ IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_MASK)

LPUART4_IPG_STOP_MODE - LPUART4 stop mode selection, cannot change when LPUART4_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_MASK)

LPUART4_IPG_STOP_MODE - LPUART4 stop mode selection, cannot change when LPUART4_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR72_LPUART4_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_MASK)

LPUART4_STOP_REQ - LPUART4 stop request

◆ IOMUXC_GPR_GPR72_LPUART4_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_MASK)

LPUART4_STOP_REQ - LPUART4 stop request

◆ IOMUXC_GPR_GPR73_DWP [1/2]

#define IOMUXC_GPR_GPR73_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_DWP_SHIFT)) & IOMUXC_GPR_GPR73_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR73_DWP [2/2]

#define IOMUXC_GPR_GPR73_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_DWP_SHIFT)) & IOMUXC_GPR_GPR73_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR73_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR73_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR73_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR73_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR73_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR73_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_MASK)

LPUART10_IPG_DOZE - LPUART10 doze mode

◆ IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_MASK)

LPUART10_IPG_DOZE - LPUART10 doze mode

◆ IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_MASK)

LPUART10_IPG_STOP_MODE - LPUART10 stop mode selection, cannot change when LPUART10_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_MASK)

LPUART10_IPG_STOP_MODE - LPUART10 stop mode selection, cannot change when LPUART10_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR73_LPUART10_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_MASK)

LPUART10_STOP_REQ - LPUART10 stop request

◆ IOMUXC_GPR_GPR73_LPUART10_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_MASK)

LPUART10_STOP_REQ - LPUART10 stop request

◆ IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_MASK)

LPUART11_IPG_DOZE - LPUART11 doze mode

◆ IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_MASK)

LPUART11_IPG_DOZE - LPUART11 doze mode

◆ IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_MASK)

LPUART11_IPG_STOP_MODE - LPUART11 stop mode selection, cannot change when LPUART11_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_MASK)

LPUART11_IPG_STOP_MODE - LPUART11 stop mode selection, cannot change when LPUART11_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR73_LPUART11_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_MASK)

LPUART11_STOP_REQ - LPUART11 stop request

◆ IOMUXC_GPR_GPR73_LPUART11_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_MASK)

LPUART11_STOP_REQ - LPUART11 stop request

◆ IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_MASK)

LPUART12_IPG_DOZE - LPUART12 doze mode

◆ IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_MASK)

LPUART12_IPG_DOZE - LPUART12 doze mode

◆ IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_MASK)

LPUART12_IPG_STOP_MODE - LPUART12 stop mode selection, cannot change when LPUART12_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_MASK)

LPUART12_IPG_STOP_MODE - LPUART12 stop mode selection, cannot change when LPUART12_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR73_LPUART12_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_MASK)

LPUART12_STOP_REQ - LPUART12 stop request

◆ IOMUXC_GPR_GPR73_LPUART12_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_MASK)

LPUART12_STOP_REQ - LPUART12 stop request

◆ IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_MASK)

LPUART5_IPG_DOZE - LPUART5 doze mode

◆ IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_MASK)

LPUART5_IPG_DOZE - LPUART5 doze mode

◆ IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_MASK)

LPUART5_IPG_STOP_MODE - LPUART5 stop mode selection, cannot change when LPUART5_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_MASK)

LPUART5_IPG_STOP_MODE - LPUART5 stop mode selection, cannot change when LPUART5_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR73_LPUART5_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_MASK)

LPUART5_STOP_REQ - LPUART5 stop request

◆ IOMUXC_GPR_GPR73_LPUART5_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_MASK)

LPUART5_STOP_REQ - LPUART5 stop request

◆ IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_MASK)

LPUART6_IPG_DOZE - LPUART6 doze mode

◆ IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_MASK)

LPUART6_IPG_DOZE - LPUART6 doze mode

◆ IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_MASK)

LPUART6_IPG_STOP_MODE - LPUART6 stop mode selection, cannot change when LPUART6_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_MASK)

LPUART6_IPG_STOP_MODE - LPUART6 stop mode selection, cannot change when LPUART6_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR73_LPUART6_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_MASK)

LPUART6_STOP_REQ - LPUART6 stop request

◆ IOMUXC_GPR_GPR73_LPUART6_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_MASK)

LPUART6_STOP_REQ - LPUART6 stop request

◆ IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_MASK)

LPUART7_IPG_DOZE - LPUART7 doze mode

◆ IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_MASK)

LPUART7_IPG_DOZE - LPUART7 doze mode

◆ IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_MASK)

LPUART7_IPG_STOP_MODE - LPUART7 stop mode selection, cannot change when LPUART7_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_MASK)

LPUART7_IPG_STOP_MODE - LPUART7 stop mode selection, cannot change when LPUART7_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR73_LPUART7_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_MASK)

LPUART7_STOP_REQ - LPUART7 stop request

◆ IOMUXC_GPR_GPR73_LPUART7_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_MASK)

LPUART7_STOP_REQ - LPUART7 stop request

◆ IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_MASK)

LPUART8_IPG_DOZE - LPUART8 doze mode

◆ IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_MASK)

LPUART8_IPG_DOZE - LPUART8 doze mode

◆ IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_MASK)

LPUART8_IPG_STOP_MODE - LPUART8 stop mode selection, cannot change when LPUART8_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_MASK)

LPUART8_IPG_STOP_MODE - LPUART8 stop mode selection, cannot change when LPUART8_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR73_LPUART8_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_MASK)

LPUART8_STOP_REQ - LPUART8 stop request

◆ IOMUXC_GPR_GPR73_LPUART8_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_MASK)

LPUART8_STOP_REQ - LPUART8 stop request

◆ IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_MASK)

LPUART9_IPG_DOZE - LPUART9 doze mode

◆ IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_MASK)

LPUART9_IPG_DOZE - LPUART9 doze mode

◆ IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_MASK)

LPUART9_IPG_STOP_MODE - LPUART9 stop mode selection, cannot change when LPUART9_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_MASK)

LPUART9_IPG_STOP_MODE - LPUART9 stop mode selection, cannot change when LPUART9_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR73_LPUART9_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_MASK)

LPUART9_STOP_REQ - LPUART9 stop request

◆ IOMUXC_GPR_GPR73_LPUART9_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_MASK)

LPUART9_STOP_REQ - LPUART9 stop request

◆ IOMUXC_GPR_GPR73_MIC_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR73_MIC_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_MIC_IPG_DOZE_MASK)

MIC_IPG_DOZE - MIC doze mode

◆ IOMUXC_GPR_GPR73_MIC_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR73_MIC_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_MIC_IPG_DOZE_MASK)

MIC_IPG_DOZE - MIC doze mode

◆ IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE [1/2]

#define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_MASK)

MIC_IPG_STOP_MODE - MIC stop mode selection, cannot change when MIC_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE [2/2]

#define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_MASK)

MIC_IPG_STOP_MODE - MIC stop mode selection, cannot change when MIC_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_GPR_GPR73_MIC_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR73_MIC_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_MIC_STOP_REQ_MASK)

MIC_STOP_REQ - MIC stop request

◆ IOMUXC_GPR_GPR73_MIC_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR73_MIC_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_MIC_STOP_REQ_MASK)

MIC_STOP_REQ - MIC stop request

◆ IOMUXC_GPR_GPR74_DWP [1/2]

#define IOMUXC_GPR_GPR74_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_DWP_SHIFT)) & IOMUXC_GPR_GPR74_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR74_DWP [2/2]

#define IOMUXC_GPR_GPR74_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_DWP_SHIFT)) & IOMUXC_GPR_GPR74_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR74_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR74_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR74_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR74_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR74_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR74_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS [1/2]

#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_MASK)

FLEXIO1_STOP_REQ_BUS - FLEXIO1 bus clock domain stop request

◆ IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS [2/2]

#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_MASK)

FLEXIO1_STOP_REQ_BUS - FLEXIO1 bus clock domain stop request

◆ IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER [1/2]

#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_MASK)

FLEXIO1_STOP_REQ_PER - FLEXIO1 peripheral clock domain stop request

◆ IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER [2/2]

#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_MASK)

FLEXIO1_STOP_REQ_PER - FLEXIO1 peripheral clock domain stop request

◆ IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS [1/2]

#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_MASK)

FLEXIO2_STOP_REQ_BUS - FLEXIO2 bus clock domain stop request

◆ IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS [2/2]

#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_MASK)

FLEXIO2_STOP_REQ_BUS - FLEXIO2 bus clock domain stop request

◆ IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER [1/2]

#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_MASK)

FLEXIO2_STOP_REQ_PER - FLEXIO2 peripheral clock domain stop request

◆ IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER [2/2]

#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_MASK)

FLEXIO2_STOP_REQ_PER - FLEXIO2 peripheral clock domain stop request

◆ IOMUXC_GPR_GPR74_PIT1_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR74_PIT1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_PIT1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_PIT1_STOP_REQ_MASK)

PIT1_STOP_REQ - PIT1 stop request

◆ IOMUXC_GPR_GPR74_PIT1_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR74_PIT1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_PIT1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_PIT1_STOP_REQ_MASK)

PIT1_STOP_REQ - PIT1 stop request

◆ IOMUXC_GPR_GPR74_PIT2_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR74_PIT2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_PIT2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_PIT2_STOP_REQ_MASK)

PIT2_STOP_REQ - PIT2 stop request

◆ IOMUXC_GPR_GPR74_PIT2_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR74_PIT2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_PIT2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_PIT2_STOP_REQ_MASK)

PIT2_STOP_REQ - PIT2 stop request

◆ IOMUXC_GPR_GPR74_SAI1_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR74_SAI1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI1_STOP_REQ_MASK)

SAI1_STOP_REQ - SAI1 stop request

◆ IOMUXC_GPR_GPR74_SAI1_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR74_SAI1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI1_STOP_REQ_MASK)

SAI1_STOP_REQ - SAI1 stop request

◆ IOMUXC_GPR_GPR74_SAI2_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR74_SAI2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI2_STOP_REQ_MASK)

SAI2_STOP_REQ - SAI2 stop request

◆ IOMUXC_GPR_GPR74_SAI2_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR74_SAI2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI2_STOP_REQ_MASK)

SAI2_STOP_REQ - SAI2 stop request

◆ IOMUXC_GPR_GPR74_SAI3_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR74_SAI3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI3_STOP_REQ_MASK)

SAI3_STOP_REQ - SAI3 stop request

◆ IOMUXC_GPR_GPR74_SAI3_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR74_SAI3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI3_STOP_REQ_MASK)

SAI3_STOP_REQ - SAI3 stop request

◆ IOMUXC_GPR_GPR74_SAI4_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR74_SAI4_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI4_STOP_REQ_MASK)

SAI4_STOP_REQ - SAI4 stop request

◆ IOMUXC_GPR_GPR74_SAI4_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR74_SAI4_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI4_STOP_REQ_MASK)

SAI4_STOP_REQ - SAI4 stop request

◆ IOMUXC_GPR_GPR74_SEMC_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR74_SEMC_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SEMC_STOP_REQ_MASK)

SEMC_STOP_REQ - SEMC stop request

◆ IOMUXC_GPR_GPR74_SEMC_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR74_SEMC_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SEMC_STOP_REQ_MASK)

SEMC_STOP_REQ - SEMC stop request

◆ IOMUXC_GPR_GPR74_SIM1_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_MASK)

SIM1_IPG_DOZE - SIM1 doze mode

◆ IOMUXC_GPR_GPR74_SIM1_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_MASK)

SIM1_IPG_DOZE - SIM1 doze mode

◆ IOMUXC_GPR_GPR74_SIM2_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_MASK)

SIM2_IPG_DOZE - SIM2 doze mode

◆ IOMUXC_GPR_GPR74_SIM2_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_MASK)

SIM2_IPG_DOZE - SIM2 doze mode

◆ IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_MASK)

SNVS_HP_IPG_DOZE - SNVS_HP doze mode

◆ IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_MASK)

SNVS_HP_IPG_DOZE - SNVS_HP doze mode

◆ IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ [1/2]

#define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_MASK)

SNVS_HP_STOP_REQ - SNVS_HP stop request

◆ IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ [2/2]

#define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_MASK)

SNVS_HP_STOP_REQ - SNVS_HP stop request

◆ IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_MASK)

WDOG1_IPG_DOZE - WDOG1 doze mode

◆ IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_MASK)

WDOG1_IPG_DOZE - WDOG1 doze mode

◆ IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE [1/2]

#define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_MASK)

WDOG2_IPG_DOZE - WDOG2 doze mode

◆ IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE [2/2]

#define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_MASK)

WDOG2_IPG_DOZE - WDOG2 doze mode

◆ IOMUXC_GPR_GPR75_ADC1_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_ADC1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ADC1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ADC1_STOP_ACK_MASK)

ADC1_STOP_ACK - ADC1 stop acknowledge

◆ IOMUXC_GPR_GPR75_ADC1_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_ADC1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ADC1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ADC1_STOP_ACK_MASK)

ADC1_STOP_ACK - ADC1 stop acknowledge

◆ IOMUXC_GPR_GPR75_ADC2_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_ADC2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ADC2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ADC2_STOP_ACK_MASK)

ADC2_STOP_ACK - ADC2 stop acknowledge

◆ IOMUXC_GPR_GPR75_ADC2_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_ADC2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ADC2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ADC2_STOP_ACK_MASK)

ADC2_STOP_ACK - ADC2 stop acknowledge

◆ IOMUXC_GPR_GPR75_CAAM_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_CAAM_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAAM_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAAM_STOP_ACK_MASK)

CAAM_STOP_ACK - CAAM stop acknowledge

◆ IOMUXC_GPR_GPR75_CAAM_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_CAAM_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAAM_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAAM_STOP_ACK_MASK)

CAAM_STOP_ACK - CAAM stop acknowledge

◆ IOMUXC_GPR_GPR75_CAN1_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_CAN1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN1_STOP_ACK_MASK)

CAN1_STOP_ACK - CAN1 stop acknowledge

◆ IOMUXC_GPR_GPR75_CAN1_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_CAN1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN1_STOP_ACK_MASK)

CAN1_STOP_ACK - CAN1 stop acknowledge

◆ IOMUXC_GPR_GPR75_CAN2_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_CAN2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN2_STOP_ACK_MASK)

CAN2_STOP_ACK - CAN2 stop acknowledge

◆ IOMUXC_GPR_GPR75_CAN2_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_CAN2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN2_STOP_ACK_MASK)

CAN2_STOP_ACK - CAN2 stop acknowledge

◆ IOMUXC_GPR_GPR75_CAN3_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_CAN3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN3_STOP_ACK_MASK)

CAN3_STOP_ACK - CAN3 stop acknowledge

◆ IOMUXC_GPR_GPR75_CAN3_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_CAN3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN3_STOP_ACK_MASK)

CAN3_STOP_ACK - CAN3 stop acknowledge

◆ IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_MASK)

EDMA_LPSR_STOP_ACK - EDMA_LPSR stop acknowledge

◆ IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_MASK)

EDMA_LPSR_STOP_ACK - EDMA_LPSR stop acknowledge

◆ IOMUXC_GPR_GPR75_EDMA_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_EDMA_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_EDMA_STOP_ACK_MASK)

EDMA_STOP_ACK - EDMA stop acknowledge

◆ IOMUXC_GPR_GPR75_EDMA_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_EDMA_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_EDMA_STOP_ACK_MASK)

EDMA_STOP_ACK - EDMA stop acknowledge

◆ IOMUXC_GPR_GPR75_ENET1G_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_MASK)

ENET1G_STOP_ACK - ENET1G stop acknowledge

◆ IOMUXC_GPR_GPR75_ENET1G_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_MASK)

ENET1G_STOP_ACK - ENET1G stop acknowledge

◆ IOMUXC_GPR_GPR75_ENET_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_ENET_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ENET_STOP_ACK_MASK)

ENET_STOP_ACK - ENET stop acknowledge

◆ IOMUXC_GPR_GPR75_ENET_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_ENET_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ENET_STOP_ACK_MASK)

ENET_STOP_ACK - ENET stop acknowledge

◆ IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_MASK)

FLEXSPI1_STOP_ACK - FLEXSPI1 stop acknowledge

◆ IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_MASK)

FLEXSPI1_STOP_ACK - FLEXSPI1 stop acknowledge

◆ IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_MASK)

FLEXSPI2_STOP_ACK - FLEXSPI2 stop acknowledge

◆ IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_MASK)

FLEXSPI2_STOP_ACK - FLEXSPI2 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_MASK)

LPI2C1_STOP_ACK - LPI2C1 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_MASK)

LPI2C1_STOP_ACK - LPI2C1 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_MASK)

LPI2C2_STOP_ACK - LPI2C2 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_MASK)

LPI2C2_STOP_ACK - LPI2C2 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_MASK)

LPI2C3_STOP_ACK - LPI2C3 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_MASK)

LPI2C3_STOP_ACK - LPI2C3 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_MASK)

LPI2C4_STOP_ACK - LPI2C4 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_MASK)

LPI2C4_STOP_ACK - LPI2C4 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_MASK)

LPI2C5_STOP_ACK - LPI2C5 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_MASK)

LPI2C5_STOP_ACK - LPI2C5 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_MASK)

LPI2C6_STOP_ACK - LPI2C6 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_MASK)

LPI2C6_STOP_ACK - LPI2C6 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_MASK)

LPSPI1_STOP_ACK - LPSPI1 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_MASK)

LPSPI1_STOP_ACK - LPSPI1 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_MASK)

LPSPI2_STOP_ACK - LPSPI2 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_MASK)

LPSPI2_STOP_ACK - LPSPI2 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_MASK)

LPSPI3_STOP_ACK - LPSPI3 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_MASK)

LPSPI3_STOP_ACK - LPSPI3 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_MASK)

LPSPI4_STOP_ACK - LPSPI4 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_MASK)

LPSPI4_STOP_ACK - LPSPI4 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_MASK)

LPSPI5_STOP_ACK - LPSPI5 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_MASK)

LPSPI5_STOP_ACK - LPSPI5 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_MASK)

LPSPI6_STOP_ACK - LPSPI6 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_MASK)

LPSPI6_STOP_ACK - LPSPI6 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPUART1_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_MASK)

LPUART1_STOP_ACK - LPUART1 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPUART1_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_MASK)

LPUART1_STOP_ACK - LPUART1 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPUART2_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_MASK)

LPUART2_STOP_ACK - LPUART2 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPUART2_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_MASK)

LPUART2_STOP_ACK - LPUART2 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPUART3_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_MASK)

LPUART3_STOP_ACK - LPUART3 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPUART3_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_MASK)

LPUART3_STOP_ACK - LPUART3 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPUART4_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_MASK)

LPUART4_STOP_ACK - LPUART4 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPUART4_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_MASK)

LPUART4_STOP_ACK - LPUART4 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPUART5_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_MASK)

LPUART5_STOP_ACK - LPUART5 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPUART5_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_MASK)

LPUART5_STOP_ACK - LPUART5 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPUART6_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_MASK)

LPUART6_STOP_ACK - LPUART6 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPUART6_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_MASK)

LPUART6_STOP_ACK - LPUART6 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPUART7_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_MASK)

LPUART7_STOP_ACK - LPUART7 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPUART7_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_MASK)

LPUART7_STOP_ACK - LPUART7 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPUART8_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR75_LPUART8_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_MASK)

LPUART8_STOP_ACK - LPUART8 stop acknowledge

◆ IOMUXC_GPR_GPR75_LPUART8_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR75_LPUART8_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_MASK)

LPUART8_STOP_ACK - LPUART8 stop acknowledge

◆ IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS [1/2]

#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_MASK)

FLEXIO1_STOP_ACK_BUS - FLEXIO1 stop acknowledge of bus clock domain

◆ IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS [2/2]

#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_MASK)

FLEXIO1_STOP_ACK_BUS - FLEXIO1 stop acknowledge of bus clock domain

◆ IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER [1/2]

#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_MASK)

FLEXIO1_STOP_ACK_PER - FLEXIO1 stop acknowledge of peripheral clock domain

◆ IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER [2/2]

#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_MASK)

FLEXIO1_STOP_ACK_PER - FLEXIO1 stop acknowledge of peripheral clock domain

◆ IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS [1/2]

#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_MASK)

FLEXIO2_STOP_ACK_BUS - FLEXIO2 stop acknowledge of bus clock domain

◆ IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS [2/2]

#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_MASK)

FLEXIO2_STOP_ACK_BUS - FLEXIO2 stop acknowledge of bus clock domain

◆ IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER [1/2]

#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_MASK)

FLEXIO2_STOP_ACK_PER - FLEXIO2 stop acknowledge of peripheral clock domain

◆ IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER [2/2]

#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_MASK)

FLEXIO2_STOP_ACK_PER - FLEXIO2 stop acknowledge of peripheral clock domain

◆ IOMUXC_GPR_GPR76_LPUART10_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_MASK)

LPUART10_STOP_ACK - LPUART10 stop acknowledge

◆ IOMUXC_GPR_GPR76_LPUART10_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_MASK)

LPUART10_STOP_ACK - LPUART10 stop acknowledge

◆ IOMUXC_GPR_GPR76_LPUART11_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_MASK)

LPUART11_STOP_ACK - LPUART11 stop acknowledge

◆ IOMUXC_GPR_GPR76_LPUART11_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_MASK)

LPUART11_STOP_ACK - LPUART11 stop acknowledge

◆ IOMUXC_GPR_GPR76_LPUART12_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_MASK)

LPUART12_STOP_ACK - LPUART12 stop acknowledge

◆ IOMUXC_GPR_GPR76_LPUART12_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_MASK)

LPUART12_STOP_ACK - LPUART12 stop acknowledge

◆ IOMUXC_GPR_GPR76_LPUART9_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_MASK)

LPUART9_STOP_ACK - LPUART9 stop acknowledge

◆ IOMUXC_GPR_GPR76_LPUART9_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_MASK)

LPUART9_STOP_ACK - LPUART9 stop acknowledge

◆ IOMUXC_GPR_GPR76_MIC_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR76_MIC_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_MIC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_MIC_STOP_ACK_MASK)

MIC_STOP_ACK - MIC stop acknowledge

◆ IOMUXC_GPR_GPR76_MIC_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR76_MIC_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_MIC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_MIC_STOP_ACK_MASK)

MIC_STOP_ACK - MIC stop acknowledge

◆ IOMUXC_GPR_GPR76_PIT1_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR76_PIT1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_PIT1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_PIT1_STOP_ACK_MASK)

PIT1_STOP_ACK - PIT1 stop acknowledge

◆ IOMUXC_GPR_GPR76_PIT1_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR76_PIT1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_PIT1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_PIT1_STOP_ACK_MASK)

PIT1_STOP_ACK - PIT1 stop acknowledge

◆ IOMUXC_GPR_GPR76_PIT2_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR76_PIT2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_PIT2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_PIT2_STOP_ACK_MASK)

PIT2_STOP_ACK - PIT2 stop acknowledge

◆ IOMUXC_GPR_GPR76_PIT2_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR76_PIT2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_PIT2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_PIT2_STOP_ACK_MASK)

PIT2_STOP_ACK - PIT2 stop acknowledge

◆ IOMUXC_GPR_GPR76_SAI1_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR76_SAI1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI1_STOP_ACK_MASK)

SAI1_STOP_ACK - SAI1 stop acknowledge

◆ IOMUXC_GPR_GPR76_SAI1_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR76_SAI1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI1_STOP_ACK_MASK)

SAI1_STOP_ACK - SAI1 stop acknowledge

◆ IOMUXC_GPR_GPR76_SAI2_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR76_SAI2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI2_STOP_ACK_MASK)

SAI2_STOP_ACK - SAI2 stop acknowledge

◆ IOMUXC_GPR_GPR76_SAI2_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR76_SAI2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI2_STOP_ACK_MASK)

SAI2_STOP_ACK - SAI2 stop acknowledge

◆ IOMUXC_GPR_GPR76_SAI3_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR76_SAI3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI3_STOP_ACK_MASK)

SAI3_STOP_ACK - SAI3 stop acknowledge

◆ IOMUXC_GPR_GPR76_SAI3_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR76_SAI3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI3_STOP_ACK_MASK)

SAI3_STOP_ACK - SAI3 stop acknowledge

◆ IOMUXC_GPR_GPR76_SAI4_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR76_SAI4_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI4_STOP_ACK_MASK)

SAI4_STOP_ACK - SAI4 stop acknowledge

◆ IOMUXC_GPR_GPR76_SAI4_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR76_SAI4_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI4_STOP_ACK_MASK)

SAI4_STOP_ACK - SAI4 stop acknowledge

◆ IOMUXC_GPR_GPR76_SEMC_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR76_SEMC_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SEMC_STOP_ACK_MASK)

SEMC_STOP_ACK - SEMC stop acknowledge

◆ IOMUXC_GPR_GPR76_SEMC_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR76_SEMC_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SEMC_STOP_ACK_MASK)

SEMC_STOP_ACK - SEMC stop acknowledge

◆ IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK [1/2]

#define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_MASK)

SNVS_HP_STOP_ACK - SNVS_HP stop acknowledge

◆ IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK [2/2]

#define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_MASK)

SNVS_HP_STOP_ACK - SNVS_HP stop acknowledge

◆ IOMUXC_GPR_GPR7_DWP [1/2]

#define IOMUXC_GPR_GPR7_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_DWP_SHIFT)) & IOMUXC_GPR_GPR7_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR7_DWP [2/2]

#define IOMUXC_GPR_GPR7_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_DWP_SHIFT)) & IOMUXC_GPR_GPR7_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR7_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR7_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR7_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR7_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR7_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR7_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR7_GINT [1/2]

#define IOMUXC_GPR_GPR7_GINT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_GINT_SHIFT)) & IOMUXC_GPR_GPR7_GINT_MASK)

GINT - Global interrupt

◆ IOMUXC_GPR_GPR7_GINT [2/2]

#define IOMUXC_GPR_GPR7_GINT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_GINT_SHIFT)) & IOMUXC_GPR_GPR7_GINT_MASK)

GINT - Global interrupt

◆ IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK

#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK)

LPI2C1_STOP_ACK - LPI2C1 stop acknowledge 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted (the module is in Stop mode)

◆ IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ

#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK)

LPI2C1_STOP_REQ - LPI2C1 stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK

#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK)

LPI2C2_STOP_ACK - LPI2C2 stop acknowledge 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

◆ IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ

#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK)

LPI2C2_STOP_REQ - LPI2C2 stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK

#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK)

LPI2C3_STOP_ACK - LPI2C3 stop acknowledge 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

◆ IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ

#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK)

LPI2C3_STOP_REQ - LPI2C3 stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK

#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK)

LPI2C4_STOP_ACK - LPI2C4 stop acknowledge 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

◆ IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ

#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK)

LPI2C4_STOP_REQ - LPI2C4 stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK

#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK)

LPSPI1_STOP_ACK - LPSPI1 stop acknowledge 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

◆ IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ

#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK)

LPSPI1_STOP_REQ - LPSPI1 stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK

#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK)

LPSPI2_STOP_ACK - LPSPI2 stop acknowledge 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

◆ IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ

#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK)

LPSPI2_STOP_REQ - LPSPI2 stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK

#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK)

LPSPI3_STOP_ACK - LPSPI3 stop acknowledge 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

◆ IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ

#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK)

LPSPI3_STOP_REQ - LPSPI3 stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK

#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK)

LPSPI4_STOP_ACK - LPSPI4 stop acknowledge 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

◆ IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ

#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK)

LPSPI4_STOP_REQ - LPSPI4 stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR7_LPUART1_STOP_ACK

#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK)

LPUART1_STOP_ACK - LPUART1 stop acknowledge 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

◆ IOMUXC_GPR_GPR7_LPUART1_STOP_REQ

#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK)

LPUART1_STOP_REQ - LPUART1 stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR7_LPUART2_STOP_ACK

#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK)

LPUART2_STOP_ACK - LPUART2 stop acknowledge 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

◆ IOMUXC_GPR_GPR7_LPUART2_STOP_REQ

#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK)

LPUART2_STOP_REQ - LPUART2 stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR7_LPUART3_STOP_ACK

#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK)

LPUART3_STOP_ACK - LPUART3 stop acknowledge 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

◆ IOMUXC_GPR_GPR7_LPUART3_STOP_REQ

#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK)

LPUART3_STOP_REQ - LPUART3 stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR7_LPUART4_STOP_ACK

#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK)

LPUART4_STOP_ACK - LPUART4 stop acknowledge 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

◆ IOMUXC_GPR_GPR7_LPUART4_STOP_REQ

#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK)

LPUART4_STOP_REQ - LPUART4 stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR7_LPUART5_STOP_ACK

#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK)

LPUART5_STOP_ACK - LPUART5 stop acknowledge 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

◆ IOMUXC_GPR_GPR7_LPUART5_STOP_REQ

#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK)

LPUART5_STOP_REQ - LPUART5 stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR7_LPUART6_STOP_ACK

#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK)

LPUART6_STOP_ACK - LPUART6 stop acknowledge 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

◆ IOMUXC_GPR_GPR7_LPUART6_STOP_REQ

#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK)

LPUART6_STOP_REQ - LPUART6 stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR7_LPUART7_STOP_ACK

#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK)

LPUART7_STOP_ACK - LPUART7 stop acknowledge 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted

◆ IOMUXC_GPR_GPR7_LPUART7_STOP_REQ

#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK)

LPUART7_STOP_REQ - LPUART7 stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR7_LPUART8_STOP_ACK

#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK)

LPUART8_STOP_ACK - LPUART8 stop acknowledge 0b0..stop acknowledge is not asserted 0b1..stop acknowledge is asserted (the module is in Stop mode)

◆ IOMUXC_GPR_GPR7_LPUART8_STOP_REQ

#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK)

LPUART8_STOP_REQ - LPUART8 stop request 0b0..stop request off 0b1..stop request on

◆ IOMUXC_GPR_GPR8_DWP [1/2]

#define IOMUXC_GPR_GPR8_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_DWP_SHIFT)) & IOMUXC_GPR_GPR8_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR8_DWP [2/2]

#define IOMUXC_GPR_GPR8_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_DWP_SHIFT)) & IOMUXC_GPR_GPR8_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR8_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR8_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR8_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR8_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR8_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR8_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK)

LPI2C1_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

◆ IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK)

LPI2C1_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

◆ IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK)

LPI2C2_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

◆ IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK)

LPI2C2_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

◆ IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK)

LPI2C3_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

◆ IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK)

LPI2C3_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

◆ IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK)

LPI2C4_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

◆ IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK)

LPI2C4_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

◆ IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK)

LPSPI1_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

◆ IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK)

LPSPI1_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

◆ IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK)

LPSPI2_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

◆ IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK)

LPSPI2_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

◆ IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK)

LPSPI3_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

◆ IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK)

LPSPI3_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

◆ IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK)

LPSPI4_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

◆ IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK)

LPSPI4_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

◆ IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK)

LPUART1_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

◆ IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK)

LPUART1_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

◆ IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK)

LPUART2_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

◆ IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK)

LPUART2_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

◆ IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK)

LPUART3_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

◆ IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK)

LPUART3_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

◆ IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK)

LPUART4_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

◆ IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK)

LPUART4_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

◆ IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK)

LPUART5_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

◆ IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK)

LPUART5_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

◆ IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK)

LPUART6_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

◆ IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK)

LPUART6_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

◆ IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK)

LPUART7_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

◆ IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK)

LPUART7_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

◆ IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE

#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK)

LPUART8_IPG_DOZE 0b0..not in doze mode 0b1..in doze mode

◆ IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE

#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK)

LPUART8_IPG_STOP_MODE 0b0..the module is functional in Stop mode 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted

◆ IOMUXC_GPR_GPR8_WDOG1_MASK [1/2]

#define IOMUXC_GPR_GPR8_WDOG1_MASK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR8_WDOG1_MASK_MASK)

WDOG1_MASK - WDOG1 timeout mask for WDOG_ANY

◆ IOMUXC_GPR_GPR8_WDOG1_MASK [2/2]

#define IOMUXC_GPR_GPR8_WDOG1_MASK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR8_WDOG1_MASK_MASK)

WDOG1_MASK - WDOG1 timeout mask for WDOG_ANY

◆ IOMUXC_GPR_GPR9_DWP [1/2]

#define IOMUXC_GPR_GPR9_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_DWP_SHIFT)) & IOMUXC_GPR_GPR9_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR9_DWP [2/2]

#define IOMUXC_GPR_GPR9_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_DWP_SHIFT)) & IOMUXC_GPR_GPR9_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_GPR_GPR9_DWP_LOCK [1/2]

#define IOMUXC_GPR_GPR9_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR9_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR9_DWP_LOCK [2/2]

#define IOMUXC_GPR_GPR9_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR9_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_GPR_GPR9_WDOG2_MASK [1/2]

#define IOMUXC_GPR_GPR9_WDOG2_MASK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR9_WDOG2_MASK_MASK)

WDOG2_MASK - WDOG2 timeout mask for WDOG_ANY

◆ IOMUXC_GPR_GPR9_WDOG2_MASK [2/2]

#define IOMUXC_GPR_GPR9_WDOG2_MASK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR9_WDOG2_MASK_MASK)

WDOG2_MASK - WDOG2 timeout mask for WDOG_ANY

◆ IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW [1/2]

#define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK)

CM4_INIT_VTOR_LOW - CM4 Vector table offset value lower bits out of reset

◆ IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW [2/2]

#define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK)

CM4_INIT_VTOR_LOW - CM4 Vector table offset value lower bits out of reset

◆ IOMUXC_LPSR_GPR_GPR0_DWP [1/2]

#define IOMUXC_LPSR_GPR_GPR0_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_LPSR_GPR_GPR0_DWP [2/2]

#define IOMUXC_LPSR_GPR_GPR0_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_LPSR_GPR_GPR0_DWP_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_LPSR_GPR_GPR0_DWP_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT [1/2]

#define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK)

APC_AC_R4_BOT - APC start address of memory region-4

◆ IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT [2/2]

#define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK)

APC_AC_R4_BOT - APC start address of memory region-4

◆ IOMUXC_LPSR_GPR_GPR10_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR10_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR10_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR10_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP [1/2]

#define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK)

APC_AC_R4_TOP - APC end address of memory region-4

◆ IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP [2/2]

#define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK)

APC_AC_R4_TOP - APC end address of memory region-4

◆ IOMUXC_LPSR_GPR_GPR11_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR11_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR11_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR11_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT [1/2]

#define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK)

APC_AC_R5_BOT - APC start address of memory region-5

◆ IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT [2/2]

#define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK)

APC_AC_R5_BOT - APC start address of memory region-5

◆ IOMUXC_LPSR_GPR_GPR12_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR12_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR12_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR12_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP [1/2]

#define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK)

APC_AC_R5_TOP - APC end address of memory region-5

◆ IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP [2/2]

#define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK)

APC_AC_R5_TOP - APC end address of memory region-5

◆ IOMUXC_LPSR_GPR_GPR13_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR13_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR13_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR13_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT [1/2]

#define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK)

APC_AC_R6_BOT - APC start address of memory region-6

◆ IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT [2/2]

#define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK)

APC_AC_R6_BOT - APC start address of memory region-6

◆ IOMUXC_LPSR_GPR_GPR14_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR14_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR14_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR14_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP [1/2]

#define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK)

APC_AC_R6_TOP - APC end address of memory region-6

◆ IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP [2/2]

#define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK)

APC_AC_R6_TOP - APC end address of memory region-6

◆ IOMUXC_LPSR_GPR_GPR15_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR15_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR15_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR15_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT [1/2]

#define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK)

APC_AC_R7_BOT - APC start address of memory region-7

◆ IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT [2/2]

#define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK)

APC_AC_R7_BOT - APC start address of memory region-7

◆ IOMUXC_LPSR_GPR_GPR16_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR16_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR16_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR16_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP [1/2]

#define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK)

APC_AC_R7_TOP - APC end address of memory region-7

◆ IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP [2/2]

#define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK)

APC_AC_R7_TOP - APC end address of memory region-7

◆ IOMUXC_LPSR_GPR_GPR17_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR17_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR17_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR17_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE [1/2]

#define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK)

APC_R0_ENCRYPT_ENABLE - APC memory region-0 encryption enable 0b1..Encryption enabled 0b0..No effect

◆ IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE [2/2]

#define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK)

APC_R0_ENCRYPT_ENABLE - APC memory region-0 encryption enable 0b1..Encryption enabled 0b0..No effect

◆ IOMUXC_LPSR_GPR_GPR18_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR18_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_LOCK_MASK)

LOCK - Lock the write to bit 15:0

◆ IOMUXC_LPSR_GPR_GPR18_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR18_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_LOCK_MASK)

LOCK - Lock the write to bit 15:0

◆ IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH [1/2]

#define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK)

CM4_INIT_VTOR_HIGH - CM4 Vector table offset value higher bits out of reset

◆ IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH [2/2]

#define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK)

CM4_INIT_VTOR_HIGH - CM4 Vector table offset value higher bits out of reset

◆ IOMUXC_LPSR_GPR_GPR1_DWP [1/2]

#define IOMUXC_LPSR_GPR_GPR1_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_LPSR_GPR_GPR1_DWP [2/2]

#define IOMUXC_LPSR_GPR_GPR1_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_LPSR_GPR_GPR1_DWP_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_LPSR_GPR_GPR1_DWP_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE [1/2]

#define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK)

APC_R2_ENCRYPT_ENABLE - APC memory region-2 encryption enable 0b1..Encryption enabled 0b0..No effect

◆ IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE [2/2]

#define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK)

APC_R2_ENCRYPT_ENABLE - APC memory region-2 encryption enable 0b1..Encryption enabled 0b0..No effect

◆ IOMUXC_LPSR_GPR_GPR20_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR20_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_LOCK_MASK)

LOCK - Lock the write to bit 15:0

◆ IOMUXC_LPSR_GPR_GPR20_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR20_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_LOCK_MASK)

LOCK - Lock the write to bit 15:0

◆ IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE [1/2]

#define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK)

APC_R3_ENCRYPT_ENABLE - APC memory region-3 encryption enable 0b1..Encryption enabled 0b0..No effect

◆ IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE [2/2]

#define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK)

APC_R3_ENCRYPT_ENABLE - APC memory region-3 encryption enable 0b1..Encryption enabled 0b0..No effect

◆ IOMUXC_LPSR_GPR_GPR21_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR21_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_LOCK_MASK)

LOCK - Lock the write to bit 15:0

◆ IOMUXC_LPSR_GPR_GPR21_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR21_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_LOCK_MASK)

LOCK - Lock the write to bit 15:0

◆ IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE [1/2]

#define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK)

APC_R4_ENCRYPT_ENABLE - APC memory region-4 encryption enable 0b1..Encryption enabled 0b0..No effect

◆ IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE [2/2]

#define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK)

APC_R4_ENCRYPT_ENABLE - APC memory region-4 encryption enable 0b1..Encryption enabled 0b0..No effect

◆ IOMUXC_LPSR_GPR_GPR22_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR22_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_LOCK_MASK)

LOCK - Lock the write to bit 15:0

◆ IOMUXC_LPSR_GPR_GPR22_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR22_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_LOCK_MASK)

LOCK - Lock the write to bit 15:0

◆ IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE [1/2]

#define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK)

APC_R5_ENCRYPT_ENABLE - APC memory region-5 encryption enable 0b1..Encryption enabled 0b0..No effect

◆ IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE [2/2]

#define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK)

APC_R5_ENCRYPT_ENABLE - APC memory region-5 encryption enable 0b1..Encryption enabled 0b0..No effect

◆ IOMUXC_LPSR_GPR_GPR23_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR23_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_LOCK_MASK)

LOCK - Lock the write to bit 15:0

◆ IOMUXC_LPSR_GPR_GPR23_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR23_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_LOCK_MASK)

LOCK - Lock the write to bit 15:0

◆ IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE [1/2]

#define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK)

APC_R6_ENCRYPT_ENABLE - APC memory region-6 encryption enable 0b1..Encryption enabled 0b0..No effect

◆ IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE [2/2]

#define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK)

APC_R6_ENCRYPT_ENABLE - APC memory region-6 encryption enable 0b1..Encryption enabled 0b0..No effect

◆ IOMUXC_LPSR_GPR_GPR24_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR24_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_LOCK_MASK)

LOCK - Lock the write to bit 15:0

◆ IOMUXC_LPSR_GPR_GPR24_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR24_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_LOCK_MASK)

LOCK - Lock the write to bit 15:0

◆ IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE [1/2]

#define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK)

APC_R7_ENCRYPT_ENABLE - APC memory region-7 encryption enable 0b1..Encryption enabled 0b0..No effect

◆ IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE [2/2]

#define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK)

APC_R7_ENCRYPT_ENABLE - APC memory region-7 encryption enable 0b1..Encryption enabled 0b0..No effect

◆ IOMUXC_LPSR_GPR_GPR25_APC_VALID [1/2]

#define IOMUXC_LPSR_GPR_GPR25_APC_VALID (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK)

APC_VALID - APC global enable bit 0b1..Enable encryption for GPRx[APC_x_ENCRYPT_ENABLE] (valid for GPR2-GPR25) 0b0..No effect

◆ IOMUXC_LPSR_GPR_GPR25_APC_VALID [2/2]

#define IOMUXC_LPSR_GPR_GPR25_APC_VALID (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK)

APC_VALID - APC global enable bit 0b1..Enable encryption for GPRx[APC_x_ENCRYPT_ENABLE] (valid for GPR2-GPR25) 0b0..No effect

◆ IOMUXC_LPSR_GPR_GPR25_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR25_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_LOCK_MASK)

LOCK - Lock the write to bit 15:0

◆ IOMUXC_LPSR_GPR_GPR25_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR25_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_LOCK_MASK)

LOCK - Lock the write to bit 15:0

◆ IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR [1/2]

#define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK)

CM7_INIT_VTOR - Vector table offset register out of reset. See the ARM v7-M Architecture Reference Manual for more information about the vector table offset register (VTOR).

◆ IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR [2/2]

#define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK)

CM7_INIT_VTOR - Vector table offset register out of reset. See the ARM v7-M Architecture Reference Manual for more information about the vector table offset register (VTOR).

◆ IOMUXC_LPSR_GPR_GPR26_DWP [1/2]

#define IOMUXC_LPSR_GPR_GPR26_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_LPSR_GPR_GPR26_DWP [2/2]

#define IOMUXC_LPSR_GPR_GPR26_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_LPSR_GPR_GPR26_DWP_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_LPSR_GPR_GPR26_DWP_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_LPSR_GPR_GPR26_FIELD_0 [1/2]

#define IOMUXC_LPSR_GPR_GPR26_FIELD_0 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK)

FIELD_0 - General purpose bits

◆ IOMUXC_LPSR_GPR_GPR26_FIELD_0 [2/2]

#define IOMUXC_LPSR_GPR_GPR26_FIELD_0 (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK)

FIELD_0 - General purpose bits

◆ IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT [1/2]

#define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK)

APC_AC_R0_BOT - APC start address of memory region-0

◆ IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT [2/2]

#define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK)

APC_AC_R0_BOT - APC start address of memory region-0

◆ IOMUXC_LPSR_GPR_GPR2_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR2_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR2_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR2_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR33_DWP [1/2]

#define IOMUXC_LPSR_GPR_GPR33_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_LPSR_GPR_GPR33_DWP [2/2]

#define IOMUXC_LPSR_GPR_GPR33_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_LPSR_GPR_GPR33_DWP_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_LPSR_GPR_GPR33_DWP_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR [1/2]

#define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK)

M4_NMI_CLEAR - Clear CM4 NMI holding register

◆ IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR [2/2]

#define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK)

M4_NMI_CLEAR - Clear CM4 NMI holding register

◆ IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR [1/2]

#define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK)

USBPHY1_WAKEUP_IRQ_CLEAR - Clear USBPHY1 wakeup interrupt holding register

◆ IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR [2/2]

#define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK)

USBPHY1_WAKEUP_IRQ_CLEAR - Clear USBPHY1 wakeup interrupt holding register

◆ IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR [1/2]

#define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK)

USBPHY2_WAKEUP_IRQ_CLEAR - Clear USBPHY1 wakeup interrupt holding register

◆ IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR [2/2]

#define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK)

USBPHY2_WAKEUP_IRQ_CLEAR - Clear USBPHY1 wakeup interrupt holding register

◆ IOMUXC_LPSR_GPR_GPR34_DWP [1/2]

#define IOMUXC_LPSR_GPR_GPR34_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_LPSR_GPR_GPR34_DWP [2/2]

#define IOMUXC_LPSR_GPR_GPR34_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_LPSR_GPR_GPR34_DWP_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_LPSR_GPR_GPR34_DWP_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE [1/2]

#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK)

GPIO_LPSR_HIGH_RANGE - GPIO_LPSR IO bank supply voltage range selection

◆ IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE [2/2]

#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK)

GPIO_LPSR_HIGH_RANGE - GPIO_LPSR IO bank supply voltage range selection

◆ IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE [1/2]

#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK)

GPIO_LPSR_LOW_RANGE - GPIO_LPSR IO bank supply voltage range selection

◆ IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE [2/2]

#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK)

GPIO_LPSR_LOW_RANGE - GPIO_LPSR IO bank supply voltage range selection

◆ IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL [1/2]

#define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK)

M4_GPC_SLEEP_SEL - CM4 sleep request selection 0b0..CM4 SLEEPDEEP is sent to GPC 0b1..CM4 SLEEPING is sent to GPC

◆ IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL [2/2]

#define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK)

M4_GPC_SLEEP_SEL - CM4 sleep request selection 0b0..CM4 SLEEPDEEP is sent to GPC 0b1..CM4 SLEEPING is sent to GPC

◆ IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK [1/2]

#define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK)

M4_NMI_MASK - Mask CM4 NMI pin input 0b0..NMI input from IO to CM4 is not blocked 0b1..NMI input from IO to CM4 is blocked

◆ IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK [2/2]

#define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK)

M4_NMI_MASK - Mask CM4 NMI pin input 0b0..NMI input from IO to CM4 is not blocked 0b1..NMI input from IO to CM4 is blocked

◆ IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK [1/2]

#define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK)

M7_NMI_MASK - Mask CM7 NMI pin input 0b0..NMI input from IO to CM7 is not blocked 0b1..NMI input from IO to CM7 is blocked

◆ IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK [2/2]

#define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK)

M7_NMI_MASK - Mask CM7 NMI pin input 0b0..NMI input from IO to CM7 is not blocked 0b1..NMI input from IO to CM7 is blocked

◆ IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP [1/2]

#define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK)

SEC_ERR_RESP - Security error response enable 0b0..OKEY response 0b1..SLVError (default)

◆ IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP [2/2]

#define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK)

SEC_ERR_RESP - Security error response enable 0b0..OKEY response 0b1..SLVError (default)

◆ IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK)

ADC1_IPG_DOZE - ADC1 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK)

ADC1_IPG_DOZE - ADC1 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK)

ADC1_IPG_STOP_MODE - ADC1 stop mode selection. This bitfield cannot change when ADC1_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK)

ADC1_IPG_STOP_MODE - ADC1 stop mode selection. This bitfield cannot change when ADC1_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK)

ADC1_STOP_REQ - ADC1 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK)

ADC1_STOP_REQ - ADC1 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK)

ADC2_IPG_DOZE - ADC2 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK)

ADC2_IPG_DOZE - ADC2 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK)

ADC2_IPG_STOP_MODE - ADC2 stop mode selection. This bitfield cannot change when ADC2_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK)

ADC2_IPG_STOP_MODE - ADC2 stop mode selection. This bitfield cannot change when ADC2_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK)

ADC2_STOP_REQ - ADC2 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK)

ADC2_STOP_REQ - ADC2 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK)

CAAM_IPG_DOZE - CAN3 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK)

CAAM_IPG_DOZE - CAN3 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK)

CAAM_STOP_REQ - CAAM stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK)

CAAM_STOP_REQ - CAAM stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK)

CAN1_IPG_DOZE - CAN1 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK)

CAN1_IPG_DOZE - CAN1 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK)

CAN1_STOP_REQ - CAN1 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK)

CAN1_STOP_REQ - CAN1 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK)

CAN2_IPG_DOZE - CAN2 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK)

CAN2_IPG_DOZE - CAN2 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK)

CAN2_STOP_REQ - CAN2 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK)

CAN2_STOP_REQ - CAN2 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK)

CAN3_IPG_DOZE - CAN3 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK)

CAN3_IPG_DOZE - CAN3 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK)

CAN3_STOP_REQ - CAN3 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK)

CAN3_STOP_REQ - CAN3 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR35_DWP [1/2]

#define IOMUXC_LPSR_GPR_GPR35_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_LPSR_GPR_GPR35_DWP [2/2]

#define IOMUXC_LPSR_GPR_GPR35_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_LPSR_GPR_GPR35_DWP_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_LPSR_GPR_GPR35_DWP_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK)

EDMA_LPSR_STOP_REQ - EDMA_LPSR stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK)

EDMA_LPSR_STOP_REQ - EDMA_LPSR stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK)

EDMA_STOP_REQ - EDMA stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK)

EDMA_STOP_REQ - EDMA stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK)

ENET1G_IPG_DOZE - ENET1G doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK)

ENET1G_IPG_DOZE - ENET1G doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK)

ENET1G_STOP_REQ - ENET1G stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK)

ENET1G_STOP_REQ - ENET1G stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK)

ENET_IPG_DOZE - ENET doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK)

ENET_IPG_DOZE - ENET doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK)

ENET_STOP_REQ - ENET stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK)

ENET_STOP_REQ - ENET stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK)

FLEXIO1_IPG_DOZE - FLEXIO2 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK)

FLEXIO1_IPG_DOZE - FLEXIO2 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK)

FLEXIO2_IPG_DOZE - FLEXIO2 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK)

FLEXIO2_IPG_DOZE - FLEXIO2 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK)

FLEXSPI1_IPG_DOZE - FLEXSPI1 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK)

FLEXSPI1_IPG_DOZE - FLEXSPI1 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK)

FLEXSPI1_STOP_REQ - FLEXSPI1 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK)

FLEXSPI1_STOP_REQ - FLEXSPI1 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK)

FLEXSPI2_IPG_DOZE - FLEXSPI2 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK)

FLEXSPI2_IPG_DOZE - FLEXSPI2 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK)

FLEXSPI2_STOP_REQ - FLEXSPI2 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK)

FLEXSPI2_STOP_REQ - FLEXSPI2 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR36_DWP [1/2]

#define IOMUXC_LPSR_GPR_GPR36_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_LPSR_GPR_GPR36_DWP [2/2]

#define IOMUXC_LPSR_GPR_GPR36_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_LPSR_GPR_GPR36_DWP_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_LPSR_GPR_GPR36_DWP_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK)

GPT1_IPG_DOZE - GPT1 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK)

GPT1_IPG_DOZE - GPT1 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK)

GPT2_IPG_DOZE - GPT2 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK)

GPT2_IPG_DOZE - GPT2 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK)

GPT3_IPG_DOZE - GPT3 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK)

GPT3_IPG_DOZE - GPT3 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK)

GPT4_IPG_DOZE - GPT4 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK)

GPT4_IPG_DOZE - GPT4 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK)

GPT5_IPG_DOZE - GPT5 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK)

GPT5_IPG_DOZE - GPT5 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK)

GPT6_IPG_DOZE - GPT6 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK)

GPT6_IPG_DOZE - GPT6 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK)

LPI2C1_IPG_DOZE - LPI2C1 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK)

LPI2C1_IPG_DOZE - LPI2C1 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK)

LPI2C1_IPG_STOP_MODE - LPI2C1 stop mode selection. This bitfield cannot change when LPI2C1_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK)

LPI2C1_IPG_STOP_MODE - LPI2C1 stop mode selection. This bitfield cannot change when LPI2C1_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK)

LPI2C1_STOP_REQ - LPI2C1 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK)

LPI2C1_STOP_REQ - LPI2C1 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK)

LPI2C2_IPG_DOZE - LPI2C2 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK)

LPI2C2_IPG_DOZE - LPI2C2 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK)

LPI2C2_IPG_STOP_MODE - LPI2C2 stop mode selection. This bitfield cannot change when LPI2C2_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK)

LPI2C2_IPG_STOP_MODE - LPI2C2 stop mode selection. This bitfield cannot change when LPI2C2_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK)

LPI2C2_STOP_REQ - LPI2C2 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK)

LPI2C2_STOP_REQ - LPI2C2 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK)

LPI2C3_IPG_DOZE - LPI2C3 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK)

LPI2C3_IPG_DOZE - LPI2C3 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK)

LPI2C3_IPG_STOP_MODE - LPI2C3 stop mode selection. This bitfield cannot change when LPI2C3_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK)

LPI2C3_IPG_STOP_MODE - LPI2C3 stop mode selection. This bitfield cannot change when LPI2C3_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK)

LPI2C3_STOP_REQ - LPI2C3 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK)

LPI2C3_STOP_REQ - LPI2C3 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK)

LPI2C4_IPG_DOZE - LPI2C4 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK)

LPI2C4_IPG_DOZE - LPI2C4 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK)

LPI2C4_IPG_STOP_MODE - LPI2C4 stop mode selection. This bitfield cannot change when LPI2C4_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK)

LPI2C4_IPG_STOP_MODE - LPI2C4 stop mode selection. This bitfield cannot change when LPI2C4_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK)

LPI2C4_STOP_REQ - LPI2C4 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK)

LPI2C4_STOP_REQ - LPI2C4 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK)

LPI2C5_IPG_DOZE - LPI2C5 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK)

LPI2C5_IPG_DOZE - LPI2C5 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK)

LPI2C5_IPG_STOP_MODE - LPI2C5 stop mode selection. This bitfield cannot change when LPI2C5_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK)

LPI2C5_IPG_STOP_MODE - LPI2C5 stop mode selection. This bitfield cannot change when LPI2C5_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK)

LPI2C5_STOP_REQ - LPI2C5 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK)

LPI2C5_STOP_REQ - LPI2C5 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK)

LPI2C6_IPG_DOZE - LPI2C6 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK)

LPI2C6_IPG_DOZE - LPI2C6 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK)

LPI2C6_IPG_STOP_MODE - LPI2C6 stop mode selection. This bitfield cannot change when LPI2C6_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK)

LPI2C6_IPG_STOP_MODE - LPI2C6 stop mode selection. This bitfield cannot change when LPI2C6_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK)

LPI2C6_STOP_REQ - LPI2C6 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK)

LPI2C6_STOP_REQ - LPI2C6 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK)

LPSPI1_IPG_DOZE - LPSPI1 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK)

LPSPI1_IPG_DOZE - LPSPI1 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK)

LPSPI1_IPG_STOP_MODE - LPSPI1 stop mode selection. This bitfield cannot change when LPSPI1_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK)

LPSPI1_IPG_STOP_MODE - LPSPI1 stop mode selection. This bitfield cannot change when LPSPI1_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK)

LPSPI1_STOP_REQ - LPSPI1 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK)

LPSPI1_STOP_REQ - LPSPI1 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR37_DWP [1/2]

#define IOMUXC_LPSR_GPR_GPR37_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_LPSR_GPR_GPR37_DWP [2/2]

#define IOMUXC_LPSR_GPR_GPR37_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_LPSR_GPR_GPR37_DWP_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_LPSR_GPR_GPR37_DWP_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK)

LPSPI2_IPG_DOZE - LPSPI2 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK)

LPSPI2_IPG_DOZE - LPSPI2 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK)

LPSPI2_IPG_STOP_MODE - LPSPI2 stop mode selection. This bitfield cannot change when LPSPI2_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK)

LPSPI2_IPG_STOP_MODE - LPSPI2 stop mode selection. This bitfield cannot change when LPSPI2_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK)

LPSPI2_STOP_REQ - LPSPI2 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK)

LPSPI2_STOP_REQ - LPSPI2 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK)

LPSPI3_IPG_DOZE - LPSPI3 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK)

LPSPI3_IPG_DOZE - LPSPI3 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK)

LPSPI3_IPG_STOP_MODE - LPSPI3 stop mode selection. This bitfield cannot change when LPSPI3_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK)

LPSPI3_IPG_STOP_MODE - LPSPI3 stop mode selection. This bitfield cannot change when LPSPI3_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK)

LPSPI3_STOP_REQ - LPSPI3 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK)

LPSPI3_STOP_REQ - LPSPI3 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK)

LPSPI4_IPG_DOZE - LPSPI4 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK)

LPSPI4_IPG_DOZE - LPSPI4 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK)

LPSPI4_IPG_STOP_MODE - LPSPI4 stop mode selection. This bitfield cannot change when LPSPI4_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK)

LPSPI4_IPG_STOP_MODE - LPSPI4 stop mode selection. This bitfield cannot change when LPSPI4_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK)

LPSPI4_STOP_REQ - LPSPI4 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK)

LPSPI4_STOP_REQ - LPSPI4 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK)

LPSPI5_IPG_DOZE - LPSPI5 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK)

LPSPI5_IPG_DOZE - LPSPI5 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK)

LPSPI5_IPG_STOP_MODE - LPSPI5 stop mode selection. This bitfield cannot change when LPSPI5_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK)

LPSPI5_IPG_STOP_MODE - LPSPI5 stop mode selection. This bitfield cannot change when LPSPI5_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK)

LPSPI5_STOP_REQ - LPSPI5 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK)

LPSPI5_STOP_REQ - LPSPI5 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK)

LPSPI6_IPG_DOZE - LPSPI6 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK)

LPSPI6_IPG_DOZE - LPSPI6 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK)

LPSPI6_IPG_STOP_MODE - LPSPI6 stop mode selection. This bitfield cannot change when LPSPI6_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK)

LPSPI6_IPG_STOP_MODE - LPSPI6 stop mode selection. This bitfield cannot change when LPSPI6_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK)

LPSPI6_STOP_REQ - LPSPI6 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK)

LPSPI6_STOP_REQ - LPSPI6 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK)

LPUART1_IPG_DOZE - LPUART1 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK)

LPUART1_IPG_DOZE - LPUART1 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK)

LPUART1_IPG_STOP_MODE - LPUART1 stop mode selection. This bitfield cannot change when LPUART1_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK)

LPUART1_IPG_STOP_MODE - LPUART1 stop mode selection. This bitfield cannot change when LPUART1_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK)

LPUART1_STOP_REQ - LPUART1 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK)

LPUART1_STOP_REQ - LPUART1 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK)

LPUART2_IPG_DOZE - LPUART2 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK)

LPUART2_IPG_DOZE - LPUART2 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK)

LPUART2_IPG_STOP_MODE - LPUART2 stop mode selection. This bitfield cannot change when LPUART2_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK)

LPUART2_IPG_STOP_MODE - LPUART2 stop mode selection. This bitfield cannot change when LPUART2_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK)

LPUART2_STOP_REQ - LPUART2 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK)

LPUART2_STOP_REQ - LPUART2 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK)

LPUART3_IPG_DOZE - LPUART3 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK)

LPUART3_IPG_DOZE - LPUART3 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK)

LPUART3_IPG_STOP_MODE - LPUART3 stop mode selection. This bitfield cannot change when LPUART3_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK)

LPUART3_IPG_STOP_MODE - LPUART3 stop mode selection. This bitfield cannot change when LPUART3_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK)

LPUART3_STOP_REQ - LPUART3 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK)

LPUART3_STOP_REQ - LPUART3 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK)

LPUART4_IPG_DOZE - LPUART4 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK)

LPUART4_IPG_DOZE - LPUART4 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK)

LPUART4_IPG_STOP_MODE - LPUART4 stop mode selection. This bitfield cannot change when LPUART4_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK)

LPUART4_IPG_STOP_MODE - LPUART4 stop mode selection. This bitfield cannot change when LPUART4_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK)

LPUART4_STOP_REQ - LPUART4 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK)

LPUART4_STOP_REQ - LPUART4 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR38_DWP [1/2]

#define IOMUXC_LPSR_GPR_GPR38_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_LPSR_GPR_GPR38_DWP [2/2]

#define IOMUXC_LPSR_GPR_GPR38_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_LPSR_GPR_GPR38_DWP_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_LPSR_GPR_GPR38_DWP_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK)

LPUART10_IPG_DOZE - LPUART10 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK)

LPUART10_IPG_DOZE - LPUART10 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK)

LPUART10_IPG_STOP_MODE - LPUART10 stop mode selection. This bitfield cannot change when LPUART10_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK)

LPUART10_IPG_STOP_MODE - LPUART10 stop mode selection. This bitfield cannot change when LPUART10_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK)

LPUART10_STOP_REQ - LPUART10 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK)

LPUART10_STOP_REQ - LPUART10 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK)

LPUART11_IPG_DOZE - LPUART11 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK)

LPUART11_IPG_DOZE - LPUART11 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK)

LPUART11_IPG_STOP_MODE - LPUART11 stop mode selection. This bitfield cannot change when LPUART11_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK)

LPUART11_IPG_STOP_MODE - LPUART11 stop mode selection. This bitfield cannot change when LPUART11_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK)

LPUART11_STOP_REQ - LPUART11 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK)

LPUART11_STOP_REQ - LPUART11 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK)

LPUART12_IPG_DOZE - LPUART12 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK)

LPUART12_IPG_DOZE - LPUART12 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK)

LPUART12_IPG_STOP_MODE - LPUART12 stop mode selection. This bitfield cannot change when LPUART12_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK)

LPUART12_IPG_STOP_MODE - LPUART12 stop mode selection. This bitfield cannot change when LPUART12_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK)

LPUART12_STOP_REQ - LPUART12 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK)

LPUART12_STOP_REQ - LPUART12 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK)

LPUART5_IPG_DOZE - LPUART5 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK)

LPUART5_IPG_DOZE - LPUART5 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK)

LPUART5_IPG_STOP_MODE - LPUART5 stop mode selection. This bitfield cannot change when LPUART5_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK)

LPUART5_IPG_STOP_MODE - LPUART5 stop mode selection. This bitfield cannot change when LPUART5_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK)

LPUART5_STOP_REQ - LPUART5 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK)

LPUART5_STOP_REQ - LPUART5 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK)

LPUART6_IPG_DOZE - LPUART6 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK)

LPUART6_IPG_DOZE - LPUART6 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK)

LPUART6_IPG_STOP_MODE - LPUART6 stop mode selection. This bitfield cannot change when LPUART6_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK)

LPUART6_IPG_STOP_MODE - LPUART6 stop mode selection. This bitfield cannot change when LPUART6_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK)

LPUART6_STOP_REQ - LPUART6 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK)

LPUART6_STOP_REQ - LPUART6 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK)

LPUART7_IPG_DOZE - LPUART7 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK)

LPUART7_IPG_DOZE - LPUART7 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK)

LPUART7_IPG_STOP_MODE - LPUART7 stop mode selection. This bitfield cannot change when LPUART7_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK)

LPUART7_IPG_STOP_MODE - LPUART7 stop mode selection. This bitfield cannot change when LPUART7_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK)

LPUART7_STOP_REQ - LPUART7 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK)

LPUART7_STOP_REQ - LPUART7 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK)

LPUART8_IPG_DOZE - LPUART8 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK)

LPUART8_IPG_DOZE - LPUART8 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK)

LPUART8_IPG_STOP_MODE - LPUART8 stop mode selection. This bitfield cannot change when LPUART8_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK)

LPUART8_IPG_STOP_MODE - LPUART8 stop mode selection. This bitfield cannot change when LPUART8_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK)

LPUART8_STOP_REQ - LPUART8 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK)

LPUART8_STOP_REQ - LPUART8 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK)

LPUART9_IPG_DOZE - LPUART9 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK)

LPUART9_IPG_DOZE - LPUART9 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK)

LPUART9_IPG_STOP_MODE - LPUART9 stop mode selection. This bitfield cannot change when LPUART9_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK)

LPUART9_IPG_STOP_MODE - LPUART9 stop mode selection. This bitfield cannot change when LPUART9_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK)

LPUART9_STOP_REQ - LPUART9 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK)

LPUART9_STOP_REQ - LPUART9 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK)

MIC_IPG_DOZE - MIC doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK)

MIC_IPG_DOZE - MIC doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE [1/2]

#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK)

MIC_IPG_STOP_MODE - MIC stop mode selection. This bitfield cannot change when MIC_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE [2/2]

#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK)

MIC_IPG_STOP_MODE - MIC stop mode selection. This bitfield cannot change when MIC_STOP_REQ is asserted. 0b0..This module is functional in Stop Mode 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.

◆ IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK)

MIC_STOP_REQ - MIC stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK)

MIC_STOP_REQ - MIC stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR39_DWP [1/2]

#define IOMUXC_LPSR_GPR_GPR39_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_LPSR_GPR_GPR39_DWP [2/2]

#define IOMUXC_LPSR_GPR_GPR39_DWP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_LPSR_GPR_GPR39_DWP_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_LPSR_GPR_GPR39_DWP_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS [1/2]

#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK)

FLEXIO1_STOP_REQ_BUS - FLEXIO1 bus clock domain stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS [2/2]

#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK)

FLEXIO1_STOP_REQ_BUS - FLEXIO1 bus clock domain stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER [1/2]

#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK)

FLEXIO1_STOP_REQ_PER - FLEXIO1 peripheral clock domain stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER [2/2]

#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK)

FLEXIO1_STOP_REQ_PER - FLEXIO1 peripheral clock domain stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS [1/2]

#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK)

FLEXIO2_STOP_REQ_BUS - FLEXIO2 bus clock domain stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS [2/2]

#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK)

FLEXIO2_STOP_REQ_BUS - FLEXIO2 bus clock domain stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER [1/2]

#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK)

FLEXIO2_STOP_REQ_PER - FLEXIO2 peripheral clock domain stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER [2/2]

#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK)

FLEXIO2_STOP_REQ_PER - FLEXIO2 peripheral clock domain stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK)

PIT1_STOP_REQ - PIT1 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK)

PIT1_STOP_REQ - PIT1 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK)

PIT2_STOP_REQ - PIT2 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK)

PIT2_STOP_REQ - PIT2 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK)

SAI1_STOP_REQ - SAI1 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK)

SAI1_STOP_REQ - SAI1 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK)

SAI2_STOP_REQ - SAI2 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK)

SAI2_STOP_REQ - SAI2 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK)

SAI3_STOP_REQ - SAI3 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK)

SAI3_STOP_REQ - SAI3 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK)

SAI4_STOP_REQ - SAI4 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK)

SAI4_STOP_REQ - SAI4 stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK)

SEMC_STOP_REQ - SEMC stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK)

SEMC_STOP_REQ - SEMC stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK)

SIM1_IPG_DOZE - SIM1 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK)

SIM1_IPG_DOZE - SIM1 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK)

SIM2_IPG_DOZE - SIM2 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK)

SIM2_IPG_DOZE - SIM2 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK)

SNVS_HP_IPG_DOZE - SNVS_HP doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK)

SNVS_HP_IPG_DOZE - SNVS_HP doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ [1/2]

#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK)

SNVS_HP_STOP_REQ - SNVS_HP stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ [2/2]

#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK)

SNVS_HP_STOP_REQ - SNVS_HP stop request 0b0..Stop request off 0b1..Stop request on

◆ IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK)

WDOG1_IPG_DOZE - WDOG1 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK)

WDOG1_IPG_DOZE - WDOG1 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE [1/2]

#define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK)

WDOG2_IPG_DOZE - WDOG2 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE [2/2]

#define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK)

WDOG2_IPG_DOZE - WDOG2 doze mode 0b0..Not in doze mode 0b1..In doze mode

◆ IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP [1/2]

#define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK)

APC_AC_R0_TOP - APC end address of memory region-0

◆ IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP [2/2]

#define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK)

APC_AC_R0_TOP - APC end address of memory region-0

◆ IOMUXC_LPSR_GPR_GPR3_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR3_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR3_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR3_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK)

ADC1_STOP_ACK - ADC1 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK)

ADC1_STOP_ACK - ADC1 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK)

ADC2_STOP_ACK - ADC2 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK)

ADC2_STOP_ACK - ADC2 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK)

CAAM_STOP_ACK - CAAM stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK)

CAAM_STOP_ACK - CAAM stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK)

CAN1_STOP_ACK - CAN1 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK)

CAN1_STOP_ACK - CAN1 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK)

CAN2_STOP_ACK - CAN2 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK)

CAN2_STOP_ACK - CAN2 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK)

CAN3_STOP_ACK - CAN3 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK)

CAN3_STOP_ACK - CAN3 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK)

EDMA_LPSR_STOP_ACK - EDMA_LPSR stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK)

EDMA_LPSR_STOP_ACK - EDMA_LPSR stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK)

EDMA_STOP_ACK - EDMA stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK)

EDMA_STOP_ACK - EDMA stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK)

ENET1G_STOP_ACK - ENET1G stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK)

ENET1G_STOP_ACK - ENET1G stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK)

ENET_STOP_ACK - ENET stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK)

ENET_STOP_ACK - ENET stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK)

FLEXSPI1_STOP_ACK - FLEXSPI1 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK)

FLEXSPI1_STOP_ACK - FLEXSPI1 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK)

FLEXSPI2_STOP_ACK - FLEXSPI2 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK)

FLEXSPI2_STOP_ACK - FLEXSPI2 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK)

LPI2C1_STOP_ACK - LPI2C1 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK)

LPI2C1_STOP_ACK - LPI2C1 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK)

LPI2C2_STOP_ACK - LPI2C2 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK)

LPI2C2_STOP_ACK - LPI2C2 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK)

LPI2C3_STOP_ACK - LPI2C3 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK)

LPI2C3_STOP_ACK - LPI2C3 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK)

LPI2C4_STOP_ACK - LPI2C4 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK)

LPI2C4_STOP_ACK - LPI2C4 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK)

LPI2C5_STOP_ACK - LPI2C5 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK)

LPI2C5_STOP_ACK - LPI2C5 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK)

LPI2C6_STOP_ACK - LPI2C6 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK)

LPI2C6_STOP_ACK - LPI2C6 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK)

LPSPI1_STOP_ACK - LPSPI1 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK)

LPSPI1_STOP_ACK - LPSPI1 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK)

LPSPI2_STOP_ACK - LPSPI2 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK)

LPSPI2_STOP_ACK - LPSPI2 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK)

LPSPI3_STOP_ACK - LPSPI3 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK)

LPSPI3_STOP_ACK - LPSPI3 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK)

LPSPI4_STOP_ACK - LPSPI4 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK)

LPSPI4_STOP_ACK - LPSPI4 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK)

LPSPI5_STOP_ACK - LPSPI5 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK)

LPSPI5_STOP_ACK - LPSPI5 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK)

LPSPI6_STOP_ACK - LPSPI6 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK)

LPSPI6_STOP_ACK - LPSPI6 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK)

LPUART1_STOP_ACK - LPUART1 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK)

LPUART1_STOP_ACK - LPUART1 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK)

LPUART2_STOP_ACK - LPUART2 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK)

LPUART2_STOP_ACK - LPUART2 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK)

LPUART3_STOP_ACK - LPUART3 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK)

LPUART3_STOP_ACK - LPUART3 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK)

LPUART4_STOP_ACK - LPUART4 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK)

LPUART4_STOP_ACK - LPUART4 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK)

LPUART5_STOP_ACK - LPUART5 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK)

LPUART5_STOP_ACK - LPUART5 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK)

LPUART6_STOP_ACK - LPUART6 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK)

LPUART6_STOP_ACK - LPUART6 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK)

LPUART7_STOP_ACK - LPUART7 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK)

LPUART7_STOP_ACK - LPUART7 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK)

LPUART8_STOP_ACK - LPUART8 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK)

LPUART8_STOP_ACK - LPUART8 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS [1/2]

#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK)

FLEXIO1_STOP_ACK_BUS - FLEXIO1 stop acknowledge of bus clock domain

◆ IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS [2/2]

#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK)

FLEXIO1_STOP_ACK_BUS - FLEXIO1 stop acknowledge of bus clock domain

◆ IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER [1/2]

#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK)

FLEXIO1_STOP_ACK_PER - FLEXIO1 stop acknowledge of peripheral clock domain

◆ IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER [2/2]

#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK)

FLEXIO1_STOP_ACK_PER - FLEXIO1 stop acknowledge of peripheral clock domain

◆ IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS [1/2]

#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK)

FLEXIO2_STOP_ACK_BUS - FLEXIO2 stop acknowledge of bus clock domain

◆ IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS [2/2]

#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK)

FLEXIO2_STOP_ACK_BUS - FLEXIO2 stop acknowledge of bus clock domain

◆ IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER [1/2]

#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK)

FLEXIO2_STOP_ACK_PER - FLEXIO2 stop acknowledge of peripheral clock domain

◆ IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER [2/2]

#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK)

FLEXIO2_STOP_ACK_PER - FLEXIO2 stop acknowledge of peripheral clock domain

◆ IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK)

LPUART10_STOP_ACK - LPUART10 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK)

LPUART10_STOP_ACK - LPUART10 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK)

LPUART11_STOP_ACK - LPUART11 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK)

LPUART11_STOP_ACK - LPUART11 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK)

LPUART12_STOP_ACK - LPUART12 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK)

LPUART12_STOP_ACK - LPUART12 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK)

LPUART9_STOP_ACK - LPUART9 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK)

LPUART9_STOP_ACK - LPUART9 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK)

MIC_STOP_ACK - MIC stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK)

MIC_STOP_ACK - MIC stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK)

PIT1_STOP_ACK - PIT1 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK)

PIT1_STOP_ACK - PIT1 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK)

PIT2_STOP_ACK - PIT2 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK)

PIT2_STOP_ACK - PIT2 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED [1/2]

#define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK)

ROM_READ_LOCKED - ROM read lock status bit

◆ IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED [2/2]

#define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK)

ROM_READ_LOCKED - ROM read lock status bit

◆ IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK)

SAI1_STOP_ACK - SAI1 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK)

SAI1_STOP_ACK - SAI1 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK)

SAI2_STOP_ACK - SAI2 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK)

SAI2_STOP_ACK - SAI2 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK)

SAI3_STOP_ACK - SAI3 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK)

SAI3_STOP_ACK - SAI3 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK)

SAI4_STOP_ACK - SAI4 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK)

SAI4_STOP_ACK - SAI4 stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK)

SEMC_STOP_ACK - SEMC stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK)

SEMC_STOP_ACK - SEMC stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK [1/2]

#define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK)

SNVS_HP_STOP_ACK - SNVS_HP stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK [2/2]

#define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK)

SNVS_HP_STOP_ACK - SNVS_HP stop acknowledge

◆ IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT [1/2]

#define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK)

APC_AC_R1_BOT - APC start address of memory region-1

◆ IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT [2/2]

#define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK)

APC_AC_R1_BOT - APC start address of memory region-1

◆ IOMUXC_LPSR_GPR_GPR4_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR4_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR4_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR4_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP [1/2]

#define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK)

APC_AC_R1_TOP - APC end address of memory region-1

◆ IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP [2/2]

#define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK)

APC_AC_R1_TOP - APC end address of memory region-1

◆ IOMUXC_LPSR_GPR_GPR5_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR5_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR5_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR5_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP [1/2]

#define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK)

APC_AC_R2_TOP - APC end address of memory region-2

◆ IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP [2/2]

#define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK)

APC_AC_R2_TOP - APC end address of memory region-2

◆ IOMUXC_LPSR_GPR_GPR7_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR7_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR7_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR7_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT [1/2]

#define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK)

APC_AC_R3_BOT - APC start address of memory region-3

◆ IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT [2/2]

#define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK)

APC_AC_R3_BOT - APC start address of memory region-3

◆ IOMUXC_LPSR_GPR_GPR8_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR8_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR8_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR8_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP [1/2]

#define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK)

APC_AC_R3_TOP - APC end address of memory region-3

◆ IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP [2/2]

#define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK)

APC_AC_R3_TOP - APC end address of memory region-3

◆ IOMUXC_LPSR_GPR_GPR9_LOCK [1/2]

#define IOMUXC_LPSR_GPR_GPR9_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_LPSR_GPR_GPR9_LOCK [2/2]

#define IOMUXC_LPSR_GPR_GPR9_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b1..Write access to bit 31:1 is blocked 0b0..Write access to bit 31:1 is not blocked

◆ IOMUXC_SNVS_GPR_GPR32_GPR [1/2]

#define IOMUXC_SNVS_GPR_GPR32_GPR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_GPR_MASK)

GPR - General purpose bits

◆ IOMUXC_SNVS_GPR_GPR32_GPR [2/2]

#define IOMUXC_SNVS_GPR_GPR32_GPR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_GPR_MASK)

GPR - General purpose bits

◆ IOMUXC_SNVS_GPR_GPR32_LOCK [1/2]

#define IOMUXC_SNVS_GPR_GPR32_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK)

LOCK - Lock the write to bit 15:0

◆ IOMUXC_SNVS_GPR_GPR32_LOCK [2/2]

#define IOMUXC_SNVS_GPR_GPR32_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK)

LOCK - Lock the write to bit 15:0

◆ IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL [1/2]

#define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK)

DCDC_IN_LOW_VOL - DCDC_IN low voltage detect 0b1..Voltage on DCDC_IN is lower than 2.6V 0b0..Voltage on DCDC_IN is higher than 2.6V

◆ IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL [2/2]

#define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK)

DCDC_IN_LOW_VOL - DCDC_IN low voltage detect 0b1..Voltage on DCDC_IN is lower than 2.6V 0b0..Voltage on DCDC_IN is higher than 2.6V

◆ IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR [1/2]

#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK)

DCDC_OVER_CUR - DCDC output over current alert 0b1..Overcurrent on DCDC output 0b0..No Overcurrent on DCDC output

◆ IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR [2/2]

#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK)

DCDC_OVER_CUR - DCDC output over current alert 0b1..Overcurrent on DCDC output 0b0..No Overcurrent on DCDC output

◆ IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL [1/2]

#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK)

DCDC_OVER_VOL - DCDC output over voltage alert 0b1..Overvoltage on DCDC VDDLP0 or VDDLP8 output 0b0..No Overvoltage on DCDC VDDLP0 or VDDLP8 output

◆ IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL [2/2]

#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK)

DCDC_OVER_VOL - DCDC output over voltage alert 0b1..Overvoltage on DCDC VDDLP0 or VDDLP8 output 0b0..No Overvoltage on DCDC VDDLP0 or VDDLP8 output

◆ IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR [1/2]

#define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK)

DCDC_STATUS_CAPT_CLR - DCDC captured status clear 0b0..No change 0b1..Clear the 3 bits of DCDC captured status: DCDC_OVER_VOL, DCDC_OVER_CUR, and DCDC_IN_LOW_VOL

◆ IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR [2/2]

#define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK)

DCDC_STATUS_CAPT_CLR - DCDC captured status clear 0b0..No change 0b1..Clear the 3 bits of DCDC captured status: DCDC_OVER_VOL, DCDC_OVER_CUR, and DCDC_IN_LOW_VOL

◆ IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK [1/2]

#define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK)

DCDC_STS_DC_OK - DCDC status OK 0b0..DCDC is settling 0b1..DCDC already settled

◆ IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK [2/2]

#define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK)

DCDC_STS_DC_OK - DCDC status OK 0b0..DCDC is settling 0b1..DCDC already settled

◆ IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN [1/2]

#define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK)

SNVS_BYPASS_EN - SNVS LDO_SNVS_ANA bypass enable 0b1..Enable bypass 0b0..Disable bypass

◆ IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN [2/2]

#define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK)

SNVS_BYPASS_EN - SNVS LDO_SNVS_ANA bypass enable 0b1..Enable bypass 0b0..Disable bypass

◆ IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK [1/2]

#define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK)

SNVS_XTAL_CLK_OK - 32K OSC ok flag 0b1..32K oscillator is stable into normal operation 0b0..32K oscillator is NOT stable into normal operation

◆ IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK [2/2]

#define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK)

SNVS_XTAL_CLK_OK - 32K OSC ok flag 0b1..32K oscillator is stable into normal operation 0b0..32K oscillator is NOT stable into normal operation

◆ IOMUXC_SNVS_GPR_GPR34_LOCK [1/2]

#define IOMUXC_SNVS_GPR_GPR34_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b0..Write access is not blocked 0b1..Write access is blocked

◆ IOMUXC_SNVS_GPR_GPR34_LOCK [2/2]

#define IOMUXC_SNVS_GPR_GPR34_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b0..Write access is not blocked 0b1..Write access is blocked

◆ IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL [1/2]

#define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK)

SNVS_CAP_TRIM_SEL - SNVS OSC load capacitor trim select 0b0..The trimming codes are selected from eFuse 0b1..The trimming codes are used from SNVS_OSC_CAP_TRIM (osc32k's load capacitor)

◆ IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL [2/2]

#define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK)

SNVS_CAP_TRIM_SEL - SNVS OSC load capacitor trim select 0b0..The trimming codes are selected from eFuse 0b1..The trimming codes are used from SNVS_OSC_CAP_TRIM (osc32k's load capacitor)

◆ IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH [1/2]

#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK)

SNVS_CLK_DET_OFFSET_HIGH - SNVS clock detect offset of high boundary frequency 0b00..No change (Default) 0b01..Add +5 to the Trim 0b10..Add +10 to the trim 0b11..Add -5 to the Trim

◆ IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH [2/2]

#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK)

SNVS_CLK_DET_OFFSET_HIGH - SNVS clock detect offset of high boundary frequency 0b00..No change (Default) 0b01..Add +5 to the Trim 0b10..Add +10 to the trim 0b11..Add -5 to the Trim

◆ IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW [1/2]

#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK)

SNVS_CLK_DET_OFFSET_LOW - SNVS clock detect offset of low boundary frequency 0b00..No change (Default) 0b01..Add +5 to the Trim 0b10..Add +10 to the trim 0b11..Add -5 to the Trim

◆ IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW [2/2]

#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK)

SNVS_CLK_DET_OFFSET_LOW - SNVS clock detect offset of low boundary frequency 0b00..No change (Default) 0b01..Add +5 to the Trim 0b10..Add +10 to the trim 0b11..Add -5 to the Trim

◆ IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM [1/2]

#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK)

SNVS_CLK_DET_TRIM - SNVS clock detect trim bits

◆ IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM [2/2]

#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK)

SNVS_CLK_DET_TRIM - SNVS clock detect trim bits

◆ IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL [1/2]

#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK)

SNVS_CLK_DET_TRIM_SEL - SNVS clock detect trim select 0b0..The trimming codes are selected from eFuse 0b1..The trimming codes of clock detector used to change the boundary frequencies are selected from SNVS_CLK_DET_TRIM

◆ IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL [2/2]

#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK)

SNVS_CLK_DET_TRIM_SEL - SNVS clock detect trim select 0b0..The trimming codes are selected from eFuse 0b1..The trimming codes of clock detector used to change the boundary frequencies are selected from SNVS_CLK_DET_TRIM

◆ IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM [1/2]

#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK)

SNVS_CORE_VOLT_DET_TRIM - SNVS core voltage detect trim

◆ IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM [2/2]

#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK)

SNVS_CORE_VOLT_DET_TRIM - SNVS core voltage detect trim

◆ IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL [1/2]

#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK)

SNVS_CORE_VOLT_DET_TRIM_SEL - SNVS core voltage detect trim select 0b0..The trimming codes are selected from eFuse 0b1..The trimming codes of core voltage detectors used to change the voltage falling trip point are selected from SNVS_CORE_VOLT_DET_TRIM

◆ IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL [2/2]

#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK)

SNVS_CORE_VOLT_DET_TRIM_SEL - SNVS core voltage detect trim select 0b0..The trimming codes are selected from eFuse 0b1..The trimming codes of core voltage detectors used to change the voltage falling trip point are selected from SNVS_CORE_VOLT_DET_TRIM

◆ IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM [1/2]

#define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK)

SNVS_OSC_CAP_TRIM - SNVS OSC load capacitor trim

◆ IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM [2/2]

#define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK)

SNVS_OSC_CAP_TRIM - SNVS OSC load capacitor trim

◆ IOMUXC_SNVS_GPR_GPR35_LOCK [1/2]

#define IOMUXC_SNVS_GPR_GPR35_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b0..Write access is not blocked 0b1..Write access is blocked

◆ IOMUXC_SNVS_GPR_GPR35_LOCK [2/2]

#define IOMUXC_SNVS_GPR_GPR35_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b0..Write access is not blocked 0b1..Write access is blocked

◆ IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH [1/2]

#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK)

SNVS_TEMP_DET_OFFSET_HIGH - SNVS temperature detect offset of high temperature boundary 0b00..No change (Default) 0b01..Add +5 to the Trim 0b10..Add +10 to the trim 0b11..Add -5 to the Trim

◆ IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH [2/2]

#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK)

SNVS_TEMP_DET_OFFSET_HIGH - SNVS temperature detect offset of high temperature boundary 0b00..No change (Default) 0b01..Add +5 to the Trim 0b10..Add +10 to the trim 0b11..Add -5 to the Trim

◆ IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW [1/2]

#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK)

SNVS_TEMP_DET_OFFSET_LOW - SNVS temperature detect offset of low temperature boundary 0b00..No change (Default) 0b01..Add +5 to the Trim 0b10..Add +10 to the trim 0b11..Add -5 to the Trim

◆ IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW [2/2]

#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK)

SNVS_TEMP_DET_OFFSET_LOW - SNVS temperature detect offset of low temperature boundary 0b00..No change (Default) 0b01..Add +5 to the Trim 0b10..Add +10 to the trim 0b11..Add -5 to the Trim

◆ IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM [1/2]

#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK)

SNVS_TEMP_DET_TRIM - SNVS temperature detect trim

◆ IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM [2/2]

#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK)

SNVS_TEMP_DET_TRIM - SNVS temperature detect trim

◆ IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL [1/2]

#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK)

SNVS_TEMP_DET_TRIM_SEL - SNVS temperature detect trim select 0b0..The trimming codes are selected from eFuse 0b1..The trimming codes to define the temperature boundaries of temperature detector are selected from SNVS_TEMP_DET_TRIM

◆ IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL [2/2]

#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK)

SNVS_TEMP_DET_TRIM_SEL - SNVS temperature detect trim select 0b0..The trimming codes are selected from eFuse 0b1..The trimming codes to define the temperature boundaries of temperature detector are selected from SNVS_TEMP_DET_TRIM

◆ IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM [1/2]

#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK)

SNVS_VOLT_DET_TRIM - SNVS voltage detect trim

◆ IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM [2/2]

#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK)

SNVS_VOLT_DET_TRIM - SNVS voltage detect trim

◆ IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL [1/2]

#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK)

SNVS_VOLT_DET_TRIM_SEL - SNVS voltage detect trim select 0b0..The trimming codes are selected from eFuse 0b1..The trimming codes of voltage detectors to change the voltage boundaries in battery voltage detecting are selected from SNVS_VOLT_DET_TRIM

◆ IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL [2/2]

#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK)

SNVS_VOLT_DET_TRIM_SEL - SNVS voltage detect trim select 0b0..The trimming codes are selected from eFuse 0b1..The trimming codes of voltage detectors to change the voltage boundaries in battery voltage detecting are selected from SNVS_VOLT_DET_TRIM

◆ IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE [1/2]

#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK)

SNVS_SRAM_PSWLARGE - SNVS SRAM large switch control bit 0b1..Switch off SNVS SRAM power for peripheral and array 0b0..Switch on SNVS SRAM power for peripheral and array

◆ IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE [2/2]

#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK)

SNVS_SRAM_PSWLARGE - SNVS SRAM large switch control bit 0b1..Switch off SNVS SRAM power for peripheral and array 0b0..Switch on SNVS SRAM power for peripheral and array

◆ IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE [1/2]

#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK)

SNVS_SRAM_PSWLARGEMP_FORCE - SNVS SRAM large switch control bit for peripheral 0b1..Switch off SNVS SRAM power for peripheral (SRAM array power is not impacted, and data can be retained) 0b0..Switch on SNVS SRAM power for peripheral

◆ IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE [2/2]

#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK)

SNVS_SRAM_PSWLARGEMP_FORCE - SNVS SRAM large switch control bit for peripheral 0b1..Switch off SNVS SRAM power for peripheral (SRAM array power is not impacted, and data can be retained) 0b0..Switch on SNVS SRAM power for peripheral

◆ IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL [1/2]

#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK)

SNVS_SRAM_PSWSMALL - SNVS SRAM small switch control bit 0b1..Switch off SNVS SRAM power for peripheral and array 0b0..Switch on SNVS SRAM power for peripheral and array

◆ IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL [2/2]

#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK)

SNVS_SRAM_PSWSMALL - SNVS SRAM small switch control bit 0b1..Switch off SNVS SRAM power for peripheral and array 0b0..Switch on SNVS SRAM power for peripheral and array

◆ IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE [1/2]

#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK)

SNVS_SRAM_PSWSMALLMP_FORCE - SNVS SRAM small switch control bit for peripheral 0b1..Switch off SNVS SRAM power for peripheral (SRAM array power is not impacted, and data can be retained) 0b0..Switch on SNVS SRAM power for peripheral

◆ IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE [2/2]

#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK)

SNVS_SRAM_PSWSMALLMP_FORCE - SNVS SRAM small switch control bit for peripheral 0b1..Switch off SNVS SRAM power for peripheral (SRAM array power is not impacted, and data can be retained) 0b0..Switch on SNVS SRAM power for peripheral

◆ IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP [1/2]

#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK)

SNVS_SRAM_SLEEP - SNVS SRAM power-down enable bit 0b0..Enable SRAM access (It should be cleared after LDO_SNVS_DIG is enabled) 0b1..SNVS SRAM can go in Shutdown/ Periphery Off Array On/ Periphery On Array Off mode. In addition, this bit ensures power-up without stuck-at /high DC current states and hence must be held to 1 during wake-up, so this bit is default high.

◆ IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP [2/2]

#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK)

SNVS_SRAM_SLEEP - SNVS SRAM power-down enable bit 0b0..Enable SRAM access (It should be cleared after LDO_SNVS_DIG is enabled) 0b1..SNVS SRAM can go in Shutdown/ Periphery Off Array On/ Periphery On Array Off mode. In addition, this bit ensures power-up without stuck-at /high DC current states and hence must be held to 1 during wake-up, so this bit is default high.

◆ IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY [1/2]

#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK)

SNVS_SRAM_STDBY - SNVS SRAM standby enable bit 0b1..SNVS SRAM enters low leakage state and large drivers are switched OFF 0b0..SNVS SRAM does not enter low leakage state

◆ IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY [2/2]

#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK)

SNVS_SRAM_STDBY - SNVS SRAM standby enable bit 0b1..SNVS SRAM enters low leakage state and large drivers are switched OFF 0b0..SNVS SRAM does not enter low leakage state

◆ IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN [1/2]

#define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK)

SNVSDIG_SNVS1P8_ISO_EN - SNVS RAM isolation enable bit 0b1..Enable the isolation to avoid extra leakage power before SNVS SRAM peripheral power or LDO_SNVS_DIG is switched off 0b0..Enable SRAM access (It should be cleared after LDO_SNVS_DIG and SNVS SRAM peripheral power is back)

◆ IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN [2/2]

#define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK)

SNVSDIG_SNVS1P8_ISO_EN - SNVS RAM isolation enable bit 0b1..Enable the isolation to avoid extra leakage power before SNVS SRAM peripheral power or LDO_SNVS_DIG is switched off 0b0..Enable SRAM access (It should be cleared after LDO_SNVS_DIG and SNVS SRAM peripheral power is back)

◆ IOMUXC_SNVS_GPR_GPR37_LOCK [1/2]

#define IOMUXC_SNVS_GPR_GPR37_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b0..Write access is not blocked 0b1..Write access is blocked

◆ IOMUXC_SNVS_GPR_GPR37_LOCK [2/2]

#define IOMUXC_SNVS_GPR_GPR37_LOCK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_LOCK_MASK)

LOCK - Lock the write to bit 31:1 0b0..Write access is not blocked 0b1..Write access is blocked

◆ IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE [1/2]

#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK)

SNVS_TAMPER_PUE - SNVS tamper detect pin pull enable bit

◆ IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE [2/2]

#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK)

SNVS_TAMPER_PUE - SNVS tamper detect pin pull enable bit

◆ IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS [1/2]

#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK)

SNVS_TAMPER_PUS - SNVS tamper detect pin pull selection bit

◆ IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS [2/2]

#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK)

SNVS_TAMPER_PUS - SNVS tamper detect pin pull selection bit

◆ IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL

#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK)

DCDC_IN_LOW_VOL 0b0..DCDC_IN is ok 0b1..DCDC_IN is too low

◆ IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR

#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK)

DCDC_OVER_CUR 0b0..No over current detected 0b1..Over current detected

◆ IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL

#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK)

DCDC_OVER_VOL 0b0..No over voltage detected 0b1..Over voltage detected

◆ IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR

#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK)

DCDC_STATUS_CAPT_CLR - DCDC captured status clear

◆ IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK

#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK)

DCDC_STS_DC_OK 0b0..DCDC is ramping up and not ready 0b1..DCDC is ready

◆ IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE

#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK)

LPSR_MODE_ENABLE 0b0..SNVS domain will reset when system reset happens 0b1..SNVS domain will only reset with SNVS POR

◆ IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE

#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE (   x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK)

POR_PULL_TYPE 0b00..100 Ohm pull up enabled for POR_B always 0b01..Disable pull in SNVS mode, 100 Ohm pull up enabled otherwise 0b10..Disable pull of POR_B always 0b11..100 Ohm pull down enabled in SNVS mode, 100 Ohm pull up enabled otherwise

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