REGION0_TOP_ADDR - End address of IEE region (n)
#define	IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_SHIFT (0U)

#define	IEE_APC_REGION0_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_MASK)

REGION0_BOT_ADDR - Start address of IEE region (n)
#define	IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_SHIFT (0U)

#define	IEE_APC_REGION0_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_MASK)

REGION0_RDC_D0 - Region control of core domain 0 for region (n)
#define	IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_MASK)

#define	IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_MASK (0x2U)

#define	IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_SHIFT (1U)

#define	IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_MASK)

REGION0_RDC_D1 - Region control of core domain 1 for region (n)
#define	IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_MASK)

#define	IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_MASK (0x2U)

#define	IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_SHIFT (1U)

#define	IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_MASK)

REGION1_TOP_ADDR - End address of IEE region (n)
#define	IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_SHIFT (0U)

#define	IEE_APC_REGION1_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_MASK)

REGION1_BOT_ADDR - Start address of IEE region (n)
#define	IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_SHIFT (0U)

#define	IEE_APC_REGION1_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_MASK)

REGION1_RDC_D0 - Region control of core domain 0 for region (n)
#define	IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_MASK)

#define	IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_MASK (0x2U)

#define	IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_SHIFT (1U)

#define	IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_MASK)

REGION1_RDC_D1 - Region control of core domain 1 for region (n)
#define	IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_MASK)

#define	IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_MASK (0x2U)

#define	IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_SHIFT (1U)

#define	IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_MASK)

REGION2_TOP_ADDR - End address of IEE region (n)
#define	IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_SHIFT (0U)

#define	IEE_APC_REGION2_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_MASK)

REGION2_BOT_ADDR - Start address of IEE region (n)
#define	IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_SHIFT (0U)

#define	IEE_APC_REGION2_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_MASK)

REGION2_RDC_D0 - Region control of core domain 0 for region (n)
#define	IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_MASK)

#define	IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_MASK (0x2U)

#define	IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_SHIFT (1U)

#define	IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_MASK)

REGION2_RDC_D1 - Region control of core domain 1 for region (n)
#define	IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_MASK)

#define	IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_MASK (0x2U)

#define	IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_SHIFT (1U)

#define	IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_MASK)

REGION3_TOP_ADDR - End address of IEE region (n)
#define	IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_SHIFT (0U)

#define	IEE_APC_REGION3_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_MASK)

REGION3_BOT_ADDR - Start address of IEE region (n)
#define	IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_SHIFT (0U)

#define	IEE_APC_REGION3_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_MASK)

REGION3_RDC_D0 - Region control of core domain 0 for region (n)
#define	IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_MASK)

#define	IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_MASK (0x2U)

#define	IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_SHIFT (1U)

#define	IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_MASK)

REGION3_RDC_D1 - Region control of core domain 1 for region (n)
#define	IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_MASK)

#define	IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_MASK (0x2U)

#define	IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_SHIFT (1U)

#define	IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_MASK)

REGION4_TOP_ADDR - End address of IEE region (n)
#define	IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_SHIFT (0U)

#define	IEE_APC_REGION4_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_MASK)

REGION4_BOT_ADDR - Start address of IEE region (n)
#define	IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_SHIFT (0U)

#define	IEE_APC_REGION4_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_MASK)

REGION4_RDC_D0 - Region control of core domain 0 for region (n)
#define	IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_MASK)

#define	IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_MASK (0x2U)

#define	IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_SHIFT (1U)

#define	IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_MASK)

REGION4_RDC_D1 - Region control of core domain 1 for region (n)
#define	IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_MASK)

#define	IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_MASK (0x2U)

#define	IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_SHIFT (1U)

#define	IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_MASK)

REGION5_TOP_ADDR - End address of IEE region (n)
#define	IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_SHIFT (0U)

#define	IEE_APC_REGION5_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_MASK)

REGION5_BOT_ADDR - Start address of IEE region (n)
#define	IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_SHIFT (0U)

#define	IEE_APC_REGION5_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_MASK)

REGION5_RDC_D0 - Region control of core domain 0 for region (n)
#define	IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_MASK)

#define	IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_MASK (0x2U)

#define	IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_SHIFT (1U)

#define	IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_MASK)

REGION5_RDC_D1 - Region control of core domain 1 for region (n)
#define	IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_MASK)

#define	IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_MASK (0x2U)

#define	IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_SHIFT (1U)

#define	IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_MASK)

REGION6_TOP_ADDR - End address of IEE region (n)
#define	IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_SHIFT (0U)

#define	IEE_APC_REGION6_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_MASK)

REGION6_BOT_ADDR - Start address of IEE region (n)
#define	IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_SHIFT (0U)

#define	IEE_APC_REGION6_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_MASK)

REGION6_RDC_D0 - Region control of core domain 0 for region (n)
#define	IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_MASK)

#define	IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_MASK (0x2U)

#define	IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_SHIFT (1U)

#define	IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_MASK)

REGION6_RDC_D1 - Region control of core domain 1 for region (n)
#define	IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_MASK)

#define	IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_MASK (0x2U)

#define	IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_SHIFT (1U)

#define	IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_MASK)

REGION7_TOP_ADDR - End address of IEE region (n)
#define	IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_SHIFT (0U)

#define	IEE_APC_REGION7_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_MASK)

REGION7_BOT_ADDR - Start address of IEE region (n)
#define	IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_SHIFT (0U)

#define	IEE_APC_REGION7_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_MASK)

REGION7_RDC_D0 - Region control of core domain 0 for region (n)
#define	IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_MASK)

#define	IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_MASK (0x2U)

#define	IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_SHIFT (1U)

#define	IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_MASK)

REGION7_RDC_D1 - Region control of core domain 1 for region (n)
#define	IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_MASK)

#define	IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_MASK (0x2U)

#define	IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_SHIFT (1U)

#define	IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_MASK)

REGION0_TOP_ADDR - End address of IEE region (n)
#define	IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_SHIFT (0U)

#define	IEE_APC_REGION0_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_MASK)

REGION0_BOT_ADDR - Start address of IEE region (n)
#define	IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_SHIFT (0U)

#define	IEE_APC_REGION0_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_MASK)

REGION0_RDC_D0 - Region control of core domain 0 for region (n)
#define	IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_MASK)

#define	IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_MASK (0x2U)

#define	IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_SHIFT (1U)

#define	IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_MASK)

REGION0_RDC_D1 - Region control of core domain 1 for region (n)
#define	IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_MASK)

#define	IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_MASK (0x2U)

#define	IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_SHIFT (1U)

#define	IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_MASK)

REGION1_TOP_ADDR - End address of IEE region (n)
#define	IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_SHIFT (0U)

#define	IEE_APC_REGION1_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_MASK)

REGION1_BOT_ADDR - Start address of IEE region (n)
#define	IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_SHIFT (0U)

#define	IEE_APC_REGION1_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_MASK)

REGION1_RDC_D0 - Region control of core domain 0 for region (n)
#define	IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_MASK)

#define	IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_MASK (0x2U)

#define	IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_SHIFT (1U)

#define	IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_MASK)

REGION1_RDC_D1 - Region control of core domain 1 for region (n)
#define	IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_MASK)

#define	IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_MASK (0x2U)

#define	IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_SHIFT (1U)

#define	IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_MASK)

REGION2_TOP_ADDR - End address of IEE region (n)
#define	IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_SHIFT (0U)

#define	IEE_APC_REGION2_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_MASK)

REGION2_BOT_ADDR - Start address of IEE region (n)
#define	IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_SHIFT (0U)

#define	IEE_APC_REGION2_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_MASK)

REGION2_RDC_D0 - Region control of core domain 0 for region (n)
#define	IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_MASK)

#define	IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_MASK (0x2U)

#define	IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_SHIFT (1U)

#define	IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_MASK)

REGION2_RDC_D1 - Region control of core domain 1 for region (n)
#define	IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_MASK)

#define	IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_MASK (0x2U)

#define	IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_SHIFT (1U)

#define	IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_MASK)

REGION3_TOP_ADDR - End address of IEE region (n)
#define	IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_SHIFT (0U)

#define	IEE_APC_REGION3_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_MASK)

REGION3_BOT_ADDR - Start address of IEE region (n)
#define	IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_SHIFT (0U)

#define	IEE_APC_REGION3_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_MASK)

REGION3_RDC_D0 - Region control of core domain 0 for region (n)
#define	IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_MASK)

#define	IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_MASK (0x2U)

#define	IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_SHIFT (1U)

#define	IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_MASK)

REGION3_RDC_D1 - Region control of core domain 1 for region (n)
#define	IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_MASK)

#define	IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_MASK (0x2U)

#define	IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_SHIFT (1U)

#define	IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_MASK)

REGION4_TOP_ADDR - End address of IEE region (n)
#define	IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_SHIFT (0U)

#define	IEE_APC_REGION4_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_MASK)

REGION4_BOT_ADDR - Start address of IEE region (n)
#define	IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_SHIFT (0U)

#define	IEE_APC_REGION4_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_MASK)

REGION4_RDC_D0 - Region control of core domain 0 for region (n)
#define	IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_MASK)

#define	IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_MASK (0x2U)

#define	IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_SHIFT (1U)

#define	IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_MASK)

REGION4_RDC_D1 - Region control of core domain 1 for region (n)
#define	IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_MASK)

#define	IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_MASK (0x2U)

#define	IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_SHIFT (1U)

#define	IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_MASK)

REGION5_TOP_ADDR - End address of IEE region (n)
#define	IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_SHIFT (0U)

#define	IEE_APC_REGION5_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_MASK)

REGION5_BOT_ADDR - Start address of IEE region (n)
#define	IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_SHIFT (0U)

#define	IEE_APC_REGION5_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_MASK)

REGION5_RDC_D0 - Region control of core domain 0 for region (n)
#define	IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_MASK)

#define	IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_MASK (0x2U)

#define	IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_SHIFT (1U)

#define	IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_MASK)

REGION5_RDC_D1 - Region control of core domain 1 for region (n)
#define	IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_MASK)

#define	IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_MASK (0x2U)

#define	IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_SHIFT (1U)

#define	IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_MASK)

REGION6_TOP_ADDR - End address of IEE region (n)
#define	IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_SHIFT (0U)

#define	IEE_APC_REGION6_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_MASK)

REGION6_BOT_ADDR - Start address of IEE region (n)
#define	IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_SHIFT (0U)

#define	IEE_APC_REGION6_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_MASK)

REGION6_RDC_D0 - Region control of core domain 0 for region (n)
#define	IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_MASK)

#define	IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_MASK (0x2U)

#define	IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_SHIFT (1U)

#define	IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_MASK)

REGION6_RDC_D1 - Region control of core domain 1 for region (n)
#define	IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_MASK)

#define	IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_MASK (0x2U)

#define	IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_SHIFT (1U)

#define	IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_MASK)

REGION7_TOP_ADDR - End address of IEE region (n)
#define	IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_SHIFT (0U)

#define	IEE_APC_REGION7_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_MASK)

REGION7_BOT_ADDR - Start address of IEE region (n)
#define	IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)

#define	IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_SHIFT (0U)

#define	IEE_APC_REGION7_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_MASK)

REGION7_RDC_D0 - Region control of core domain 0 for region (n)
#define	IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_MASK)

#define	IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_MASK (0x2U)

#define	IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_SHIFT (1U)

#define	IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_MASK)

REGION7_RDC_D1 - Region control of core domain 1 for region (n)
#define	IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)

#define	IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)

#define	IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_MASK)

#define	IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_MASK (0x2U)

#define	IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_SHIFT (1U)

#define	IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_MASK)

Detailed Description

Macro Definition Documentation

◆ IEE_APC_REGION0_BOT_ADDR_BOT_ADDR [1/2]

#define IEE_APC_REGION0_BOT_ADDR_BOT_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_MASK)

BOT_ADDR - Start address of IEE region

◆ IEE_APC_REGION0_BOT_ADDR_BOT_ADDR [2/2]

#define IEE_APC_REGION0_BOT_ADDR_BOT_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_MASK)

BOT_ADDR - Start address of IEE region

◆ IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK [1/2]

#define IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_MASK)

RDC_D0_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK [2/2]

#define IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_MASK)

RDC_D0_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS [1/2]

#define IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_MASK)

RDC_D0_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS [2/2]

#define IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_MASK)

RDC_D0_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK [1/2]

#define IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_MASK)

RDC_D1_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK [2/2]

#define IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_MASK)

RDC_D1_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS [1/2]

#define IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_MASK)

RDC_D1_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS [2/2]

#define IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_MASK)

RDC_D1_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION0_TOP_ADDR_TOP_ADDR [1/2]

#define IEE_APC_REGION0_TOP_ADDR_TOP_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_MASK)

TOP_ADDR - End address of IEE region

◆ IEE_APC_REGION0_TOP_ADDR_TOP_ADDR [2/2]

#define IEE_APC_REGION0_TOP_ADDR_TOP_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_MASK)

TOP_ADDR - End address of IEE region

◆ IEE_APC_REGION1_BOT_ADDR_BOT_ADDR [1/2]

#define IEE_APC_REGION1_BOT_ADDR_BOT_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_MASK)

BOT_ADDR - Start address of IEE region

◆ IEE_APC_REGION1_BOT_ADDR_BOT_ADDR [2/2]

#define IEE_APC_REGION1_BOT_ADDR_BOT_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_MASK)

BOT_ADDR - Start address of IEE region

◆ IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK [1/2]

#define IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_MASK)

RDC_D0_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK [2/2]

#define IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_MASK)

RDC_D0_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS [1/2]

#define IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_MASK)

RDC_D0_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS [2/2]

#define IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_MASK)

RDC_D0_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK [1/2]

#define IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_MASK)

RDC_D1_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK [2/2]

#define IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_MASK)

RDC_D1_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS [1/2]

#define IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_MASK)

RDC_D1_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS [2/2]

#define IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_MASK)

RDC_D1_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION1_TOP_ADDR_TOP_ADDR [1/2]

#define IEE_APC_REGION1_TOP_ADDR_TOP_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_MASK)

TOP_ADDR - End address of IEE region

◆ IEE_APC_REGION1_TOP_ADDR_TOP_ADDR [2/2]

#define IEE_APC_REGION1_TOP_ADDR_TOP_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_MASK)

TOP_ADDR - End address of IEE region

◆ IEE_APC_REGION2_BOT_ADDR_BOT_ADDR [1/2]

#define IEE_APC_REGION2_BOT_ADDR_BOT_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_MASK)

BOT_ADDR - Start address of IEE region

◆ IEE_APC_REGION2_BOT_ADDR_BOT_ADDR [2/2]

#define IEE_APC_REGION2_BOT_ADDR_BOT_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_MASK)

BOT_ADDR - Start address of IEE region

◆ IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK [1/2]

#define IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_MASK)

RDC_D0_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK [2/2]

#define IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_MASK)

RDC_D0_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS [1/2]

#define IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_MASK)

RDC_D0_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS [2/2]

#define IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_MASK)

RDC_D0_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK [1/2]

#define IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_MASK)

RDC_D1_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK [2/2]

#define IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_MASK)

RDC_D1_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS [1/2]

#define IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_MASK)

RDC_D1_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS [2/2]

#define IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_MASK)

RDC_D1_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION2_TOP_ADDR_TOP_ADDR [1/2]

#define IEE_APC_REGION2_TOP_ADDR_TOP_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_MASK)

TOP_ADDR - End address of IEE region

◆ IEE_APC_REGION2_TOP_ADDR_TOP_ADDR [2/2]

#define IEE_APC_REGION2_TOP_ADDR_TOP_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_MASK)

TOP_ADDR - End address of IEE region

◆ IEE_APC_REGION3_BOT_ADDR_BOT_ADDR [1/2]

#define IEE_APC_REGION3_BOT_ADDR_BOT_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_MASK)

BOT_ADDR - Start address of IEE region

◆ IEE_APC_REGION3_BOT_ADDR_BOT_ADDR [2/2]

#define IEE_APC_REGION3_BOT_ADDR_BOT_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_MASK)

BOT_ADDR - Start address of IEE region

◆ IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK [1/2]

#define IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_MASK)

RDC_D0_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK [2/2]

#define IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_MASK)

RDC_D0_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS [1/2]

#define IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_MASK)

RDC_D0_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS [2/2]

#define IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_MASK)

RDC_D0_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK [1/2]

#define IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_MASK)

RDC_D1_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK [2/2]

#define IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_MASK)

RDC_D1_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS [1/2]

#define IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_MASK)

RDC_D1_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS [2/2]

#define IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_MASK)

RDC_D1_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION3_TOP_ADDR_TOP_ADDR [1/2]

#define IEE_APC_REGION3_TOP_ADDR_TOP_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_MASK)

TOP_ADDR - End address of IEE region

◆ IEE_APC_REGION3_TOP_ADDR_TOP_ADDR [2/2]

#define IEE_APC_REGION3_TOP_ADDR_TOP_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_MASK)

TOP_ADDR - End address of IEE region

◆ IEE_APC_REGION4_BOT_ADDR_BOT_ADDR [1/2]

#define IEE_APC_REGION4_BOT_ADDR_BOT_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_MASK)

BOT_ADDR - Start address of IEE region

◆ IEE_APC_REGION4_BOT_ADDR_BOT_ADDR [2/2]

#define IEE_APC_REGION4_BOT_ADDR_BOT_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_MASK)

BOT_ADDR - Start address of IEE region

◆ IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK [1/2]

#define IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_MASK)

RDC_D0_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK [2/2]

#define IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_MASK)

RDC_D0_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS [1/2]

#define IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_MASK)

RDC_D0_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS [2/2]

#define IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_MASK)

RDC_D0_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK [1/2]

#define IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_MASK)

RDC_D1_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK [2/2]

#define IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_MASK)

RDC_D1_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS [1/2]

#define IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_MASK)

RDC_D1_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS [2/2]

#define IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_MASK)

RDC_D1_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION4_TOP_ADDR_TOP_ADDR [1/2]

#define IEE_APC_REGION4_TOP_ADDR_TOP_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_MASK)

TOP_ADDR - End address of IEE region

◆ IEE_APC_REGION4_TOP_ADDR_TOP_ADDR [2/2]

#define IEE_APC_REGION4_TOP_ADDR_TOP_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_MASK)

TOP_ADDR - End address of IEE region

◆ IEE_APC_REGION5_BOT_ADDR_BOT_ADDR [1/2]

#define IEE_APC_REGION5_BOT_ADDR_BOT_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_MASK)

BOT_ADDR - Start address of IEE region

◆ IEE_APC_REGION5_BOT_ADDR_BOT_ADDR [2/2]

#define IEE_APC_REGION5_BOT_ADDR_BOT_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_MASK)

BOT_ADDR - Start address of IEE region

◆ IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK [1/2]

#define IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_MASK)

RDC_D0_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK [2/2]

#define IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_MASK)

RDC_D0_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS [1/2]

#define IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_MASK)

RDC_D0_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS [2/2]

#define IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_MASK)

RDC_D0_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK [1/2]

#define IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_MASK)

RDC_D1_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK [2/2]

#define IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_MASK)

RDC_D1_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS [1/2]

#define IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_MASK)

RDC_D1_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS [2/2]

#define IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_MASK)

RDC_D1_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION5_TOP_ADDR_TOP_ADDR [1/2]

#define IEE_APC_REGION5_TOP_ADDR_TOP_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_MASK)

TOP_ADDR - End address of IEE region

◆ IEE_APC_REGION5_TOP_ADDR_TOP_ADDR [2/2]

#define IEE_APC_REGION5_TOP_ADDR_TOP_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_MASK)

TOP_ADDR - End address of IEE region

◆ IEE_APC_REGION6_BOT_ADDR_BOT_ADDR [1/2]

#define IEE_APC_REGION6_BOT_ADDR_BOT_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_MASK)

BOT_ADDR - Start address of IEE region

◆ IEE_APC_REGION6_BOT_ADDR_BOT_ADDR [2/2]

#define IEE_APC_REGION6_BOT_ADDR_BOT_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_MASK)

BOT_ADDR - Start address of IEE region

◆ IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK [1/2]

#define IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_MASK)

RDC_D0_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK [2/2]

#define IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_MASK)

RDC_D0_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS [1/2]

#define IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_MASK)

RDC_D0_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS [2/2]

#define IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_MASK)

RDC_D0_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK [1/2]

#define IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_MASK)

RDC_D1_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK [2/2]

#define IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_MASK)

RDC_D1_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS [1/2]

#define IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_MASK)

RDC_D1_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS [2/2]

#define IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_MASK)

RDC_D1_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION6_TOP_ADDR_TOP_ADDR [1/2]

#define IEE_APC_REGION6_TOP_ADDR_TOP_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_MASK)

TOP_ADDR - End address of IEE region

◆ IEE_APC_REGION6_TOP_ADDR_TOP_ADDR [2/2]

#define IEE_APC_REGION6_TOP_ADDR_TOP_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_MASK)

TOP_ADDR - End address of IEE region

◆ IEE_APC_REGION7_BOT_ADDR_BOT_ADDR [1/2]

#define IEE_APC_REGION7_BOT_ADDR_BOT_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_MASK)

BOT_ADDR - Start address of IEE region

◆ IEE_APC_REGION7_BOT_ADDR_BOT_ADDR [2/2]

#define IEE_APC_REGION7_BOT_ADDR_BOT_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_MASK)

BOT_ADDR - Start address of IEE region

◆ IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK [1/2]

#define IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_MASK)

RDC_D0_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK [2/2]

#define IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_MASK)

RDC_D0_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS [1/2]

#define IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_MASK)

RDC_D0_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS [2/2]

#define IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_MASK)

RDC_D0_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK [1/2]

#define IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_MASK)

RDC_D1_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK [2/2]

#define IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_MASK)

RDC_D1_LOCK - Lock bit for bit 0 0b0..Bit 0 is unlocked 0b1..Bit 0 is locked

◆ IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS [1/2]

#define IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_MASK)

RDC_D1_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS [2/2]

#define IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_MASK)

RDC_D1_WRITE_DIS - Write disable of core domain 1 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled

◆ IEE_APC_REGION7_TOP_ADDR_TOP_ADDR [1/2]

#define IEE_APC_REGION7_TOP_ADDR_TOP_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_MASK)

TOP_ADDR - End address of IEE region

◆ IEE_APC_REGION7_TOP_ADDR_TOP_ADDR [2/2]

#define IEE_APC_REGION7_TOP_ADDR_TOP_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_MASK)

TOP_ADDR - End address of IEE region

REGION0_TOP_ADDR - End address of IEE region (n)

REGION0_BOT_ADDR - Start address of IEE region (n)

REGION0_RDC_D0 - Region control of core domain 0 for region (n)

REGION0_RDC_D1 - Region control of core domain 1 for region (n)

REGION1_TOP_ADDR - End address of IEE region (n)

REGION1_BOT_ADDR - Start address of IEE region (n)

REGION1_RDC_D0 - Region control of core domain 0 for region (n)

REGION1_RDC_D1 - Region control of core domain 1 for region (n)

REGION2_TOP_ADDR - End address of IEE region (n)

REGION2_BOT_ADDR - Start address of IEE region (n)

REGION2_RDC_D0 - Region control of core domain 0 for region (n)

REGION2_RDC_D1 - Region control of core domain 1 for region (n)

REGION3_TOP_ADDR - End address of IEE region (n)

REGION3_BOT_ADDR - Start address of IEE region (n)

REGION3_RDC_D0 - Region control of core domain 0 for region (n)

REGION3_RDC_D1 - Region control of core domain 1 for region (n)

REGION4_TOP_ADDR - End address of IEE region (n)

REGION4_BOT_ADDR - Start address of IEE region (n)

REGION4_RDC_D0 - Region control of core domain 0 for region (n)

REGION4_RDC_D1 - Region control of core domain 1 for region (n)

REGION5_TOP_ADDR - End address of IEE region (n)

REGION5_BOT_ADDR - Start address of IEE region (n)

REGION5_RDC_D0 - Region control of core domain 0 for region (n)

REGION5_RDC_D1 - Region control of core domain 1 for region (n)

REGION6_TOP_ADDR - End address of IEE region (n)

REGION6_BOT_ADDR - Start address of IEE region (n)

REGION6_RDC_D0 - Region control of core domain 0 for region (n)

REGION6_RDC_D1 - Region control of core domain 1 for region (n)

REGION7_TOP_ADDR - End address of IEE region (n)

REGION7_BOT_ADDR - Start address of IEE region (n)

REGION7_RDC_D0 - Region control of core domain 0 for region (n)

REGION7_RDC_D1 - Region control of core domain 1 for region (n)

REGION0_TOP_ADDR - End address of IEE region (n)

REGION0_BOT_ADDR - Start address of IEE region (n)

REGION0_RDC_D0 - Region control of core domain 0 for region (n)

REGION0_RDC_D1 - Region control of core domain 1 for region (n)

REGION1_TOP_ADDR - End address of IEE region (n)

REGION1_BOT_ADDR - Start address of IEE region (n)

REGION1_RDC_D0 - Region control of core domain 0 for region (n)

REGION1_RDC_D1 - Region control of core domain 1 for region (n)

REGION2_TOP_ADDR - End address of IEE region (n)

REGION2_BOT_ADDR - Start address of IEE region (n)

REGION2_RDC_D0 - Region control of core domain 0 for region (n)

REGION2_RDC_D1 - Region control of core domain 1 for region (n)

REGION3_TOP_ADDR - End address of IEE region (n)

REGION3_BOT_ADDR - Start address of IEE region (n)

REGION3_RDC_D0 - Region control of core domain 0 for region (n)

REGION3_RDC_D1 - Region control of core domain 1 for region (n)

REGION4_TOP_ADDR - End address of IEE region (n)

REGION4_BOT_ADDR - Start address of IEE region (n)

REGION4_RDC_D0 - Region control of core domain 0 for region (n)

REGION4_RDC_D1 - Region control of core domain 1 for region (n)

REGION5_TOP_ADDR - End address of IEE region (n)

REGION5_BOT_ADDR - Start address of IEE region (n)

REGION5_RDC_D0 - Region control of core domain 0 for region (n)

REGION5_RDC_D1 - Region control of core domain 1 for region (n)

REGION6_TOP_ADDR - End address of IEE region (n)

REGION6_BOT_ADDR - Start address of IEE region (n)

REGION6_RDC_D0 - Region control of core domain 0 for region (n)

REGION6_RDC_D1 - Region control of core domain 1 for region (n)

REGION7_TOP_ADDR - End address of IEE region (n)

REGION7_BOT_ADDR - Start address of IEE region (n)

REGION7_RDC_D0 - Region control of core domain 0 for region (n)

REGION7_RDC_D1 - Region control of core domain 1 for region (n)

Detailed Description

Macro Definition Documentation

◆ IEE_APC_REGION0_BOT_ADDR_BOT_ADDR [1/2]

◆ IEE_APC_REGION0_BOT_ADDR_BOT_ADDR [2/2]

◆ IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK [1/2]

◆ IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK [2/2]

◆ IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS [1/2]

◆ IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS [2/2]

◆ IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK [1/2]

◆ IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK [2/2]

◆ IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS [1/2]

◆ IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS [2/2]

◆ IEE_APC_REGION0_TOP_ADDR_TOP_ADDR [1/2]

◆ IEE_APC_REGION0_TOP_ADDR_TOP_ADDR [2/2]

◆ IEE_APC_REGION1_BOT_ADDR_BOT_ADDR [1/2]

◆ IEE_APC_REGION1_BOT_ADDR_BOT_ADDR [2/2]