VERID - Version Identifier Register
#define	DAC_VERID_FEATURE_MASK (0xFFFFU)

#define	DAC_VERID_FEATURE_SHIFT (0U)

#define	DAC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_FEATURE_SHIFT)) & DAC_VERID_FEATURE_MASK)

#define	DAC_VERID_MINOR_MASK (0xFF0000U)

#define	DAC_VERID_MINOR_SHIFT (16U)

#define	DAC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MINOR_SHIFT)) & DAC_VERID_MINOR_MASK)

#define	DAC_VERID_MAJOR_MASK (0xFF000000U)

#define	DAC_VERID_MAJOR_SHIFT (24U)

#define	DAC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MAJOR_SHIFT)) & DAC_VERID_MAJOR_MASK)

PARAM - Parameter Register
#define	DAC_PARAM_FIFOSZ_MASK (0x7U)

#define	DAC_PARAM_FIFOSZ_SHIFT (0U)

#define	DAC_PARAM_FIFOSZ(x) (((uint32_t)(((uint32_t)(x)) << DAC_PARAM_FIFOSZ_SHIFT)) & DAC_PARAM_FIFOSZ_MASK)

DATA - DAC Data Register
#define	DAC_DATA_DATA0_MASK (0xFFFU)

#define	DAC_DATA_DATA0_SHIFT (0U)

#define	DAC_DATA_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DAC_DATA_DATA0_SHIFT)) & DAC_DATA_DATA0_MASK)

CR - DAC Status and Control Register
#define	DAC_CR_FULLF_MASK (0x1U)

#define	DAC_CR_FULLF_SHIFT (0U)

#define	DAC_CR_FULLF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLF_SHIFT)) & DAC_CR_FULLF_MASK)

#define	DAC_CR_NEMPTF_MASK (0x2U)

#define	DAC_CR_NEMPTF_SHIFT (1U)

#define	DAC_CR_NEMPTF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_NEMPTF_SHIFT)) & DAC_CR_NEMPTF_MASK)

#define	DAC_CR_WMF_MASK (0x4U)

#define	DAC_CR_WMF_SHIFT (2U)

#define	DAC_CR_WMF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WMF_SHIFT)) & DAC_CR_WMF_MASK)

#define	DAC_CR_UDFF_MASK (0x8U)

#define	DAC_CR_UDFF_SHIFT (3U)

#define	DAC_CR_UDFF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_UDFF_SHIFT)) & DAC_CR_UDFF_MASK)

#define	DAC_CR_OVFF_MASK (0x10U)

#define	DAC_CR_OVFF_SHIFT (4U)

#define	DAC_CR_OVFF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_OVFF_SHIFT)) & DAC_CR_OVFF_MASK)

#define	DAC_CR_FULLIE_MASK (0x100U)

#define	DAC_CR_FULLIE_SHIFT (8U)

#define	DAC_CR_FULLIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLIE_SHIFT)) & DAC_CR_FULLIE_MASK)

#define	DAC_CR_EMPTIE_MASK (0x200U)

#define	DAC_CR_EMPTIE_SHIFT (9U)

#define	DAC_CR_EMPTIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_EMPTIE_SHIFT)) & DAC_CR_EMPTIE_MASK)

#define	DAC_CR_WTMIE_MASK (0x400U)

#define	DAC_CR_WTMIE_SHIFT (10U)

#define	DAC_CR_WTMIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WTMIE_SHIFT)) & DAC_CR_WTMIE_MASK)

#define	DAC_CR_SWTRG_MASK (0x1000U)

#define	DAC_CR_SWTRG_SHIFT (12U)

#define	DAC_CR_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWTRG_SHIFT)) & DAC_CR_SWTRG_MASK)

#define	DAC_CR_TRGSEL_MASK (0x2000U)

#define	DAC_CR_TRGSEL_SHIFT (13U)

#define	DAC_CR_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_TRGSEL_SHIFT)) & DAC_CR_TRGSEL_MASK)

#define	DAC_CR_DACRFS_MASK (0x4000U)

#define	DAC_CR_DACRFS_SHIFT (14U)

#define	DAC_CR_DACRFS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACRFS_SHIFT)) & DAC_CR_DACRFS_MASK)

#define	DAC_CR_DACEN_MASK (0x8000U)

#define	DAC_CR_DACEN_SHIFT (15U)

#define	DAC_CR_DACEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACEN_SHIFT)) & DAC_CR_DACEN_MASK)

#define	DAC_CR_FIFOEN_MASK (0x10000U)

#define	DAC_CR_FIFOEN_SHIFT (16U)

#define	DAC_CR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFOEN_SHIFT)) & DAC_CR_FIFOEN_MASK)

#define	DAC_CR_SWMD_MASK (0x20000U)

#define	DAC_CR_SWMD_SHIFT (17U)

#define	DAC_CR_SWMD(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWMD_SHIFT)) & DAC_CR_SWMD_MASK)

#define	DAC_CR_UVIE_MASK (0x40000U)

#define	DAC_CR_UVIE_SHIFT (18U)

#define	DAC_CR_UVIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_UVIE_SHIFT)) & DAC_CR_UVIE_MASK)

#define	DAC_CR_FIFORST_MASK (0x200000U)

#define	DAC_CR_FIFORST_SHIFT (21U)

#define	DAC_CR_FIFORST(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFORST_SHIFT)) & DAC_CR_FIFORST_MASK)

#define	DAC_CR_SWRST_MASK (0x400000U)

#define	DAC_CR_SWRST_SHIFT (22U)

#define	DAC_CR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWRST_SHIFT)) & DAC_CR_SWRST_MASK)

#define	DAC_CR_DMAEN_MASK (0x800000U)

#define	DAC_CR_DMAEN_SHIFT (23U)

#define	DAC_CR_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DMAEN_SHIFT)) & DAC_CR_DMAEN_MASK)

#define	DAC_CR_WML_MASK (0xFF000000U)

#define	DAC_CR_WML_SHIFT (24U)

#define	DAC_CR_WML(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WML_SHIFT)) & DAC_CR_WML_MASK)

PTR - DAC FIFO Pointer Register
#define	DAC_PTR_DACWFP_MASK (0xFFU)

#define	DAC_PTR_DACWFP_SHIFT (0U)

#define	DAC_PTR_DACWFP(x) (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACWFP_SHIFT)) & DAC_PTR_DACWFP_MASK)

#define	DAC_PTR_DACRFP_MASK (0xFF0000U)

#define	DAC_PTR_DACRFP_SHIFT (16U)

#define	DAC_PTR_DACRFP(x) (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACRFP_SHIFT)) & DAC_PTR_DACRFP_MASK)

CR2 - DAC Status and Control Register 2
#define	DAC_CR2_BFEN_MASK (0x1U)

#define	DAC_CR2_BFEN_SHIFT (0U)

#define	DAC_CR2_BFEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFEN_SHIFT)) & DAC_CR2_BFEN_MASK)

#define	DAC_CR2_OEN_MASK (0x2U)

#define	DAC_CR2_OEN_SHIFT (1U)

#define	DAC_CR2_OEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_OEN_SHIFT)) & DAC_CR2_OEN_MASK)

#define	DAC_CR2_BFMS_MASK (0x4U)

#define	DAC_CR2_BFMS_SHIFT (2U)

#define	DAC_CR2_BFMS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFMS_SHIFT)) & DAC_CR2_BFMS_MASK)

#define	DAC_CR2_BFHS_MASK (0x8U)

#define	DAC_CR2_BFHS_SHIFT (3U)

#define	DAC_CR2_BFHS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFHS_SHIFT)) & DAC_CR2_BFHS_MASK)

#define	DAC_CR2_IREF2_MASK (0x10U)

#define	DAC_CR2_IREF2_SHIFT (4U)

#define	DAC_CR2_IREF2(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF2_SHIFT)) & DAC_CR2_IREF2_MASK)

#define	DAC_CR2_IREF1_MASK (0x20U)

#define	DAC_CR2_IREF1_SHIFT (5U)

#define	DAC_CR2_IREF1(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF1_SHIFT)) & DAC_CR2_IREF1_MASK)

#define	DAC_CR2_IREF_MASK (0x40U)

#define	DAC_CR2_IREF_SHIFT (6U)

#define	DAC_CR2_IREF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF_SHIFT)) & DAC_CR2_IREF_MASK)

VERID - Version Identifier Register
#define	DAC_VERID_FEATURE_MASK (0xFFFFU)

#define	DAC_VERID_FEATURE_SHIFT (0U)

#define	DAC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_FEATURE_SHIFT)) & DAC_VERID_FEATURE_MASK)

#define	DAC_VERID_MINOR_MASK (0xFF0000U)

#define	DAC_VERID_MINOR_SHIFT (16U)

#define	DAC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MINOR_SHIFT)) & DAC_VERID_MINOR_MASK)

#define	DAC_VERID_MAJOR_MASK (0xFF000000U)

#define	DAC_VERID_MAJOR_SHIFT (24U)

#define	DAC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MAJOR_SHIFT)) & DAC_VERID_MAJOR_MASK)

PARAM - Parameter Register
#define	DAC_PARAM_FIFOSZ_MASK (0x7U)

#define	DAC_PARAM_FIFOSZ_SHIFT (0U)

#define	DAC_PARAM_FIFOSZ(x) (((uint32_t)(((uint32_t)(x)) << DAC_PARAM_FIFOSZ_SHIFT)) & DAC_PARAM_FIFOSZ_MASK)

DATA - DAC Data Register
#define	DAC_DATA_DATA0_MASK (0xFFFU)

#define	DAC_DATA_DATA0_SHIFT (0U)

#define	DAC_DATA_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DAC_DATA_DATA0_SHIFT)) & DAC_DATA_DATA0_MASK)

CR - DAC Status and Control Register
#define	DAC_CR_FULLF_MASK (0x1U)

#define	DAC_CR_FULLF_SHIFT (0U)

#define	DAC_CR_FULLF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLF_SHIFT)) & DAC_CR_FULLF_MASK)

#define	DAC_CR_NEMPTF_MASK (0x2U)

#define	DAC_CR_NEMPTF_SHIFT (1U)

#define	DAC_CR_NEMPTF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_NEMPTF_SHIFT)) & DAC_CR_NEMPTF_MASK)

#define	DAC_CR_WMF_MASK (0x4U)

#define	DAC_CR_WMF_SHIFT (2U)

#define	DAC_CR_WMF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WMF_SHIFT)) & DAC_CR_WMF_MASK)

#define	DAC_CR_UDFF_MASK (0x8U)

#define	DAC_CR_UDFF_SHIFT (3U)

#define	DAC_CR_UDFF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_UDFF_SHIFT)) & DAC_CR_UDFF_MASK)

#define	DAC_CR_OVFF_MASK (0x10U)

#define	DAC_CR_OVFF_SHIFT (4U)

#define	DAC_CR_OVFF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_OVFF_SHIFT)) & DAC_CR_OVFF_MASK)

#define	DAC_CR_FULLIE_MASK (0x100U)

#define	DAC_CR_FULLIE_SHIFT (8U)

#define	DAC_CR_FULLIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLIE_SHIFT)) & DAC_CR_FULLIE_MASK)

#define	DAC_CR_EMPTIE_MASK (0x200U)

#define	DAC_CR_EMPTIE_SHIFT (9U)

#define	DAC_CR_EMPTIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_EMPTIE_SHIFT)) & DAC_CR_EMPTIE_MASK)

#define	DAC_CR_WTMIE_MASK (0x400U)

#define	DAC_CR_WTMIE_SHIFT (10U)

#define	DAC_CR_WTMIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WTMIE_SHIFT)) & DAC_CR_WTMIE_MASK)

#define	DAC_CR_SWTRG_MASK (0x1000U)

#define	DAC_CR_SWTRG_SHIFT (12U)

#define	DAC_CR_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWTRG_SHIFT)) & DAC_CR_SWTRG_MASK)

#define	DAC_CR_TRGSEL_MASK (0x2000U)

#define	DAC_CR_TRGSEL_SHIFT (13U)

#define	DAC_CR_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_TRGSEL_SHIFT)) & DAC_CR_TRGSEL_MASK)

#define	DAC_CR_DACRFS_MASK (0x4000U)

#define	DAC_CR_DACRFS_SHIFT (14U)

#define	DAC_CR_DACRFS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACRFS_SHIFT)) & DAC_CR_DACRFS_MASK)

#define	DAC_CR_DACEN_MASK (0x8000U)

#define	DAC_CR_DACEN_SHIFT (15U)

#define	DAC_CR_DACEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACEN_SHIFT)) & DAC_CR_DACEN_MASK)

#define	DAC_CR_FIFOEN_MASK (0x10000U)

#define	DAC_CR_FIFOEN_SHIFT (16U)

#define	DAC_CR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFOEN_SHIFT)) & DAC_CR_FIFOEN_MASK)

#define	DAC_CR_SWMD_MASK (0x20000U)

#define	DAC_CR_SWMD_SHIFT (17U)

#define	DAC_CR_SWMD(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWMD_SHIFT)) & DAC_CR_SWMD_MASK)

#define	DAC_CR_UVIE_MASK (0x40000U)

#define	DAC_CR_UVIE_SHIFT (18U)

#define	DAC_CR_UVIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_UVIE_SHIFT)) & DAC_CR_UVIE_MASK)

#define	DAC_CR_FIFORST_MASK (0x200000U)

#define	DAC_CR_FIFORST_SHIFT (21U)

#define	DAC_CR_FIFORST(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFORST_SHIFT)) & DAC_CR_FIFORST_MASK)

#define	DAC_CR_SWRST_MASK (0x400000U)

#define	DAC_CR_SWRST_SHIFT (22U)

#define	DAC_CR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWRST_SHIFT)) & DAC_CR_SWRST_MASK)

#define	DAC_CR_DMAEN_MASK (0x800000U)

#define	DAC_CR_DMAEN_SHIFT (23U)

#define	DAC_CR_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DMAEN_SHIFT)) & DAC_CR_DMAEN_MASK)

#define	DAC_CR_WML_MASK (0xFF000000U)

#define	DAC_CR_WML_SHIFT (24U)

#define	DAC_CR_WML(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WML_SHIFT)) & DAC_CR_WML_MASK)

PTR - DAC FIFO Pointer Register
#define	DAC_PTR_DACWFP_MASK (0xFFU)

#define	DAC_PTR_DACWFP_SHIFT (0U)

#define	DAC_PTR_DACWFP(x) (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACWFP_SHIFT)) & DAC_PTR_DACWFP_MASK)

#define	DAC_PTR_DACRFP_MASK (0xFF0000U)

#define	DAC_PTR_DACRFP_SHIFT (16U)

#define	DAC_PTR_DACRFP(x) (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACRFP_SHIFT)) & DAC_PTR_DACRFP_MASK)

CR2 - DAC Status and Control Register 2
#define	DAC_CR2_BFEN_MASK (0x1U)

#define	DAC_CR2_BFEN_SHIFT (0U)

#define	DAC_CR2_BFEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFEN_SHIFT)) & DAC_CR2_BFEN_MASK)

#define	DAC_CR2_OEN_MASK (0x2U)

#define	DAC_CR2_OEN_SHIFT (1U)

#define	DAC_CR2_OEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_OEN_SHIFT)) & DAC_CR2_OEN_MASK)

#define	DAC_CR2_BFMS_MASK (0x4U)

#define	DAC_CR2_BFMS_SHIFT (2U)

#define	DAC_CR2_BFMS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFMS_SHIFT)) & DAC_CR2_BFMS_MASK)

#define	DAC_CR2_BFHS_MASK (0x8U)

#define	DAC_CR2_BFHS_SHIFT (3U)

#define	DAC_CR2_BFHS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFHS_SHIFT)) & DAC_CR2_BFHS_MASK)

#define	DAC_CR2_IREF2_MASK (0x10U)

#define	DAC_CR2_IREF2_SHIFT (4U)

#define	DAC_CR2_IREF2(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF2_SHIFT)) & DAC_CR2_IREF2_MASK)

#define	DAC_CR2_IREF1_MASK (0x20U)

#define	DAC_CR2_IREF1_SHIFT (5U)

#define	DAC_CR2_IREF1(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF1_SHIFT)) & DAC_CR2_IREF1_MASK)

#define	DAC_CR2_IREF_MASK (0x40U)

#define	DAC_CR2_IREF_SHIFT (6U)

#define	DAC_CR2_IREF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF_SHIFT)) & DAC_CR2_IREF_MASK)

Detailed Description

Macro Definition Documentation

◆ DAC_CR2_BFEN [1/2]

#define DAC_CR2_BFEN ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFEN_SHIFT)) & DAC_CR2_BFEN_MASK)

BFEN - Buffer Enable 0b0..Opamp is not used as buffer 0b1..Opamp is used as buffer

◆ DAC_CR2_BFEN [2/2]

#define DAC_CR2_BFEN ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFEN_SHIFT)) & DAC_CR2_BFEN_MASK)

BFEN - Buffer Enable 0b0..Opamp is not used as buffer 0b1..Opamp is used as buffer

◆ DAC_CR2_BFHS [1/2]

#define DAC_CR2_BFHS ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFHS_SHIFT)) & DAC_CR2_BFHS_MASK)

BFHS - Buffer High Speed Select 0b0..Buffer high speed not selected 0b1..Buffer high speed selected

◆ DAC_CR2_BFHS [2/2]

#define DAC_CR2_BFHS ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFHS_SHIFT)) & DAC_CR2_BFHS_MASK)

BFHS - Buffer High Speed Select 0b0..Buffer high speed not selected 0b1..Buffer high speed selected

◆ DAC_CR2_BFMS [1/2]

#define DAC_CR2_BFMS ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFMS_SHIFT)) & DAC_CR2_BFMS_MASK)

BFMS - Buffer Middle Speed Select 0b0..Buffer middle speed not selected 0b1..Buffer middle speed selected

◆ DAC_CR2_BFMS [2/2]

#define DAC_CR2_BFMS ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFMS_SHIFT)) & DAC_CR2_BFMS_MASK)

BFMS - Buffer Middle Speed Select 0b0..Buffer middle speed not selected 0b1..Buffer middle speed selected

◆ DAC_CR2_IREF [1/2]

#define DAC_CR2_IREF ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF_SHIFT)) & DAC_CR2_IREF_MASK)

IREF - Internal Current Reference Select 0b0..Internal Current Reference not selected 0b1..Internal Current Reference selected

◆ DAC_CR2_IREF [2/2]

#define DAC_CR2_IREF ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF_SHIFT)) & DAC_CR2_IREF_MASK)

IREF - Internal Current Reference Select 0b0..Internal Current Reference not selected 0b1..Internal Current Reference selected

◆ DAC_CR2_IREF1 [1/2]

#define DAC_CR2_IREF1 ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF1_SHIFT)) & DAC_CR2_IREF1_MASK)

IREF1 - Internal ZTC (Zero Temperature Coefficient) Current Reference Select 0b0..Internal ZTC Current Reference not selected 0b1..Internal ZTC Current Reference selected

◆ DAC_CR2_IREF1 [2/2]

#define DAC_CR2_IREF1 ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF1_SHIFT)) & DAC_CR2_IREF1_MASK)

IREF1 - Internal ZTC (Zero Temperature Coefficient) Current Reference Select 0b0..Internal ZTC Current Reference not selected 0b1..Internal ZTC Current Reference selected

◆ DAC_CR2_IREF2 [1/2]

#define DAC_CR2_IREF2 ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF2_SHIFT)) & DAC_CR2_IREF2_MASK)

IREF2 - Internal PTAT (Proportional To Absolute Temperature) Current Reference Select 0b0..Internal PTAT Current Reference not selected 0b1..Internal PTAT Current Reference selected

◆ DAC_CR2_IREF2 [2/2]

#define DAC_CR2_IREF2 ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF2_SHIFT)) & DAC_CR2_IREF2_MASK)

IREF2 - Internal PTAT (Proportional To Absolute Temperature) Current Reference Select 0b0..Internal PTAT Current Reference not selected 0b1..Internal PTAT Current Reference selected

◆ DAC_CR2_OEN [1/2]

#define DAC_CR2_OEN ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_OEN_SHIFT)) & DAC_CR2_OEN_MASK)

OEN - Optional Enable 0b0..Output buffer is not bypassed 0b1..Output buffer is bypassed

◆ DAC_CR2_OEN [2/2]

#define DAC_CR2_OEN ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_OEN_SHIFT)) & DAC_CR2_OEN_MASK)

OEN - Optional Enable 0b0..Output buffer is not bypassed 0b1..Output buffer is bypassed

◆ DAC_CR_DACEN [1/2]

#define DAC_CR_DACEN ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACEN_SHIFT)) & DAC_CR_DACEN_MASK)

DACEN - DAC Enable 0b0..The DAC system is disabled. 0b1..The DAC system is enabled.

◆ DAC_CR_DACEN [2/2]

#define DAC_CR_DACEN ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACEN_SHIFT)) & DAC_CR_DACEN_MASK)

DACEN - DAC Enable 0b0..The DAC system is disabled. 0b1..The DAC system is enabled.

◆ DAC_CR_DACRFS [1/2]

#define DAC_CR_DACRFS ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACRFS_SHIFT)) & DAC_CR_DACRFS_MASK)

DACRFS - DAC Reference Select 0b0..The DAC selects DACREF_1 as the reference voltage. 0b1..The DAC selects DACREF_2 as the reference voltage.

◆ DAC_CR_DACRFS [2/2]

#define DAC_CR_DACRFS ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACRFS_SHIFT)) & DAC_CR_DACRFS_MASK)

DACRFS - DAC Reference Select 0b0..The DAC selects DACREF_1 as the reference voltage. 0b1..The DAC selects DACREF_2 as the reference voltage.

◆ DAC_CR_DMAEN [1/2]

#define DAC_CR_DMAEN ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DMAEN_SHIFT)) & DAC_CR_DMAEN_MASK)

DMAEN - DMA Enable Select 0b0..DMA is disabled. 0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time.

◆ DAC_CR_DMAEN [2/2]

#define DAC_CR_DMAEN ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DMAEN_SHIFT)) & DAC_CR_DMAEN_MASK)

DMAEN - DMA Enable Select 0b0..DMA is disabled. 0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time.

◆ DAC_CR_EMPTIE [1/2]

#define DAC_CR_EMPTIE ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_EMPTIE_SHIFT)) & DAC_CR_EMPTIE_MASK)

EMPTIE - Nearly Empty Interrupt Enable 0b0..FIFO Nearly Empty interrupt is disabled. 0b1..FIFO Nearly Empty interrupt is enabled.

◆ DAC_CR_EMPTIE [2/2]

#define DAC_CR_EMPTIE ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_EMPTIE_SHIFT)) & DAC_CR_EMPTIE_MASK)

EMPTIE - Nearly Empty Interrupt Enable 0b0..FIFO Nearly Empty interrupt is disabled. 0b1..FIFO Nearly Empty interrupt is enabled.

◆ DAC_CR_FIFOEN [1/2]

#define DAC_CR_FIFOEN ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFOEN_SHIFT)) & DAC_CR_FIFOEN_MASK)

FIFOEN - FIFO Enable 0b0..FIFO is disabled and only one level buffer is enabled. Any data written from this buffer goes to conversion. 0b1..FIFO is enabled. Data will first read from FIFO to buffer then go to conversion.

◆ DAC_CR_FIFOEN [2/2]

#define DAC_CR_FIFOEN ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFOEN_SHIFT)) & DAC_CR_FIFOEN_MASK)

FIFOEN - FIFO Enable 0b0..FIFO is disabled and only one level buffer is enabled. Any data written from this buffer goes to conversion. 0b1..FIFO is enabled. Data will first read from FIFO to buffer then go to conversion.

◆ DAC_CR_FIFORST [1/2]

#define DAC_CR_FIFORST ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFORST_SHIFT)) & DAC_CR_FIFORST_MASK)

FIFORST - FIFO Reset 0b0..No effect 0b1..FIFO reset

◆ DAC_CR_FIFORST [2/2]

#define DAC_CR_FIFORST ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFORST_SHIFT)) & DAC_CR_FIFORST_MASK)

FIFORST - FIFO Reset 0b0..No effect 0b1..FIFO reset

◆ DAC_CR_FULLF [1/2]

#define DAC_CR_FULLF ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLF_SHIFT)) & DAC_CR_FULLF_MASK)

FULLF - Full Flag 0b0..FIFO is not full. 0b1..FIFO is full.

◆ DAC_CR_FULLF [2/2]

#define DAC_CR_FULLF ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLF_SHIFT)) & DAC_CR_FULLF_MASK)

FULLF - Full Flag 0b0..FIFO is not full. 0b1..FIFO is full.

◆ DAC_CR_FULLIE [1/2]

#define DAC_CR_FULLIE ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLIE_SHIFT)) & DAC_CR_FULLIE_MASK)

FULLIE - Full Interrupt Enable 0b0..FIFO Full interrupt is disabled. 0b1..FIFO Full interrupt is enabled.

◆ DAC_CR_FULLIE [2/2]

#define DAC_CR_FULLIE ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLIE_SHIFT)) & DAC_CR_FULLIE_MASK)

FULLIE - Full Interrupt Enable 0b0..FIFO Full interrupt is disabled. 0b1..FIFO Full interrupt is enabled.

◆ DAC_CR_NEMPTF [1/2]

#define DAC_CR_NEMPTF ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_NEMPTF_SHIFT)) & DAC_CR_NEMPTF_MASK)

NEMPTF - Nearly Empty Flag 0b0..More than one data is available in the FIFO. 0b1..One data is available in the FIFO.

◆ DAC_CR_NEMPTF [2/2]

#define DAC_CR_NEMPTF ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_NEMPTF_SHIFT)) & DAC_CR_NEMPTF_MASK)

NEMPTF - Nearly Empty Flag 0b0..More than one data is available in the FIFO. 0b1..One data is available in the FIFO.

◆ DAC_CR_OVFF [1/2]

#define DAC_CR_OVFF ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_OVFF_SHIFT)) & DAC_CR_OVFF_MASK)

OVFF - Overflow Flag 0b0..No overflow has occurred since the last time the flag was cleared. 0b1..At least one FIFO overflow has occurred since the last time the flag was cleared.

◆ DAC_CR_OVFF [2/2]

#define DAC_CR_OVFF ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_OVFF_SHIFT)) & DAC_CR_OVFF_MASK)

OVFF - Overflow Flag 0b0..No overflow has occurred since the last time the flag was cleared. 0b1..At least one FIFO overflow has occurred since the last time the flag was cleared.

◆ DAC_CR_SWMD [1/2]

#define DAC_CR_SWMD ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWMD_SHIFT)) & DAC_CR_SWMD_MASK)

SWMD - DAC FIFO Mode Select 0b0..Normal mode 0b1..Swing back mode

◆ DAC_CR_SWMD [2/2]

#define DAC_CR_SWMD ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWMD_SHIFT)) & DAC_CR_SWMD_MASK)

SWMD - DAC FIFO Mode Select 0b0..Normal mode 0b1..Swing back mode

◆ DAC_CR_SWRST [1/2]

#define DAC_CR_SWRST ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWRST_SHIFT)) & DAC_CR_SWRST_MASK)

SWRST - Software reset

◆ DAC_CR_SWRST [2/2]

#define DAC_CR_SWRST ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWRST_SHIFT)) & DAC_CR_SWRST_MASK)

SWRST - Software reset

◆ DAC_CR_SWTRG [1/2]

#define DAC_CR_SWTRG ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWTRG_SHIFT)) & DAC_CR_SWTRG_MASK)

SWTRG - DAC Software Trigger 0b0..The DAC soft trigger is not valid. 0b1..The DAC soft trigger is valid.

◆ DAC_CR_SWTRG [2/2]

#define DAC_CR_SWTRG ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWTRG_SHIFT)) & DAC_CR_SWTRG_MASK)

SWTRG - DAC Software Trigger 0b0..The DAC soft trigger is not valid. 0b1..The DAC soft trigger is valid.

◆ DAC_CR_TRGSEL [1/2]

#define DAC_CR_TRGSEL ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_TRGSEL_SHIFT)) & DAC_CR_TRGSEL_MASK)

TRGSEL - DAC Trigger Select 0b0..The DAC hardware trigger is selected. 0b1..The DAC software trigger is selected.

◆ DAC_CR_TRGSEL [2/2]

#define DAC_CR_TRGSEL ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_TRGSEL_SHIFT)) & DAC_CR_TRGSEL_MASK)

TRGSEL - DAC Trigger Select 0b0..The DAC hardware trigger is selected. 0b1..The DAC software trigger is selected.

◆ DAC_CR_UDFF [1/2]

#define DAC_CR_UDFF ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_UDFF_SHIFT)) & DAC_CR_UDFF_MASK)

UDFF - Underflow Flag 0b0..No underflow has occurred since the last time the flag was cleared. 0b1..At least one trigger underflow has occurred since the last time the flag was cleared.

◆ DAC_CR_UDFF [2/2]

#define DAC_CR_UDFF ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_UDFF_SHIFT)) & DAC_CR_UDFF_MASK)

UDFF - Underflow Flag 0b0..No underflow has occurred since the last time the flag was cleared. 0b1..At least one trigger underflow has occurred since the last time the flag was cleared.

◆ DAC_CR_UVIE [1/2]

#define DAC_CR_UVIE ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_UVIE_SHIFT)) & DAC_CR_UVIE_MASK)

UVIE - Underflow and overflow interrupt enable 0b0..Underflow and overflow interrupt is disabled. 0b1..Underflow and overflow interrupt is enabled.

◆ DAC_CR_UVIE [2/2]

#define DAC_CR_UVIE ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_UVIE_SHIFT)) & DAC_CR_UVIE_MASK)

UVIE - Underflow and overflow interrupt enable 0b0..Underflow and overflow interrupt is disabled. 0b1..Underflow and overflow interrupt is enabled.

◆ DAC_CR_WMF [1/2]

#define DAC_CR_WMF ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WMF_SHIFT)) & DAC_CR_WMF_MASK)

WMF - FIFO Watermark Status Flag 0b0..The DAC buffer read pointer has not reached the watermark level. 0b1..The DAC buffer read pointer has reached the watermark level.

◆ DAC_CR_WMF [2/2]

#define DAC_CR_WMF ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WMF_SHIFT)) & DAC_CR_WMF_MASK)

WMF - FIFO Watermark Status Flag 0b0..The DAC buffer read pointer has not reached the watermark level. 0b1..The DAC buffer read pointer has reached the watermark level.

◆ DAC_CR_WML [1/2]

#define DAC_CR_WML ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WML_SHIFT)) & DAC_CR_WML_MASK)

WML - Watermark Level Select

◆ DAC_CR_WML [2/2]

#define DAC_CR_WML ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WML_SHIFT)) & DAC_CR_WML_MASK)

WML - Watermark Level Select

◆ DAC_CR_WTMIE [1/2]

#define DAC_CR_WTMIE ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WTMIE_SHIFT)) & DAC_CR_WTMIE_MASK)

WTMIE - Watermark Interrupt Enable 0b0..Watermark interrupt is disabled. 0b1..Watermark interrupt is enabled.

◆ DAC_CR_WTMIE [2/2]

#define DAC_CR_WTMIE ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WTMIE_SHIFT)) & DAC_CR_WTMIE_MASK)

WTMIE - Watermark Interrupt Enable 0b0..Watermark interrupt is disabled. 0b1..Watermark interrupt is enabled.

◆ DAC_DATA_DATA0 [1/2]

#define DAC_DATA_DATA0 ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_DATA_DATA0_SHIFT)) & DAC_DATA_DATA0_MASK)

DATA0 - FIFO DATA0

◆ DAC_DATA_DATA0 [2/2]

#define DAC_DATA_DATA0 ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_DATA_DATA0_SHIFT)) & DAC_DATA_DATA0_MASK)

DATA0 - FIFO DATA0

◆ DAC_PARAM_FIFOSZ [1/2]

#define DAC_PARAM_FIFOSZ ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_PARAM_FIFOSZ_SHIFT)) & DAC_PARAM_FIFOSZ_MASK)

FIFOSZ - FIFO size 0b000..FIFO depth is 2 0b001..FIFO depth is 4 0b010..FIFO depth is 8 0b011..FIFO depth is 16 0b100..FIFO depth is 32 0b101..FIFO depth is 64 0b110..FIFO depth is 128 0b111..FIFO depth is 256

◆ DAC_PARAM_FIFOSZ [2/2]

#define DAC_PARAM_FIFOSZ ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_PARAM_FIFOSZ_SHIFT)) & DAC_PARAM_FIFOSZ_MASK)

FIFOSZ - FIFO size 0b000..FIFO depth is 2 0b001..FIFO depth is 4 0b010..FIFO depth is 8 0b011..FIFO depth is 16 0b100..FIFO depth is 32 0b101..FIFO depth is 64 0b110..FIFO depth is 128 0b111..FIFO depth is 256

◆ DAC_PTR_DACRFP [1/2]

#define DAC_PTR_DACRFP ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACRFP_SHIFT)) & DAC_PTR_DACRFP_MASK)

DACRFP - DACRFP

◆ DAC_PTR_DACRFP [2/2]

#define DAC_PTR_DACRFP ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACRFP_SHIFT)) & DAC_PTR_DACRFP_MASK)

DACRFP - DACRFP

◆ DAC_PTR_DACWFP [1/2]

#define DAC_PTR_DACWFP ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACWFP_SHIFT)) & DAC_PTR_DACWFP_MASK)

DACWFP - DACWFP

◆ DAC_PTR_DACWFP [2/2]

#define DAC_PTR_DACWFP ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACWFP_SHIFT)) & DAC_PTR_DACWFP_MASK)

DACWFP - DACWFP

◆ DAC_VERID_FEATURE [1/2]

#define DAC_VERID_FEATURE ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_FEATURE_SHIFT)) & DAC_VERID_FEATURE_MASK)

FEATURE - Feature Identification Number 0b0000000000000000..Standard feature set 0b0000000000000001..C40 feature set 0b0000000000000010..5V DAC feature set 0b0000000000000100..ADC BIST feature set

◆ DAC_VERID_FEATURE [2/2]

#define DAC_VERID_FEATURE ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_FEATURE_SHIFT)) & DAC_VERID_FEATURE_MASK)

FEATURE - Feature Identification Number 0b0000000000000000..Standard feature set 0b0000000000000001..C40 feature set 0b0000000000000010..5V DAC feature set 0b0000000000000100..ADC BIST feature set

◆ DAC_VERID_MAJOR [1/2]

#define DAC_VERID_MAJOR ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MAJOR_SHIFT)) & DAC_VERID_MAJOR_MASK)

MAJOR - Major version number

◆ DAC_VERID_MAJOR [2/2]

#define DAC_VERID_MAJOR ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MAJOR_SHIFT)) & DAC_VERID_MAJOR_MASK)

MAJOR - Major version number

◆ DAC_VERID_MINOR [1/2]

#define DAC_VERID_MINOR ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MINOR_SHIFT)) & DAC_VERID_MINOR_MASK)

MINOR - Minor version number

◆ DAC_VERID_MINOR [2/2]

#define DAC_VERID_MINOR ( x ) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MINOR_SHIFT)) & DAC_VERID_MINOR_MASK)

MINOR - Minor version number

VERID - Version Identifier Register

PARAM - Parameter Register

DATA - DAC Data Register

CR - DAC Status and Control Register

PTR - DAC FIFO Pointer Register

CR2 - DAC Status and Control Register 2

VERID - Version Identifier Register

PARAM - Parameter Register

DATA - DAC Data Register

CR - DAC Status and Control Register

PTR - DAC FIFO Pointer Register

CR2 - DAC Status and Control Register 2

Detailed Description

Macro Definition Documentation

◆ DAC_CR2_BFEN [1/2]

◆ DAC_CR2_BFEN [2/2]

◆ DAC_CR2_BFHS [1/2]

◆ DAC_CR2_BFHS [2/2]

◆ DAC_CR2_BFMS [1/2]

◆ DAC_CR2_BFMS [2/2]

◆ DAC_CR2_IREF [1/2]

◆ DAC_CR2_IREF [2/2]

◆ DAC_CR2_IREF1 [1/2]

◆ DAC_CR2_IREF1 [2/2]

◆ DAC_CR2_IREF2 [1/2]

◆ DAC_CR2_IREF2 [2/2]

◆ DAC_CR2_OEN [1/2]

◆ DAC_CR2_OEN [2/2]

◆ DAC_CR_DACEN [1/2]

◆ DAC_CR_DACEN [2/2]

◆ DAC_CR_DACRFS [1/2]

◆ DAC_CR_DACRFS [2/2]

◆ DAC_CR_DMAEN [1/2]

◆ DAC_CR_DMAEN [2/2]

◆ DAC_CR_EMPTIE [1/2]

◆ DAC_CR_EMPTIE [2/2]

◆ DAC_CR_FIFOEN [1/2]

◆ DAC_CR_FIFOEN [2/2]

◆ DAC_CR_FIFORST [1/2]

◆ DAC_CR_FIFORST [2/2]

◆ DAC_CR_FULLF [1/2]

◆ DAC_CR_FULLF [2/2]

◆ DAC_CR_FULLIE [1/2]

◆ DAC_CR_FULLIE [2/2]

◆ DAC_CR_NEMPTF [1/2]

◆ DAC_CR_NEMPTF [2/2]

◆ DAC_CR_OVFF [1/2]

◆ DAC_CR_OVFF [2/2]

◆ DAC_CR_SWMD [1/2]

◆ DAC_CR_SWMD [2/2]

◆ DAC_CR_SWRST [1/2]

◆ DAC_CR_SWRST [2/2]

◆ DAC_CR_SWTRG [1/2]

◆ DAC_CR_SWTRG [2/2]

◆ DAC_CR_TRGSEL [1/2]

◆ DAC_CR_TRGSEL [2/2]

◆ DAC_CR_UDFF [1/2]

◆ DAC_CR_UDFF [2/2]

◆ DAC_CR_UVIE [1/2]

◆ DAC_CR_UVIE [2/2]

◆ DAC_CR_WMF [1/2]

◆ DAC_CR_WMF [2/2]

◆ DAC_CR_WML [1/2]

◆ DAC_CR_WML [2/2]

◆ DAC_CR_WTMIE [1/2]

◆ DAC_CR_WTMIE [2/2]

◆ DAC_DATA_DATA0 [1/2]

◆ DAC_DATA_DATA0 [2/2]

◆ DAC_PARAM_FIFOSZ [1/2]

◆ DAC_PARAM_FIFOSZ [2/2]

◆ DAC_PTR_DACRFP [1/2]

◆ DAC_PTR_DACRFP [2/2]

◆ DAC_PTR_DACWFP [1/2]

◆ DAC_PTR_DACWFP [2/2]

◆ DAC_VERID_FEATURE [1/2]

◆ DAC_VERID_FEATURE [2/2]

◆ DAC_VERID_MAJOR [1/2]

◆ DAC_VERID_MAJOR [2/2]

◆ DAC_VERID_MINOR [1/2]

◆ DAC_VERID_MINOR [2/2]