Trace Port Interface (TPI)

Type definitions for the Trace Port Interface (TPI) More...

Modules
	Floating Point Unit (FPU)
	Type definitions for the Floating Point Unit (FPU)

Data Structures
struct	TPI_Type
	Structure type to access the Trace Port Interface Register (TPI). More...
#define	TPI_ACPR_PRESCALER_Pos   0U
#define	TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
#define	TPI_SPPR_TXMODE_Pos   0U
#define	TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
#define	TPI_FFSR_FtNonStop_Pos   3U
#define	TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define	TPI_FFSR_TCPresent_Pos   2U
#define	TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
#define	TPI_FFSR_FtStopped_Pos   1U
#define	TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
#define	TPI_FFSR_FlInProg_Pos   0U
#define	TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
#define	TPI_FFCR_TrigIn_Pos   8U
#define	TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
#define	TPI_FFCR_EnFCont_Pos   1U
#define	TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
#define	TPI_TRIGGER_TRIGGER_Pos   0U
#define	TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
#define	TPI_FIFO0_ITM_ATVALID_Pos   29U
#define	TPI_FIFO0_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)
#define	TPI_FIFO0_ITM_bytecount_Pos   27U
#define	TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
#define	TPI_FIFO0_ETM_ATVALID_Pos   26U
#define	TPI_FIFO0_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)
#define	TPI_FIFO0_ETM_bytecount_Pos   24U
#define	TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
#define	TPI_FIFO0_ETM2_Pos   16U
#define	TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)
#define	TPI_FIFO0_ETM1_Pos   8U
#define	TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)
#define	TPI_FIFO0_ETM0_Pos   0U
#define	TPI_FIFO0_ETM0_Msk   (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
#define	TPI_ITATBCTR2_ATREADY2_Pos   0U
#define	TPI_ITATBCTR2_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)
#define	TPI_ITATBCTR2_ATREADY1_Pos   0U
#define	TPI_ITATBCTR2_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)
#define	TPI_FIFO1_ITM_ATVALID_Pos   29U
#define	TPI_FIFO1_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)
#define	TPI_FIFO1_ITM_bytecount_Pos   27U
#define	TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
#define	TPI_FIFO1_ETM_ATVALID_Pos   26U
#define	TPI_FIFO1_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)
#define	TPI_FIFO1_ETM_bytecount_Pos   24U
#define	TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
#define	TPI_FIFO1_ITM2_Pos   16U
#define	TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)
#define	TPI_FIFO1_ITM1_Pos   8U
#define	TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)
#define	TPI_FIFO1_ITM0_Pos   0U
#define	TPI_FIFO1_ITM0_Msk   (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
#define	TPI_ITATBCTR0_ATREADY2_Pos   0U
#define	TPI_ITATBCTR0_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)
#define	TPI_ITATBCTR0_ATREADY1_Pos   0U
#define	TPI_ITATBCTR0_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)
#define	TPI_ITCTRL_Mode_Pos   0U
#define	TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
#define	TPI_DEVID_NRZVALID_Pos   11U
#define	TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define	TPI_DEVID_MANCVALID_Pos   10U
#define	TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define	TPI_DEVID_PTINVALID_Pos   9U
#define	TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define	TPI_DEVID_MinBufSz_Pos   6U
#define	TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)
#define	TPI_DEVID_AsynClkIn_Pos   5U
#define	TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)
#define	TPI_DEVID_NrTraceInput_Pos   0U
#define	TPI_DEVID_NrTraceInput_Msk   (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
#define	TPI_DEVTYPE_SubType_Pos   4U
#define	TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
#define	TPI_DEVTYPE_MajorType_Pos   0U
#define	TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
#define	TPI_ACPR_PRESCALER_Pos   0U
#define	TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
#define	TPI_SPPR_TXMODE_Pos   0U
#define	TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
#define	TPI_FFSR_FtNonStop_Pos   3U
#define	TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define	TPI_FFSR_TCPresent_Pos   2U
#define	TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
#define	TPI_FFSR_FtStopped_Pos   1U
#define	TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
#define	TPI_FFSR_FlInProg_Pos   0U
#define	TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
#define	TPI_FFCR_TrigIn_Pos   8U
#define	TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
#define	TPI_FFCR_EnFCont_Pos   1U
#define	TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
#define	TPI_TRIGGER_TRIGGER_Pos   0U
#define	TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
#define	TPI_FIFO0_ITM_ATVALID_Pos   29U
#define	TPI_FIFO0_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)
#define	TPI_FIFO0_ITM_bytecount_Pos   27U
#define	TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
#define	TPI_FIFO0_ETM_ATVALID_Pos   26U
#define	TPI_FIFO0_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)
#define	TPI_FIFO0_ETM_bytecount_Pos   24U
#define	TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
#define	TPI_FIFO0_ETM2_Pos   16U
#define	TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)
#define	TPI_FIFO0_ETM1_Pos   8U
#define	TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)
#define	TPI_FIFO0_ETM0_Pos   0U
#define	TPI_FIFO0_ETM0_Msk   (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
#define	TPI_ITATBCTR2_ATREADY2_Pos   0U
#define	TPI_ITATBCTR2_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)
#define	TPI_ITATBCTR2_ATREADY1_Pos   0U
#define	TPI_ITATBCTR2_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)
#define	TPI_FIFO1_ITM_ATVALID_Pos   29U
#define	TPI_FIFO1_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)
#define	TPI_FIFO1_ITM_bytecount_Pos   27U
#define	TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
#define	TPI_FIFO1_ETM_ATVALID_Pos   26U
#define	TPI_FIFO1_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)
#define	TPI_FIFO1_ETM_bytecount_Pos   24U
#define	TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
#define	TPI_FIFO1_ITM2_Pos   16U
#define	TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)
#define	TPI_FIFO1_ITM1_Pos   8U
#define	TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)
#define	TPI_FIFO1_ITM0_Pos   0U
#define	TPI_FIFO1_ITM0_Msk   (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
#define	TPI_ITATBCTR0_ATREADY2_Pos   0U
#define	TPI_ITATBCTR0_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)
#define	TPI_ITATBCTR0_ATREADY1_Pos   0U
#define	TPI_ITATBCTR0_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)
#define	TPI_ITCTRL_Mode_Pos   0U
#define	TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
#define	TPI_DEVID_NRZVALID_Pos   11U
#define	TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define	TPI_DEVID_MANCVALID_Pos   10U
#define	TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define	TPI_DEVID_PTINVALID_Pos   9U
#define	TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define	TPI_DEVID_MinBufSz_Pos   6U
#define	TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)
#define	TPI_DEVID_AsynClkIn_Pos   5U
#define	TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)
#define	TPI_DEVID_NrTraceInput_Pos   0U
#define	TPI_DEVID_NrTraceInput_Msk   (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
#define	TPI_DEVTYPE_SubType_Pos   4U
#define	TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
#define	TPI_DEVTYPE_MajorType_Pos   0U
#define	TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

Detailed Description

Type definitions for the Trace Port Interface (TPI)

Macro Definition Documentation

TPI_ACPR_PRESCALER_Msk [1/2]

#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

TPI_ACPR_PRESCALER_Msk [2/2]

#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

TPI_ACPR_PRESCALER_Pos [1/2]

#define TPI_ACPR_PRESCALER_Pos   0U

TPI ACPR: PRESCALER Position

TPI_ACPR_PRESCALER_Pos [2/2]

#define TPI_ACPR_PRESCALER_Pos   0U

TPI ACPR: PRESCALER Position

TPI_DEVID_AsynClkIn_Msk [1/2]

#define TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

TPI_DEVID_AsynClkIn_Msk [2/2]

#define TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

TPI_DEVID_AsynClkIn_Pos [1/2]

#define TPI_DEVID_AsynClkIn_Pos   5U

TPI DEVID: AsynClkIn Position

TPI_DEVID_AsynClkIn_Pos [2/2]

#define TPI_DEVID_AsynClkIn_Pos   5U

TPI DEVID: AsynClkIn Position

TPI_DEVID_MANCVALID_Msk [1/2]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

TPI_DEVID_MANCVALID_Msk [2/2]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

TPI_DEVID_MANCVALID_Pos [1/2]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

TPI_DEVID_MANCVALID_Pos [2/2]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

TPI_DEVID_MinBufSz_Msk [1/2]

#define TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

TPI_DEVID_MinBufSz_Msk [2/2]

#define TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

TPI_DEVID_MinBufSz_Pos [1/2]

#define TPI_DEVID_MinBufSz_Pos   6U

TPI DEVID: MinBufSz Position

TPI_DEVID_MinBufSz_Pos [2/2]

#define TPI_DEVID_MinBufSz_Pos   6U

TPI DEVID: MinBufSz Position

TPI_DEVID_NrTraceInput_Msk [1/2]

#define TPI_DEVID_NrTraceInput_Msk   (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

TPI_DEVID_NrTraceInput_Msk [2/2]

#define TPI_DEVID_NrTraceInput_Msk   (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

TPI_DEVID_NrTraceInput_Pos [1/2]

#define TPI_DEVID_NrTraceInput_Pos   0U

TPI DEVID: NrTraceInput Position

TPI_DEVID_NrTraceInput_Pos [2/2]

#define TPI_DEVID_NrTraceInput_Pos   0U

TPI DEVID: NrTraceInput Position

TPI_DEVID_NRZVALID_Msk [1/2]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

TPI_DEVID_NRZVALID_Msk [2/2]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

TPI_DEVID_NRZVALID_Pos [1/2]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

TPI_DEVID_NRZVALID_Pos [2/2]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

TPI_DEVID_PTINVALID_Msk [1/2]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

TPI_DEVID_PTINVALID_Msk [2/2]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

TPI_DEVID_PTINVALID_Pos [1/2]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

TPI_DEVID_PTINVALID_Pos [2/2]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

TPI_DEVTYPE_MajorType_Msk [1/2]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

TPI_DEVTYPE_MajorType_Msk [2/2]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

TPI_DEVTYPE_MajorType_Pos [1/2]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

TPI_DEVTYPE_MajorType_Pos [2/2]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

TPI_DEVTYPE_SubType_Msk [1/2]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

TPI_DEVTYPE_SubType_Msk [2/2]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

TPI_DEVTYPE_SubType_Pos [1/2]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

TPI_DEVTYPE_SubType_Pos [2/2]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

TPI_FFCR_EnFCont_Msk [1/2]

#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

TPI_FFCR_EnFCont_Msk [2/2]

#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

TPI_FFCR_EnFCont_Pos [1/2]

#define TPI_FFCR_EnFCont_Pos   1U

TPI FFCR: EnFCont Position

TPI_FFCR_EnFCont_Pos [2/2]

#define TPI_FFCR_EnFCont_Pos   1U

TPI FFCR: EnFCont Position

TPI_FFCR_TrigIn_Msk [1/2]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

TPI_FFCR_TrigIn_Msk [2/2]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

TPI_FFCR_TrigIn_Pos [1/2]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

TPI_FFCR_TrigIn_Pos [2/2]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

TPI_FFSR_FlInProg_Msk [1/2]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

TPI_FFSR_FlInProg_Msk [2/2]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

TPI_FFSR_FlInProg_Pos [1/2]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

TPI_FFSR_FlInProg_Pos [2/2]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

TPI_FFSR_FtNonStop_Msk [1/2]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

TPI_FFSR_FtNonStop_Msk [2/2]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

TPI_FFSR_FtNonStop_Pos [1/2]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

TPI_FFSR_FtNonStop_Pos [2/2]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

TPI_FFSR_FtStopped_Msk [1/2]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

TPI_FFSR_FtStopped_Msk [2/2]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

TPI_FFSR_FtStopped_Pos [1/2]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

TPI_FFSR_FtStopped_Pos [2/2]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

TPI_FFSR_TCPresent_Msk [1/2]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

TPI_FFSR_TCPresent_Msk [2/2]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

TPI_FFSR_TCPresent_Pos [1/2]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

TPI_FFSR_TCPresent_Pos [2/2]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

TPI_FIFO0_ETM0_Msk [1/2]

#define TPI_FIFO0_ETM0_Msk   (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)

TPI FIFO0: ETM0 Mask

TPI_FIFO0_ETM0_Msk [2/2]

#define TPI_FIFO0_ETM0_Msk   (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)

TPI FIFO0: ETM0 Mask

TPI_FIFO0_ETM0_Pos [1/2]

#define TPI_FIFO0_ETM0_Pos   0U

TPI FIFO0: ETM0 Position

TPI_FIFO0_ETM0_Pos [2/2]

#define TPI_FIFO0_ETM0_Pos   0U

TPI FIFO0: ETM0 Position

TPI_FIFO0_ETM1_Msk [1/2]

#define TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)

TPI FIFO0: ETM1 Mask

TPI_FIFO0_ETM1_Msk [2/2]

#define TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)

TPI FIFO0: ETM1 Mask

TPI_FIFO0_ETM1_Pos [1/2]

#define TPI_FIFO0_ETM1_Pos   8U

TPI FIFO0: ETM1 Position

TPI_FIFO0_ETM1_Pos [2/2]

#define TPI_FIFO0_ETM1_Pos   8U

TPI FIFO0: ETM1 Position

TPI_FIFO0_ETM2_Msk [1/2]

#define TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)

TPI FIFO0: ETM2 Mask

TPI_FIFO0_ETM2_Msk [2/2]

#define TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)

TPI FIFO0: ETM2 Mask

TPI_FIFO0_ETM2_Pos [1/2]

#define TPI_FIFO0_ETM2_Pos   16U

TPI FIFO0: ETM2 Position

TPI_FIFO0_ETM2_Pos [2/2]

#define TPI_FIFO0_ETM2_Pos   16U

TPI FIFO0: ETM2 Position

TPI_FIFO0_ETM_ATVALID_Msk [1/2]

#define TPI_FIFO0_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)

TPI FIFO0: ETM_ATVALID Mask

TPI_FIFO0_ETM_ATVALID_Msk [2/2]

#define TPI_FIFO0_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)

TPI FIFO0: ETM_ATVALID Mask

TPI_FIFO0_ETM_ATVALID_Pos [1/2]

#define TPI_FIFO0_ETM_ATVALID_Pos   26U

TPI FIFO0: ETM_ATVALID Position

TPI_FIFO0_ETM_ATVALID_Pos [2/2]

#define TPI_FIFO0_ETM_ATVALID_Pos   26U

TPI FIFO0: ETM_ATVALID Position

TPI_FIFO0_ETM_bytecount_Msk [1/2]

#define TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

TPI FIFO0: ETM_bytecount Mask

TPI_FIFO0_ETM_bytecount_Msk [2/2]

#define TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

TPI FIFO0: ETM_bytecount Mask

TPI_FIFO0_ETM_bytecount_Pos [1/2]

#define TPI_FIFO0_ETM_bytecount_Pos   24U

TPI FIFO0: ETM_bytecount Position

TPI_FIFO0_ETM_bytecount_Pos [2/2]

#define TPI_FIFO0_ETM_bytecount_Pos   24U

TPI FIFO0: ETM_bytecount Position

TPI_FIFO0_ITM_ATVALID_Msk [1/2]

#define TPI_FIFO0_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)

TPI FIFO0: ITM_ATVALID Mask

TPI_FIFO0_ITM_ATVALID_Msk [2/2]

#define TPI_FIFO0_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)

TPI FIFO0: ITM_ATVALID Mask

TPI_FIFO0_ITM_ATVALID_Pos [1/2]

#define TPI_FIFO0_ITM_ATVALID_Pos   29U

TPI FIFO0: ITM_ATVALID Position

TPI_FIFO0_ITM_ATVALID_Pos [2/2]

#define TPI_FIFO0_ITM_ATVALID_Pos   29U

TPI FIFO0: ITM_ATVALID Position

TPI_FIFO0_ITM_bytecount_Msk [1/2]

#define TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

TPI FIFO0: ITM_bytecount Mask

TPI_FIFO0_ITM_bytecount_Msk [2/2]

#define TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

TPI FIFO0: ITM_bytecount Mask

TPI_FIFO0_ITM_bytecount_Pos [1/2]

#define TPI_FIFO0_ITM_bytecount_Pos   27U

TPI FIFO0: ITM_bytecount Position

TPI_FIFO0_ITM_bytecount_Pos [2/2]

#define TPI_FIFO0_ITM_bytecount_Pos   27U

TPI FIFO0: ITM_bytecount Position

TPI_FIFO1_ETM_ATVALID_Msk [1/2]

#define TPI_FIFO1_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)

TPI FIFO1: ETM_ATVALID Mask

TPI_FIFO1_ETM_ATVALID_Msk [2/2]

#define TPI_FIFO1_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)

TPI FIFO1: ETM_ATVALID Mask

TPI_FIFO1_ETM_ATVALID_Pos [1/2]

#define TPI_FIFO1_ETM_ATVALID_Pos   26U

TPI FIFO1: ETM_ATVALID Position

TPI_FIFO1_ETM_ATVALID_Pos [2/2]

#define TPI_FIFO1_ETM_ATVALID_Pos   26U

TPI FIFO1: ETM_ATVALID Position

TPI_FIFO1_ETM_bytecount_Msk [1/2]

#define TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

TPI FIFO1: ETM_bytecount Mask

TPI_FIFO1_ETM_bytecount_Msk [2/2]

#define TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

TPI FIFO1: ETM_bytecount Mask

TPI_FIFO1_ETM_bytecount_Pos [1/2]

#define TPI_FIFO1_ETM_bytecount_Pos   24U

TPI FIFO1: ETM_bytecount Position

TPI_FIFO1_ETM_bytecount_Pos [2/2]

#define TPI_FIFO1_ETM_bytecount_Pos   24U

TPI FIFO1: ETM_bytecount Position

TPI_FIFO1_ITM0_Msk [1/2]

#define TPI_FIFO1_ITM0_Msk   (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)

TPI FIFO1: ITM0 Mask

TPI_FIFO1_ITM0_Msk [2/2]

#define TPI_FIFO1_ITM0_Msk   (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)

TPI FIFO1: ITM0 Mask

TPI_FIFO1_ITM0_Pos [1/2]

#define TPI_FIFO1_ITM0_Pos   0U

TPI FIFO1: ITM0 Position

TPI_FIFO1_ITM0_Pos [2/2]

#define TPI_FIFO1_ITM0_Pos   0U

TPI FIFO1: ITM0 Position

TPI_FIFO1_ITM1_Msk [1/2]

#define TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)

TPI FIFO1: ITM1 Mask

TPI_FIFO1_ITM1_Msk [2/2]

#define TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)

TPI FIFO1: ITM1 Mask

TPI_FIFO1_ITM1_Pos [1/2]

#define TPI_FIFO1_ITM1_Pos   8U

TPI FIFO1: ITM1 Position

TPI_FIFO1_ITM1_Pos [2/2]

#define TPI_FIFO1_ITM1_Pos   8U

TPI FIFO1: ITM1 Position

TPI_FIFO1_ITM2_Msk [1/2]

#define TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)

TPI FIFO1: ITM2 Mask

TPI_FIFO1_ITM2_Msk [2/2]

#define TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)

TPI FIFO1: ITM2 Mask

TPI_FIFO1_ITM2_Pos [1/2]

#define TPI_FIFO1_ITM2_Pos   16U

TPI FIFO1: ITM2 Position

TPI_FIFO1_ITM2_Pos [2/2]

#define TPI_FIFO1_ITM2_Pos   16U

TPI FIFO1: ITM2 Position

TPI_FIFO1_ITM_ATVALID_Msk [1/2]

#define TPI_FIFO1_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)

TPI FIFO1: ITM_ATVALID Mask

TPI_FIFO1_ITM_ATVALID_Msk [2/2]

#define TPI_FIFO1_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)

TPI FIFO1: ITM_ATVALID Mask

TPI_FIFO1_ITM_ATVALID_Pos [1/2]

#define TPI_FIFO1_ITM_ATVALID_Pos   29U

TPI FIFO1: ITM_ATVALID Position

TPI_FIFO1_ITM_ATVALID_Pos [2/2]

#define TPI_FIFO1_ITM_ATVALID_Pos   29U

TPI FIFO1: ITM_ATVALID Position

TPI_FIFO1_ITM_bytecount_Msk [1/2]

#define TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

TPI FIFO1: ITM_bytecount Mask

TPI_FIFO1_ITM_bytecount_Msk [2/2]

#define TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

TPI FIFO1: ITM_bytecount Mask

TPI_FIFO1_ITM_bytecount_Pos [1/2]

#define TPI_FIFO1_ITM_bytecount_Pos   27U

TPI FIFO1: ITM_bytecount Position

TPI_FIFO1_ITM_bytecount_Pos [2/2]

#define TPI_FIFO1_ITM_bytecount_Pos   27U

TPI FIFO1: ITM_bytecount Position

TPI_ITATBCTR0_ATREADY1_Msk [1/2]

#define TPI_ITATBCTR0_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)

TPI ITATBCTR0: ATREADY1 Mask

TPI_ITATBCTR0_ATREADY1_Msk [2/2]

#define TPI_ITATBCTR0_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)

TPI ITATBCTR0: ATREADY1 Mask

TPI_ITATBCTR0_ATREADY1_Pos [1/2]

#define TPI_ITATBCTR0_ATREADY1_Pos   0U

TPI ITATBCTR0: ATREADY1 Position

TPI_ITATBCTR0_ATREADY1_Pos [2/2]

#define TPI_ITATBCTR0_ATREADY1_Pos   0U

TPI ITATBCTR0: ATREADY1 Position

TPI_ITATBCTR0_ATREADY2_Msk [1/2]

#define TPI_ITATBCTR0_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)

TPI ITATBCTR0: ATREADY2 Mask

TPI_ITATBCTR0_ATREADY2_Msk [2/2]

#define TPI_ITATBCTR0_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)

TPI ITATBCTR0: ATREADY2 Mask

TPI_ITATBCTR0_ATREADY2_Pos [1/2]

#define TPI_ITATBCTR0_ATREADY2_Pos   0U

TPI ITATBCTR0: ATREADY2 Position

TPI_ITATBCTR0_ATREADY2_Pos [2/2]

#define TPI_ITATBCTR0_ATREADY2_Pos   0U

TPI ITATBCTR0: ATREADY2 Position

TPI_ITATBCTR2_ATREADY1_Msk [1/2]

#define TPI_ITATBCTR2_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)

TPI ITATBCTR2: ATREADY1 Mask

TPI_ITATBCTR2_ATREADY1_Msk [2/2]

#define TPI_ITATBCTR2_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)

TPI ITATBCTR2: ATREADY1 Mask

TPI_ITATBCTR2_ATREADY1_Pos [1/2]

#define TPI_ITATBCTR2_ATREADY1_Pos   0U

TPI ITATBCTR2: ATREADY1 Position

TPI_ITATBCTR2_ATREADY1_Pos [2/2]

#define TPI_ITATBCTR2_ATREADY1_Pos   0U

TPI ITATBCTR2: ATREADY1 Position

TPI_ITATBCTR2_ATREADY2_Msk [1/2]

#define TPI_ITATBCTR2_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)

TPI ITATBCTR2: ATREADY2 Mask

TPI_ITATBCTR2_ATREADY2_Msk [2/2]

#define TPI_ITATBCTR2_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)

TPI ITATBCTR2: ATREADY2 Mask

TPI_ITATBCTR2_ATREADY2_Pos [1/2]

#define TPI_ITATBCTR2_ATREADY2_Pos   0U

TPI ITATBCTR2: ATREADY2 Position

TPI_ITATBCTR2_ATREADY2_Pos [2/2]

#define TPI_ITATBCTR2_ATREADY2_Pos   0U

TPI ITATBCTR2: ATREADY2 Position

TPI_ITCTRL_Mode_Msk [1/2]

#define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)

TPI ITCTRL: Mode Mask

TPI_ITCTRL_Mode_Msk [2/2]

#define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)

TPI ITCTRL: Mode Mask

TPI_ITCTRL_Mode_Pos [1/2]

#define TPI_ITCTRL_Mode_Pos   0U

TPI ITCTRL: Mode Position

TPI_ITCTRL_Mode_Pos [2/2]

#define TPI_ITCTRL_Mode_Pos   0U

TPI ITCTRL: Mode Position

TPI_SPPR_TXMODE_Msk [1/2]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

TPI_SPPR_TXMODE_Msk [2/2]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

TPI_SPPR_TXMODE_Pos [1/2]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

TPI_SPPR_TXMODE_Pos [2/2]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

TPI_TRIGGER_TRIGGER_Msk [1/2]

#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)

TPI TRIGGER: TRIGGER Mask

TPI_TRIGGER_TRIGGER_Msk [2/2]

#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)

TPI TRIGGER: TRIGGER Mask

TPI_TRIGGER_TRIGGER_Pos [1/2]

#define TPI_TRIGGER_TRIGGER_Pos   0U

TPI TRIGGER: TRIGGER Position

TPI_TRIGGER_TRIGGER_Pos [2/2]

#define TPI_TRIGGER_TRIGGER_Pos   0U

TPI TRIGGER: TRIGGER Position