ANADIG_OSC Register Masks

OSC_48M_CTRL - 48MHz RCOSC Control Register
#define	ANADIG_OSC_OSC_48M_CTRL_TEN_MASK   (0x2U)
#define	ANADIG_OSC_OSC_48M_CTRL_TEN_SHIFT   (1U)
#define	ANADIG_OSC_OSC_48M_CTRL_TEN(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_TEN_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_TEN_MASK)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK   (0x1000000U)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_SHIFT   (24U)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK   (0x40000000U)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_SHIFT   (30U)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK   (0x80000000U)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_SHIFT   (31U)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK)

OSC_24M_CTRL - 24MHz OSC Control Register
#define	ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_MASK   (0x1U)
#define	ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_SHIFT   (0U)
#define	ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_MASK)
#define	ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK   (0x2U)
#define	ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_SHIFT   (1U)
#define	ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK)
#define	ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK   (0x4U)
#define	ANADIG_OSC_OSC_24M_CTRL_LP_EN_SHIFT   (2U)
#define	ANADIG_OSC_OSC_24M_CTRL_LP_EN(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_LP_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_MASK   (0x8U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_SHIFT   (3U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_MASK)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK   (0x10U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_EN_SHIFT   (4U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_EN(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK   (0x80U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_SHIFT   (7U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK   (0x40000000U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_SHIFT   (30U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK   (0x80000000U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_SHIFT   (31U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK)

OSC_400M_CTRL0 - 400MHz RCOSC Control0 Register
#define	ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_MASK   (0x80000000U)
#define	ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_SHIFT   (31U)
#define	ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_MASK)

OSC_400M_CTRL1 - 400MHz RCOSC Control1 Register
#define	ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK   (0x1U)
#define	ANADIG_OSC_OSC_400M_CTRL1_PWD_SHIFT   (0U)
#define	ANADIG_OSC_OSC_400M_CTRL1_PWD(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_PWD_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK)
#define	ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK   (0x2U)
#define	ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_SHIFT   (1U)
#define	ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK)
#define	ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK   (0x80000000U)
#define	ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_SHIFT   (31U)
#define	ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK)

OSC_400M_CTRL2 - 400MHz RCOSC Control2 Register
#define	ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_MASK   (0x1U)
#define	ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_SHIFT   (0U)
#define	ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_MASK)
#define	ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_MASK   (0x400U)
#define	ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_SHIFT   (10U)
#define	ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_MASK)
#define	ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_MASK   (0xFF000000U)
#define	ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_SHIFT   (24U)
#define	ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_MASK)

OSC_16M_CTRL - 16MHz RCOSC Control Register
#define	ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK   (0x2U)
#define	ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_SHIFT   (1U)
#define	ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK)
#define	ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_MASK   (0x8U)
#define	ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_SHIFT   (3U)
#define	ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_MASK)
#define	ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_MASK   (0x100U)
#define	ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_SHIFT   (8U)
#define	ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_MASK)
#define	ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK   (0x80000000U)
#define	ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_SHIFT   (31U)
#define	ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK)

OSC_48M_CTRL - 48MHz RCOSC Control Register
#define	ANADIG_OSC_OSC_48M_CTRL_TEN_MASK   (0x2U)
#define	ANADIG_OSC_OSC_48M_CTRL_TEN_SHIFT   (1U)
#define	ANADIG_OSC_OSC_48M_CTRL_TEN(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_TEN_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_TEN_MASK)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK   (0x1000000U)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_SHIFT   (24U)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK   (0x40000000U)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_SHIFT   (30U)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK   (0x80000000U)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_SHIFT   (31U)
#define	ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK)

OSC_24M_CTRL - 24MHz OSC Control Register
#define	ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_MASK   (0x1U)
#define	ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_SHIFT   (0U)
#define	ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_MASK)
#define	ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK   (0x2U)
#define	ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_SHIFT   (1U)
#define	ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK)
#define	ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK   (0x4U)
#define	ANADIG_OSC_OSC_24M_CTRL_LP_EN_SHIFT   (2U)
#define	ANADIG_OSC_OSC_24M_CTRL_LP_EN(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_LP_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_MASK   (0x8U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_SHIFT   (3U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_MASK)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK   (0x10U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_EN_SHIFT   (4U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_EN(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK   (0x80U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_SHIFT   (7U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK   (0x40000000U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_SHIFT   (30U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK   (0x80000000U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_SHIFT   (31U)
#define	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK)

OSC_400M_CTRL0 - 400MHz RCOSC Control0 Register
#define	ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_MASK   (0x80000000U)
#define	ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_SHIFT   (31U)
#define	ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_MASK)

OSC_400M_CTRL1 - 400MHz RCOSC Control1 Register
#define	ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK   (0x1U)
#define	ANADIG_OSC_OSC_400M_CTRL1_PWD_SHIFT   (0U)
#define	ANADIG_OSC_OSC_400M_CTRL1_PWD(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_PWD_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK)
#define	ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK   (0x2U)
#define	ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_SHIFT   (1U)
#define	ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK)
#define	ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK   (0x80000000U)
#define	ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_SHIFT   (31U)
#define	ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK)

OSC_400M_CTRL2 - 400MHz RCOSC Control2 Register
#define	ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_MASK   (0x1U)
#define	ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_SHIFT   (0U)
#define	ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_MASK)
#define	ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_MASK   (0x400U)
#define	ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_SHIFT   (10U)
#define	ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_MASK)
#define	ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_MASK   (0xFF000000U)
#define	ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_SHIFT   (24U)
#define	ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_MASK)

OSC_16M_CTRL - 16MHz RCOSC Control Register
#define	ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK   (0x2U)
#define	ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_SHIFT   (1U)
#define	ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK)
#define	ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_MASK   (0x8U)
#define	ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_SHIFT   (3U)
#define	ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_MASK)
#define	ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_MASK   (0x100U)
#define	ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_SHIFT   (8U)
#define	ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_MASK)
#define	ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK   (0x80000000U)
#define	ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_SHIFT   (31U)
#define	ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK)

Detailed Description

Macro Definition Documentation

ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M [1/2]

#define ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK)

EN_IRC4M16M - Enable Clock Output 0b0..Disable 0b1..Enable

ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M [2/2]

#define ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK)

EN_IRC4M16M - Enable Clock Output 0b0..Disable 0b1..Enable

ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE [1/2]

#define ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_MASK)

EN_POWER_SAVE - Power Save Enable 0b0..Disable 0b1..Enable

ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE [2/2]

#define ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_MASK)

EN_POWER_SAVE - Power Save Enable 0b0..Disable 0b1..Enable

ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE [1/2]

#define ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK)

RC_16M_CONTROL_MODE - Control Mode for 16MHz Oscillator 0b0..Software mode (default) 0b1..GPC mode (Setpoint)

ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE [2/2]

#define ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK)

RC_16M_CONTROL_MODE - Control Mode for 16MHz Oscillator 0b0..Software mode (default) 0b1..GPC mode (Setpoint)

ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M [1/2]

#define ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_MASK)

SOURCE_SEL_16M - Source select 0b0..16MHz Oscillator 0b1..24MHz Oscillator

ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M [2/2]

#define ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_MASK)

SOURCE_SEL_16M - Source select 0b0..16MHz Oscillator 0b1..24MHz Oscillator

ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK [1/2]

#define ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_MASK)

BYPASS_CLK - 24MHz OSC Bypass Clock

ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK [2/2]

#define ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_MASK)

BYPASS_CLK - 24MHz OSC Bypass Clock

ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN [1/2]

#define ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK)

BYPASS_EN - 24MHz OSC Bypass Enable 0b0..Disable 0b1..Enable

ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN [2/2]

#define ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK)

BYPASS_EN - 24MHz OSC Bypass Enable 0b0..Disable 0b1..Enable

ANADIG_OSC_OSC_24M_CTRL_LP_EN [1/2]

#define ANADIG_OSC_OSC_24M_CTRL_LP_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_LP_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK)

LP_EN - 24MHz OSC Low-Power Mode Enable 0b0..High Gain mode (HP) 0b1..Low-power mode (LP)

ANADIG_OSC_OSC_24M_CTRL_LP_EN [2/2]

#define ANADIG_OSC_OSC_24M_CTRL_LP_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_LP_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK)

LP_EN - 24MHz OSC Low-Power Mode Enable 0b0..High Gain mode (HP) 0b1..Low-power mode (LP)

ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE [1/2]

#define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK)

OSC_24M_CONTROL_MODE - 24MHz OSC Control Mode 0b0..Software mode (default) 0b1..GPC mode (Setpoint)

ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE [2/2]

#define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK)

OSC_24M_CONTROL_MODE - 24MHz OSC Control Mode 0b0..Software mode (default) 0b1..GPC mode (Setpoint)

ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE [1/2]

#define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK)

OSC_24M_GATE - 24MHz OSC Gate Control 0b0..Not Gated 0b1..Gated

ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE [2/2]

#define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK)

OSC_24M_GATE - 24MHz OSC Gate Control 0b0..Not Gated 0b1..Gated

ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE [1/2]

#define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)

OSC_24M_STABLE - 24MHz OSC Stable 0b0..Not Stable 0b1..Stable

ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE [2/2]

#define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)

OSC_24M_STABLE - 24MHz OSC Stable 0b0..Not Stable 0b1..Stable

ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE [1/2]

#define ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_MASK)

OSC_COMP_MODE - 24MHz OSC Comparator Mode 0b0..Single-ended mode (default) 0b1..Differential mode (test mode)

ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE [2/2]

#define ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_MASK)

OSC_COMP_MODE - 24MHz OSC Comparator Mode 0b0..Single-ended mode (default) 0b1..Differential mode (test mode)

ANADIG_OSC_OSC_24M_CTRL_OSC_EN [1/2]

#define ANADIG_OSC_OSC_24M_CTRL_OSC_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK)

OSC_EN - 24MHz OSC Enable 0b0..Disable 0b1..Enable

ANADIG_OSC_OSC_24M_CTRL_OSC_EN [2/2]

#define ANADIG_OSC_OSC_24M_CTRL_OSC_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK)

OSC_EN - 24MHz OSC Enable 0b0..Disable 0b1..Enable

ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY [1/2]

#define ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_MASK)

OSC400M_AI_BUSY - 400MHz OSC AI BUSY

ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY [2/2]

#define ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_MASK)

OSC400M_AI_BUSY - 400MHz OSC AI BUSY

ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG [1/2]

#define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK)

CLKGATE_400MEG - Clock gate control for 400MHz RCOSC 0b0..Not Gated 0b1..Gated

ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG [2/2]

#define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK)

CLKGATE_400MEG - Clock gate control for 400MHz RCOSC 0b0..Not Gated 0b1..Gated

ANADIG_OSC_OSC_400M_CTRL1_PWD [1/2]

#define ANADIG_OSC_OSC_400M_CTRL1_PWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_PWD_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK)

PWD - Power down control for 400MHz RCOSC 0b0..No Power down 0b1..Power down

ANADIG_OSC_OSC_400M_CTRL1_PWD [2/2]

#define ANADIG_OSC_OSC_400M_CTRL1_PWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_PWD_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK)

PWD - Power down control for 400MHz RCOSC 0b0..No Power down 0b1..Power down

ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE [1/2]

#define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK)

RC_400M_CONTROL_MODE - 400MHz RCOSC Control mode 0b0..Software mode (default) 0b1..GPC mode (Setpoint)

ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE [2/2]

#define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK)

RC_400M_CONTROL_MODE - 400MHz RCOSC Control mode 0b0..Software mode (default) 0b1..GPC mode (Setpoint)

ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK [1/2]

#define ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_MASK)

ENABLE_CLK - Clock enable 0b0..Clock is disabled before entering GPC mode 0b1..Clock is enabled before entering GPC mode

ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK [2/2]

#define ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_MASK)

ENABLE_CLK - Clock enable 0b0..Clock is disabled before entering GPC mode 0b1..Clock is enabled before entering GPC mode

ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL [1/2]

#define ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_MASK)

OSC_TUNE_VAL - Oscillator Tune Value

ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL [2/2]

#define ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_MASK)

OSC_TUNE_VAL - Oscillator Tune Value

ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP [1/2]

#define ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_MASK)

TUNE_BYP - Bypass tuning logic 0b0..Use the output of tuning logic to run the oscillator 0b1..Bypass the tuning logic and use the programmed OSC_TUNE_VAL to run the oscillator

ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP [2/2]

#define ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_MASK)

TUNE_BYP - Bypass tuning logic 0b0..Use the output of tuning logic to run the oscillator 0b1..Bypass the tuning logic and use the programmed OSC_TUNE_VAL to run the oscillator

ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE [1/2]

#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK)

RC_48M_CONTROL_MODE - 48MHz RCOSC Control Mode 0b0..Software mode (default) 0b1..GPC mode (Setpoint)

ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE [2/2]

#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK)

RC_48M_CONTROL_MODE - 48MHz RCOSC Control Mode 0b0..Software mode (default) 0b1..GPC mode (Setpoint)

ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE [1/2]

#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK)

RC_48M_DIV2_CONTROL_MODE - RCOSC_48M_DIV2 Control Mode 0b0..Software mode (default) 0b1..GPC mode (Setpoint)

ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE [2/2]

#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK)

RC_48M_DIV2_CONTROL_MODE - RCOSC_48M_DIV2 Control Mode 0b0..Software mode (default) 0b1..GPC mode (Setpoint)

ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN [1/2]

#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK)

RC_48M_DIV2_EN - RCOSC_48M_DIV2 Enable 0b0..Disable 0b1..Enable

ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN [2/2]

#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK)

RC_48M_DIV2_EN - RCOSC_48M_DIV2 Enable 0b0..Disable 0b1..Enable

ANADIG_OSC_OSC_48M_CTRL_TEN [1/2]

#define ANADIG_OSC_OSC_48M_CTRL_TEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_TEN_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_TEN_MASK)

TEN - 48MHz RCOSC Enable 0b0..Power down 0b1..Power up

ANADIG_OSC_OSC_48M_CTRL_TEN [2/2]

#define ANADIG_OSC_OSC_48M_CTRL_TEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_TEN_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_TEN_MASK)

TEN - 48MHz RCOSC Enable 0b0..Power down 0b1..Power up