MISC_DIFPROG - Chip Silicon Version Register
#define	ANADIG_MISC_MISC_DIFPROG_CHIPID_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_MISC_DIFPROG_CHIPID_SHIFT (0U)

#define	ANADIG_MISC_MISC_DIFPROG_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_MISC_DIFPROG_CHIPID_SHIFT)) & ANADIG_MISC_MISC_DIFPROG_CHIPID_MASK)

VDDSOC_AI_CTRL - VDDSOC_AI_CTRL_REGISTER
#define	ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK (0xFFU)

#define	ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT (0U)

#define	ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT)) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK)

#define	ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK (0x10000U)

#define	ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT (16U)

#define	ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT)) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK)

VDDSOC_AI_WDATA - VDDSOC_AI_WDATA_REGISTER
#define	ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_SHIFT (0U)

#define	ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_SHIFT)) & ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_MASK)

VDDSOC_AI_RDATA - VDDSOC_AI_RDATA_REGISTER
#define	ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_SHIFT (0U)

#define	ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_SHIFT)) & ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_MASK)

VDDSOC2PLL_AI_CTRL_1G - VDDSOC2PLL_AI_CTRL_1G_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK (0xFFU)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT (0U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK (0x100U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_SHIFT (8U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK (0x200U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_SHIFT (9U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK (0x10000U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT (16U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK)

VDDSOC2PLL_AI_WDATA_1G - VDDSOC2PLL_AI_WDATA_1G_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_SHIFT (0U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_MASK)

VDDSOC2PLL_AI_RDATA_1G - VDDSOC2PLL_AI_RDATA_1G_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_SHIFT (0U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_MASK)

VDDSOC2PLL_AI_CTRL_AUDIO - VDDSOC_AI_CTRL_AUDIO_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK (0xFFU)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT (0U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK (0x100U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_SHIFT (8U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK (0x200U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_SHIFT (9U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK (0x10000U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT (16U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK)

VDDSOC2PLL_AI_WDATA_AUDIO - VDDSOC_AI_WDATA_AUDIO_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_SHIFT (0U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_MASK)

VDDSOC2PLL_AI_RDATA_AUDIO - VDDSOC2PLL_AI_RDATA_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_SHIFT (0U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_MASK)

VDDSOC2PLL_AI_CTRL_VIDEO - VDDSOC2PLL_AI_CTRL_VIDEO_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK (0xFFU)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT (0U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK (0x100U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_SHIFT (8U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK (0x200U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_SHIFT (9U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK (0x10000U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT (16U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK)

VDDSOC2PLL_AI_WDATA_VIDEO - VDDSOC2PLL_AI_WDATA_VIDEO_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_SHIFT (0U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_MASK)

VDDSOC2PLL_AI_RDATA_VIDEO - VDDSOC2PLL_AI_RDATA_VIDEO_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_SHIFT (0U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_MASK)

VDDLPSR_AI_CTRL - VDDSOC_AI_CTRL_REGISTER
#define	ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK (0xFFU)

#define	ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT (0U)

#define	ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK)

#define	ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK (0x10000U)

#define	ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT (16U)

#define	ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK)

VDDLPSR_AI_WDATA - VDDLPSR_AI_WDATA_REGISTER
#define	ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_SHIFT (0U)

#define	ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_MASK)

VDDLPSR_AI_RDATA_REFTOP - VDDLPSR_AI_RDATA_REFTOP_REGISTER
#define	ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_SHIFT (0U)

#define	ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_MASK)

VDDLPSR_AI_RDATA_TMPSNS - VDDLPSR_AI_RDATA_TMPSNS_REGISTER
#define	ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_SHIFT (0U)

#define	ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_MASK)

VDDLPSR_AI400M_CTRL - VDDLPSR_AI400M_CTRL_REGISTER
#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK (0xFFU)

#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT (0U)

#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK)

#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK (0x100U)

#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_SHIFT (8U)

#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK)

#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK (0x200U)

#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_SHIFT (9U)

#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK)

#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK (0x10000U)

#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT (16U)

#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK)

VDDLPSR_AI400M_WDATA - VDDLPSR_AI400M_WDATA_REGISTER
#define	ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_SHIFT (0U)

#define	ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_MASK)

VDDLPSR_AI400M_RDATA - VDDLPSR_AI400M_RDATA_REGISTER
#define	ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_SHIFT (0U)

#define	ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_MASK)

MISC_DIFPROG - Chip Silicon Version Register
#define	ANADIG_MISC_MISC_DIFPROG_CHIPID_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_MISC_DIFPROG_CHIPID_SHIFT (0U)

#define	ANADIG_MISC_MISC_DIFPROG_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_MISC_DIFPROG_CHIPID_SHIFT)) & ANADIG_MISC_MISC_DIFPROG_CHIPID_MASK)

VDDSOC_AI_CTRL - VDDSOC_AI_CTRL_REGISTER
#define	ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK (0xFFU)

#define	ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT (0U)

#define	ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT)) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK)

#define	ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK (0x10000U)

#define	ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT (16U)

#define	ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT)) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK)

VDDSOC_AI_WDATA - VDDSOC_AI_WDATA_REGISTER
#define	ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_SHIFT (0U)

#define	ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_SHIFT)) & ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_MASK)

VDDSOC_AI_RDATA - VDDSOC_AI_RDATA_REGISTER
#define	ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_SHIFT (0U)

#define	ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_SHIFT)) & ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_MASK)

VDDSOC2PLL_AI_CTRL_1G - VDDSOC2PLL_AI_CTRL_1G_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK (0xFFU)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT (0U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK (0x100U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_SHIFT (8U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK (0x200U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_SHIFT (9U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK (0x10000U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT (16U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK)

VDDSOC2PLL_AI_WDATA_1G - VDDSOC2PLL_AI_WDATA_1G_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_SHIFT (0U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_MASK)

VDDSOC2PLL_AI_RDATA_1G - VDDSOC2PLL_AI_RDATA_1G_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_SHIFT (0U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_MASK)

VDDSOC2PLL_AI_CTRL_AUDIO - VDDSOC_AI_CTRL_AUDIO_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK (0xFFU)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT (0U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK (0x100U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_SHIFT (8U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK (0x200U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_SHIFT (9U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK (0x10000U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT (16U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK)

VDDSOC2PLL_AI_WDATA_AUDIO - VDDSOC_AI_WDATA_AUDIO_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_SHIFT (0U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_MASK)

VDDSOC2PLL_AI_RDATA_AUDIO - VDDSOC2PLL_AI_RDATA_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_SHIFT (0U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_MASK)

VDDSOC2PLL_AI_CTRL_VIDEO - VDDSOC2PLL_AI_CTRL_VIDEO_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK (0xFFU)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT (0U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK (0x100U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_SHIFT (8U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK (0x200U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_SHIFT (9U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK (0x10000U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT (16U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK)

VDDSOC2PLL_AI_WDATA_VIDEO - VDDSOC2PLL_AI_WDATA_VIDEO_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_SHIFT (0U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_MASK)

VDDSOC2PLL_AI_RDATA_VIDEO - VDDSOC2PLL_AI_RDATA_VIDEO_REGISTER
#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_SHIFT (0U)

#define	ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_MASK)

VDDLPSR_AI_CTRL - VDDSOC_AI_CTRL_REGISTER
#define	ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK (0xFFU)

#define	ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT (0U)

#define	ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK)

#define	ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK (0x10000U)

#define	ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT (16U)

#define	ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK)

VDDLPSR_AI_WDATA - VDDLPSR_AI_WDATA_REGISTER
#define	ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_SHIFT (0U)

#define	ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_MASK)

VDDLPSR_AI_RDATA_REFTOP - VDDLPSR_AI_RDATA_REFTOP_REGISTER
#define	ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_SHIFT (0U)

#define	ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_MASK)

VDDLPSR_AI_RDATA_TMPSNS - VDDLPSR_AI_RDATA_TMPSNS_REGISTER
#define	ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_SHIFT (0U)

#define	ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_MASK)

VDDLPSR_AI400M_CTRL - VDDLPSR_AI400M_CTRL_REGISTER
#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK (0xFFU)

#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT (0U)

#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK)

#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK (0x100U)

#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_SHIFT (8U)

#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK)

#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK (0x200U)

#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_SHIFT (9U)

#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK)

#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK (0x10000U)

#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT (16U)

#define	ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK)

VDDLPSR_AI400M_WDATA - VDDLPSR_AI400M_WDATA_REGISTER
#define	ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_SHIFT (0U)

#define	ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_MASK)

VDDLPSR_AI400M_RDATA - VDDLPSR_AI400M_RDATA_REGISTER
#define	ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_MASK (0xFFFFFFFFU)

#define	ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_SHIFT (0U)

#define	ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_MASK)

Detailed Description

Macro Definition Documentation

◆ ANADIG_MISC_MISC_DIFPROG_CHIPID [1/2]

#define ANADIG_MISC_MISC_DIFPROG_CHIPID ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_MISC_DIFPROG_CHIPID_SHIFT)) & ANADIG_MISC_MISC_DIFPROG_CHIPID_MASK)

CHIPID - Chip ID

◆ ANADIG_MISC_MISC_DIFPROG_CHIPID [2/2]

#define ANADIG_MISC_MISC_DIFPROG_CHIPID ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_MISC_DIFPROG_CHIPID_SHIFT)) & ANADIG_MISC_MISC_DIFPROG_CHIPID_MASK)

CHIPID - Chip ID

◆ ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR [1/2]

#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK)

VDDLPSR_AI400M_ADDR - VDDLPSR_AI400M_ADDR

◆ ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR [2/2]

#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK)

VDDLPSR_AI400M_ADDR - VDDLPSR_AI400M_ADDR

◆ ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB [1/2]

#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK)

VDDLPSR_AI400M_RWB - VDDLPSR_AI400M_RWB

◆ ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB [2/2]

#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK)

VDDLPSR_AI400M_RWB - VDDLPSR_AI400M_RWB

◆ ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M [1/2]

#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK)

VDDLPSR_AITOGGLE_400M - VDDLPSR_AITOGGLE_400M

◆ ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M [2/2]

#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK)

VDDLPSR_AITOGGLE_400M - VDDLPSR_AITOGGLE_400M

◆ ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M [1/2]

#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK)

VDDLPSR_AITOGGLE_DONE_400M - VDDLPSR_AITOGGLE_DONE_400M

◆ ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M [2/2]

#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK)

VDDLPSR_AITOGGLE_DONE_400M - VDDLPSR_AITOGGLE_DONE_400M

◆ ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA [1/2]

#define ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_MASK)

VDDLPSR_AI400M_RDATA - VDDLPSR_AI400M_RDATA

◆ ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA [2/2]

#define ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_MASK)

VDDLPSR_AI400M_RDATA - VDDLPSR_AI400M_RDATA

◆ ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA [1/2]

#define ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_MASK)

VDDLPSR_AI400M_WDATA - VDDLPSR_AI400M_WDATA

◆ ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA [2/2]

#define ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_MASK)

VDDLPSR_AI400M_WDATA - VDDLPSR_AI400M_WDATA

◆ ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR [1/2]

#define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK)

VDDLPSR_AI_ADDR - VDDLPSR_AI_ADDR

◆ ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR [2/2]

#define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK)

VDDLPSR_AI_ADDR - VDDLPSR_AI_ADDR

◆ ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB [1/2]

#define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK)

VDDLPSR_AIRWB - VDDLPSR_AIRWB

◆ ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB [2/2]

#define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK)

VDDLPSR_AIRWB - VDDLPSR_AIRWB

◆ ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP [1/2]

#define ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_MASK)

VDDLPSR_AI_RDATA_REFTOP - VDDLPSR_AI_RDATA_REFTOP

◆ ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP [2/2]

#define ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_MASK)

VDDLPSR_AI_RDATA_REFTOP - VDDLPSR_AI_RDATA_REFTOP

◆ ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS [1/2]

#define ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_MASK)

VDDLPSR_AI_RDATA_TMPSNS - VDDLPSR_AI_RDATA_TMPSNS

◆ ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS [2/2]

#define ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_MASK)

VDDLPSR_AI_RDATA_TMPSNS - VDDLPSR_AI_RDATA_TMPSNS

◆ ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA [1/2]

#define ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_MASK)

VDDLPSR_AI_WDATA - VDD_LPSR_AI_WDATA

◆ ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA [2/2]

#define ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_MASK)

VDDLPSR_AI_WDATA - VDD_LPSR_AI_WDATA

◆ ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G [1/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK)

VDDSOC2PLL_AIADDR_1G - VDDSOC2PLL_AIADDR_1G

◆ ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G [2/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK)

VDDSOC2PLL_AIADDR_1G - VDDSOC2PLL_AIADDR_1G

◆ ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G [1/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK)

VDDSOC2PLL_AIRWB_1G - VDDSOC2PLL_AIRWB_1G

◆ ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G [2/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK)

VDDSOC2PLL_AIRWB_1G - VDDSOC2PLL_AIRWB_1G

◆ ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G [1/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK)

VDDSOC2PLL_AITOGGLE_1G - VDDSOC2PLL_AITOGGLE_1G

◆ ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G [2/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK)

VDDSOC2PLL_AITOGGLE_1G - VDDSOC2PLL_AITOGGLE_1G

◆ ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G [1/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK)

VDDSOC2PLL_AITOGGLE_DONE_1G - VDDSOC2PLL_AITOGGLE_DONE_1G

◆ ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G [2/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK)

VDDSOC2PLL_AITOGGLE_DONE_1G - VDDSOC2PLL_AITOGGLE_DONE_1G

◆ ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO [1/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK)

VDDSOC2PLL_AI_ADDR_AUDIO - VDDSOC2PLL_AI_ADDR_AUDIO

◆ ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO [2/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK)

VDDSOC2PLL_AI_ADDR_AUDIO - VDDSOC2PLL_AI_ADDR_AUDIO

◆ ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO [1/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK)

VDDSOC2PLL_AIRWB_AUDIO - VDDSOC_AIRWB

◆ ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO [2/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK)

VDDSOC2PLL_AIRWB_AUDIO - VDDSOC_AIRWB

◆ ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO [1/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK)

VDDSOC2PLL_AITOGGLE_AUDIO - VDDSOC2PLL_AITOGGLE_AUDIO

◆ ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO [2/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK)

VDDSOC2PLL_AITOGGLE_AUDIO - VDDSOC2PLL_AITOGGLE_AUDIO

◆ ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO [1/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK)

VDDSOC2PLL_AITOGGLE_DONE_AUDIO - VDDSOC2PLL_AITOGGLE_DONE_AUDIO

◆ ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO [2/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK)

VDDSOC2PLL_AITOGGLE_DONE_AUDIO - VDDSOC2PLL_AITOGGLE_DONE_AUDIO

◆ ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO [1/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK)

VDDSOC2PLL_AIADDR_VIDEO - VDDSOC2PLL_AIADDR_VIDEO

◆ ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO [2/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK)

VDDSOC2PLL_AIADDR_VIDEO - VDDSOC2PLL_AIADDR_VIDEO

◆ ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO [1/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK)

VDDSOC2PLL_AIRWB_VIDEO - VDDSOC2PLL_AIRWB_VIDEO

◆ ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO [2/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK)

VDDSOC2PLL_AIRWB_VIDEO - VDDSOC2PLL_AIRWB_VIDEO

◆ ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO [1/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK)

VDDSOC2PLL_AITOGGLE_DONE_VIDEO - VDDSOC2PLL_AITOGGLE_DONE_VIDEO

◆ ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO [2/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK)

VDDSOC2PLL_AITOGGLE_DONE_VIDEO - VDDSOC2PLL_AITOGGLE_DONE_VIDEO

◆ ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO [1/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK)

VDDSOC2PLL_AITOGGLE_VIDEO - VDDSOC2PLL_AITOGGLE_VIDEO

◆ ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO [2/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK)

VDDSOC2PLL_AITOGGLE_VIDEO - VDDSOC2PLL_AITOGGLE_VIDEO

◆ ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G [1/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_MASK)

VDDSOC2PLL_AI_RDATA_1G - VDDSOC2PLL_AI_RDATA_1G

◆ ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G [2/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_MASK)

VDDSOC2PLL_AI_RDATA_1G - VDDSOC2PLL_AI_RDATA_1G

◆ ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO [1/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_MASK)

VDDSOC2PLL_AI_RDATA_AUDIO - VDDSOC2PLL_AI_RDATA_AUDIO

◆ ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO [2/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_MASK)

VDDSOC2PLL_AI_RDATA_AUDIO - VDDSOC2PLL_AI_RDATA_AUDIO

◆ ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO [1/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_MASK)

VDDSOC2PLL_AI_RDATA_VIDEO - VDDSOC2PLL_AI_RDATA_VIDEO

◆ ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO [2/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_MASK)

VDDSOC2PLL_AI_RDATA_VIDEO - VDDSOC2PLL_AI_RDATA_VIDEO

◆ ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G [1/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_MASK)

VDDSOC2PLL_AI_WDATA_1G - VDDSOC2PLL_AI_WDATA_1G

◆ ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G [2/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_MASK)

VDDSOC2PLL_AI_WDATA_1G - VDDSOC2PLL_AI_WDATA_1G

◆ ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO [1/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_MASK)

VDDSOC2PLL_AI_WDATA_AUDIO - VDDSOC2PLL_AI_WDATA_AUDIO

◆ ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO [2/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_MASK)

VDDSOC2PLL_AI_WDATA_AUDIO - VDDSOC2PLL_AI_WDATA_AUDIO

◆ ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO [1/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_MASK)

VDDSOC2PLL_AI_WDATA_VIDEO - VDDSOC2PLL_AI_WDATA_VIDEO

◆ ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO [2/2]

#define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_MASK)

VDDSOC2PLL_AI_WDATA_VIDEO - VDDSOC2PLL_AI_WDATA_VIDEO

◆ ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR [1/2]

#define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT)) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK)

VDDSOC_AI_ADDR - VDDSOC_AI_ADDR

◆ ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR [2/2]

#define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT)) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK)

VDDSOC_AI_ADDR - VDDSOC_AI_ADDR

◆ ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB [1/2]

#define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB ( x ) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT)) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK)

VDDSOC_AIRWB - VDDSOC_AIRWB

◆ ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB [2/2]