ADC interrupts definition

Macros
#define	ADC_IT_RDY   ADC_IER_ADRDYIE
#define	ADC_IT_EOSMP   ADC_IER_EOSMPIE
#define	ADC_IT_EOC   ADC_IER_EOCIE
#define	ADC_IT_EOS   ADC_IER_EOSIE
#define	ADC_IT_OVR   ADC_IER_OVRIE
#define	ADC_IT_JEOC   ADC_IER_JEOCIE
#define	ADC_IT_JEOS   ADC_IER_JEOSIE
#define	ADC_IT_AWD1   ADC_IER_AWD1IE
#define	ADC_IT_AWD2   ADC_IER_AWD2IE
#define	ADC_IT_AWD3   ADC_IER_AWD3IE
#define	ADC_IT_JQOVF   ADC_IER_JQOVFIE
#define	ADC_IT_AWD   ADC_IT_AWD1

Detailed Description

Macro Definition Documentation

ADC_IT_AWD

#define ADC_IT_AWD   ADC_IT_AWD1

ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog

ADC_IT_AWD1

#define ADC_IT_AWD1   ADC_IER_AWD1IE

ADC Analog watchdog 1 interrupt source (main analog watchdog)

ADC_IT_AWD2

#define ADC_IT_AWD2   ADC_IER_AWD2IE

ADC Analog watchdog 2 interrupt source (additional analog watchdog)

ADC_IT_AWD3

#define ADC_IT_AWD3   ADC_IER_AWD3IE

ADC Analog watchdog 3 interrupt source (additional analog watchdog)

ADC_IT_EOC

#define ADC_IT_EOC   ADC_IER_EOCIE

ADC End of regular conversion interrupt source

ADC_IT_EOS

#define ADC_IT_EOS   ADC_IER_EOSIE

ADC End of regular sequence of conversions interrupt source

ADC_IT_EOSMP

#define ADC_IT_EOSMP   ADC_IER_EOSMPIE

ADC End of sampling interrupt source

ADC_IT_JEOC

#define ADC_IT_JEOC   ADC_IER_JEOCIE

ADC End of injected conversion interrupt source

ADC_IT_JEOS

#define ADC_IT_JEOS   ADC_IER_JEOSIE

ADC End of injected sequence of conversions interrupt source

ADC_IT_JQOVF

#define ADC_IT_JQOVF   ADC_IER_JQOVFIE

ADC Injected Context Queue Overflow interrupt source

ADC_IT_OVR

#define ADC_IT_OVR   ADC_IER_OVRIE

ADC overrun interrupt source

ADC_IT_RDY

#define ADC_IT_RDY   ADC_IER_ADRDYIE

ADC Ready interrupt source