fsl_mu.h

/*
 * Copyright (c) 2015, Freescale Semiconductor, Inc.
 * Copyright 2016-2022 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
#ifndef _FSL_MU_H_
#define _FSL_MU_H_
 
#include "fsl_common.h"
 
/******************************************************************************
 * Definitions
 *****************************************************************************/
 
/* Compatibility Macros */
#ifndef MU_CR_NMI_MASK
#define MU_CR_NMI_MASK 0U
#endif
 
#if (defined(FSL_FEATURE_MU_HAS_RESET_INT) && FSL_FEATURE_MU_HAS_RESET_INT)
 
#ifndef FSL_FEATURE_MU_HAS_RESET_ASSERT_INT
#define FSL_FEATURE_MU_HAS_RESET_ASSERT_INT 1
#endif
 
#ifndef FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT
#define FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT 1
#endif
 
#endif /* FSL_FEATURE_MU_HAS_RESET_INT */
 
#define FSL_MU_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
enum _mu_status_flags
{
    kMU_Tx0EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 3U)), 
    kMU_Tx1EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 2U)), 
    kMU_Tx2EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 1U)), 
    kMU_Tx3EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 0U)), 
    kMU_Rx0FullFlag = (1U << (MU_SR_RFn_SHIFT + 3U)), 
    kMU_Rx1FullFlag = (1U << (MU_SR_RFn_SHIFT + 2U)), 
    kMU_Rx2FullFlag = (1U << (MU_SR_RFn_SHIFT + 1U)), 
    kMU_Rx3FullFlag = (1U << (MU_SR_RFn_SHIFT + 0U)), 
    kMU_GenInt0Flag = (1U << (MU_SR_GIPn_SHIFT + 3U)), 
    kMU_GenInt1Flag = (1U << (MU_SR_GIPn_SHIFT + 2U)), 
    kMU_GenInt2Flag = (1U << (MU_SR_GIPn_SHIFT + 1U)), 
    kMU_GenInt3Flag = (1U << (MU_SR_GIPn_SHIFT + 0U)), 
    kMU_EventPendingFlag  = MU_SR_EP_MASK,  
    kMU_FlagsUpdatingFlag = MU_SR_FUP_MASK, 
#if (defined(FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT)
    kMU_ResetAssertInterruptFlag = MU_SR_RAIP_MASK, 
#endif
#if (defined(FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT)
    kMU_ResetDeassertInterruptFlag = MU_SR_RDIP_MASK, 
#endif
 
#if (defined(FSL_FEATURE_MU_HAS_SR_RS) && FSL_FEATURE_MU_HAS_SR_RS)
    kMU_OtherSideInResetFlag = MU_SR_RS_MASK, 
#endif
 
#if (defined(FSL_FEATURE_MU_HAS_SR_MURIP) && FSL_FEATURE_MU_HAS_SR_MURIP)
    kMU_MuResetInterruptFlag = MU_SR_MURIP_MASK, 
#endif
#if (defined(FSL_FEATURE_MU_HAS_SR_HRIP) && FSL_FEATURE_MU_HAS_SR_HRIP)
    kMU_HardwareResetInterruptFlag = MU_SR_HRIP_MASK, 
#endif
};
 
enum _mu_interrupt_enable
{
    kMU_Tx0EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 3U)), 
    kMU_Tx1EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 2U)), 
    kMU_Tx2EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 1U)), 
    kMU_Tx3EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 0U)), 
    kMU_Rx0FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 3U)), 
    kMU_Rx1FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 2U)), 
    kMU_Rx2FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 1U)), 
    kMU_Rx3FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 0U)), 
    kMU_GenInt0InterruptEnable = (int)(1U << (MU_CR_GIEn_SHIFT + 3U)), 
    kMU_GenInt1InterruptEnable = (1U << (MU_CR_GIEn_SHIFT + 2U)),      
    kMU_GenInt2InterruptEnable = (1U << (MU_CR_GIEn_SHIFT + 1U)),      
    kMU_GenInt3InterruptEnable = (1U << (MU_CR_GIEn_SHIFT + 0U)),      
#if (defined(FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT)
    kMU_ResetAssertInterruptEnable = MU_CR_RAIE_MASK, 
#endif
#if (defined(FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT)
    kMU_ResetDeassertInterruptEnable = MU_CR_RDIE_MASK, 
#endif
#if (defined(FSL_FEATURE_MU_HAS_SR_MURIP) && FSL_FEATURE_MU_HAS_SR_MURIP)
    kMU_MuResetInterruptEnable = MU_CR_MURIE_MASK, 
#endif
#if (defined(FSL_FEATURE_MU_HAS_SR_HRIP) && FSL_FEATURE_MU_HAS_SR_HRIP)
    kMU_HardwareResetInterruptEnable = MU_CR_HRIE_MASK, 
#endif
};
 
enum _mu_interrupt_trigger
{
#if !(defined(FSL_FEATURE_MU_NO_NMI) && FSL_FEATURE_MU_NO_NMI)
    kMU_NmiInterruptTrigger = MU_CR_NMI_MASK, 
#endif
    kMU_GenInt0InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 3U)), 
    kMU_GenInt1InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 2U)), 
    kMU_GenInt2InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 1U)), 
    kMU_GenInt3InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 0U))  
};
 
typedef enum _mu_msg_reg_index
{
    kMU_MsgReg0 = 0,
    kMU_MsgReg1,
    kMU_MsgReg2,
    kMU_MsgReg3,
} mu_msg_reg_index_t;
 
/*******************************************************************************
 * API
 ******************************************************************************/
 
#if defined(__cplusplus)
extern "C" {
#endif
 
void MU_Init(MU_Type *base);
 
void MU_Deinit(MU_Type *base);
 
/* @} */
 
static inline void MU_SendMsgNonBlocking(MU_Type *base, uint32_t regIndex, uint32_t msg)
{
    assert(regIndex < MU_TR_COUNT);
 
    base->TR[regIndex] = msg;
}
 
void MU_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg);
 
static inline uint32_t MU_ReceiveMsgNonBlocking(MU_Type *base, uint32_t regIndex)
{
    assert(regIndex < MU_TR_COUNT);
 
    return base->RR[regIndex];
}
 
uint32_t MU_ReceiveMsg(MU_Type *base, uint32_t regIndex);
 
/* @} */
 
static inline void MU_SetFlagsNonBlocking(MU_Type *base, uint32_t flags)
{
    uint32_t reg = base->CR;
    reg          = (reg & ~((MU_CR_GIRn_MASK | MU_CR_NMI_MASK) | MU_CR_Fn_MASK)) | MU_CR_Fn(flags);
    base->CR     = reg;
}
 
void MU_SetFlags(MU_Type *base, uint32_t flags);
 
static inline uint32_t MU_GetFlags(MU_Type *base)
{
    return (base->SR & MU_SR_Fn_MASK) >> MU_SR_Fn_SHIFT;
}
 
/* @} */
 
static inline uint32_t MU_GetStatusFlags(MU_Type *base)
{
    return (base->SR & (MU_SR_TEn_MASK | MU_SR_RFn_MASK | MU_SR_GIPn_MASK | MU_SR_EP_MASK | MU_SR_FUP_MASK
#if (defined(FSL_FEATURE_MU_HAS_SR_RS) && FSL_FEATURE_MU_HAS_SR_RS)
                        | MU_SR_RS_MASK
#endif
#if (defined(FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT)
                        | MU_SR_RAIP_MASK
#endif
#if (defined(FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT)
                        | MU_SR_RDIP_MASK
#endif
#if (defined(FSL_FEATURE_MU_HAS_SR_MURIP) && FSL_FEATURE_MU_HAS_SR_MURIP)
                        | MU_SR_MURIP_MASK
#endif
#if (defined(FSL_FEATURE_MU_HAS_SR_HRIP) && FSL_FEATURE_MU_HAS_SR_HRIP)
                        | MU_SR_HRIP_MASK
#endif
                        ));
}
 
static inline uint32_t MU_GetInterruptsPending(MU_Type *base)
{
    uint32_t irqMask = base->CR & (MU_CR_GIEn_MASK | MU_CR_TIEn_MASK | MU_CR_RIEn_MASK);
    return (base->SR & irqMask);
}
 
static inline void MU_ClearStatusFlags(MU_Type *base, uint32_t mask)
{
    /* regMask is the mask of w1c status bits. */
    uint32_t regMask = MU_SR_GIPn_MASK;
 
#if (defined(FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT)
    regMask |= MU_SR_RAIP_MASK;
#endif
#if (defined(FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT)
    regMask |= MU_SR_RDIP_MASK;
#endif
 
#if (defined(FSL_FEATURE_MU_HAS_SR_MURIP) && FSL_FEATURE_MU_HAS_SR_MURIP)
    regMask |= MU_SR_MURIP_MASK;
#endif
 
#if (defined(FSL_FEATURE_MU_HAS_SR_HRIP) && FSL_FEATURE_MU_HAS_SR_HRIP)
    regMask |= MU_SR_HRIP_MASK;
#endif
 
    base->SR = (mask & regMask);
}
 
static inline void MU_EnableInterrupts(MU_Type *base, uint32_t mask)
{
    uint32_t reg = base->CR;
    reg          = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | mask;
    base->CR     = reg;
}
 
static inline void MU_DisableInterrupts(MU_Type *base, uint32_t mask)
{
    uint32_t reg = base->CR;
    reg &= ~((MU_CR_GIRn_MASK | MU_CR_NMI_MASK) | mask);
    base->CR = reg;
}
 
status_t MU_TriggerInterrupts(MU_Type *base, uint32_t mask);
 
#if !(defined(FSL_FEATURE_MU_NO_NMI) && FSL_FEATURE_MU_NO_NMI)
static inline void MU_ClearNmi(MU_Type *base)
{
    base->SR = MU_SR_NMIC_MASK;
}
#endif /* FSL_FEATURE_MU_NO_NMI */
 
/* @} */
 
#if !(defined(FSL_FEATURE_MU_NO_RSTH) && FSL_FEATURE_MU_NO_RSTH)
void MU_BootCoreB(MU_Type *base, mu_core_boot_mode_t mode);
 
static inline void MU_HoldCoreBReset(MU_Type *base)
{
#if (defined(FSL_FEATURE_MU_HAS_CCR) && FSL_FEATURE_MU_HAS_CCR)
    base->CCR |= MU_CCR_RSTH_MASK;
#else  /* FSL_FEATURE_MU_HAS_CCR */
    uint32_t reg = base->CR;
    reg          = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | MU_CR_RSTH_MASK;
    base->CR     = reg;
#endif /* FSL_FEATURE_MU_HAS_CCR */
}
 
void MU_BootOtherCore(MU_Type *base, mu_core_boot_mode_t mode);
 
static inline void MU_HoldOtherCoreReset(MU_Type *base)
{
    /*
     * MU_HoldOtherCoreReset and MU_HoldCoreBReset are the same, MU_HoldCoreBReset
     * is kept for compatible with older platforms.
     */
    MU_HoldCoreBReset(base);
}
#endif /* FSL_FEATURE_MU_NO_RSTH */
 
#if !(defined(FSL_FEATURE_MU_NO_MUR) && FSL_FEATURE_MU_NO_MUR)
static inline void MU_ResetBothSides(MU_Type *base)
{
    uint32_t reg = base->CR;
    reg          = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | MU_CR_MUR_MASK;
    base->CR     = reg;
 
#if (defined(FSL_FEATURE_MU_HAS_SR_RS) && FSL_FEATURE_MU_HAS_SR_RS)
    /* Wait for the other side out of reset. */
    while (0U != (base->SR & MU_SR_RS_MASK))
    {
    }
#endif /* FSL_FEATURE_MU_HAS_SR_RS */
}
#endif /* FSL_FEATURE_MU_NO_MUR  */
 
#if (defined(FSL_FEATURE_MU_HAS_HRM) && FSL_FEATURE_MU_HAS_HRM)
static inline void MU_MaskHardwareReset(MU_Type *base, bool mask)
{
#if (defined(FSL_FEATURE_MU_HAS_CCR) && FSL_FEATURE_MU_HAS_CCR)
    if (mask)
    {
        base->CCR |= MU_CCR_HRM_MASK;
    }
    else
    {
        base->CCR &= ~MU_CCR_HRM_MASK;
    }
#else  /* FSL_FEATURE_MU_HAS_CCR */
    if (mask)
    {
        base->CR |= MU_CR_HRM_MASK;
    }
    else
    {
        base->CR &= ~MU_CR_HRM_MASK;
    }
#endif /* FSL_FEATURE_MU_HAS_CCR  */
}
#endif /* FSL_FEATURE_MU_HAS_HRM */
 
#if !(defined(FSL_FEATURE_MU_NO_HR) && FSL_FEATURE_MU_NO_HR)
void MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode);
#endif /* FSL_FEATURE_MU_NO_HR */
 
#if !(defined(FSL_FEATURE_MU_NO_CLKE) && FSL_FEATURE_MU_NO_CLKE)
static inline void MU_SetClockOnOtherCoreEnable(MU_Type *base, bool enable)
{
#if (defined(FSL_FEATURE_MU_HAS_CCR) && FSL_FEATURE_MU_HAS_CCR)
    if (enable)
    {
        base->CCR |= MU_CCR_CLKE_MASK;
    }
    else
    {
        base->CCR &= ~MU_CCR_CLKE_MASK;
    }
#else  /* FSL_FEATURE_MU_HAS_CCR */
    uint32_t reg = base->CR;
 
    reg &= ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK);
 
    if (enable)
    {
        reg |= MU_CR_CLKE_MASK;
    }
    else
    {
        reg &= ~MU_CR_CLKE_MASK;
    }
 
    base->CR = reg;
#endif /* FSL_FEATURE_MU_HAS_CCR */
}
#endif /* FSL_FEATURE_MU_NO_CLKE */
 
#if !(defined(FSL_FEATURE_MU_NO_PM) && FSL_FEATURE_MU_NO_PM)
static inline mu_power_mode_t MU_GetOtherCorePowerMode(MU_Type *base)
{
    uint32_t ret = (base->SR & MU_SR_PM_MASK) >> MU_SR_PM_SHIFT;
 
    return (mu_power_mode_t)ret;
}
#endif /* FSL_FEATURE_MU_NO_PM */
 
/* @} */
 
#if defined(__cplusplus)
}
#endif /*_cplusplus*/
#endif /* _FSL_MU_H_*/