fsl_flexram.h

/*
 * Copyright 2017-2022 NXP
 * All rights reserved.
 *
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
 
#ifndef _FSL_FLEXRAM_H_
#define _FSL_FLEXRAM_H_
 
#include "fsl_common.h"
#include "fsl_flexram_allocate.h"
 
/******************************************************************************
 * Definitions.
 *****************************************************************************/
 
#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 0U))
#ifndef FLEXRAM_ECC_ERROR_DETAILED_INFO
#define FLEXRAM_ECC_ERROR_DETAILED_INFO \
    0U /* Define to zero means get raw ECC error information, which needs parse it by user. */
#endif
 
enum
{
    kFLEXRAM_Read  = 0U, 
    kFLEXRAM_Write = 1U, 
};
 
enum
{
    kFLEXRAM_OCRAMAccessError = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK, 
    kFLEXRAM_DTCMAccessError  = FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK,  
    kFLEXRAM_ITCMAccessError  = FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK,  
#if defined(FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR) && FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR
    kFLEXRAM_OCRAMMagicAddrMatch = FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK, 
    kFLEXRAM_DTCMMagicAddrMatch  = FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK,  
    kFLEXRAM_ITCMMagicAddrMatch  = FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK,  
#if defined(FSL_FEATURE_FLEXRAM_HAS_ECC) && FSL_FEATURE_FLEXRAM_HAS_ECC
    kFLEXRAM_OCRAMECCMultiError  = FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_MASK,
    kFLEXRAM_OCRAMECCSingleError = FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_MASK,
    kFLEXRAM_ITCMECCMultiError   = FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_MASK,
    kFLEXRAM_ITCMECCSingleError  = FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_MASK,
    kFLEXRAM_D0TCMECCMultiError  = FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_MASK,
    kFLEXRAM_D0TCMECCSingleError = FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_MASK,
    kFLEXRAM_D1TCMECCMultiError  = FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_MASK,
    kFLEXRAM_D1TCMECCSingleError = FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_MASK,
 
    kFLEXRAM_InterruptStatusAll =
        FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK |
        FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK |
        FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK | FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK |
        FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_MASK | FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_MASK |
        FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_MASK | FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_MASK |
        FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_MASK | FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_MASK |
        FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_MASK | FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_MASK,
#else
    kFLEXRAM_InterruptStatusAll = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK |
                                  FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK |
                                  FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK | FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK,
#endif /* FSL_FEATURE_FLEXRAM_HAS_ECC */
 
#else
    kFLEXRAM_InterruptStatusAll = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK |
                                  FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, 
#endif /* FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR */
 
};
 
typedef enum _flexram_tcm_access_mode
{
    kFLEXRAM_TCMAccessFastMode = 0U, 
    kFLEXRAM_TCMAccessWaitMode = 1U, 
} flexram_tcm_access_mode_t;
 
enum
{
    kFLEXRAM_TCMSize32KB  = 32 * 1024U,  
    kFLEXRAM_TCMSize64KB  = 64 * 1024U,  
    kFLEXRAM_TCMSize128KB = 128 * 1024U, 
    kFLEXRAM_TCMSize256KB = 256 * 1024U, 
    kFLEXRAM_TCMSize512KB = 512 * 1024U, 
};
 
#if (defined(FSL_FEATURE_FLEXRAM_HAS_ECC) && FSL_FEATURE_FLEXRAM_HAS_ECC)
typedef enum _flexram_memory_type
{
    kFLEXRAM_OCRAM = 0U, 
    kFLEXRAM_ITCM  = 1U, 
    kFLEXRAM_D0TCM = 2U, 
    kFLEXRAM_D1TCM = 3U, 
} flexram_memory_type_t;
 
typedef struct _flexram_ecc_error_type
{
    uint8_t SingleBitPos;          
    uint8_t SecondBitPos;          
    bool Fource1BitDataInversion;  
    bool FourceOneNCDataInversion; 
    bool FourceConti1BitDataInversion; 
    bool FourceContiNCDataInversion;   
} flexram_ecc_error_type_t;
 
typedef struct _flexram_ocram_ecc_single_error_info
{
#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
    uint8_t OcramSingleErrorECCCipher;   
    uint8_t OcramSingleErrorECCSyndrome; 
#else
    uint32_t OcramSingleErrorInfo; 
#endif                                /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
    uint32_t OcramSingleErrorAddr;    
    uint32_t OcramSingleErrorDataLSB; 
    uint32_t OcramSingleErrorDataMSB; 
} flexram_ocram_ecc_single_error_info_t;
 
typedef struct _flexram_ocram_ecc_multi_error_info
{
#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
    uint8_t OcramMultiErrorECCCipher; 
#else
    uint32_t OcramMultiErrorInfo;  
#endif                               /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
    uint32_t OcramMultiErrorAddr;    
    uint32_t OcramMultiErrorDataLSB; 
    uint32_t OcramMultiErrorDataMSB; 
} flexram_ocram_ecc_multi_error_info_t;
 
typedef struct _flexram_itcm_ecc_single_error_info
{
#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
    uint8_t ItcmSingleErrorTCMWriteRead;  
    uint8_t ItcmSingleErrorTCMAccessSize; 
    uint8_t ItcmSingleErrorTCMMaster;     
    uint8_t ItcmSingleErrorTCMPrivilege;  
    uint8_t ItcmSingleErrorBitPostion;    
#else
    uint32_t ItcmSingleErrorInfo;  
#endif                               /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
    uint32_t ItcmSingleErrorAddr;    
    uint32_t ItcmSingleErrorDataLSB; 
    uint32_t ItcmSingleErrorDataMSB; 
} flexram_itcm_ecc_single_error_info_t;
 
typedef struct _flexram_itcm_ecc_multi_error_info
{
#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
    uint8_t ItcmMultiErrorTCMWriteRead;  
    uint8_t ItcmMultiErrorTCMAccessSize; 
    uint8_t ItcmMultiErrorTCMMaster;     
    uint8_t ItcmMultiErrorTCMPrivilege;  
    uint8_t ItcmMultiErrorECCSyndrome;   
#else
    uint32_t ItcmMultiErrorInfo;   
#endif                              /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
    uint32_t ItcmMultiErrorAddr;    
    uint32_t ItcmMultiErrorDataLSB; 
    uint32_t ItcmMultiErrorDataMSB; 
} flexram_itcm_ecc_multi_error_info_t;
 
typedef struct _flexram_dtcm_ecc_single_error_info
{
#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
    uint8_t DtcmSingleErrorTCMWriteRead;  
    uint8_t DtcmSingleErrorTCMAccessSize; 
    uint8_t DtcmSingleErrorTCMMaster;     
    uint8_t DtcmSingleErrorTCMPrivilege;  
    uint8_t DtcmSingleErrorBitPostion;    
#else
    uint32_t DtcmSingleErrorInfo;  
#endif                            /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
    uint32_t DtcmSingleErrorAddr; 
    uint32_t DtcmSingleErrorData; 
} flexram_dtcm_ecc_single_error_info_t;
 
typedef struct _flexram_dtcm_ecc_multi_error_info
{
#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
    uint8_t DtcmMultiErrorTCMWriteRead;  
    uint8_t DtcmMultiErrorTCMAccessSize; 
    uint8_t DtcmMultiErrorTCMMaster;     
    uint8_t DtcmMultiErrorTCMPrivilege;  
    uint8_t DtcmMultiErrorECCSyndrome;   
#else
    uint32_t DtcmMultiErrorInfo;   
#endif                           /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
    uint32_t DtcmMultiErrorAddr; 
    uint32_t DtcmMultiErrorData; 
} flexram_dtcm_ecc_multi_error_info_t;
 
#endif /* FSL_FEATURE_FLEXRAM_HAS_ECC */
 
/*******************************************************************************
 * APIs
 ******************************************************************************/
 
#if defined(__cplusplus)
extern "C" {
#endif
 
void FLEXRAM_Init(FLEXRAM_Type *base);
 
void FLEXRAM_Deinit(FLEXRAM_Type *base);
 
/* @} */
 
static inline uint32_t FLEXRAM_GetInterruptStatus(FLEXRAM_Type *base)
{
    return base->INT_STATUS & (uint32_t)kFLEXRAM_InterruptStatusAll;
}
 
static inline void FLEXRAM_ClearInterruptStatus(FLEXRAM_Type *base, uint32_t status)
{
    base->INT_STATUS |= status;
}
 
static inline void FLEXRAM_EnableInterruptStatus(FLEXRAM_Type *base, uint32_t status)
{
    base->INT_STAT_EN |= status;
}
 
static inline void FLEXRAM_DisableInterruptStatus(FLEXRAM_Type *base, uint32_t status)
{
    base->INT_STAT_EN &= ~status;
}
 
/* @} */
 
static inline void FLEXRAM_EnableInterruptSignal(FLEXRAM_Type *base, uint32_t status)
{
    base->INT_SIG_EN |= status;
}
 
static inline void FLEXRAM_DisableInterruptSignal(FLEXRAM_Type *base, uint32_t status)
{
    base->INT_SIG_EN &= ~status;
}
/* @} */
 
static inline void FLEXRAM_SetTCMReadAccessMode(FLEXRAM_Type *base, flexram_tcm_access_mode_t mode)
{
    base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK;
    base->TCM_CTRL |= (uint32_t)mode;
}
 
static inline void FLEXRAM_SetTCMWriteAccessMode(FLEXRAM_Type *base, flexram_tcm_access_mode_t mode)
{
    base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK;
    base->TCM_CTRL |= (uint32_t)mode;
}
 
static inline void FLEXRAM_EnableForceRamClockOn(FLEXRAM_Type *base, bool enable)
{
    if (enable)
    {
        base->TCM_CTRL |= FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK;
    }
    else
    {
        base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK;
    }
}
 
#if defined(FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR) && FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR
static inline void FLEXRAM_SetOCRAMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
{
    base->OCRAM_MAGIC_ADDR = FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(rwSel) |
                             FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR((uint32_t)magicAddr >> 3);
}
 
static inline void FLEXRAM_SetDTCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
{
    base->DTCM_MAGIC_ADDR = FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(rwSel) |
                            FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR((uint32_t)magicAddr >> 3);
}
 
static inline void FLEXRAM_SetITCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
{
    base->ITCM_MAGIC_ADDR = FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(rwSel) |
                            FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR((uint32_t)magicAddr >> 3);
}
#endif /* FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR */
 
#if (defined(FSL_FEATURE_FLEXRAM_HAS_ECC) && FSL_FEATURE_FLEXRAM_HAS_ECC)
void FLEXRAM_EnableECC(FLEXRAM_Type *base, bool OcramECCEnable, bool TcmECCEnable);
 
void FLEXRAM_ErrorInjection(FLEXRAM_Type *base, flexram_memory_type_t memory, flexram_ecc_error_type_t *error);
 
void FLEXRAM_GetOcramSingleErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_single_error_info_t *info);
 
void FLEXRAM_GetOcramMultiErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_multi_error_info_t *info);
 
void FLEXRAM_GetItcmSingleErroInfo(FLEXRAM_Type *base, flexram_itcm_ecc_single_error_info_t *info);
 
void FLEXRAM_GetItcmMultiErroInfo(FLEXRAM_Type *base, flexram_itcm_ecc_multi_error_info_t *info);
 
void FLEXRAM_GetDtcmSingleErroInfo(FLEXRAM_Type *base, flexram_dtcm_ecc_single_error_info_t *info, uint8_t bank);
 
void FLEXRAM_GetDtcmMultiErroInfo(FLEXRAM_Type *base, flexram_dtcm_ecc_multi_error_info_t *info, uint8_t bank);
 
#endif /* FSL_FEATURE_FLEXRAM_HAS_ECC */
 
#if defined(__cplusplus)
}
#endif
 
#endif