fsl_acmp.h

/*
 * Copyright (c) 2015, Freescale Semiconductor, Inc.
 * Copyright 2016-2020 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
 
#ifndef _FSL_ACMP_H_
#define _FSL_ACMP_H_
 
#include "fsl_common.h"
 
/*******************************************************************************
 * Definitions
 ******************************************************************************/
 
#define FSL_ACMP_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 6U))
#define CMP_C0_CFx_MASK  (CMP_C0_CFR_MASK | CMP_C0_CFF_MASK)
#define CMP_C1_CHNn_MASK 0xFF0000U /* C1_CHN0 - C1_CHN7. */
#define CMP_C2_CHnF_MASK 0xFF0000U /* C2_CH0F - C2_CH7F. */
 
enum _acmp_interrupt_enable
{
    kACMP_OutputRisingInterruptEnable  = (1U << 0U), 
    kACMP_OutputFallingInterruptEnable = (1U << 1U), 
    kACMP_RoundRobinInterruptEnable    = (1U << 2U), 
};
 
enum _acmp_status_flags
{
    kACMP_OutputRisingEventFlag  = CMP_C0_CFR_MASK,  
    kACMP_OutputFallingEventFlag = CMP_C0_CFF_MASK,  
    kACMP_OutputAssertEventFlag  = CMP_C0_COUT_MASK, 
};
 
#if defined(FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT) && (FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT == 1U)
typedef enum _acmp_offset_mode
{
    kACMP_OffsetLevel0 = 0U, 
    kACMP_OffsetLevel1 = 1U, 
} acmp_offset_mode_t;
#endif /* FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT */
 
typedef enum _acmp_hysteresis_mode
{
    kACMP_HysteresisLevel0 = 0U, 
    kACMP_HysteresisLevel1 = 1U, 
    kACMP_HysteresisLevel2 = 2U, 
    kACMP_HysteresisLevel3 = 3U, 
} acmp_hysteresis_mode_t;
 
typedef enum _acmp_reference_voltage_source
{
    kACMP_VrefSourceVin1 = 0U, 
    kACMP_VrefSourceVin2 = 1U, 
} acmp_reference_voltage_source_t;
 
#if defined(FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT) && (FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT == 1U)
typedef enum _acmp_port_input
{
    kACMP_PortInputFromDAC = 0U, 
    kACMP_PortInputFromMux = 1U, 
} acmp_port_input_t;
#endif /* FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT */
 
typedef enum _acmp_fixed_port
{
    kACMP_FixedPlusPort  = 0U, 
    kACMP_FixedMinusPort = 1U, 
} acmp_fixed_port_t;
 
#if defined(FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT) && (FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT == 1U)
typedef enum _acmp_dac_work_mode
{
    kACMP_DACWorkLowSpeedMode  = 0U, 
    kACMP_DACWorkHighSpeedMode = 1U, 
} acmp_dac_work_mode_t;
#endif /* FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT */
 
typedef struct _acmp_config
{
#if defined(FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT) && (FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT == 1U)
    acmp_offset_mode_t offsetMode;         
#endif                                     /* FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT */
    acmp_hysteresis_mode_t hysteresisMode; 
    bool enableHighSpeed;                  
    bool enableInvertOutput;               
    bool useUnfilteredOutput;              
    bool enablePinOut;                     
} acmp_config_t;
 
typedef struct _acmp_channel_config
{
#if defined(FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT) && (FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT == 1U)
    acmp_port_input_t positivePortInput; 
#endif                                   /* FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT */
    uint32_t plusMuxInput;               
#if defined(FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT) && (FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT == 1U)
    acmp_port_input_t negativePortInput; 
#endif                                   /* FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT */
    uint32_t minusMuxInput;              
} acmp_channel_config_t;
 
typedef struct _acmp_filter_config
{
    bool enableSample;     
    uint32_t filterCount;  
    uint32_t filterPeriod; 
} acmp_filter_config_t;
 
typedef struct _acmp_dac_config
{
    acmp_reference_voltage_source_t referenceVoltageSource; 
    uint32_t DACValue; 
#if defined(FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT) && (FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT == 1U)
    bool enableOutput; 
#endif                 /* FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT */
 
#if defined(FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT) && (FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT == 1U)
    acmp_dac_work_mode_t workMode;
#endif /* FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT */
} acmp_dac_config_t;
 
typedef struct _acmp_round_robin_config
{
    acmp_fixed_port_t fixedPort; 
    uint32_t fixedChannelNumber; 
    uint32_t checkerChannelMask; 
    uint32_t sampleClockCount;   
    uint32_t delayModulus;       
} acmp_round_robin_config_t;
 
#if defined(FSL_FEATURE_ACMP_HAS_C3_REG) && (FSL_FEATURE_ACMP_HAS_C3_REG == 1U)
 
typedef enum _acmp_discrete_clock_source
{
    kACMP_DiscreteClockSlow = 0U, 
    kACMP_DiscreteClockFast = 1U, 
} acmp_discrete_clock_source_t;
 
typedef enum _acmp_discrete_sample_time
{
    kACMP_DiscreteSampleTimeAs1T   = 0U, 
    kACMP_DiscreteSampleTimeAs2T   = 1U, 
    kACMP_DiscreteSampleTimeAs4T   = 2U, 
    kACMP_DiscreteSampleTimeAs8T   = 3U, 
    kACMP_DiscreteSampleTimeAs16T  = 4U, 
    kACMP_DiscreteSampleTimeAs32T  = 5U, 
    kACMP_DiscreteSampleTimeAs64T  = 6U, 
    kACMP_DiscreteSampleTimeAs256T = 7U, 
} acmp_discrete_sample_time_t;
 
typedef enum _acmp_discrete_phase_time
{
    kACMP_DiscretePhaseTimeAlt0 = 0U, 
    kACMP_DiscretePhaseTimeAlt1 = 1U, 
    kACMP_DiscretePhaseTimeAlt2 = 2U, 
    kACMP_DiscretePhaseTimeAlt3 = 3U, 
    kACMP_DiscretePhaseTimeAlt4 = 4U, 
    kACMP_DiscretePhaseTimeAlt5 = 5U, 
    kACMP_DiscretePhaseTimeAlt6 = 6U, 
    kACMP_DiscretePhaseTimeAlt7 = 7U, 
} acmp_discrete_phase_time_t;
 
typedef struct _acmp_discrete_mode_config
{
    bool enablePositiveChannelDiscreteMode; 
    bool enableNegativeChannelDiscreteMode; 
    bool enableResistorDivider; 
    acmp_discrete_clock_source_t clockSource; 
    acmp_discrete_sample_time_t sampleTime;   
    acmp_discrete_phase_time_t phase1Time;    
    acmp_discrete_phase_time_t phase2Time;    
} acmp_discrete_mode_config_t;
 
#endif /* FSL_FEATURE_ACMP_HAS_C3_REG */
 
#if defined(__cplusplus)
extern "C" {
#endif
 
/*******************************************************************************
 * API
 ******************************************************************************/
 
void ACMP_Init(CMP_Type *base, const acmp_config_t *config);
 
void ACMP_Deinit(CMP_Type *base);
 
void ACMP_GetDefaultConfig(acmp_config_t *config);
 
/* @} */
 
void ACMP_Enable(CMP_Type *base, bool enable);
 
#if defined(FSL_FEATURE_ACMP_HAS_C0_LINKEN_BIT) && (FSL_FEATURE_ACMP_HAS_C0_LINKEN_BIT == 1U)
void ACMP_EnableLinkToDAC(CMP_Type *base, bool enable);
#endif /* FSL_FEATURE_ACMP_HAS_C0_LINKEN_BIT */
 
void ACMP_SetChannelConfig(CMP_Type *base, const acmp_channel_config_t *config);
 
/* @} */
 
void ACMP_EnableDMA(CMP_Type *base, bool enable);
 
void ACMP_EnableWindowMode(CMP_Type *base, bool enable);
 
void ACMP_SetFilterConfig(CMP_Type *base, const acmp_filter_config_t *config);
 
void ACMP_SetDACConfig(CMP_Type *base, const acmp_dac_config_t *config);
 
void ACMP_SetRoundRobinConfig(CMP_Type *base, const acmp_round_robin_config_t *config);
 
void ACMP_SetRoundRobinPreState(CMP_Type *base, uint32_t mask);
 
static inline uint32_t ACMP_GetRoundRobinStatusFlags(CMP_Type *base)
{
    return (((base->C2) & CMP_C2_CHnF_MASK) >> CMP_C2_CH0F_SHIFT);
}
 
void ACMP_ClearRoundRobinStatusFlags(CMP_Type *base, uint32_t mask);
 
static inline uint32_t ACMP_GetRoundRobinResult(CMP_Type *base)
{
    return ((base->C2 & CMP_C2_ACOn_MASK) >> CMP_C2_ACOn_SHIFT);
}
 
/* @} */
 
void ACMP_EnableInterrupts(CMP_Type *base, uint32_t mask);
 
void ACMP_DisableInterrupts(CMP_Type *base, uint32_t mask);
 
/* @} */
 
uint32_t ACMP_GetStatusFlags(CMP_Type *base);
 
void ACMP_ClearStatusFlags(CMP_Type *base, uint32_t mask);
 
/* @} */
 
#if defined(FSL_FEATURE_ACMP_HAS_C3_REG) && (FSL_FEATURE_ACMP_HAS_C3_REG == 1U)
void ACMP_SetDiscreteModeConfig(CMP_Type *base, const acmp_discrete_mode_config_t *config);
 
void ACMP_GetDefaultDiscreteModeConfig(acmp_discrete_mode_config_t *config);
 
/* @} */
#endif /* FSL_FEATURE_ACMP_HAS_C3_REG */
 
#if defined(__cplusplus)
}
#endif
 
#endif /* _FSL_ACMP_H_ */