79#pragma ANSI_strict off
122 uint32_t pbridge_a_reserved2[7];
135 uint32_t pbridge_a_reserved3[7];
240 uint32_t pbridge_b_reserved2[7];
257 uint32_t pbridge_b_reserved3;
285 uint32_t pbridge_b_reserved4[5];
386 union FMPLL_SYNCR_tag {
406 union FMPLL_SYNSR_tag {
506 uint32_t EBI_reserved1;
530 uint32_t EBI_reserved2[4];
671 int32_t SIU_reserved0;
680 int32_t SIU_reserved00;
735 union SIU_DIRER_tag {
758 union SIU_DIRSR_tag {
815 union SIU_IREER_tag {
838 union SIU_IFEER_tag {
869 int32_t SIU_reserved1[3];
887 int16_t SIU_reserved_0[224];
897 int32_t SIU_reserved_3[64];
964 int32_t SIU_reserved2[29];
1009 union EMIOS_MCR_tag {
1087 uint32_t emios_reserved[5];
1089 struct EMIOS_CH_tag {
1102 union EMIOS_CCR_tag {
1126 union EMIOS_CSR_tag {
1143 uint32_t emios_channel_reserved[2];
1172 uint32_t SCMMISEN:1;
1193 uint32_t etpu_reserved1;
1219 uint32_t etpu_reserved3;
1221 uint32_t etpu_reserved4;
1252 uint32_t SERVER_ID1:4;
1258 uint32_t SERVER_ID2:4;
1264 uint32_t etpu_reserved5[4];
1265 uint32_t etpu_reserved6[4];
1267 uint32_t etpu_reserved7[108];
1308 uint32_t etpu_reserved8;
1310 uint32_t etpu_reserved9[2];
1349 uint32_t etpu_reserved10;
1351 uint32_t etpu_reserved11[2];
1390 uint32_t etpu_reserved12;
1392 uint32_t etpu_reserved13[2];
1431 uint32_t etpu_reserved14;
1433 uint32_t etpu_reserved15[2];
1472 uint32_t etpu_reserved16;
1474 uint32_t etpu_reserved17[2];
1513 uint32_t etpu_reserved19;
1515 uint32_t etpu_reserved20[10];
1553 uint32_t etpu_reserved22;
1555 uint32_t etpu_reserved20a[2];
1594 uint32_t etpu_reserved22a;
1596 uint32_t etpu_reserved23[90];
1641 uint32_t etpu_reserved23;
1673 uint32_t xbar_reserved1[3];
1688 uint32_t xbar_reserved2[59];
1714 uint32_t xbar_reserved3[3];
1729 uint32_t xbar_reserved4[123];
1755 uint32_t xbar_reserved5[3];
1769 uint32_t xbar_reserved6[187];
1795 uint32_t xbar_reserved7[3];
1810 uint32_t xbar_reserved8[59];
1836 uint32_t xbar_reserved9[3];
1857 uint32_t ecsm_reserved1[5];
1859 uint16_t ecsm_reserved2;
1865 uint8_t ecsm_reserved3[3];
1871 uint8_t ecsm_reserved4[3];
1877 uint32_t ecsm_reserved5a[1];
1897 uint32_t ecsm_reserved5c[6];
1899 uint8_t ecsm_reserved6[3];
1910 uint8_t mcm_reserved8[3];
1921 uint16_t ecsm_reserved9;
1934 uint32_t ecsm_reserved10;
1943 uint16_t ecsm_reserved11;
1986 uint8_t ecsm_reserved12[2];
2037 int32_t INTC_reserved00;
2047 uint32_t intc_reserved1;
2058 uint32_t intc_reserved2;
2067 uint32_t intc_reserved3;
2078 uint32_t intc_reserved4[6];
2103 int32_t EQADC_reserved00;
2128 uint32_t eqadc_reserved1;
2130 uint32_t eqadc_reserved2;
2140 uint32_t eqadc_reserved3;
2142 uint32_t eqadc_reserved4;
2156 uint32_t eqadc_reserved5;
2177 uint32_t eqadc_reserved6;
2197 uint32_t POPNXTPTR:4;
2201 uint32_t eqadc_reserved7;
2203 uint32_t eqadc_reserved8;
2213 uint32_t eqadc_reserved9;
2226 uint32_t TC_LCFTCB0:11;
2241 uint32_t TC_LCFTCB1:11;
2257 uint32_t TC_LCFTSSI:11;
2274 uint32_t eqadc_reserved11;
2295 uint32_t eqadc_reserved12[17];
2305 uint32_t eqadc_reserved13[12];
2309 uint32_t eqadc_reserved14[32];
2319 uint32_t eqadc_reserved15[12];
2332 uint32_t CONT_SCKE:1;
2357 uint32_t dspi_reserved1;
2402 uint32_t TXNXTPTR:4;
2404 uint32_t POPNXTPTR:4;
2417 uint32_t TFFFDIRS:1;
2422 uint32_t RFDFDIRS:1;
2461 uint32_t DSPI_reserved_txf[12];
2471 uint32_t DSPI_reserved_rxf[12];
2500 uint32_t SER_DATA:16;
2508 uint32_t ASER_DATA:16;
2516 uint32_t COMP_DATA:16;
2524 uint32_t DESER_DATA:16;
2533 union ESCI_CR1_tag {
2557 union ESCI_CR2_tag {
2714 int32_t FLEXCAN_reserved00;
2927 uint32_t flexcan2_reserved2[19];
2940 uint32_t TIMESTAMP:16;
2962 uint32_t flexcan2_reserved3[256];
2978 uint32_t fec_reserved_start[0x1];
3020 uint32_t fec_reserved_eimr;
3026 uint32_t R_DES_ACTIVE:1;
3035 uint32_t X_DES_ACTIVE:1;
3040 uint32_t fec_reserved_tdar[3];
3046 uint32_t ETHER_EN:1;
3051 uint32_t fec_reserved_ecr[6];
3069 uint32_t DIS_PREAMBLE:1;
3070 uint32_t MII_SPEED:6;
3075 uint32_t fec_reserved_mscr[7];
3080 uint32_t MIB_DISABLE:1;
3081 uint32_t MIB_IDLE:1;
3086 uint32_t fec_reserved_mibc[7];
3097 uint32_t MII_MODE:1;
3103 uint32_t fec_reserved_rcr[15];
3109 uint32_t RFC_PAUSE:1;
3110 uint32_t TFC_PAUSE:1;
3117 uint32_t fec_reserved_tcr[7];
3138 uint32_t PAUSE_DUR:16;
3142 uint32_t fec_reserved_opd[10];
3172 uint32_t fec_reserved_galr[7];
3182 uint32_t fec_reserved_tfwr;
3197 uint32_t R_FSTART:8;
3202 uint32_t fec_reserved_frsr[11];
3207 uint32_t R_DES_START:30;
3215 uint32_t X_DES_START:30;
3224 uint32_t R_BUF_SIZE:7;
3229 uint32_t fec_reserved_emrbr[29];
3289 } RMON_T_P512TO1023;
3293 } RMON_T_P1024TO2047;
3351 uint32_t fec_reserved_rmon_t_octets_ok[2];
3389 uint32_t fec_reserved_rmon_r_jab;
3409 } RMON_R_P512TO1023;
3413 } RMON_R_P1024TO2047;
3456 typedef union uMVR {
3464 typedef union uMCR {
3475 uint16_t PRESCALE:3;
3505 uint16_t MBSEG2DS:7;
3507 uint16_t MBSEG1DS:7;
3515 uint16_t LAST_MB_SEG1:7;
3517 uint16_t LAST_MB_UTIL:7;
3521 typedef union uPOCR {
3664 typedef union uPSR0 {
3668 uint16_t SLOTMODE:2;
3670 uint16_t PROTSTATE:3;
3671 uint16_t SUBSTATE:4;
3673 uint16_t WAKEUPSTATUS:3;
3680 typedef union uPSR1 {
3693 typedef union uPSR2 {
3708 uint16_t CLKCORRFAILCNT:4;
3711 typedef union uPSR3 {
3774 uint16_t SYNFRID:10;
3801 uint16_t TI1CYCVAL:6;
3803 uint16_t TI1CYCMSK:6;
3808 typedef union uSSSR {
3815 uint16_t SLOTNUMBER:11;
3832 uint16_t STATUSMASK:4;
3835 typedef union uSSR {
3861 uint16_t CYCCNTMSK:6;
3863 uint16_t CYCCNTVAL:6;
3879 uint16_t FIFODEPTH:8;
3881 uint16_t ENTRYSIZE:7;
3911 typedef union uPCR0 {
3914 uint16_t ACTION_POINT_OFFSET:6;
3915 uint16_t STATIC_SLOT_LENGTH:10;
3919 typedef union uPCR1 {
3923 uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14;
3927 typedef union uPCR2 {
3930 uint16_t MINISLOT_AFTER_ACTION_POINT:6;
3931 uint16_t NUMBER_OF_STATIC_SLOTS:10;
3935 typedef union uPCR3 {
3938 uint16_t WAKEUP_SYMBOL_RX_LOW:6;
3939 uint16_t MINISLOT_ACTION_POINT_OFFSET:5;
3940 uint16_t COLDSTART_ATTEMPTS:5;
3944 typedef union uPCR4 {
3947 uint16_t CAS_RX_LOW_MAX:7;
3948 uint16_t WAKEUP_SYMBOL_RX_WINDOW:9;
3952 typedef union uPCR5 {
3955 uint16_t TSS_TRANSMITTER:4;
3956 uint16_t WAKEUP_SYMBOL_TX_LOW:6;
3957 uint16_t WAKEUP_SYMBOL_RX_IDLE:6;
3961 typedef union uPCR6 {
3965 uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8;
3966 uint16_t MACRO_INITIAL_OFFSET_A:7;
3970 typedef union uPCR7 {
3973 uint16_t DECODING_CORRECTION_B:9;
3974 uint16_t MICRO_PER_MACRO_NOM_HALF:7;
3978 typedef union uPCR8 {
3981 uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;
3982 uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;
3983 uint16_t WAKEUP_SYMBOL_TX_IDLE:8;
3987 typedef union uPCR9 {
3990 uint16_t MINISLOT_EXISTS:1;
3991 uint16_t SYMBOL_WINDOW_EXISTS:1;
3992 uint16_t OFFSET_CORRECTION_OUT:14;
3999 uint16_t SINGLE_SLOT_ENABLED:1;
4000 uint16_t WAKEUP_CHANNEL:1;
4001 uint16_t MACRO_PER_CYCLE:14;
4008 uint16_t KEY_SLOT_USED_FOR_STARTUP:1;
4009 uint16_t KEY_SLOT_USED_FOR_SYNC:1;
4010 uint16_t OFFSET_CORRECTION_START:14;
4017 uint16_t ALLOW_PASSIVE_TO_ACTIVE:5;
4018 uint16_t KEY_SLOT_HEADER_CRC:11;
4025 uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;
4026 uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10;
4033 uint16_t RATE_CORRECTION_OUT:11;
4034 uint16_t LISTEN_TIMEOUT_H:5;
4041 uint16_t LISTEN_TIMEOUT_L:16;
4048 uint16_t MACRO_INITIAL_OFFSET_B:7;
4049 uint16_t NOISE_LISTEN_TIMEOUT_H:9;
4056 uint16_t NOISE_LISTEN_TIMEOUT_L:16;
4063 uint16_t WAKEUP_PATTERN:6;
4064 uint16_t KEY_SLOT_ID:10;
4071 uint16_t DECODING_CORRECTION_A:9;
4072 uint16_t PAYLOAD_LENGTH_STATIC:7;
4079 uint16_t MICRO_INITIAL_OFFSET_B:8;
4080 uint16_t MICRO_INITIAL_OFFSET_A:8;
4087 uint16_t EXTERN_RATE_CORRECTION:3;
4088 uint16_t LATEST_TX:13;
4096 uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11;
4097 uint16_t MICRO_PER_CYCLE_H:4;
4104 uint16_t micro_per_cycle_l:16;
4111 uint16_t CLUSTER_DRIFT_DAMPING:5;
4112 uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7;
4113 uint16_t MICRO_PER_CYCLE_MIN_H:4;
4120 uint16_t MICRO_PER_CYCLE_MIN_L:16;
4127 uint16_t ALLOW_HALT_DUE_TO_CLOCK:1;
4128 uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11;
4129 uint16_t MICRO_PER_CYCLE_MAX_H:4;
4136 uint16_t MICRO_PER_CYCLE_MAX_L:16;
4143 uint16_t DYNAMIC_SLOT_IDLE_PHASE:2;
4144 uint16_t MACRO_AFTER_OFFSET_CORRECTION:14;
4151 uint16_t EXTERN_OFFSET_CORRECTION:3;
4152 uint16_t MINISLOTS_MAX:13;
4160 uint16_t SYNC_NODE_MAX:4;
4216 typedef union uPDAR {
4252 typedef union uNMVR {
4267 typedef union uSSCR {
4270 typedef union uRFSR {
4310 uint16_t reserved3a[1];
4333 uint16_t reserved3[1];
4349 volatile SSR_t SSR[8];
4398 uint16_t reserved2[17];
4464 uint16_t DATA_OFFSET;
4470#define SRAM_START 0x40000000
4471#define SRAM_SIZE 0x14000
4472#define SRAM_END 0x40013FFF
4474#define FLASH_START 0x0
4475#define FLASH_SIZE 0x200000
4476#define FLASH_END 0x1FFFFF
4479#define PBRIDGE_A (*(volatile struct PBRIDGE_A_tag *) 0xC3F00000)
4480#define FMPLL (*(volatile struct FMPLL_tag *) 0xC3F80000)
4481#define EBI (*(volatile struct EBI_tag *) 0xC3F84000)
4482#define FLASH (*(volatile struct FLASH_tag *) 0xC3F88000)
4483#define SIU (*(volatile struct SIU_tag *) 0xC3F90000)
4485#define EMIOS (*(volatile struct EMIOS_tag *) 0xC3FA0000)
4486#define ETPU (*(volatile struct ETPU_tag *) 0xC3FC0000)
4487#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000)
4488#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000)
4489#define ETPU_DATA_RAM_END 0xC3FC89FC
4490#define CODE_RAM (*( uint32_t *) 0xC3FD0000)
4491#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000)
4493#define PBRIDGE_B (*(volatile struct PBRIDGE_B_tag *) 0xFFF00000)
4494#define XBAR (*(volatile struct XBAR_tag *) 0xFFF04000)
4495#define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000)
4496#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000)
4497#define INTC (*(volatile struct INTC_tag *) 0xFFF48000)
4499#define EQADC (*(volatile struct EQADC_tag *) 0xFFF80000)
4501#define DSPI_A (*(volatile struct DSPI_tag *) 0xFFF90000)
4502#define DSPI_B (*(volatile struct DSPI_tag *) 0xFFF94000)
4503#define DSPI_C (*(volatile struct DSPI_tag *) 0xFFF98000)
4504#define DSPI_D (*(volatile struct DSPI_tag *) 0xFFF9C000)
4506#define ESCI_A (*(volatile struct ESCI_tag *) 0xFFFB0000)
4507#define ESCI_B (*(volatile struct ESCI_tag *) 0xFFFB4000)
4509#define CAN_A (*(volatile struct FLEXCAN2_tag *) 0xFFFC0000)
4510#define CAN_B (*(volatile struct FLEXCAN2_tag *) 0xFFFC4000)
4511#define CAN_C (*(volatile struct FLEXCAN2_tag *) 0xFFFC8000)
4512#define CAN_D (*(volatile struct FLEXCAN2_tag *) 0xFFFCC000)
4513#define CAN_E (*(volatile struct FLEXCAN2_tag *) 0xFFFD0000)
4515#define FEC (*(volatile struct FEC_tag *) 0xFFF4C000)
4517#define FR (*(volatile struct FR_tag *) 0xFFFE0000)
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