61#pragma ANSI_strict off
82 uint32_t crp_reserved1[3];
108 uint32_t crp_reserved2[10];
152 uint32_t crp_reserved3[2];
181 uint32_t crp_reserved4;
189 uint32_t WKRLLOVRF:1;
203 uint32_t crp_reserved5[3];
243 uint32_t CONT_SCKE:1;
268 uint32_t dspi_reserved1;
273 uint32_t SPI_TCNT:16;
315 uint32_t POPNXTPTR:4;
372 uint32_t DSPI_reserved_txf[12];
382 uint32_t DSPI_reserved_rxf[12];
407 uint32_t SER_DATA:16;
415 uint32_t ASER_DATA:16;
423 uint32_t COMP_DATA:16;
431 uint32_t DESER_DATA:16;
474 uint32_t ebi_cal_cs_reserved [2];
494 uint32_t EBI_reserved1;
518 uint32_t EBI_reserved2[4];
634 uint32_t emios_reserved1[4];
702 uint32_t emios_channel_reserved[2];
719 uint32_t eqadc_reserved0;
744 uint32_t eqadc_reserved1;
746 uint32_t eqadc_reserved2;
756 uint32_t eqadc_reserved3;
758 uint32_t eqadc_reserved4;
772 uint32_t eqadc_reserved5;
793 uint32_t eqadc_reserved6;
813 uint32_t POPNXTPTR:4;
817 uint32_t eqadc_reserved7;
819 uint32_t eqadc_reserved8;
829 uint32_t eqadc_reserved9;
842 uint32_t TC_LCFT0:11;
846 uint32_t eqadc_reserved10[2];
861 uint32_t eqadc_reserved11[20];
871 uint32_t eqadc_reserved12[12];
875 uint32_t eqadc_reserved13[32];
885 uint32_t eqadc_reserved14[12];
1186 uint32_t LPRIO_EN:1;
1222 uint32_t FLEXCAN_reserved1;
1430 uint32_t FLEXCAN_reserved2[19];
1443 uint32_t TIMESTAMP:16;
1465 uint32_t FLEXCAN_reserved3[256];
1480 uint32_t FMPLL_reserved0;
1602 uint32_t VTES_PRC1:1;
1604 uint32_t HVEN_PRC1:1;
1612 int32_t INTC_reserved1;
1642 uint32_t VTBA_PRC1:21;
1643 uint32_t INTVEC_PRC1:9;
1671 uint32_t intc_reserved2[6];
1688 uint32_t mcm_reserved1[5];
1690 uint16_t mcm_reserved2;
1704 uint8_t mcm_reserved3[3];
1710 uint8_t mcm_reserved4[3];
1720 uint32_t mcm_reserved5[1];
1730 uint32_t mcm_reserved6[6];
1731 uint8_t mcm_reserved7[3];
1742 uint8_t mcm_reserved8[3];
1753 uint16_t mcm_reserved9;
1766 uint32_t mcm_reserved10;
1772 uint16_t mcm_reserved11;
1787 uint8_t PROTECTION:4;
1806 uint16_t mcm_reserved12;
1821 uint8_t PROTECTION:4;
1851 uint32_t mpu_reserved1[3];
1907 uint32_t mpu_reserved2[246];
1913 uint32_t SRTADDR:27;
1921 uint32_t ENDADDR:27;
1959 uint32_t mpu_reserved3[192];
1993 uint32_t pit_reserved1[23];
2002 uint32_t pit_reserved2[23];
2090 uint32_t sema4_reserved1[12];
2114 uint16_t sema4_reserved2[3];
2138 uint16_t sema4_reserved3[27];
2162 uint16_t sema4_reserved4[3];
2186 uint16_t sema4_reserved5[59];
2199 uint16_t sema4_reserved6;
2217 int32_t SIU_reserved0;
2222 uint32_t PARTNUM:16;
2226 uint32_t MASKNUM_MAJOR:4;
2227 uint32_t MASKNUM_MINOR:4;
2231 int32_t SIU_reserved1;
2452 int32_t SIU_reserved2[2];
2470 int32_t SIU_reserved3[295];
2480 int32_t SIU_reserved4[91];
2490 int32_t SIU_reserved5[27];
2528 uint32_t SELEMIOS15:2;
2529 uint32_t SELEMIOS14:2;
2530 uint32_t SELEMIOS13:2;
2531 uint32_t SELEMIOS12:2;
2532 uint32_t SELEMIOS11:2;
2533 uint32_t SELEMIOS10:2;
2534 uint32_t SELEMIOS9:2;
2535 uint32_t SELEMIOS8:2;
2536 uint32_t SELEMIOS7:2;
2537 uint32_t SELEMIOS6:2;
2538 uint32_t SELEMIOS5:2;
2539 uint32_t SELEMIOS4:2;
2540 uint32_t SELEMIOS3:2;
2541 uint32_t SELEMIOS2:2;
2542 uint32_t SELEMIOS1:2;
2543 uint32_t SELEMIOS0:2;
2547 int32_t SIU_reserved6[29];
2583 int32_t SIU_reserved7[2];
2588 uint32_t SYSCLKSEL:2;
2589 uint32_t SYSCLKDIV:2;
2590 uint32_t SWTCLKSEL:1;
2592 uint32_t LPCLKDIV7:2;
2593 uint32_t LPCLKDIV6:2;
2594 uint32_t LPCLKDIV5:2;
2595 uint32_t LPCLKDIV4:2;
2596 uint32_t LPCLKDIV3:2;
2597 uint32_t LPCLKDIV2:2;
2598 uint32_t LPCLKDIV1:2;
2599 uint32_t LPCLKDIV0:2;
2611 int32_t SIU_reserved8[149];
2653 int32_t SIU_reserved9[11];
2696 int32_t SIU_reserved10[12];
2701 uint32_t PB_MASK:16;
2709 uint32_t PC_MASK:16;
2717 uint32_t PD_MASK:16;
2725 uint32_t PE_MASK:16;
2733 uint32_t PF_MASK:16;
2741 uint32_t PG_MASK:16;
2749 uint32_t PH_MASK:16;
2757 uint32_t PJ_MASK:16;
2786 uint16_t PRESCALE:3;
2805 uint16_t MBSEG2DS:7;
2807 uint16_t MBSEG1DS:7;
2816 uint16_t LAST_MB_SEG1:6;
2818 uint16_t LAST_MB_UTIL:6;
2969 uint16_t SLOTMODE:2;
2971 uint16_t PROTSTATE:3;
2972 uint16_t SUBSTATE:4;
2974 uint16_t WAKEUPSTATUS:3;
3009 uint16_t CLKCORRFAILCNT:4;
3083 uint16_t SYNFRID:10;
3110 uint16_t TI1CYCVAL:6;
3112 uint16_t TI1CYCMSK:6;
3124 uint16_t SLOTNUMBER:11;
3141 uint16_t STATUSMASK:4;
3170 uint16_t CYCCNTMSK:6;
3172 uint16_t CYCCNTVAL:6;
3190 uint16_t FIFODEPTH:8;
3192 uint16_t ENTRYSIZE:7;
3225 uint16_t ACTION_POINT_OFFSET:6;
3226 uint16_t STATIC_SLOT_LENGTH:10;
3234 uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14;
3241 uint16_t MINISLOT_AFTER_ACTION_POINT:6;
3242 uint16_t NUMBER_OF_STATIC_SLOTS:10;
3249 uint16_t WAKEUP_SYMBOL_RX_LOW:6;
3250 uint16_t MINISLOT_ACTION_POINT_OFFSET:5;
3251 uint16_t COLDSTART_ATTEMPTS:5;
3258 uint16_t CAS_RX_LOW_MAX:7;
3259 uint16_t WAKEUP_SYMBOL_RX_WINDOW:9;
3266 uint16_t TSS_TRANSMITTER:4;
3267 uint16_t WAKEUP_SYMBOL_TX_LOW:6;
3268 uint16_t WAKEUP_SYMBOL_RX_IDLE:6;
3276 uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8;
3277 uint16_t MACRO_INITIAL_OFFSET_A:7;
3284 uint16_t DECODING_CORRECTION_B:9;
3285 uint16_t MICRO_PER_MACRO_NOM_HALF:7;
3292 uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;
3293 uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;
3294 uint16_t WAKEUP_SYMBOL_TX_IDLE:8;
3301 uint16_t MINISLOT_EXISTS:1;
3302 uint16_t SYMBOL_WINDOW_EXISTS:1;
3303 uint16_t OFFSET_CORRECTION_OUT:14;
3310 uint16_t SINGLE_SLOT_ENABLED:1;
3311 uint16_t WAKEUP_CHANNEL:1;
3312 uint16_t MACRO_PER_CYCLE:14;
3319 uint16_t KEY_SLOT_USED_FOR_STARTUP:1;
3320 uint16_t KEY_SLOT_USED_FOR_SYNC:1;
3321 uint16_t OFFSET_CORRECTION_START:14;
3328 uint16_t ALLOW_PASSIVE_TO_ACTIVE:5;
3329 uint16_t KEY_SLOT_HEADER_CRC:11;
3336 uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;
3337 uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10;
3344 uint16_t RATE_CORRECTION_OUT:11;
3345 uint16_t LISTEN_TIMEOUT_H:5;
3352 uint16_t LISTEN_TIMEOUT_L:16;
3359 uint16_t MACRO_INITIAL_OFFSET_B:7;
3360 uint16_t NOISE_LISTEN_TIMEOUT_H:9;
3367 uint16_t NOISE_LISTEN_TIMEOUT_L:16;
3374 uint16_t WAKEUP_PATTERN:6;
3375 uint16_t KEY_SLOT_ID:10;
3382 uint16_t DECODING_CORRECTION_A:9;
3383 uint16_t PAYLOAD_LENGTH_STATIC:7;
3390 uint16_t MICRO_INITIAL_OFFSET_B:8;
3391 uint16_t MICRO_INITIAL_OFFSET_A:8;
3398 uint16_t EXTERN_RATE_CORRECTION:3;
3399 uint16_t LATEST_TX:13;
3407 uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11;
3408 uint16_t MICRO_PER_CYCLE_H:4;
3415 uint16_t micro_per_cycle_l:16;
3422 uint16_t CLUSTER_DRIFT_DAMPING:5;
3423 uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7;
3424 uint16_t MICRO_PER_CYCLE_MIN_H:4;
3431 uint16_t MICRO_PER_CYCLE_MIN_L:16;
3438 uint16_t ALLOW_HALT_DUE_TO_CLOCK:1;
3439 uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11;
3440 uint16_t MICRO_PER_CYCLE_MAX_H:4;
3447 uint16_t MICRO_PER_CYCLE_MAX_L:16;
3454 uint16_t DYNAMIC_SLOT_IDLE_PHASE:2;
3455 uint16_t MACRO_AFTER_OFFSET_CORRECTION:14;
3462 uint16_t EXTERN_OFFSET_CORRECTION:3;
3463 uint16_t MINISLOTS_MAX:13;
3471 uint16_t SYNC_NODE_MAX:4;
3622 uint16_t reserved0[1];
3625 uint16_t reserved1[1];
3626 uint16_t reserved2[1];
3664 volatile SSR_t SSR[8];
3713 uint16_t reserved3[17];
3779 uint16_t DATA_OFFSET;
3792 uint32_t MDATOBSE:1;
3800 uint32_t MSVRQCIE:1;
3802 uint32_t MSBFEPOL:1;
3803 uint32_t MDBFEPOL:1;
3828 uint32_t RXCCHA_ACEN:1;
3838 uint32_t RXACHA_ACEN:1;
3848 uint32_t TXCCHA_ACEN:1;
3858 uint32_t TXACHA_ACEN:1;
3868 uint32_t TXSCHA_ACEN:1;
3895 uint32_t RXICHA_ACEN:1;
3905 uint32_t TXICHA_ACEN:1;
3916#define SRAM_START 0x40000000UL
3917#define SRAM_SIZE 0x14000UL
3918#define SRAM_END 0x40013FFFUL
3920#define FLASH_START 0x0UL
3921#define FLASH_SIZE 0x180000UL
3922#define FLASH_END 0x17FFFFUL
3925#define SEMA4 (*(volatile struct SEMA4_tag *) 0xFFF10000UL)
3926#define MPU (*(volatile struct MPU_tag *) 0xFFF14000UL)
3927#define MCM (*(volatile struct MCM_tag *) 0xFFF40000UL)
3928#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL)
3929#define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL)
3930#define EQADC (*(volatile struct EQADC_tag *) 0xFFF80000UL)
3931#define MLB (*(volatile struct MLB_tag *) 0xFFF84000UL)
3932#define I2C (*(volatile struct I2C_tag *) 0xFFF88000UL)
3933#define DSPI_A (*(volatile struct DSPI_tag *) 0xFFF90000UL)
3934#define DSPI_B (*(volatile struct DSPI_tag *) 0xFFF94000UL)
3935#define DSPI_C (*(volatile struct DSPI_tag *) 0xFFF98000UL)
3936#define DSPI_D (*(volatile struct DSPI_tag *) 0xFFF9C000UL)
3937#define ESCI_A (*(volatile struct ESCI_tag *) 0xFFFA0000UL)
3938#define ESCI_B (*(volatile struct ESCI_tag *) 0xFFFA4000UL)
3939#define ESCI_C (*(volatile struct ESCI_tag *) 0xFFFA8000UL)
3940#define ESCI_D (*(volatile struct ESCI_tag *) 0xFFFAC000UL)
3941#define ESCI_E (*(volatile struct ESCI_tag *) 0xFFFB0000UL)
3942#define ESCI_F (*(volatile struct ESCI_tag *) 0xFFFB4000UL)
3943#define ESCI_G (*(volatile struct ESCI_tag *) 0xFFFB8000UL)
3944#define ESCI_H (*(volatile struct ESCI_tag *) 0xFFFBC000UL)
3945#define CAN_A (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL)
3946#define CAN_B (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL)
3947#define CAN_C (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL)
3948#define CAN_D (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL)
3949#define CAN_E (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL)
3950#define CAN_F (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL)
3951#define FR (*(volatile struct FR_tag *) 0xFFFD8000UL)
3952#define DMAMUX (*(volatile struct DMAMUX_tag *) 0xFFFDC000UL)
3953#define PIT (*(volatile struct PIT_tag *) 0xFFFE0000UL)
3954#define EMIOS (*(volatile struct EMIOS_tag *) 0xFFFE4000UL)
3955#define SIU (*(volatile struct SIU_tag *) 0xFFFE8000UL)
3956#define CRP (*(volatile struct CRP_tag *) 0xFFFEC000UL)
3957#define FMPLL (*(volatile struct FMPLL_tag *) 0xFFFF0000UL)
3958#define EBI (*(volatile struct EBI_tag *) 0xFFFF4000UL)
3959#define FLASH (*(volatile struct FLASH_tag *) 0xFFFF8000UL)
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