37#ifndef LIBBSP_ARM_SHARED_CACHE_L1_H
38#define LIBBSP_ARM_SHARED_CACHE_L1_H
48#define ARM_CACHE_L1_CPU_DATA_ALIGNMENT 32
49#define ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT 32
51#define ARM_CACHE_L1_CSS_ID_DATA \
52 (ARM_CP15_CACHE_CSS_ID_DATA | ARM_CP15_CACHE_CSS_LEVEL(0))
53#define ARM_CACHE_L1_CSS_ID_INSTRUCTION \
54 (ARM_CP15_CACHE_CSS_ID_INSTRUCTION | ARM_CP15_CACHE_CSS_LEVEL(0))
55#define ARM_CACHE_L1_DATA_LINE_MASK ( ARM_CACHE_L1_CPU_DATA_ALIGNMENT - 1 )
56#define ARM_CACHE_L1_INSTRUCTION_LINE_MASK \
57 ( ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT \
61static void arm_cache_l1_errata_764369_handler(
void )
64 _ARM_Data_synchronization_barrier();
76static inline void arm_cache_l1_properties_for_level(
78 uint32_t *l1Associativity,
80 uint32_t level_and_inst_dat
85 ccsidr = arm_cp15_get_cache_size_id_for_level(level_and_inst_dat);
88 *l1LineSize = arm_ccsidr_get_line_power(ccsidr);
90 *l1Associativity = arm_ccsidr_get_associativity(ccsidr);
92 *l1NumSets = arm_ccsidr_get_num_sets(ccsidr);
104static inline uint32_t arm_cache_l1_get_set_way_param(
105 const uint32_t log_2_line_bytes,
106 const uint32_t associativity,
107 const uint32_t cache_level_idx,
111 uint32_t way_shift = __builtin_clz( associativity - 1 );
116 << way_shift ) | ( set << log_2_line_bytes ) | ( cache_level_idx << 1 ) );
119static inline void arm_cache_l1_flush_1_data_line(
const void *d_addr )
122 arm_cp15_data_cache_clean_and_invalidate_line( d_addr );
125 _ARM_Data_synchronization_barrier();
128static inline void arm_cache_l1_flush_entire_data(
void )
130 uint32_t l1LineSize, l1Associativity, l1NumSets;
132 uint32_t set_way_param;
135 _ARM_Data_memory_barrier();
138 arm_cache_l1_properties_for_level( &l1LineSize,
139 &l1Associativity, &l1NumSets,
140 ARM_CACHE_L1_CSS_ID_DATA);
142 for (
w = 0;
w < l1Associativity; ++
w ) {
143 for ( s = 0; s < l1NumSets; ++s ) {
144 set_way_param = arm_cache_l1_get_set_way_param(
151 arm_cp15_data_cache_clean_line_by_set_and_way( set_way_param );
156 _ARM_Data_synchronization_barrier();
159static inline void arm_cache_l1_invalidate_entire_data(
void )
161 uint32_t l1LineSize, l1Associativity, l1NumSets;
163 uint32_t set_way_param;
166 _ARM_Data_memory_barrier();
169 arm_cache_l1_properties_for_level( &l1LineSize,
170 &l1Associativity, &l1NumSets,
171 ARM_CACHE_L1_CSS_ID_DATA);
173 for (
w = 0;
w < l1Associativity; ++
w ) {
174 for ( s = 0; s < l1NumSets; ++s ) {
175 set_way_param = arm_cache_l1_get_set_way_param(
182 arm_cp15_data_cache_invalidate_line_by_set_and_way( set_way_param );
187 _ARM_Data_synchronization_barrier();
190static inline void arm_cache_l1_clean_and_invalidate_entire_data(
void )
192 uint32_t l1LineSize, l1Associativity, l1NumSets;
194 uint32_t set_way_param;
197 _ARM_Data_memory_barrier();
201 arm_cache_l1_properties_for_level( &l1LineSize,
202 &l1Associativity, &l1NumSets,
203 ARM_CACHE_L1_CSS_ID_DATA);
205 for (
w = 0;
w < l1Associativity; ++
w ) {
206 for ( s = 0; s < l1NumSets; ++s ) {
207 set_way_param = arm_cache_l1_get_set_way_param(
214 arm_cp15_data_cache_clean_and_invalidate_line_by_set_and_way(
220 _ARM_Data_synchronization_barrier();
223static inline void arm_cache_l1_flush_data_range(
228 if ( n_bytes != 0 ) {
229 uint32_t adx = (uint32_t) d_addr
230 & ~ARM_CACHE_L1_DATA_LINE_MASK;
231 const uint32_t ADDR_LAST =
232 (uint32_t)( (
size_t) d_addr + n_bytes - 1 );
234 arm_cache_l1_errata_764369_handler();
236 for (; adx <= ADDR_LAST; adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT ) {
238 arm_cp15_data_cache_clean_and_invalidate_line( (
void*)adx );
241 _ARM_Data_synchronization_barrier();
246static inline void arm_cache_l1_invalidate_1_data_line(
250 arm_cp15_data_cache_invalidate_line( d_addr );
253 _ARM_Data_synchronization_barrier();
256static inline void arm_cache_l1_freeze_data(
void )
261static inline void arm_cache_l1_unfreeze_data(
void )
266static inline void arm_cache_l1_invalidate_1_instruction_line(
270 arm_cp15_instruction_cache_invalidate_line( i_addr );
273 _ARM_Data_synchronization_barrier();
276static inline void arm_cache_l1_invalidate_data_range(
281 if ( n_bytes != 0 ) {
282 uint32_t adx = (uint32_t) d_addr
283 & ~ARM_CACHE_L1_DATA_LINE_MASK;
285 (uint32_t)( (
size_t)d_addr + n_bytes -1);
287 arm_cache_l1_errata_764369_handler();
292 adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT ) {
294 arm_cp15_data_cache_invalidate_line( (
void*)adx );
297 _ARM_Data_synchronization_barrier();
301static inline void arm_cache_l1_invalidate_instruction_range(
306 if ( n_bytes != 0 ) {
307 uint32_t adx = (uint32_t) i_addr
308 & ~ARM_CACHE_L1_INSTRUCTION_LINE_MASK;
310 (uint32_t)( (
size_t)i_addr + n_bytes -1);
312 arm_cache_l1_errata_764369_handler();
317 adx += ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT ) {
319 arm_cp15_instruction_cache_invalidate_line( (
void*)adx );
322 _ARM_Data_synchronization_barrier();
326static inline void arm_cache_l1_invalidate_entire_instruction(
void )
328 uint32_t ctrl = arm_cp15_get_control();
334 arm_cp15_instruction_cache_inner_shareable_invalidate_all();
337 arm_cp15_instruction_cache_invalidate();
340 arm_cp15_instruction_cache_invalidate();
343 if ( ( ctrl & ARM_CP15_CTRL_Z ) != 0 ) {
344 #if defined(__ARM_ARCH_7A__)
345 arm_cp15_branch_predictor_inner_shareable_invalidate_all();
347 #if defined(__ARM_ARCH_6KZ__) || defined(__ARM_ARCH_7A__)
348 arm_cp15_branch_predictor_invalidate_all();
353static inline void arm_cache_l1_freeze_instruction(
void )
358static inline void arm_cache_l1_unfreeze_instruction(
void )
363static inline void arm_cache_l1_disable_data(
void )
366 arm_cache_l1_flush_entire_data();
369 arm_cp15_set_control( arm_cp15_get_control() & ~ARM_CP15_CTRL_C );
372static inline void arm_cache_l1_disable_instruction(
void )
375 _ARM_Data_synchronization_barrier();
378 arm_cache_l1_invalidate_entire_instruction();
381 arm_cp15_set_control( arm_cp15_get_control() & ~ARM_CP15_CTRL_I );
384static inline size_t arm_cache_l1_get_data_cache_size(
void )
387 uint32_t line_size = 0;
388 uint32_t associativity = 0;
389 uint32_t num_sets = 0;
391 arm_cache_l1_properties_for_level( &line_size,
392 &associativity, &num_sets,
393 ARM_CACHE_L1_CSS_ID_DATA);
395 size = (1 << line_size) * associativity * num_sets;
400static inline size_t arm_cache_l1_get_instruction_cache_size(
void )
403 uint32_t line_size = 0;
404 uint32_t associativity = 0;
405 uint32_t num_sets = 0;
407 arm_cache_l1_properties_for_level( &line_size,
408 &associativity, &num_sets,
409 ARM_CACHE_L1_CSS_ID_INSTRUCTION);
411 size = (1 << line_size) * associativity * num_sets;
ARM co-processor 15 (CP15) API.
unsigned w
Definition: tlb.h:16