35#ifndef _RTEMS_SCORE_AARCH64_SYSTEM_REGISTERS_H
36#define _RTEMS_SCORE_AARCH64_SYSTEM_REGISTERS_H
46static inline uint64_t _AArch64_Read_actlr_el1(
void )
51 "mrs %0, ACTLR_EL1" :
"=&r" ( value ) : :
"memory"
57static inline void _AArch64_Write_actlr_el1( uint64_t value )
60 "msr ACTLR_EL1, %0" : :
"r" ( value ) :
"memory"
66static inline uint64_t _AArch64_Read_actlr_el2(
void )
71 "mrs %0, ACTLR_EL2" :
"=&r" ( value ) : :
"memory"
77static inline void _AArch64_Write_actlr_el2( uint64_t value )
80 "msr ACTLR_EL2, %0" : :
"r" ( value ) :
"memory"
86static inline uint64_t _AArch64_Read_actlr_el3(
void )
91 "mrs %0, ACTLR_EL3" :
"=&r" ( value ) : :
"memory"
97static inline void _AArch64_Write_actlr_el3( uint64_t value )
100 "msr ACTLR_EL3, %0" : :
"r" ( value ) :
"memory"
106static inline uint64_t _AArch64_Read_afsr0_el1(
void )
111 "mrs %0, AFSR0_EL1" :
"=&r" ( value ) : :
"memory"
117static inline void _AArch64_Write_afsr0_el1( uint64_t value )
120 "msr AFSR0_EL1, %0" : :
"r" ( value ) :
"memory"
126static inline uint64_t _AArch64_Read_afsr0_el2(
void )
131 "mrs %0, AFSR0_EL2" :
"=&r" ( value ) : :
"memory"
137static inline void _AArch64_Write_afsr0_el2( uint64_t value )
140 "msr AFSR0_EL2, %0" : :
"r" ( value ) :
"memory"
146static inline uint64_t _AArch64_Read_afsr0_el3(
void )
151 "mrs %0, AFSR0_EL3" :
"=&r" ( value ) : :
"memory"
157static inline void _AArch64_Write_afsr0_el3( uint64_t value )
160 "msr AFSR0_EL3, %0" : :
"r" ( value ) :
"memory"
166static inline uint64_t _AArch64_Read_afsr1_el1(
void )
171 "mrs %0, AFSR1_EL1" :
"=&r" ( value ) : :
"memory"
177static inline void _AArch64_Write_afsr1_el1( uint64_t value )
180 "msr AFSR1_EL1, %0" : :
"r" ( value ) :
"memory"
186static inline uint64_t _AArch64_Read_afsr1_el2(
void )
191 "mrs %0, AFSR1_EL2" :
"=&r" ( value ) : :
"memory"
197static inline void _AArch64_Write_afsr1_el2( uint64_t value )
200 "msr AFSR1_EL2, %0" : :
"r" ( value ) :
"memory"
206static inline uint64_t _AArch64_Read_afsr1_el3(
void )
211 "mrs %0, AFSR1_EL3" :
"=&r" ( value ) : :
"memory"
217static inline void _AArch64_Write_afsr1_el3( uint64_t value )
220 "msr AFSR1_EL3, %0" : :
"r" ( value ) :
"memory"
226static inline uint64_t _AArch64_Read_aidr_el1(
void )
231 "mrs %0, AIDR_EL1" :
"=&r" ( value ) : :
"memory"
239static inline uint64_t _AArch64_Read_amair_el1(
void )
244 "mrs %0, AMAIR_EL1" :
"=&r" ( value ) : :
"memory"
250static inline void _AArch64_Write_amair_el1( uint64_t value )
253 "msr AMAIR_EL1, %0" : :
"r" ( value ) :
"memory"
259static inline uint64_t _AArch64_Read_amair_el2(
void )
264 "mrs %0, AMAIR_EL2" :
"=&r" ( value ) : :
"memory"
270static inline void _AArch64_Write_amair_el2( uint64_t value )
273 "msr AMAIR_EL2, %0" : :
"r" ( value ) :
"memory"
279static inline uint64_t _AArch64_Read_amair_el3(
void )
284 "mrs %0, AMAIR_EL3" :
"=&r" ( value ) : :
"memory"
290static inline void _AArch64_Write_amair_el3( uint64_t value )
293 "msr AMAIR_EL3, %0" : :
"r" ( value ) :
"memory"
299static inline uint64_t _AArch64_Read_apdakeyhi_el1(
void )
304 "mrs %0, APDAKEYHI_EL1" :
"=&r" ( value ) : :
"memory"
310static inline void _AArch64_Write_apdakeyhi_el1( uint64_t value )
313 "msr APDAKEYHI_EL1, %0" : :
"r" ( value ) :
"memory"
319static inline uint64_t _AArch64_Read_apdakeylo_el1(
void )
324 "mrs %0, APDAKEYLO_EL1" :
"=&r" ( value ) : :
"memory"
330static inline void _AArch64_Write_apdakeylo_el1( uint64_t value )
333 "msr APDAKEYLO_EL1, %0" : :
"r" ( value ) :
"memory"
339static inline uint64_t _AArch64_Read_apdbkeyhi_el1(
void )
344 "mrs %0, APDBKEYHI_EL1" :
"=&r" ( value ) : :
"memory"
350static inline void _AArch64_Write_apdbkeyhi_el1( uint64_t value )
353 "msr APDBKEYHI_EL1, %0" : :
"r" ( value ) :
"memory"
359static inline uint64_t _AArch64_Read_apdbkeylo_el1(
void )
364 "mrs %0, APDBKEYLO_EL1" :
"=&r" ( value ) : :
"memory"
370static inline void _AArch64_Write_apdbkeylo_el1( uint64_t value )
373 "msr APDBKEYLO_EL1, %0" : :
"r" ( value ) :
"memory"
379static inline uint64_t _AArch64_Read_apgakeyhi_el1(
void )
384 "mrs %0, APGAKEYHI_EL1" :
"=&r" ( value ) : :
"memory"
390static inline void _AArch64_Write_apgakeyhi_el1( uint64_t value )
393 "msr APGAKEYHI_EL1, %0" : :
"r" ( value ) :
"memory"
399static inline uint64_t _AArch64_Read_apgakeylo_el1(
void )
404 "mrs %0, APGAKEYLO_EL1" :
"=&r" ( value ) : :
"memory"
410static inline void _AArch64_Write_apgakeylo_el1( uint64_t value )
413 "msr APGAKEYLO_EL1, %0" : :
"r" ( value ) :
"memory"
419static inline uint64_t _AArch64_Read_apiakeyhi_el1(
void )
424 "mrs %0, APIAKEYHI_EL1" :
"=&r" ( value ) : :
"memory"
430static inline void _AArch64_Write_apiakeyhi_el1( uint64_t value )
433 "msr APIAKEYHI_EL1, %0" : :
"r" ( value ) :
"memory"
439static inline uint64_t _AArch64_Read_apiakeylo_el1(
void )
444 "mrs %0, APIAKEYLO_EL1" :
"=&r" ( value ) : :
"memory"
450static inline void _AArch64_Write_apiakeylo_el1( uint64_t value )
453 "msr APIAKEYLO_EL1, %0" : :
"r" ( value ) :
"memory"
459static inline uint64_t _AArch64_Read_apibkeyhi_el1(
void )
464 "mrs %0, APIBKEYHI_EL1" :
"=&r" ( value ) : :
"memory"
470static inline void _AArch64_Write_apibkeyhi_el1( uint64_t value )
473 "msr APIBKEYHI_EL1, %0" : :
"r" ( value ) :
"memory"
479static inline uint64_t _AArch64_Read_apibkeylo_el1(
void )
484 "mrs %0, APIBKEYLO_EL1" :
"=&r" ( value ) : :
"memory"
490static inline void _AArch64_Write_apibkeylo_el1( uint64_t value )
493 "msr APIBKEYLO_EL1, %0" : :
"r" ( value ) :
"memory"
499#define AARCH64_CCSIDR2_EL1_NUMSETS( _val ) ( ( _val ) << 0 )
500#define AARCH64_CCSIDR2_EL1_NUMSETS_SHIFT 0
501#define AARCH64_CCSIDR2_EL1_NUMSETS_MASK 0xffffffU
502#define AARCH64_CCSIDR2_EL1_NUMSETS_GET( _reg ) \
503 ( ( ( _reg ) >> 0 ) & 0xffffffU )
505static inline uint64_t _AArch64_Read_ccsidr2_el1(
void )
510 "mrs %0, CCSIDR2_EL1" :
"=&r" ( value ) : :
"memory"
518#define AARCH64_CCSIDR_EL1_LINESIZE( _val ) ( ( _val ) << 0 )
519#define AARCH64_CCSIDR_EL1_LINESIZE_SHIFT 0
520#define AARCH64_CCSIDR_EL1_LINESIZE_MASK 0x7U
521#define AARCH64_CCSIDR_EL1_LINESIZE_GET( _reg ) \
522 ( ( ( _reg ) >> 0 ) & 0x7U )
524#define AARCH64_CCSIDR_EL1_ASSOCIATIVITY_0( _val ) ( ( _val ) << 3 )
525#define AARCH64_CCSIDR_EL1_ASSOCIATIVITY_SHIFT_0 3
526#define AARCH64_CCSIDR_EL1_ASSOCIATIVITY_MASK_0 0x1ff8U
527#define AARCH64_CCSIDR_EL1_ASSOCIATIVITY_GET_0( _reg ) \
528 ( ( ( _reg ) >> 3 ) & 0x3ffU )
530#define AARCH64_CCSIDR_EL1_ASSOCIATIVITY_1( _val ) ( ( _val ) << 3 )
531#define AARCH64_CCSIDR_EL1_ASSOCIATIVITY_SHIFT_1 3
532#define AARCH64_CCSIDR_EL1_ASSOCIATIVITY_MASK_1 0xfffff8U
533#define AARCH64_CCSIDR_EL1_ASSOCIATIVITY_GET_1( _reg ) \
534 ( ( ( _reg ) >> 3 ) & 0x1fffffU )
536#define AARCH64_CCSIDR_EL1_NUMSETS_0( _val ) ( ( _val ) << 13 )
537#define AARCH64_CCSIDR_EL1_NUMSETS_SHIFT_0 13
538#define AARCH64_CCSIDR_EL1_NUMSETS_MASK_0 0xfffe000U
539#define AARCH64_CCSIDR_EL1_NUMSETS_GET_0( _reg ) \
540 ( ( ( _reg ) >> 13 ) & 0x7fffU )
542#define AARCH64_CCSIDR_EL1_NUMSETS_1( _val ) ( ( _val ) << 32 )
543#define AARCH64_CCSIDR_EL1_NUMSETS_SHIFT_1 32
544#define AARCH64_CCSIDR_EL1_NUMSETS_MASK_1 0xffffff00000000ULL
545#define AARCH64_CCSIDR_EL1_NUMSETS_GET_1( _reg ) \
546 ( ( ( _reg ) >> 32 ) & 0xffffffULL )
548static inline uint64_t _AArch64_Read_ccsidr_el1(
void )
553 "mrs %0, CCSIDR_EL1" :
"=&r" ( value ) : :
"memory"
561#define AARCH64_CLIDR_EL1_CTYPE1( _val ) ( ( _val ) << 0 )
562#define AARCH64_CLIDR_EL1_CTYPE1_SHIFT 0
563#define AARCH64_CLIDR_EL1_CTYPE1_MASK ( 0x7U << 0 )
564#define AARCH64_CLIDR_EL1_CTYPE1_GET( _reg ) \
565 ( ( ( _reg ) >> 0 ) & 0x7U )
567#define AARCH64_CLIDR_EL1_CTYPE2( _val ) ( ( _val ) << 3 )
568#define AARCH64_CLIDR_EL1_CTYPE2_SHIFT 3
569#define AARCH64_CLIDR_EL1_CTYPE2_MASK ( 0x7U << 3 )
570#define AARCH64_CLIDR_EL1_CTYPE2_GET( _reg ) \
571 ( ( ( _reg ) >> 3 ) & 0x7U )
573#define AARCH64_CLIDR_EL1_CTYPE3( _val ) ( ( _val ) << 6 )
574#define AARCH64_CLIDR_EL1_CTYPE3_SHIFT 6
575#define AARCH64_CLIDR_EL1_CTYPE3_MASK ( 0x7U << 6 )
576#define AARCH64_CLIDR_EL1_CTYPE3_GET( _reg ) \
577 ( ( ( _reg ) >> 6 ) & 0x7U )
579#define AARCH64_CLIDR_EL1_CTYPE4( _val ) ( ( _val ) << 9 )
580#define AARCH64_CLIDR_EL1_CTYPE4_SHIFT 9
581#define AARCH64_CLIDR_EL1_CTYPE4_MASK ( 0x7U << 9 )
582#define AARCH64_CLIDR_EL1_CTYPE4_GET( _reg ) \
583 ( ( ( _reg ) >> 9 ) & 0x7U )
585#define AARCH64_CLIDR_EL1_CTYPE5( _val ) ( ( _val ) << 12 )
586#define AARCH64_CLIDR_EL1_CTYPE5_SHIFT 12
587#define AARCH64_CLIDR_EL1_CTYPE5_MASK ( 0x7U << 12 )
588#define AARCH64_CLIDR_EL1_CTYPE5_GET( _reg ) \
589 ( ( ( _reg ) >> 12 ) & 0x7U )
591#define AARCH64_CLIDR_EL1_CTYPE6( _val ) ( ( _val ) << 15 )
592#define AARCH64_CLIDR_EL1_CTYPE6_SHIFT 15
593#define AARCH64_CLIDR_EL1_CTYPE6_MASK ( 0x7U << 15 )
594#define AARCH64_CLIDR_EL1_CTYPE6_GET( _reg ) \
595 ( ( ( _reg ) >> 15 ) & 0x7U )
597#define AARCH64_CLIDR_EL1_CTYPE7( _val ) ( ( _val ) << 18 )
598#define AARCH64_CLIDR_EL1_CTYPE7_SHIFT 18
599#define AARCH64_CLIDR_EL1_CTYPE7_MASK ( 0x7U << 18 )
600#define AARCH64_CLIDR_EL1_CTYPE7_GET( _reg ) \
601 ( ( ( _reg ) >> 18 ) & 0x7U )
603#define AARCH64_CLIDR_EL1_LOUIS( _val ) ( ( _val ) << 21 )
604#define AARCH64_CLIDR_EL1_LOUIS_SHIFT 21
605#define AARCH64_CLIDR_EL1_LOUIS_MASK 0xe00000U
606#define AARCH64_CLIDR_EL1_LOUIS_GET( _reg ) \
607 ( ( ( _reg ) >> 21 ) & 0x7U )
609#define AARCH64_CLIDR_EL1_LOC( _val ) ( ( _val ) << 24 )
610#define AARCH64_CLIDR_EL1_LOC_SHIFT 24
611#define AARCH64_CLIDR_EL1_LOC_MASK 0x7000000U
612#define AARCH64_CLIDR_EL1_LOC_GET( _reg ) \
613 ( ( ( _reg ) >> 24 ) & 0x7U )
615#define AARCH64_CLIDR_EL1_LOUU( _val ) ( ( _val ) << 27 )
616#define AARCH64_CLIDR_EL1_LOUU_SHIFT 27
617#define AARCH64_CLIDR_EL1_LOUU_MASK 0x38000000U
618#define AARCH64_CLIDR_EL1_LOUU_GET( _reg ) \
619 ( ( ( _reg ) >> 27 ) & 0x7U )
621#define AARCH64_CLIDR_EL1_ICB( _val ) ( ( _val ) << 30 )
622#define AARCH64_CLIDR_EL1_ICB_SHIFT 30
623#define AARCH64_CLIDR_EL1_ICB_MASK 0x1c0000000ULL
624#define AARCH64_CLIDR_EL1_ICB_GET( _reg ) \
625 ( ( ( _reg ) >> 30 ) & 0x7ULL )
627static inline uint64_t _AArch64_Read_clidr_el1(
void )
632 "mrs %0, CLIDR_EL1" :
"=&r" ( value ) : :
"memory"
640#define AARCH64_CONTEXTIDR_EL1_PROCID( _val ) ( ( _val ) << 0 )
641#define AARCH64_CONTEXTIDR_EL1_PROCID_SHIFT 0
642#define AARCH64_CONTEXTIDR_EL1_PROCID_MASK 0xffffffffU
643#define AARCH64_CONTEXTIDR_EL1_PROCID_GET( _reg ) \
644 ( ( ( _reg ) >> 0 ) & 0xffffffffU )
646static inline uint64_t _AArch64_Read_contextidr_el1(
void )
651 "mrs %0, CONTEXTIDR_EL1" :
"=&r" ( value ) : :
"memory"
657static inline void _AArch64_Write_contextidr_el1( uint64_t value )
660 "msr CONTEXTIDR_EL1, %0" : :
"r" ( value ) :
"memory"
666#define AARCH64_CONTEXTIDR_EL2_PROCID( _val ) ( ( _val ) << 0 )
667#define AARCH64_CONTEXTIDR_EL2_PROCID_SHIFT 0
668#define AARCH64_CONTEXTIDR_EL2_PROCID_MASK 0xffffffffU
669#define AARCH64_CONTEXTIDR_EL2_PROCID_GET( _reg ) \
670 ( ( ( _reg ) >> 0 ) & 0xffffffffU )
672static inline uint64_t _AArch64_Read_contextidr_el2(
void )
677 "mrs %0, CONTEXTIDR_EL2" :
"=&r" ( value ) : :
"memory"
683static inline void _AArch64_Write_contextidr_el2( uint64_t value )
686 "msr CONTEXTIDR_EL2, %0" : :
"r" ( value ) :
"memory"
692#define AARCH64_CPACR_EL1_ZEN( _val ) ( ( _val ) << 16 )
693#define AARCH64_CPACR_EL1_ZEN_SHIFT 16
694#define AARCH64_CPACR_EL1_ZEN_MASK 0x30000U
695#define AARCH64_CPACR_EL1_ZEN_GET( _reg ) \
696 ( ( ( _reg ) >> 16 ) & 0x3U )
698#define AARCH64_CPACR_EL1_FPEN( _val ) ( ( _val ) << 20 )
699#define AARCH64_CPACR_EL1_FPEN_SHIFT 20
700#define AARCH64_CPACR_EL1_FPEN_MASK 0x300000U
701#define AARCH64_CPACR_EL1_FPEN_GET( _reg ) \
702 ( ( ( _reg ) >> 20 ) & 0x3U )
704#define AARCH64_CPACR_EL1_TTA 0x10000000U
706static inline uint64_t _AArch64_Read_cpacr_el1(
void )
711 "mrs %0, CPACR_EL1" :
"=&r" ( value ) : :
"memory"
717static inline void _AArch64_Write_cpacr_el1( uint64_t value )
720 "msr CPACR_EL1, %0" : :
"r" ( value ) :
"memory"
726#define AARCH64_CPTR_EL2_TZ 0x100U
728#define AARCH64_CPTR_EL2_TFP 0x400U
730#define AARCH64_CPTR_EL2_ZEN( _val ) ( ( _val ) << 16 )
731#define AARCH64_CPTR_EL2_ZEN_SHIFT 16
732#define AARCH64_CPTR_EL2_ZEN_MASK 0x30000U
733#define AARCH64_CPTR_EL2_ZEN_GET( _reg ) \
734 ( ( ( _reg ) >> 16 ) & 0x3U )
736#define AARCH64_CPTR_EL2_TTA_0 0x100000U
738#define AARCH64_CPTR_EL2_FPEN( _val ) ( ( _val ) << 20 )
739#define AARCH64_CPTR_EL2_FPEN_SHIFT 20
740#define AARCH64_CPTR_EL2_FPEN_MASK 0x300000U
741#define AARCH64_CPTR_EL2_FPEN_GET( _reg ) \
742 ( ( ( _reg ) >> 20 ) & 0x3U )
744#define AARCH64_CPTR_EL2_TTA_1 0x10000000U
746#define AARCH64_CPTR_EL2_TAM 0x40000000U
748#define AARCH64_CPTR_EL2_TCPAC 0x80000000U
750static inline uint64_t _AArch64_Read_cptr_el2(
void )
755 "mrs %0, CPTR_EL2" :
"=&r" ( value ) : :
"memory"
761static inline void _AArch64_Write_cptr_el2( uint64_t value )
764 "msr CPTR_EL2, %0" : :
"r" ( value ) :
"memory"
770#define AARCH64_CPTR_EL3_EZ 0x100U
772#define AARCH64_CPTR_EL3_TFP 0x400U
774#define AARCH64_CPTR_EL3_TTA 0x100000U
776#define AARCH64_CPTR_EL3_TAM 0x40000000U
778#define AARCH64_CPTR_EL3_TCPAC 0x80000000U
780static inline uint64_t _AArch64_Read_cptr_el3(
void )
785 "mrs %0, CPTR_EL3" :
"=&r" ( value ) : :
"memory"
791static inline void _AArch64_Write_cptr_el3( uint64_t value )
794 "msr CPTR_EL3, %0" : :
"r" ( value ) :
"memory"
800#define AARCH64_CSSELR_EL1_IND 0x1U
802#define AARCH64_CSSELR_EL1_LEVEL( _val ) ( ( _val ) << 1 )
803#define AARCH64_CSSELR_EL1_LEVEL_SHIFT 1
804#define AARCH64_CSSELR_EL1_LEVEL_MASK 0xeU
805#define AARCH64_CSSELR_EL1_LEVEL_GET( _reg ) \
806 ( ( ( _reg ) >> 1 ) & 0x7U )
808#define AARCH64_CSSELR_EL1_TND 0x10U
810static inline uint64_t _AArch64_Read_csselr_el1(
void )
815 "mrs %0, CSSELR_EL1" :
"=&r" ( value ) : :
"memory"
821static inline void _AArch64_Write_csselr_el1( uint64_t value )
824 "msr CSSELR_EL1, %0" : :
"r" ( value ) :
"memory"
830#define AARCH64_CTR_EL0_IMINLINE( _val ) ( ( _val ) << 0 )
831#define AARCH64_CTR_EL0_IMINLINE_SHIFT 0
832#define AARCH64_CTR_EL0_IMINLINE_MASK 0xfU
833#define AARCH64_CTR_EL0_IMINLINE_GET( _reg ) \
834 ( ( ( _reg ) >> 0 ) & 0xfU )
836#define AARCH64_CTR_EL0_L1IP( _val ) ( ( _val ) << 14 )
837#define AARCH64_CTR_EL0_L1IP_SHIFT 14
838#define AARCH64_CTR_EL0_L1IP_MASK 0xc000U
839#define AARCH64_CTR_EL0_L1IP_GET( _reg ) \
840 ( ( ( _reg ) >> 14 ) & 0x3U )
842#define AARCH64_CTR_EL0_DMINLINE( _val ) ( ( _val ) << 16 )
843#define AARCH64_CTR_EL0_DMINLINE_SHIFT 16
844#define AARCH64_CTR_EL0_DMINLINE_MASK 0xf0000U
845#define AARCH64_CTR_EL0_DMINLINE_GET( _reg ) \
846 ( ( ( _reg ) >> 16 ) & 0xfU )
848#define AARCH64_CTR_EL0_ERG( _val ) ( ( _val ) << 20 )
849#define AARCH64_CTR_EL0_ERG_SHIFT 20
850#define AARCH64_CTR_EL0_ERG_MASK 0xf00000U
851#define AARCH64_CTR_EL0_ERG_GET( _reg ) \
852 ( ( ( _reg ) >> 20 ) & 0xfU )
854#define AARCH64_CTR_EL0_CWG( _val ) ( ( _val ) << 24 )
855#define AARCH64_CTR_EL0_CWG_SHIFT 24
856#define AARCH64_CTR_EL0_CWG_MASK 0xf000000U
857#define AARCH64_CTR_EL0_CWG_GET( _reg ) \
858 ( ( ( _reg ) >> 24 ) & 0xfU )
860#define AARCH64_CTR_EL0_IDC 0x10000000U
862#define AARCH64_CTR_EL0_DIC 0x20000000U
864#define AARCH64_CTR_EL0_TMINLINE( _val ) ( ( _val ) << 32 )
865#define AARCH64_CTR_EL0_TMINLINE_SHIFT 32
866#define AARCH64_CTR_EL0_TMINLINE_MASK 0x3f00000000ULL
867#define AARCH64_CTR_EL0_TMINLINE_GET( _reg ) \
868 ( ( ( _reg ) >> 32 ) & 0x3fULL )
870static inline uint64_t _AArch64_Read_ctr_el0(
void )
875 "mrs %0, CTR_EL0" :
"=&r" ( value ) : :
"memory"
883static inline uint64_t _AArch64_Read_dacr32_el2(
void )
888 "mrs %0, DACR32_EL2" :
"=&r" ( value ) : :
"memory"
894static inline void _AArch64_Write_dacr32_el2( uint64_t value )
897 "msr DACR32_EL2, %0" : :
"r" ( value ) :
"memory"
903#define AARCH64_DCZID_EL0_BS( _val ) ( ( _val ) << 0 )
904#define AARCH64_DCZID_EL0_BS_SHIFT 0
905#define AARCH64_DCZID_EL0_BS_MASK 0xfU
906#define AARCH64_DCZID_EL0_BS_GET( _reg ) \
907 ( ( ( _reg ) >> 0 ) & 0xfU )
909#define AARCH64_DCZID_EL0_DZP 0x10U
911static inline uint64_t _AArch64_Read_dczid_el0(
void )
916 "mrs %0, DCZID_EL0" :
"=&r" ( value ) : :
"memory"
924#define AARCH64_ESR_EL1_DIRECTION 0x1U
926#define AARCH64_ESR_EL1_ERETA 0x1U
928#define AARCH64_ESR_EL1_IOF 0x1U
930#define AARCH64_ESR_EL1_TI 0x1U
932#define AARCH64_ESR_EL1_BTYPE( _val ) ( ( _val ) << 0 )
933#define AARCH64_ESR_EL1_BTYPE_SHIFT 0
934#define AARCH64_ESR_EL1_BTYPE_MASK 0x3U
935#define AARCH64_ESR_EL1_BTYPE_GET( _reg ) \
936 ( ( ( _reg ) >> 0 ) & 0x3U )
938#define AARCH64_ESR_EL1_DFSC( _val ) ( ( _val ) << 0 )
939#define AARCH64_ESR_EL1_DFSC_SHIFT 0
940#define AARCH64_ESR_EL1_DFSC_MASK 0x3fU
941#define AARCH64_ESR_EL1_DFSC_GET( _reg ) \
942 ( ( ( _reg ) >> 0 ) & 0x3fU )
944#define AARCH64_ESR_EL1_IFSC( _val ) ( ( _val ) << 0 )
945#define AARCH64_ESR_EL1_IFSC_SHIFT 0
946#define AARCH64_ESR_EL1_IFSC_MASK 0x3fU
947#define AARCH64_ESR_EL1_IFSC_GET( _reg ) \
948 ( ( ( _reg ) >> 0 ) & 0x3fU )
950#define AARCH64_ESR_EL1_COMMENT( _val ) ( ( _val ) << 0 )
951#define AARCH64_ESR_EL1_COMMENT_SHIFT 0
952#define AARCH64_ESR_EL1_COMMENT_MASK 0xffffU
953#define AARCH64_ESR_EL1_COMMENT_GET( _reg ) \
954 ( ( ( _reg ) >> 0 ) & 0xffffU )
956#define AARCH64_ESR_EL1_IMM16( _val ) ( ( _val ) << 0 )
957#define AARCH64_ESR_EL1_IMM16_SHIFT 0
958#define AARCH64_ESR_EL1_IMM16_MASK 0xffffU
959#define AARCH64_ESR_EL1_IMM16_GET( _reg ) \
960 ( ( ( _reg ) >> 0 ) & 0xffffU )
962#define AARCH64_ESR_EL1_ISS( _val ) ( ( _val ) << 0 )
963#define AARCH64_ESR_EL1_ISS_SHIFT 0
964#define AARCH64_ESR_EL1_ISS_MASK 0x1ffffffU
965#define AARCH64_ESR_EL1_ISS_GET( _reg ) \
966 ( ( ( _reg ) >> 0 ) & 0x1ffffffU )
968#define AARCH64_ESR_EL1_DZF 0x2U
970#define AARCH64_ESR_EL1_ERET 0x2U
972#define AARCH64_ESR_EL1_AM( _val ) ( ( _val ) << 1 )
973#define AARCH64_ESR_EL1_AM_SHIFT 1
974#define AARCH64_ESR_EL1_AM_MASK 0xeU
975#define AARCH64_ESR_EL1_AM_GET( _reg ) \
976 ( ( ( _reg ) >> 1 ) & 0x7U )
978#define AARCH64_ESR_EL1_CRM( _val ) ( ( _val ) << 1 )
979#define AARCH64_ESR_EL1_CRM_SHIFT 1
980#define AARCH64_ESR_EL1_CRM_MASK 0x1eU
981#define AARCH64_ESR_EL1_CRM_GET( _reg ) \
982 ( ( ( _reg ) >> 1 ) & 0xfU )
984#define AARCH64_ESR_EL1_OFF 0x4U
986#define AARCH64_ESR_EL1_UFF 0x8U
988#define AARCH64_ESR_EL1_IXF 0x10U
990#define AARCH64_ESR_EL1_OFFSET 0x10U
992#define AARCH64_ESR_EL1_RN( _val ) ( ( _val ) << 5 )
993#define AARCH64_ESR_EL1_RN_SHIFT 5
994#define AARCH64_ESR_EL1_RN_MASK 0x3e0U
995#define AARCH64_ESR_EL1_RN_GET( _reg ) \
996 ( ( ( _reg ) >> 5 ) & 0x1fU )
998#define AARCH64_ESR_EL1_RT( _val ) ( ( _val ) << 5 )
999#define AARCH64_ESR_EL1_RT_SHIFT 5
1000#define AARCH64_ESR_EL1_RT_MASK 0x3e0U
1001#define AARCH64_ESR_EL1_RT_GET( _reg ) \
1002 ( ( ( _reg ) >> 5 ) & 0x1fU )
1004#define AARCH64_ESR_EL1_EX 0x40U
1006#define AARCH64_ESR_EL1_WNR 0x40U
1008#define AARCH64_ESR_EL1_IDF 0x80U
1010#define AARCH64_ESR_EL1_S1PTW 0x80U
1012#define AARCH64_ESR_EL1_CM 0x100U
1014#define AARCH64_ESR_EL1_VECITR( _val ) ( ( _val ) << 8 )
1015#define AARCH64_ESR_EL1_VECITR_SHIFT 8
1016#define AARCH64_ESR_EL1_VECITR_MASK 0x700U
1017#define AARCH64_ESR_EL1_VECITR_GET( _reg ) \
1018 ( ( ( _reg ) >> 8 ) & 0x7U )
1020#define AARCH64_ESR_EL1_EA 0x200U
1022#define AARCH64_ESR_EL1_FNV 0x400U
1024#define AARCH64_ESR_EL1_AET( _val ) ( ( _val ) << 10 )
1025#define AARCH64_ESR_EL1_AET_SHIFT 10
1026#define AARCH64_ESR_EL1_AET_MASK 0x1c00U
1027#define AARCH64_ESR_EL1_AET_GET( _reg ) \
1028 ( ( ( _reg ) >> 10 ) & 0x7U )
1030#define AARCH64_ESR_EL1_CRN( _val ) ( ( _val ) << 10 )
1031#define AARCH64_ESR_EL1_CRN_SHIFT 10
1032#define AARCH64_ESR_EL1_CRN_MASK 0x3c00U
1033#define AARCH64_ESR_EL1_CRN_GET( _reg ) \
1034 ( ( ( _reg ) >> 10 ) & 0xfU )
1036#define AARCH64_ESR_EL1_RT2( _val ) ( ( _val ) << 10 )
1037#define AARCH64_ESR_EL1_RT2_SHIFT 10
1038#define AARCH64_ESR_EL1_RT2_MASK 0x7c00U
1039#define AARCH64_ESR_EL1_RT2_GET( _reg ) \
1040 ( ( ( _reg ) >> 10 ) & 0x1fU )
1042#define AARCH64_ESR_EL1_SET( _val ) ( ( _val ) << 11 )
1043#define AARCH64_ESR_EL1_SET_SHIFT 11
1044#define AARCH64_ESR_EL1_SET_MASK 0x1800U
1045#define AARCH64_ESR_EL1_SET_GET( _reg ) \
1046 ( ( ( _reg ) >> 11 ) & 0x3U )
1048#define AARCH64_ESR_EL1_IMM8( _val ) ( ( _val ) << 12 )
1049#define AARCH64_ESR_EL1_IMM8_SHIFT 12
1050#define AARCH64_ESR_EL1_IMM8_MASK 0xff000U
1051#define AARCH64_ESR_EL1_IMM8_GET( _reg ) \
1052 ( ( ( _reg ) >> 12 ) & 0xffU )
1054#define AARCH64_ESR_EL1_IESB 0x2000U
1056#define AARCH64_ESR_EL1_VNCR 0x2000U
1058#define AARCH64_ESR_EL1_AR 0x4000U
1060#define AARCH64_ESR_EL1_OP1( _val ) ( ( _val ) << 14 )
1061#define AARCH64_ESR_EL1_OP1_SHIFT 14
1062#define AARCH64_ESR_EL1_OP1_MASK 0x1c000U
1063#define AARCH64_ESR_EL1_OP1_GET( _reg ) \
1064 ( ( ( _reg ) >> 14 ) & 0x7U )
1066#define AARCH64_ESR_EL1_OPC1_0( _val ) ( ( _val ) << 14 )
1067#define AARCH64_ESR_EL1_OPC1_SHIFT_0 14
1068#define AARCH64_ESR_EL1_OPC1_MASK_0 0x1c000U
1069#define AARCH64_ESR_EL1_OPC1_GET_0( _reg ) \
1070 ( ( ( _reg ) >> 14 ) & 0x7U )
1072#define AARCH64_ESR_EL1_SF 0x8000U
1074#define AARCH64_ESR_EL1_OPC1_1( _val ) ( ( _val ) << 16 )
1075#define AARCH64_ESR_EL1_OPC1_SHIFT_1 16
1076#define AARCH64_ESR_EL1_OPC1_MASK_1 0xf0000U
1077#define AARCH64_ESR_EL1_OPC1_GET_1( _reg ) \
1078 ( ( ( _reg ) >> 16 ) & 0xfU )
1080#define AARCH64_ESR_EL1_SRT( _val ) ( ( _val ) << 16 )
1081#define AARCH64_ESR_EL1_SRT_SHIFT 16
1082#define AARCH64_ESR_EL1_SRT_MASK 0x1f0000U
1083#define AARCH64_ESR_EL1_SRT_GET( _reg ) \
1084 ( ( ( _reg ) >> 16 ) & 0x1fU )
1086#define AARCH64_ESR_EL1_OP2( _val ) ( ( _val ) << 17 )
1087#define AARCH64_ESR_EL1_OP2_SHIFT 17
1088#define AARCH64_ESR_EL1_OP2_MASK 0xe0000U
1089#define AARCH64_ESR_EL1_OP2_GET( _reg ) \
1090 ( ( ( _reg ) >> 17 ) & 0x7U )
1092#define AARCH64_ESR_EL1_OPC2( _val ) ( ( _val ) << 17 )
1093#define AARCH64_ESR_EL1_OPC2_SHIFT 17
1094#define AARCH64_ESR_EL1_OPC2_MASK 0xe0000U
1095#define AARCH64_ESR_EL1_OPC2_GET( _reg ) \
1096 ( ( ( _reg ) >> 17 ) & 0x7U )
1098#define AARCH64_ESR_EL1_CCKNOWNPASS 0x80000U
1100#define AARCH64_ESR_EL1_OP0( _val ) ( ( _val ) << 20 )
1101#define AARCH64_ESR_EL1_OP0_SHIFT 20
1102#define AARCH64_ESR_EL1_OP0_MASK 0x300000U
1103#define AARCH64_ESR_EL1_OP0_GET( _reg ) \
1104 ( ( ( _reg ) >> 20 ) & 0x3U )
1106#define AARCH64_ESR_EL1_COND( _val ) ( ( _val ) << 20 )
1107#define AARCH64_ESR_EL1_COND_SHIFT 20
1108#define AARCH64_ESR_EL1_COND_MASK 0xf00000U
1109#define AARCH64_ESR_EL1_COND_GET( _reg ) \
1110 ( ( ( _reg ) >> 20 ) & 0xfU )
1112#define AARCH64_ESR_EL1_SSE 0x200000U
1114#define AARCH64_ESR_EL1_SAS( _val ) ( ( _val ) << 22 )
1115#define AARCH64_ESR_EL1_SAS_SHIFT 22
1116#define AARCH64_ESR_EL1_SAS_MASK 0xc00000U
1117#define AARCH64_ESR_EL1_SAS_GET( _reg ) \
1118 ( ( ( _reg ) >> 22 ) & 0x3U )
1120#define AARCH64_ESR_EL1_TFV 0x800000U
1122#define AARCH64_ESR_EL1_CV 0x1000000U
1124#define AARCH64_ESR_EL1_IDS 0x1000000U
1126#define AARCH64_ESR_EL1_ISV 0x1000000U
1128#define AARCH64_ESR_EL1_IL 0x2000000U
1130#define AARCH64_ESR_EL1_EC( _val ) ( ( _val ) << 26 )
1131#define AARCH64_ESR_EL1_EC_SHIFT 26
1132#define AARCH64_ESR_EL1_EC_MASK 0xfc000000U
1133#define AARCH64_ESR_EL1_EC_GET( _reg ) \
1134 ( ( ( _reg ) >> 26 ) & 0x3fU )
1136static inline uint64_t _AArch64_Read_esr_el1(
void )
1141 "mrs %0, ESR_EL1" :
"=&r" ( value ) : :
"memory"
1147static inline void _AArch64_Write_esr_el1( uint64_t value )
1150 "msr ESR_EL1, %0" : :
"r" ( value ) :
"memory"
1156#define AARCH64_ESR_EL2_DIRECTION 0x1U
1158#define AARCH64_ESR_EL2_ERETA 0x1U
1160#define AARCH64_ESR_EL2_IOF 0x1U
1162#define AARCH64_ESR_EL2_TI 0x1U
1164#define AARCH64_ESR_EL2_BTYPE( _val ) ( ( _val ) << 0 )
1165#define AARCH64_ESR_EL2_BTYPE_SHIFT 0
1166#define AARCH64_ESR_EL2_BTYPE_MASK 0x3U
1167#define AARCH64_ESR_EL2_BTYPE_GET( _reg ) \
1168 ( ( ( _reg ) >> 0 ) & 0x3U )
1170#define AARCH64_ESR_EL2_DFSC( _val ) ( ( _val ) << 0 )
1171#define AARCH64_ESR_EL2_DFSC_SHIFT 0
1172#define AARCH64_ESR_EL2_DFSC_MASK 0x3fU
1173#define AARCH64_ESR_EL2_DFSC_GET( _reg ) \
1174 ( ( ( _reg ) >> 0 ) & 0x3fU )
1176#define AARCH64_ESR_EL2_IFSC( _val ) ( ( _val ) << 0 )
1177#define AARCH64_ESR_EL2_IFSC_SHIFT 0
1178#define AARCH64_ESR_EL2_IFSC_MASK 0x3fU
1179#define AARCH64_ESR_EL2_IFSC_GET( _reg ) \
1180 ( ( ( _reg ) >> 0 ) & 0x3fU )
1182#define AARCH64_ESR_EL2_COMMENT( _val ) ( ( _val ) << 0 )
1183#define AARCH64_ESR_EL2_COMMENT_SHIFT 0
1184#define AARCH64_ESR_EL2_COMMENT_MASK 0xffffU
1185#define AARCH64_ESR_EL2_COMMENT_GET( _reg ) \
1186 ( ( ( _reg ) >> 0 ) & 0xffffU )
1188#define AARCH64_ESR_EL2_IMM16( _val ) ( ( _val ) << 0 )
1189#define AARCH64_ESR_EL2_IMM16_SHIFT 0
1190#define AARCH64_ESR_EL2_IMM16_MASK 0xffffU
1191#define AARCH64_ESR_EL2_IMM16_GET( _reg ) \
1192 ( ( ( _reg ) >> 0 ) & 0xffffU )
1194#define AARCH64_ESR_EL2_ISS( _val ) ( ( _val ) << 0 )
1195#define AARCH64_ESR_EL2_ISS_SHIFT 0
1196#define AARCH64_ESR_EL2_ISS_MASK 0x1ffffffU
1197#define AARCH64_ESR_EL2_ISS_GET( _reg ) \
1198 ( ( ( _reg ) >> 0 ) & 0x1ffffffU )
1200#define AARCH64_ESR_EL2_DZF 0x2U
1202#define AARCH64_ESR_EL2_ERET 0x2U
1204#define AARCH64_ESR_EL2_AM( _val ) ( ( _val ) << 1 )
1205#define AARCH64_ESR_EL2_AM_SHIFT 1
1206#define AARCH64_ESR_EL2_AM_MASK 0xeU
1207#define AARCH64_ESR_EL2_AM_GET( _reg ) \
1208 ( ( ( _reg ) >> 1 ) & 0x7U )
1210#define AARCH64_ESR_EL2_CRM( _val ) ( ( _val ) << 1 )
1211#define AARCH64_ESR_EL2_CRM_SHIFT 1
1212#define AARCH64_ESR_EL2_CRM_MASK 0x1eU
1213#define AARCH64_ESR_EL2_CRM_GET( _reg ) \
1214 ( ( ( _reg ) >> 1 ) & 0xfU )
1216#define AARCH64_ESR_EL2_OFF 0x4U
1218#define AARCH64_ESR_EL2_UFF 0x8U
1220#define AARCH64_ESR_EL2_IXF 0x10U
1222#define AARCH64_ESR_EL2_OFFSET 0x10U
1224#define AARCH64_ESR_EL2_RN( _val ) ( ( _val ) << 5 )
1225#define AARCH64_ESR_EL2_RN_SHIFT 5
1226#define AARCH64_ESR_EL2_RN_MASK 0x3e0U
1227#define AARCH64_ESR_EL2_RN_GET( _reg ) \
1228 ( ( ( _reg ) >> 5 ) & 0x1fU )
1230#define AARCH64_ESR_EL2_RT( _val ) ( ( _val ) << 5 )
1231#define AARCH64_ESR_EL2_RT_SHIFT 5
1232#define AARCH64_ESR_EL2_RT_MASK 0x3e0U
1233#define AARCH64_ESR_EL2_RT_GET( _reg ) \
1234 ( ( ( _reg ) >> 5 ) & 0x1fU )
1236#define AARCH64_ESR_EL2_EX 0x40U
1238#define AARCH64_ESR_EL2_WNR 0x40U
1240#define AARCH64_ESR_EL2_IDF 0x80U
1242#define AARCH64_ESR_EL2_S1PTW 0x80U
1244#define AARCH64_ESR_EL2_CM 0x100U
1246#define AARCH64_ESR_EL2_VECITR( _val ) ( ( _val ) << 8 )
1247#define AARCH64_ESR_EL2_VECITR_SHIFT 8
1248#define AARCH64_ESR_EL2_VECITR_MASK 0x700U
1249#define AARCH64_ESR_EL2_VECITR_GET( _reg ) \
1250 ( ( ( _reg ) >> 8 ) & 0x7U )
1252#define AARCH64_ESR_EL2_EA 0x200U
1254#define AARCH64_ESR_EL2_FNV 0x400U
1256#define AARCH64_ESR_EL2_AET( _val ) ( ( _val ) << 10 )
1257#define AARCH64_ESR_EL2_AET_SHIFT 10
1258#define AARCH64_ESR_EL2_AET_MASK 0x1c00U
1259#define AARCH64_ESR_EL2_AET_GET( _reg ) \
1260 ( ( ( _reg ) >> 10 ) & 0x7U )
1262#define AARCH64_ESR_EL2_CRN( _val ) ( ( _val ) << 10 )
1263#define AARCH64_ESR_EL2_CRN_SHIFT 10
1264#define AARCH64_ESR_EL2_CRN_MASK 0x3c00U
1265#define AARCH64_ESR_EL2_CRN_GET( _reg ) \
1266 ( ( ( _reg ) >> 10 ) & 0xfU )
1268#define AARCH64_ESR_EL2_RT2( _val ) ( ( _val ) << 10 )
1269#define AARCH64_ESR_EL2_RT2_SHIFT 10
1270#define AARCH64_ESR_EL2_RT2_MASK 0x7c00U
1271#define AARCH64_ESR_EL2_RT2_GET( _reg ) \
1272 ( ( ( _reg ) >> 10 ) & 0x1fU )
1274#define AARCH64_ESR_EL2_SET( _val ) ( ( _val ) << 11 )
1275#define AARCH64_ESR_EL2_SET_SHIFT 11
1276#define AARCH64_ESR_EL2_SET_MASK 0x1800U
1277#define AARCH64_ESR_EL2_SET_GET( _reg ) \
1278 ( ( ( _reg ) >> 11 ) & 0x3U )
1280#define AARCH64_ESR_EL2_IMM8( _val ) ( ( _val ) << 12 )
1281#define AARCH64_ESR_EL2_IMM8_SHIFT 12
1282#define AARCH64_ESR_EL2_IMM8_MASK 0xff000U
1283#define AARCH64_ESR_EL2_IMM8_GET( _reg ) \
1284 ( ( ( _reg ) >> 12 ) & 0xffU )
1286#define AARCH64_ESR_EL2_IESB 0x2000U
1288#define AARCH64_ESR_EL2_VNCR 0x2000U
1290#define AARCH64_ESR_EL2_AR 0x4000U
1292#define AARCH64_ESR_EL2_OP1( _val ) ( ( _val ) << 14 )
1293#define AARCH64_ESR_EL2_OP1_SHIFT 14
1294#define AARCH64_ESR_EL2_OP1_MASK 0x1c000U
1295#define AARCH64_ESR_EL2_OP1_GET( _reg ) \
1296 ( ( ( _reg ) >> 14 ) & 0x7U )
1298#define AARCH64_ESR_EL2_OPC1_0( _val ) ( ( _val ) << 14 )
1299#define AARCH64_ESR_EL2_OPC1_SHIFT_0 14
1300#define AARCH64_ESR_EL2_OPC1_MASK_0 0x1c000U
1301#define AARCH64_ESR_EL2_OPC1_GET_0( _reg ) \
1302 ( ( ( _reg ) >> 14 ) & 0x7U )
1304#define AARCH64_ESR_EL2_SF 0x8000U
1306#define AARCH64_ESR_EL2_OPC1_1( _val ) ( ( _val ) << 16 )
1307#define AARCH64_ESR_EL2_OPC1_SHIFT_1 16
1308#define AARCH64_ESR_EL2_OPC1_MASK_1 0xf0000U
1309#define AARCH64_ESR_EL2_OPC1_GET_1( _reg ) \
1310 ( ( ( _reg ) >> 16 ) & 0xfU )
1312#define AARCH64_ESR_EL2_SRT( _val ) ( ( _val ) << 16 )
1313#define AARCH64_ESR_EL2_SRT_SHIFT 16
1314#define AARCH64_ESR_EL2_SRT_MASK 0x1f0000U
1315#define AARCH64_ESR_EL2_SRT_GET( _reg ) \
1316 ( ( ( _reg ) >> 16 ) & 0x1fU )
1318#define AARCH64_ESR_EL2_OP2( _val ) ( ( _val ) << 17 )
1319#define AARCH64_ESR_EL2_OP2_SHIFT 17
1320#define AARCH64_ESR_EL2_OP2_MASK 0xe0000U
1321#define AARCH64_ESR_EL2_OP2_GET( _reg ) \
1322 ( ( ( _reg ) >> 17 ) & 0x7U )
1324#define AARCH64_ESR_EL2_OPC2( _val ) ( ( _val ) << 17 )
1325#define AARCH64_ESR_EL2_OPC2_SHIFT 17
1326#define AARCH64_ESR_EL2_OPC2_MASK 0xe0000U
1327#define AARCH64_ESR_EL2_OPC2_GET( _reg ) \
1328 ( ( ( _reg ) >> 17 ) & 0x7U )
1330#define AARCH64_ESR_EL2_CCKNOWNPASS 0x80000U
1332#define AARCH64_ESR_EL2_OP0( _val ) ( ( _val ) << 20 )
1333#define AARCH64_ESR_EL2_OP0_SHIFT 20
1334#define AARCH64_ESR_EL2_OP0_MASK 0x300000U
1335#define AARCH64_ESR_EL2_OP0_GET( _reg ) \
1336 ( ( ( _reg ) >> 20 ) & 0x3U )
1338#define AARCH64_ESR_EL2_COND( _val ) ( ( _val ) << 20 )
1339#define AARCH64_ESR_EL2_COND_SHIFT 20
1340#define AARCH64_ESR_EL2_COND_MASK 0xf00000U
1341#define AARCH64_ESR_EL2_COND_GET( _reg ) \
1342 ( ( ( _reg ) >> 20 ) & 0xfU )
1344#define AARCH64_ESR_EL2_SSE 0x200000U
1346#define AARCH64_ESR_EL2_SAS( _val ) ( ( _val ) << 22 )
1347#define AARCH64_ESR_EL2_SAS_SHIFT 22
1348#define AARCH64_ESR_EL2_SAS_MASK 0xc00000U
1349#define AARCH64_ESR_EL2_SAS_GET( _reg ) \
1350 ( ( ( _reg ) >> 22 ) & 0x3U )
1352#define AARCH64_ESR_EL2_TFV 0x800000U
1354#define AARCH64_ESR_EL2_CV 0x1000000U
1356#define AARCH64_ESR_EL2_IDS 0x1000000U
1358#define AARCH64_ESR_EL2_ISV 0x1000000U
1360#define AARCH64_ESR_EL2_IL 0x2000000U
1362#define AARCH64_ESR_EL2_EC( _val ) ( ( _val ) << 26 )
1363#define AARCH64_ESR_EL2_EC_SHIFT 26
1364#define AARCH64_ESR_EL2_EC_MASK 0xfc000000U
1365#define AARCH64_ESR_EL2_EC_GET( _reg ) \
1366 ( ( ( _reg ) >> 26 ) & 0x3fU )
1368static inline uint64_t _AArch64_Read_esr_el2(
void )
1373 "mrs %0, ESR_EL2" :
"=&r" ( value ) : :
"memory"
1379static inline void _AArch64_Write_esr_el2( uint64_t value )
1382 "msr ESR_EL2, %0" : :
"r" ( value ) :
"memory"
1388#define AARCH64_ESR_EL3_DIRECTION 0x1U
1390#define AARCH64_ESR_EL3_ERETA 0x1U
1392#define AARCH64_ESR_EL3_IOF 0x1U
1394#define AARCH64_ESR_EL3_TI 0x1U
1396#define AARCH64_ESR_EL3_BTYPE( _val ) ( ( _val ) << 0 )
1397#define AARCH64_ESR_EL3_BTYPE_SHIFT 0
1398#define AARCH64_ESR_EL3_BTYPE_MASK 0x3U
1399#define AARCH64_ESR_EL3_BTYPE_GET( _reg ) \
1400 ( ( ( _reg ) >> 0 ) & 0x3U )
1402#define AARCH64_ESR_EL3_DFSC( _val ) ( ( _val ) << 0 )
1403#define AARCH64_ESR_EL3_DFSC_SHIFT 0
1404#define AARCH64_ESR_EL3_DFSC_MASK 0x3fU
1405#define AARCH64_ESR_EL3_DFSC_GET( _reg ) \
1406 ( ( ( _reg ) >> 0 ) & 0x3fU )
1408#define AARCH64_ESR_EL3_IFSC( _val ) ( ( _val ) << 0 )
1409#define AARCH64_ESR_EL3_IFSC_SHIFT 0
1410#define AARCH64_ESR_EL3_IFSC_MASK 0x3fU
1411#define AARCH64_ESR_EL3_IFSC_GET( _reg ) \
1412 ( ( ( _reg ) >> 0 ) & 0x3fU )
1414#define AARCH64_ESR_EL3_COMMENT( _val ) ( ( _val ) << 0 )
1415#define AARCH64_ESR_EL3_COMMENT_SHIFT 0
1416#define AARCH64_ESR_EL3_COMMENT_MASK 0xffffU
1417#define AARCH64_ESR_EL3_COMMENT_GET( _reg ) \
1418 ( ( ( _reg ) >> 0 ) & 0xffffU )
1420#define AARCH64_ESR_EL3_IMM16( _val ) ( ( _val ) << 0 )
1421#define AARCH64_ESR_EL3_IMM16_SHIFT 0
1422#define AARCH64_ESR_EL3_IMM16_MASK 0xffffU
1423#define AARCH64_ESR_EL3_IMM16_GET( _reg ) \
1424 ( ( ( _reg ) >> 0 ) & 0xffffU )
1426#define AARCH64_ESR_EL3_ISS( _val ) ( ( _val ) << 0 )
1427#define AARCH64_ESR_EL3_ISS_SHIFT 0
1428#define AARCH64_ESR_EL3_ISS_MASK 0x1ffffffU
1429#define AARCH64_ESR_EL3_ISS_GET( _reg ) \
1430 ( ( ( _reg ) >> 0 ) & 0x1ffffffU )
1432#define AARCH64_ESR_EL3_DZF 0x2U
1434#define AARCH64_ESR_EL3_ERET 0x2U
1436#define AARCH64_ESR_EL3_AM( _val ) ( ( _val ) << 1 )
1437#define AARCH64_ESR_EL3_AM_SHIFT 1
1438#define AARCH64_ESR_EL3_AM_MASK 0xeU
1439#define AARCH64_ESR_EL3_AM_GET( _reg ) \
1440 ( ( ( _reg ) >> 1 ) & 0x7U )
1442#define AARCH64_ESR_EL3_CRM( _val ) ( ( _val ) << 1 )
1443#define AARCH64_ESR_EL3_CRM_SHIFT 1
1444#define AARCH64_ESR_EL3_CRM_MASK 0x1eU
1445#define AARCH64_ESR_EL3_CRM_GET( _reg ) \
1446 ( ( ( _reg ) >> 1 ) & 0xfU )
1448#define AARCH64_ESR_EL3_OFF 0x4U
1450#define AARCH64_ESR_EL3_UFF 0x8U
1452#define AARCH64_ESR_EL3_IXF 0x10U
1454#define AARCH64_ESR_EL3_OFFSET 0x10U
1456#define AARCH64_ESR_EL3_RN( _val ) ( ( _val ) << 5 )
1457#define AARCH64_ESR_EL3_RN_SHIFT 5
1458#define AARCH64_ESR_EL3_RN_MASK 0x3e0U
1459#define AARCH64_ESR_EL3_RN_GET( _reg ) \
1460 ( ( ( _reg ) >> 5 ) & 0x1fU )
1462#define AARCH64_ESR_EL3_RT( _val ) ( ( _val ) << 5 )
1463#define AARCH64_ESR_EL3_RT_SHIFT 5
1464#define AARCH64_ESR_EL3_RT_MASK 0x3e0U
1465#define AARCH64_ESR_EL3_RT_GET( _reg ) \
1466 ( ( ( _reg ) >> 5 ) & 0x1fU )
1468#define AARCH64_ESR_EL3_EX 0x40U
1470#define AARCH64_ESR_EL3_WNR 0x40U
1472#define AARCH64_ESR_EL3_IDF 0x80U
1474#define AARCH64_ESR_EL3_S1PTW 0x80U
1476#define AARCH64_ESR_EL3_CM 0x100U
1478#define AARCH64_ESR_EL3_VECITR( _val ) ( ( _val ) << 8 )
1479#define AARCH64_ESR_EL3_VECITR_SHIFT 8
1480#define AARCH64_ESR_EL3_VECITR_MASK 0x700U
1481#define AARCH64_ESR_EL3_VECITR_GET( _reg ) \
1482 ( ( ( _reg ) >> 8 ) & 0x7U )
1484#define AARCH64_ESR_EL3_EA 0x200U
1486#define AARCH64_ESR_EL3_FNV 0x400U
1488#define AARCH64_ESR_EL3_AET( _val ) ( ( _val ) << 10 )
1489#define AARCH64_ESR_EL3_AET_SHIFT 10
1490#define AARCH64_ESR_EL3_AET_MASK 0x1c00U
1491#define AARCH64_ESR_EL3_AET_GET( _reg ) \
1492 ( ( ( _reg ) >> 10 ) & 0x7U )
1494#define AARCH64_ESR_EL3_CRN( _val ) ( ( _val ) << 10 )
1495#define AARCH64_ESR_EL3_CRN_SHIFT 10
1496#define AARCH64_ESR_EL3_CRN_MASK 0x3c00U
1497#define AARCH64_ESR_EL3_CRN_GET( _reg ) \
1498 ( ( ( _reg ) >> 10 ) & 0xfU )
1500#define AARCH64_ESR_EL3_RT2( _val ) ( ( _val ) << 10 )
1501#define AARCH64_ESR_EL3_RT2_SHIFT 10
1502#define AARCH64_ESR_EL3_RT2_MASK 0x7c00U
1503#define AARCH64_ESR_EL3_RT2_GET( _reg ) \
1504 ( ( ( _reg ) >> 10 ) & 0x1fU )
1506#define AARCH64_ESR_EL3_SET( _val ) ( ( _val ) << 11 )
1507#define AARCH64_ESR_EL3_SET_SHIFT 11
1508#define AARCH64_ESR_EL3_SET_MASK 0x1800U
1509#define AARCH64_ESR_EL3_SET_GET( _reg ) \
1510 ( ( ( _reg ) >> 11 ) & 0x3U )
1512#define AARCH64_ESR_EL3_IMM8( _val ) ( ( _val ) << 12 )
1513#define AARCH64_ESR_EL3_IMM8_SHIFT 12
1514#define AARCH64_ESR_EL3_IMM8_MASK 0xff000U
1515#define AARCH64_ESR_EL3_IMM8_GET( _reg ) \
1516 ( ( ( _reg ) >> 12 ) & 0xffU )
1518#define AARCH64_ESR_EL3_IESB 0x2000U
1520#define AARCH64_ESR_EL3_VNCR 0x2000U
1522#define AARCH64_ESR_EL3_AR 0x4000U
1524#define AARCH64_ESR_EL3_OP1( _val ) ( ( _val ) << 14 )
1525#define AARCH64_ESR_EL3_OP1_SHIFT 14
1526#define AARCH64_ESR_EL3_OP1_MASK 0x1c000U
1527#define AARCH64_ESR_EL3_OP1_GET( _reg ) \
1528 ( ( ( _reg ) >> 14 ) & 0x7U )
1530#define AARCH64_ESR_EL3_OPC1_0( _val ) ( ( _val ) << 14 )
1531#define AARCH64_ESR_EL3_OPC1_SHIFT_0 14
1532#define AARCH64_ESR_EL3_OPC1_MASK_0 0x1c000U
1533#define AARCH64_ESR_EL3_OPC1_GET_0( _reg ) \
1534 ( ( ( _reg ) >> 14 ) & 0x7U )
1536#define AARCH64_ESR_EL3_SF 0x8000U
1538#define AARCH64_ESR_EL3_OPC1_1( _val ) ( ( _val ) << 16 )
1539#define AARCH64_ESR_EL3_OPC1_SHIFT_1 16
1540#define AARCH64_ESR_EL3_OPC1_MASK_1 0xf0000U
1541#define AARCH64_ESR_EL3_OPC1_GET_1( _reg ) \
1542 ( ( ( _reg ) >> 16 ) & 0xfU )
1544#define AARCH64_ESR_EL3_SRT( _val ) ( ( _val ) << 16 )
1545#define AARCH64_ESR_EL3_SRT_SHIFT 16
1546#define AARCH64_ESR_EL3_SRT_MASK 0x1f0000U
1547#define AARCH64_ESR_EL3_SRT_GET( _reg ) \
1548 ( ( ( _reg ) >> 16 ) & 0x1fU )
1550#define AARCH64_ESR_EL3_OP2( _val ) ( ( _val ) << 17 )
1551#define AARCH64_ESR_EL3_OP2_SHIFT 17
1552#define AARCH64_ESR_EL3_OP2_MASK 0xe0000U
1553#define AARCH64_ESR_EL3_OP2_GET( _reg ) \
1554 ( ( ( _reg ) >> 17 ) & 0x7U )
1556#define AARCH64_ESR_EL3_OPC2( _val ) ( ( _val ) << 17 )
1557#define AARCH64_ESR_EL3_OPC2_SHIFT 17
1558#define AARCH64_ESR_EL3_OPC2_MASK 0xe0000U
1559#define AARCH64_ESR_EL3_OPC2_GET( _reg ) \
1560 ( ( ( _reg ) >> 17 ) & 0x7U )
1562#define AARCH64_ESR_EL3_CCKNOWNPASS 0x80000U
1564#define AARCH64_ESR_EL3_OP0( _val ) ( ( _val ) << 20 )
1565#define AARCH64_ESR_EL3_OP0_SHIFT 20
1566#define AARCH64_ESR_EL3_OP0_MASK 0x300000U
1567#define AARCH64_ESR_EL3_OP0_GET( _reg ) \
1568 ( ( ( _reg ) >> 20 ) & 0x3U )
1570#define AARCH64_ESR_EL3_COND( _val ) ( ( _val ) << 20 )
1571#define AARCH64_ESR_EL3_COND_SHIFT 20
1572#define AARCH64_ESR_EL3_COND_MASK 0xf00000U
1573#define AARCH64_ESR_EL3_COND_GET( _reg ) \
1574 ( ( ( _reg ) >> 20 ) & 0xfU )
1576#define AARCH64_ESR_EL3_SSE 0x200000U
1578#define AARCH64_ESR_EL3_SAS( _val ) ( ( _val ) << 22 )
1579#define AARCH64_ESR_EL3_SAS_SHIFT 22
1580#define AARCH64_ESR_EL3_SAS_MASK 0xc00000U
1581#define AARCH64_ESR_EL3_SAS_GET( _reg ) \
1582 ( ( ( _reg ) >> 22 ) & 0x3U )
1584#define AARCH64_ESR_EL3_TFV 0x800000U
1586#define AARCH64_ESR_EL3_CV 0x1000000U
1588#define AARCH64_ESR_EL3_IDS 0x1000000U
1590#define AARCH64_ESR_EL3_ISV 0x1000000U
1592#define AARCH64_ESR_EL3_IL 0x2000000U
1594#define AARCH64_ESR_EL3_EC( _val ) ( ( _val ) << 26 )
1595#define AARCH64_ESR_EL3_EC_SHIFT 26
1596#define AARCH64_ESR_EL3_EC_MASK 0xfc000000U
1597#define AARCH64_ESR_EL3_EC_GET( _reg ) \
1598 ( ( ( _reg ) >> 26 ) & 0x3fU )
1600static inline uint64_t _AArch64_Read_esr_el3(
void )
1605 "mrs %0, ESR_EL3" :
"=&r" ( value ) : :
"memory"
1611static inline void _AArch64_Write_esr_el3( uint64_t value )
1614 "msr ESR_EL3, %0" : :
"r" ( value ) :
"memory"
1620static inline uint64_t _AArch64_Read_far_el1(
void )
1625 "mrs %0, FAR_EL1" :
"=&r" ( value ) : :
"memory"
1631static inline void _AArch64_Write_far_el1( uint64_t value )
1634 "msr FAR_EL1, %0" : :
"r" ( value ) :
"memory"
1640static inline uint64_t _AArch64_Read_far_el2(
void )
1645 "mrs %0, FAR_EL2" :
"=&r" ( value ) : :
"memory"
1651static inline void _AArch64_Write_far_el2( uint64_t value )
1654 "msr FAR_EL2, %0" : :
"r" ( value ) :
"memory"
1660static inline uint64_t _AArch64_Read_far_el3(
void )
1665 "mrs %0, FAR_EL3" :
"=&r" ( value ) : :
"memory"
1671static inline void _AArch64_Write_far_el3( uint64_t value )
1674 "msr FAR_EL3, %0" : :
"r" ( value ) :
"memory"
1680#define AARCH64_FPEXC32_EL2_IOF 0x1U
1682#define AARCH64_FPEXC32_EL2_DZF 0x2U
1684#define AARCH64_FPEXC32_EL2_OFF 0x4U
1686#define AARCH64_FPEXC32_EL2_UFF 0x8U
1688#define AARCH64_FPEXC32_EL2_IXF 0x10U
1690#define AARCH64_FPEXC32_EL2_IDF 0x80U
1692#define AARCH64_FPEXC32_EL2_VECITR( _val ) ( ( _val ) << 8 )
1693#define AARCH64_FPEXC32_EL2_VECITR_SHIFT 8
1694#define AARCH64_FPEXC32_EL2_VECITR_MASK 0x700U
1695#define AARCH64_FPEXC32_EL2_VECITR_GET( _reg ) \
1696 ( ( ( _reg ) >> 8 ) & 0x7U )
1698#define AARCH64_FPEXC32_EL2_TFV 0x4000000U
1700#define AARCH64_FPEXC32_EL2_VV 0x8000000U
1702#define AARCH64_FPEXC32_EL2_FP2V 0x10000000U
1704#define AARCH64_FPEXC32_EL2_DEX 0x20000000U
1706#define AARCH64_FPEXC32_EL2_EN 0x40000000U
1708#define AARCH64_FPEXC32_EL2_EX 0x80000000U
1710static inline uint64_t _AArch64_Read_fpexc32_el2(
void )
1715 "mrs %0, FPEXC32_EL2" :
"=&r" ( value ) : :
"memory"
1721static inline void _AArch64_Write_fpexc32_el2( uint64_t value )
1724 "msr FPEXC32_EL2, %0" : :
"r" ( value ) :
"memory"
1730#define AARCH64_GCR_EL1_EXCLUDE( _val ) ( ( _val ) << 0 )
1731#define AARCH64_GCR_EL1_EXCLUDE_SHIFT 0
1732#define AARCH64_GCR_EL1_EXCLUDE_MASK 0xffffU
1733#define AARCH64_GCR_EL1_EXCLUDE_GET( _reg ) \
1734 ( ( ( _reg ) >> 0 ) & 0xffffU )
1736#define AARCH64_GCR_EL1_RRND 0x10000U
1738static inline uint64_t _AArch64_Read_gcr_el1(
void )
1743 "mrs %0, GCR_EL1" :
"=&r" ( value ) : :
"memory"
1749static inline void _AArch64_Write_gcr_el1( uint64_t value )
1752 "msr GCR_EL1, %0" : :
"r" ( value ) :
"memory"
1758#define AARCH64_GMID_EL1_BS( _val ) ( ( _val ) << 0 )
1759#define AARCH64_GMID_EL1_BS_SHIFT 0
1760#define AARCH64_GMID_EL1_BS_MASK 0xfU
1761#define AARCH64_GMID_EL1_BS_GET( _reg ) \
1762 ( ( ( _reg ) >> 0 ) & 0xfU )
1764static inline uint64_t _AArch64_Read_gmid_el1(
void )
1769 "mrs %0, GMID_EL1" :
"=&r" ( value ) : :
"memory"
1777static inline uint64_t _AArch64_Read_hacr_el2(
void )
1782 "mrs %0, HACR_EL2" :
"=&r" ( value ) : :
"memory"
1788static inline void _AArch64_Write_hacr_el2( uint64_t value )
1791 "msr HACR_EL2, %0" : :
"r" ( value ) :
"memory"
1797#define AARCH64_HAFGRTR_EL2_AMCNTEN0 0x1U
1799#define AARCH64_HAFGRTR_EL2_AMCNTEN1 0x20000U
1801#define AARCH64_HAFGRTR_EL2_AMEVCNTR10_EL0 0x40000U
1803#define AARCH64_HAFGRTR_EL2_AMEVTYPER10_EL0 0x80000U
1805#define AARCH64_HAFGRTR_EL2_AMEVCNTR11_EL0 0x100000U
1807#define AARCH64_HAFGRTR_EL2_AMEVTYPER11_EL0 0x200000U
1809#define AARCH64_HAFGRTR_EL2_AMEVCNTR12_EL0 0x400000U
1811#define AARCH64_HAFGRTR_EL2_AMEVTYPER12_EL0 0x800000U
1813#define AARCH64_HAFGRTR_EL2_AMEVCNTR13_EL0 0x1000000U
1815#define AARCH64_HAFGRTR_EL2_AMEVTYPER13_EL0 0x2000000U
1817#define AARCH64_HAFGRTR_EL2_AMEVCNTR14_EL0 0x4000000U
1819#define AARCH64_HAFGRTR_EL2_AMEVTYPER14_EL0 0x8000000U
1821#define AARCH64_HAFGRTR_EL2_AMEVCNTR15_EL0 0x10000000U
1823#define AARCH64_HAFGRTR_EL2_AMEVTYPER15_EL0 0x20000000U
1825#define AARCH64_HAFGRTR_EL2_AMEVCNTR16_EL0 0x40000000U
1827#define AARCH64_HAFGRTR_EL2_AMEVTYPER16_EL0 0x80000000U
1829#define AARCH64_HAFGRTR_EL2_AMEVCNTR17_EL0 0x100000000ULL
1831#define AARCH64_HAFGRTR_EL2_AMEVTYPER17_EL0 0x200000000ULL
1833#define AARCH64_HAFGRTR_EL2_AMEVCNTR18_EL0 0x400000000ULL
1835#define AARCH64_HAFGRTR_EL2_AMEVTYPER18_EL0 0x800000000ULL
1837#define AARCH64_HAFGRTR_EL2_AMEVCNTR19_EL0 0x1000000000ULL
1839#define AARCH64_HAFGRTR_EL2_AMEVTYPER19_EL0 0x2000000000ULL
1841#define AARCH64_HAFGRTR_EL2_AMEVCNTR110_EL0 0x4000000000ULL
1843#define AARCH64_HAFGRTR_EL2_AMEVTYPER110_EL0 0x8000000000ULL
1845#define AARCH64_HAFGRTR_EL2_AMEVCNTR111_EL0 0x10000000000ULL
1847#define AARCH64_HAFGRTR_EL2_AMEVTYPER111_EL0 0x20000000000ULL
1849#define AARCH64_HAFGRTR_EL2_AMEVCNTR112_EL0 0x40000000000ULL
1851#define AARCH64_HAFGRTR_EL2_AMEVTYPER112_EL0 0x80000000000ULL
1853#define AARCH64_HAFGRTR_EL2_AMEVCNTR113_EL0 0x100000000000ULL
1855#define AARCH64_HAFGRTR_EL2_AMEVTYPER113_EL0 0x200000000000ULL
1857#define AARCH64_HAFGRTR_EL2_AMEVCNTR114_EL0 0x400000000000ULL
1859#define AARCH64_HAFGRTR_EL2_AMEVTYPER114_EL0 0x800000000000ULL
1861#define AARCH64_HAFGRTR_EL2_AMEVCNTR115_EL0 0x1000000000000ULL
1863#define AARCH64_HAFGRTR_EL2_AMEVTYPER115_EL0 0x2000000000000ULL
1865static inline uint64_t _AArch64_Read_hafgrtr_el2(
void )
1870 "mrs %0, HAFGRTR_EL2" :
"=&r" ( value ) : :
"memory"
1876static inline void _AArch64_Write_hafgrtr_el2( uint64_t value )
1879 "msr HAFGRTR_EL2, %0" : :
"r" ( value ) :
"memory"
1885#define AARCH64_HCR_EL2_VM 0x1U
1887#define AARCH64_HCR_EL2_SWIO 0x2U
1889#define AARCH64_HCR_EL2_PTW 0x4U
1891#define AARCH64_HCR_EL2_FMO 0x8U
1893#define AARCH64_HCR_EL2_IMO 0x10U
1895#define AARCH64_HCR_EL2_AMO 0x20U
1897#define AARCH64_HCR_EL2_VF 0x40U
1899#define AARCH64_HCR_EL2_VI 0x80U
1901#define AARCH64_HCR_EL2_VSE 0x100U
1903#define AARCH64_HCR_EL2_FB 0x200U
1905#define AARCH64_HCR_EL2_BSU( _val ) ( ( _val ) << 10 )
1906#define AARCH64_HCR_EL2_BSU_SHIFT 10
1907#define AARCH64_HCR_EL2_BSU_MASK 0xc00U
1908#define AARCH64_HCR_EL2_BSU_GET( _reg ) \
1909 ( ( ( _reg ) >> 10 ) & 0x3U )
1911#define AARCH64_HCR_EL2_DC 0x1000U
1913#define AARCH64_HCR_EL2_TWI 0x2000U
1915#define AARCH64_HCR_EL2_TWE 0x4000U
1917#define AARCH64_HCR_EL2_TID0 0x8000U
1919#define AARCH64_HCR_EL2_TID1 0x10000U
1921#define AARCH64_HCR_EL2_TID2 0x20000U
1923#define AARCH64_HCR_EL2_TID3 0x40000U
1925#define AARCH64_HCR_EL2_TSC 0x80000U
1927#define AARCH64_HCR_EL2_TIDCP 0x100000U
1929#define AARCH64_HCR_EL2_TACR 0x200000U
1931#define AARCH64_HCR_EL2_TSW 0x400000U
1933#define AARCH64_HCR_EL2_TPCP 0x800000U
1935#define AARCH64_HCR_EL2_TPU 0x1000000U
1937#define AARCH64_HCR_EL2_TTLB 0x2000000U
1939#define AARCH64_HCR_EL2_TVM 0x4000000U
1941#define AARCH64_HCR_EL2_TGE 0x8000000U
1943#define AARCH64_HCR_EL2_TDZ 0x10000000U
1945#define AARCH64_HCR_EL2_HCD 0x20000000U
1947#define AARCH64_HCR_EL2_TRVM 0x40000000U
1949#define AARCH64_HCR_EL2_RW 0x80000000U
1951#define AARCH64_HCR_EL2_CD 0x100000000ULL
1953#define AARCH64_HCR_EL2_ID 0x200000000ULL
1955#define AARCH64_HCR_EL2_E2H 0x400000000ULL
1957#define AARCH64_HCR_EL2_TLOR 0x800000000ULL
1959#define AARCH64_HCR_EL2_TERR 0x1000000000ULL
1961#define AARCH64_HCR_EL2_TEA 0x2000000000ULL
1963#define AARCH64_HCR_EL2_MIOCNCE 0x4000000000ULL
1965#define AARCH64_HCR_EL2_APK 0x10000000000ULL
1967#define AARCH64_HCR_EL2_API 0x20000000000ULL
1969#define AARCH64_HCR_EL2_NV 0x40000000000ULL
1971#define AARCH64_HCR_EL2_NV1 0x80000000000ULL
1973#define AARCH64_HCR_EL2_AT 0x100000000000ULL
1975#define AARCH64_HCR_EL2_NV2 0x200000000000ULL
1977#define AARCH64_HCR_EL2_FWB 0x400000000000ULL
1979#define AARCH64_HCR_EL2_FIEN 0x800000000000ULL
1981#define AARCH64_HCR_EL2_TID4 0x2000000000000ULL
1983#define AARCH64_HCR_EL2_TICAB 0x4000000000000ULL
1985#define AARCH64_HCR_EL2_AMVOFFEN 0x8000000000000ULL
1987#define AARCH64_HCR_EL2_TOCU 0x10000000000000ULL
1989#define AARCH64_HCR_EL2_ENSCXT 0x20000000000000ULL
1991#define AARCH64_HCR_EL2_TTLBIS 0x40000000000000ULL
1993#define AARCH64_HCR_EL2_TTLBOS 0x80000000000000ULL
1995#define AARCH64_HCR_EL2_ATA 0x100000000000000ULL
1997#define AARCH64_HCR_EL2_DCT 0x200000000000000ULL
1999#define AARCH64_HCR_EL2_TID5 0x400000000000000ULL
2001#define AARCH64_HCR_EL2_TWEDEN 0x800000000000000ULL
2003#define AARCH64_HCR_EL2_TWEDEL( _val ) ( ( _val ) << 60 )
2004#define AARCH64_HCR_EL2_TWEDEL_SHIFT 60
2005#define AARCH64_HCR_EL2_TWEDEL_MASK 0xf000000000000000ULL
2006#define AARCH64_HCR_EL2_TWEDEL_GET( _reg ) \
2007 ( ( ( _reg ) >> 60 ) & 0xfULL )
2009static inline uint64_t _AArch64_Read_hcr_el2(
void )
2014 "mrs %0, HCR_EL2" :
"=&r" ( value ) : :
"memory"
2020static inline void _AArch64_Write_hcr_el2( uint64_t value )
2023 "msr HCR_EL2, %0" : :
"r" ( value ) :
"memory"
2029#define AARCH64_HDFGRTR_EL2_DBGBCRN_EL1 0x1U
2031#define AARCH64_HDFGRTR_EL2_DBGBVRN_EL1 0x2U
2033#define AARCH64_HDFGRTR_EL2_DBGWCRN_EL1 0x4U
2035#define AARCH64_HDFGRTR_EL2_DBGWVRN_EL1 0x8U
2037#define AARCH64_HDFGRTR_EL2_MDSCR_EL1 0x10U
2039#define AARCH64_HDFGRTR_EL2_DBGCLAIM 0x20U
2041#define AARCH64_HDFGRTR_EL2_DBGAUTHSTATUS_EL1 0x40U
2043#define AARCH64_HDFGRTR_EL2_DBGPRCR_EL1 0x80U
2045#define AARCH64_HDFGRTR_EL2_OSLSR_EL1 0x200U
2047#define AARCH64_HDFGRTR_EL2_OSECCR_EL1 0x400U
2049#define AARCH64_HDFGRTR_EL2_OSDLR_EL1 0x800U
2051#define AARCH64_HDFGRTR_EL2_PMEVCNTRN_EL0 0x1000U
2053#define AARCH64_HDFGRTR_EL2_PMEVTYPERN_EL0 0x2000U
2055#define AARCH64_HDFGRTR_EL2_PMCCFILTR_EL0 0x4000U
2057#define AARCH64_HDFGRTR_EL2_PMCCNTR_EL0 0x8000U
2059#define AARCH64_HDFGRTR_EL2_PMCNTEN 0x10000U
2061#define AARCH64_HDFGRTR_EL2_PMINTEN 0x20000U
2063#define AARCH64_HDFGRTR_EL2_PMOVS 0x40000U
2065#define AARCH64_HDFGRTR_EL2_PMSELR_EL0 0x80000U
2067#define AARCH64_HDFGRTR_EL2_PMMIR_EL1 0x400000U
2069#define AARCH64_HDFGRTR_EL2_PMBLIMITR_EL1 0x800000U
2071#define AARCH64_HDFGRTR_EL2_PMBPTR_EL1 0x1000000U
2073#define AARCH64_HDFGRTR_EL2_PMBSR_EL1 0x2000000U
2075#define AARCH64_HDFGRTR_EL2_PMSCR_EL1 0x4000000U
2077#define AARCH64_HDFGRTR_EL2_PMSEVFR_EL1 0x8000000U
2079#define AARCH64_HDFGRTR_EL2_PMSFCR_EL1 0x10000000U
2081#define AARCH64_HDFGRTR_EL2_PMSICR_EL1 0x20000000U
2083#define AARCH64_HDFGRTR_EL2_PMSIDR_EL1 0x40000000U
2085#define AARCH64_HDFGRTR_EL2_PMSIRR_EL1 0x80000000U
2087#define AARCH64_HDFGRTR_EL2_PMSLATFR_EL1 0x100000000ULL
2089#define AARCH64_HDFGRTR_EL2_TRC 0x200000000ULL
2091#define AARCH64_HDFGRTR_EL2_TRCAUTHSTATUS 0x400000000ULL
2093#define AARCH64_HDFGRTR_EL2_TRCAUXCTLR 0x800000000ULL
2095#define AARCH64_HDFGRTR_EL2_TRCCLAIM 0x1000000000ULL
2097#define AARCH64_HDFGRTR_EL2_TRCCNTVRN 0x2000000000ULL
2099#define AARCH64_HDFGRTR_EL2_TRCID 0x10000000000ULL
2101#define AARCH64_HDFGRTR_EL2_TRCIMSPECN 0x20000000000ULL
2103#define AARCH64_HDFGRTR_EL2_TRCOSLSR 0x80000000000ULL
2105#define AARCH64_HDFGRTR_EL2_TRCPRGCTLR 0x100000000000ULL
2107#define AARCH64_HDFGRTR_EL2_TRCSEQSTR 0x200000000000ULL
2109#define AARCH64_HDFGRTR_EL2_TRCSSCSRN 0x400000000000ULL
2111#define AARCH64_HDFGRTR_EL2_TRCSTATR 0x800000000000ULL
2113#define AARCH64_HDFGRTR_EL2_TRCVICTLR 0x1000000000000ULL
2115#define AARCH64_HDFGRTR_EL2_PMUSERENR_EL0 0x200000000000000ULL
2117#define AARCH64_HDFGRTR_EL2_PMCEIDN_EL0 0x400000000000000ULL
2119static inline uint64_t _AArch64_Read_hdfgrtr_el2(
void )
2124 "mrs %0, HDFGRTR_EL2" :
"=&r" ( value ) : :
"memory"
2130static inline void _AArch64_Write_hdfgrtr_el2( uint64_t value )
2133 "msr HDFGRTR_EL2, %0" : :
"r" ( value ) :
"memory"
2139#define AARCH64_HDFGWTR_EL2_DBGBCRN_EL1 0x1U
2141#define AARCH64_HDFGWTR_EL2_DBGBVRN_EL1 0x2U
2143#define AARCH64_HDFGWTR_EL2_DBGWCRN_EL1 0x4U
2145#define AARCH64_HDFGWTR_EL2_DBGWVRN_EL1 0x8U
2147#define AARCH64_HDFGWTR_EL2_MDSCR_EL1 0x10U
2149#define AARCH64_HDFGWTR_EL2_DBGCLAIM 0x20U
2151#define AARCH64_HDFGWTR_EL2_DBGPRCR_EL1 0x80U
2153#define AARCH64_HDFGWTR_EL2_OSLAR_EL1 0x100U
2155#define AARCH64_HDFGWTR_EL2_OSECCR_EL1 0x400U
2157#define AARCH64_HDFGWTR_EL2_OSDLR_EL1 0x800U
2159#define AARCH64_HDFGWTR_EL2_PMEVCNTRN_EL0 0x1000U
2161#define AARCH64_HDFGWTR_EL2_PMEVTYPERN_EL0 0x2000U
2163#define AARCH64_HDFGWTR_EL2_PMCCFILTR_EL0 0x4000U
2165#define AARCH64_HDFGWTR_EL2_PMCCNTR_EL0 0x8000U
2167#define AARCH64_HDFGWTR_EL2_PMCNTEN 0x10000U
2169#define AARCH64_HDFGWTR_EL2_PMINTEN 0x20000U
2171#define AARCH64_HDFGWTR_EL2_PMOVS 0x40000U
2173#define AARCH64_HDFGWTR_EL2_PMSELR_EL0 0x80000U
2175#define AARCH64_HDFGWTR_EL2_PMSWINC_EL0 0x100000U
2177#define AARCH64_HDFGWTR_EL2_PMCR_EL0 0x200000U
2179#define AARCH64_HDFGWTR_EL2_PMBLIMITR_EL1 0x800000U
2181#define AARCH64_HDFGWTR_EL2_PMBPTR_EL1 0x1000000U
2183#define AARCH64_HDFGWTR_EL2_PMBSR_EL1 0x2000000U
2185#define AARCH64_HDFGWTR_EL2_PMSCR_EL1 0x4000000U
2187#define AARCH64_HDFGWTR_EL2_PMSEVFR_EL1 0x8000000U
2189#define AARCH64_HDFGWTR_EL2_PMSFCR_EL1 0x10000000U
2191#define AARCH64_HDFGWTR_EL2_PMSICR_EL1 0x20000000U
2193#define AARCH64_HDFGWTR_EL2_PMSIRR_EL1 0x80000000U
2195#define AARCH64_HDFGWTR_EL2_PMSLATFR_EL1 0x100000000ULL
2197#define AARCH64_HDFGWTR_EL2_TRC 0x200000000ULL
2199#define AARCH64_HDFGWTR_EL2_TRCAUXCTLR 0x800000000ULL
2201#define AARCH64_HDFGWTR_EL2_TRCCLAIM 0x1000000000ULL
2203#define AARCH64_HDFGWTR_EL2_TRCCNTVRN 0x2000000000ULL
2205#define AARCH64_HDFGWTR_EL2_TRCIMSPECN 0x20000000000ULL
2207#define AARCH64_HDFGWTR_EL2_TRCOSLAR 0x40000000000ULL
2209#define AARCH64_HDFGWTR_EL2_TRCPRGCTLR 0x100000000000ULL
2211#define AARCH64_HDFGWTR_EL2_TRCSEQSTR 0x200000000000ULL
2213#define AARCH64_HDFGWTR_EL2_TRCSSCSRN 0x400000000000ULL
2215#define AARCH64_HDFGWTR_EL2_TRCVICTLR 0x1000000000000ULL
2217#define AARCH64_HDFGWTR_EL2_TRFCR_EL1 0x2000000000000ULL
2219#define AARCH64_HDFGWTR_EL2_PMUSERENR_EL0 0x200000000000000ULL
2221static inline uint64_t _AArch64_Read_hdfgwtr_el2(
void )
2226 "mrs %0, HDFGWTR_EL2" :
"=&r" ( value ) : :
"memory"
2232static inline void _AArch64_Write_hdfgwtr_el2( uint64_t value )
2235 "msr HDFGWTR_EL2, %0" : :
"r" ( value ) :
"memory"
2241#define AARCH64_HFGITR_EL2_ICIALLUIS 0x1U
2243#define AARCH64_HFGITR_EL2_ICIALLU 0x2U
2245#define AARCH64_HFGITR_EL2_ICIVAU 0x4U
2247#define AARCH64_HFGITR_EL2_DCIVAC 0x8U
2249#define AARCH64_HFGITR_EL2_DCISW 0x10U
2251#define AARCH64_HFGITR_EL2_DCCSW 0x20U
2253#define AARCH64_HFGITR_EL2_DCCISW 0x40U
2255#define AARCH64_HFGITR_EL2_DCCVAU 0x80U
2257#define AARCH64_HFGITR_EL2_DCCVAP 0x100U
2259#define AARCH64_HFGITR_EL2_DCCVADP 0x200U
2261#define AARCH64_HFGITR_EL2_DCCIVAC 0x400U
2263#define AARCH64_HFGITR_EL2_DCZVA 0x800U
2265#define AARCH64_HFGITR_EL2_ATS1E1R 0x1000U
2267#define AARCH64_HFGITR_EL2_ATS1E1W 0x2000U
2269#define AARCH64_HFGITR_EL2_ATS1E0R 0x4000U
2271#define AARCH64_HFGITR_EL2_ATS1E0W 0x8000U
2273#define AARCH64_HFGITR_EL2_ATS1E1RP 0x10000U
2275#define AARCH64_HFGITR_EL2_ATS1E1WP 0x20000U
2277#define AARCH64_HFGITR_EL2_TLBIVMALLE1OS 0x40000U
2279#define AARCH64_HFGITR_EL2_TLBIVAE1OS 0x80000U
2281#define AARCH64_HFGITR_EL2_TLBIASIDE1OS 0x100000U
2283#define AARCH64_HFGITR_EL2_TLBIVAAE1OS 0x200000U
2285#define AARCH64_HFGITR_EL2_TLBIVALE1OS 0x400000U
2287#define AARCH64_HFGITR_EL2_TLBIVAALE1OS 0x800000U
2289#define AARCH64_HFGITR_EL2_TLBIRVAE1OS 0x1000000U
2291#define AARCH64_HFGITR_EL2_TLBIRVAAE1OS 0x2000000U
2293#define AARCH64_HFGITR_EL2_TLBIRVALE1OS 0x4000000U
2295#define AARCH64_HFGITR_EL2_TLBIRVAALE1OS 0x8000000U
2297#define AARCH64_HFGITR_EL2_TLBIVMALLE1IS 0x10000000U
2299#define AARCH64_HFGITR_EL2_TLBIVAE1IS 0x20000000U
2301#define AARCH64_HFGITR_EL2_TLBIASIDE1IS 0x40000000U
2303#define AARCH64_HFGITR_EL2_TLBIVAAE1IS 0x80000000U
2305#define AARCH64_HFGITR_EL2_TLBIVALE1IS 0x100000000ULL
2307#define AARCH64_HFGITR_EL2_TLBIVAALE1IS 0x200000000ULL
2309#define AARCH64_HFGITR_EL2_TLBIRVAE1IS 0x400000000ULL
2311#define AARCH64_HFGITR_EL2_TLBIRVAAE1IS 0x800000000ULL
2313#define AARCH64_HFGITR_EL2_TLBIRVALE1IS 0x1000000000ULL
2315#define AARCH64_HFGITR_EL2_TLBIRVAALE1IS 0x2000000000ULL
2317#define AARCH64_HFGITR_EL2_TLBIRVAE1 0x4000000000ULL
2319#define AARCH64_HFGITR_EL2_TLBIRVAAE1 0x8000000000ULL
2321#define AARCH64_HFGITR_EL2_TLBIRVALE1 0x10000000000ULL
2323#define AARCH64_HFGITR_EL2_TLBIRVAALE1 0x20000000000ULL
2325#define AARCH64_HFGITR_EL2_TLBIVMALLE1 0x40000000000ULL
2327#define AARCH64_HFGITR_EL2_TLBIVAE1 0x80000000000ULL
2329#define AARCH64_HFGITR_EL2_TLBIASIDE1 0x100000000000ULL
2331#define AARCH64_HFGITR_EL2_TLBIVAAE1 0x200000000000ULL
2333#define AARCH64_HFGITR_EL2_TLBIVALE1 0x400000000000ULL
2335#define AARCH64_HFGITR_EL2_TLBIVAALE1 0x800000000000ULL
2337#define AARCH64_HFGITR_EL2_CFPRCTX 0x1000000000000ULL
2339#define AARCH64_HFGITR_EL2_DVPRCTX 0x2000000000000ULL
2341#define AARCH64_HFGITR_EL2_CPPRCTX 0x4000000000000ULL
2343#define AARCH64_HFGITR_EL2_ERET 0x8000000000000ULL
2345#define AARCH64_HFGITR_EL2_SVC_EL0 0x10000000000000ULL
2347#define AARCH64_HFGITR_EL2_SVC_EL1 0x20000000000000ULL
2349#define AARCH64_HFGITR_EL2_DCCVAC 0x40000000000000ULL
2351static inline uint64_t _AArch64_Read_hfgitr_el2(
void )
2356 "mrs %0, HFGITR_EL2" :
"=&r" ( value ) : :
"memory"
2362static inline void _AArch64_Write_hfgitr_el2( uint64_t value )
2365 "msr HFGITR_EL2, %0" : :
"r" ( value ) :
"memory"
2371#define AARCH64_HFGRTR_EL2_AFSR0_EL1 0x1U
2373#define AARCH64_HFGRTR_EL2_AFSR1_EL1 0x2U
2375#define AARCH64_HFGRTR_EL2_AIDR_EL1 0x4U
2377#define AARCH64_HFGRTR_EL2_AMAIR_EL1 0x8U
2379#define AARCH64_HFGRTR_EL2_APDAKEY 0x10U
2381#define AARCH64_HFGRTR_EL2_APDBKEY 0x20U
2383#define AARCH64_HFGRTR_EL2_APGAKEY 0x40U
2385#define AARCH64_HFGRTR_EL2_APIAKEY 0x80U
2387#define AARCH64_HFGRTR_EL2_APIBKEY 0x100U
2389#define AARCH64_HFGRTR_EL2_CCSIDR_EL1 0x200U
2391#define AARCH64_HFGRTR_EL2_CLIDR_EL1 0x400U
2393#define AARCH64_HFGRTR_EL2_CONTEXTIDR_EL1 0x800U
2395#define AARCH64_HFGRTR_EL2_CPACR_EL1 0x1000U
2397#define AARCH64_HFGRTR_EL2_CSSELR_EL1 0x2000U
2399#define AARCH64_HFGRTR_EL2_CTR_EL0 0x4000U
2401#define AARCH64_HFGRTR_EL2_DCZID_EL0 0x8000U
2403#define AARCH64_HFGRTR_EL2_ESR_EL1 0x10000U
2405#define AARCH64_HFGRTR_EL2_FAR_EL1 0x20000U
2407#define AARCH64_HFGRTR_EL2_ISR_EL1 0x40000U
2409#define AARCH64_HFGRTR_EL2_LORC_EL1 0x80000U
2411#define AARCH64_HFGRTR_EL2_LOREA_EL1 0x100000U
2413#define AARCH64_HFGRTR_EL2_LORID_EL1 0x200000U
2415#define AARCH64_HFGRTR_EL2_LORN_EL1 0x400000U
2417#define AARCH64_HFGRTR_EL2_LORSA_EL1 0x800000U
2419#define AARCH64_HFGRTR_EL2_MAIR_EL1 0x1000000U
2421#define AARCH64_HFGRTR_EL2_MIDR_EL1 0x2000000U
2423#define AARCH64_HFGRTR_EL2_MPIDR_EL1 0x4000000U
2425#define AARCH64_HFGRTR_EL2_PAR_EL1 0x8000000U
2427#define AARCH64_HFGRTR_EL2_REVIDR_EL1 0x10000000U
2429#define AARCH64_HFGRTR_EL2_SCTLR_EL1 0x20000000U
2431#define AARCH64_HFGRTR_EL2_SCXTNUM_EL1 0x40000000U
2433#define AARCH64_HFGRTR_EL2_SCXTNUM_EL0 0x80000000U
2435#define AARCH64_HFGRTR_EL2_TCR_EL1 0x100000000ULL
2437#define AARCH64_HFGRTR_EL2_TPIDR_EL1 0x200000000ULL
2439#define AARCH64_HFGRTR_EL2_TPIDRRO_EL0 0x400000000ULL
2441#define AARCH64_HFGRTR_EL2_TPIDR_EL0 0x800000000ULL
2443#define AARCH64_HFGRTR_EL2_TTBR0_EL1 0x1000000000ULL
2445#define AARCH64_HFGRTR_EL2_TTBR1_EL1 0x2000000000ULL
2447#define AARCH64_HFGRTR_EL2_VBAR_EL1 0x4000000000ULL
2449#define AARCH64_HFGRTR_EL2_ICC_IGRPENN_EL1 0x8000000000ULL
2451#define AARCH64_HFGRTR_EL2_ERRIDR_EL1 0x10000000000ULL
2453#define AARCH64_HFGRTR_EL2_ERRSELR_EL1 0x20000000000ULL
2455#define AARCH64_HFGRTR_EL2_ERXFR_EL1 0x40000000000ULL
2457#define AARCH64_HFGRTR_EL2_ERXCTLR_EL1 0x80000000000ULL
2459#define AARCH64_HFGRTR_EL2_ERXSTATUS_EL1 0x100000000000ULL
2461#define AARCH64_HFGRTR_EL2_ERXMISCN_EL1 0x200000000000ULL
2463#define AARCH64_HFGRTR_EL2_ERXPFGF_EL1 0x400000000000ULL
2465#define AARCH64_HFGRTR_EL2_ERXPFGCTL_EL1 0x800000000000ULL
2467#define AARCH64_HFGRTR_EL2_ERXPFGCDN_EL1 0x1000000000000ULL
2469#define AARCH64_HFGRTR_EL2_ERXADDR_EL1 0x2000000000000ULL
2471static inline uint64_t _AArch64_Read_hfgrtr_el2(
void )
2476 "mrs %0, HFGRTR_EL2" :
"=&r" ( value ) : :
"memory"
2482static inline void _AArch64_Write_hfgrtr_el2( uint64_t value )
2485 "msr HFGRTR_EL2, %0" : :
"r" ( value ) :
"memory"
2491#define AARCH64_HFGWTR_EL2_AFSR0_EL1 0x1U
2493#define AARCH64_HFGWTR_EL2_AFSR1_EL1 0x2U
2495#define AARCH64_HFGWTR_EL2_AMAIR_EL1 0x8U
2497#define AARCH64_HFGWTR_EL2_APDAKEY 0x10U
2499#define AARCH64_HFGWTR_EL2_APDBKEY 0x20U
2501#define AARCH64_HFGWTR_EL2_APGAKEY 0x40U
2503#define AARCH64_HFGWTR_EL2_APIAKEY 0x80U
2505#define AARCH64_HFGWTR_EL2_APIBKEY 0x100U
2507#define AARCH64_HFGWTR_EL2_CONTEXTIDR_EL1 0x800U
2509#define AARCH64_HFGWTR_EL2_CPACR_EL1 0x1000U
2511#define AARCH64_HFGWTR_EL2_CSSELR_EL1 0x2000U
2513#define AARCH64_HFGWTR_EL2_ESR_EL1 0x10000U
2515#define AARCH64_HFGWTR_EL2_FAR_EL1 0x20000U
2517#define AARCH64_HFGWTR_EL2_LORC_EL1 0x80000U
2519#define AARCH64_HFGWTR_EL2_LOREA_EL1 0x100000U
2521#define AARCH64_HFGWTR_EL2_LORN_EL1 0x400000U
2523#define AARCH64_HFGWTR_EL2_LORSA_EL1 0x800000U
2525#define AARCH64_HFGWTR_EL2_MAIR_EL1 0x1000000U
2527#define AARCH64_HFGWTR_EL2_PAR_EL1 0x8000000U
2529#define AARCH64_HFGWTR_EL2_SCTLR_EL1 0x20000000U
2531#define AARCH64_HFGWTR_EL2_SCXTNUM_EL1 0x40000000U
2533#define AARCH64_HFGWTR_EL2_SCXTNUM_EL0 0x80000000U
2535#define AARCH64_HFGWTR_EL2_TCR_EL1 0x100000000ULL
2537#define AARCH64_HFGWTR_EL2_TPIDR_EL1 0x200000000ULL
2539#define AARCH64_HFGWTR_EL2_TPIDRRO_EL0 0x400000000ULL
2541#define AARCH64_HFGWTR_EL2_TPIDR_EL0 0x800000000ULL
2543#define AARCH64_HFGWTR_EL2_TTBR0_EL1 0x1000000000ULL
2545#define AARCH64_HFGWTR_EL2_TTBR1_EL1 0x2000000000ULL
2547#define AARCH64_HFGWTR_EL2_VBAR_EL1 0x4000000000ULL
2549#define AARCH64_HFGWTR_EL2_ICC_IGRPENN_EL1 0x8000000000ULL
2551#define AARCH64_HFGWTR_EL2_ERRSELR_EL1 0x20000000000ULL
2553#define AARCH64_HFGWTR_EL2_ERXCTLR_EL1 0x80000000000ULL
2555#define AARCH64_HFGWTR_EL2_ERXSTATUS_EL1 0x100000000000ULL
2557#define AARCH64_HFGWTR_EL2_ERXMISCN_EL1 0x200000000000ULL
2559#define AARCH64_HFGWTR_EL2_ERXPFGCTL_EL1 0x800000000000ULL
2561#define AARCH64_HFGWTR_EL2_ERXPFGCDN_EL1 0x1000000000000ULL
2563#define AARCH64_HFGWTR_EL2_ERXADDR_EL1 0x2000000000000ULL
2565static inline uint64_t _AArch64_Read_hfgwtr_el2(
void )
2570 "mrs %0, HFGWTR_EL2" :
"=&r" ( value ) : :
"memory"
2576static inline void _AArch64_Write_hfgwtr_el2( uint64_t value )
2579 "msr HFGWTR_EL2, %0" : :
"r" ( value ) :
"memory"
2585#define AARCH64_HPFAR_EL2_FIPA_47_12( _val ) ( ( _val ) << 4 )
2586#define AARCH64_HPFAR_EL2_FIPA_47_12_SHIFT 4
2587#define AARCH64_HPFAR_EL2_FIPA_47_12_MASK 0xfffffffff0ULL
2588#define AARCH64_HPFAR_EL2_FIPA_47_12_GET( _reg ) \
2589 ( ( ( _reg ) >> 4 ) & 0xfffffffffULL )
2591#define AARCH64_HPFAR_EL2_FIPA_51_48( _val ) ( ( _val ) << 40 )
2592#define AARCH64_HPFAR_EL2_FIPA_51_48_SHIFT 40
2593#define AARCH64_HPFAR_EL2_FIPA_51_48_MASK 0xf0000000000ULL
2594#define AARCH64_HPFAR_EL2_FIPA_51_48_GET( _reg ) \
2595 ( ( ( _reg ) >> 40 ) & 0xfULL )
2597#define AARCH64_HPFAR_EL2_NS 0x8000000000000000ULL
2599static inline uint64_t _AArch64_Read_hpfar_el2(
void )
2604 "mrs %0, HPFAR_EL2" :
"=&r" ( value ) : :
"memory"
2610static inline void _AArch64_Write_hpfar_el2( uint64_t value )
2613 "msr HPFAR_EL2, %0" : :
"r" ( value ) :
"memory"
2619static inline uint64_t _AArch64_Read_hstr_el2(
void )
2624 "mrs %0, HSTR_EL2" :
"=&r" ( value ) : :
"memory"
2630static inline void _AArch64_Write_hstr_el2( uint64_t value )
2633 "msr HSTR_EL2, %0" : :
"r" ( value ) :
"memory"
2639static inline uint64_t _AArch64_Read_id_aa64afr0_el1(
void )
2644 "mrs %0, ID_AA64AFR0_EL1" :
"=&r" ( value ) : :
"memory"
2652static inline uint64_t _AArch64_Read_id_aa64afr1_el1(
void )
2657 "mrs %0, ID_AA64AFR1_EL1" :
"=&r" ( value ) : :
"memory"
2665#define AARCH64_ID_AA64DFR0_EL1_DEBUGVER( _val ) ( ( _val ) << 0 )
2666#define AARCH64_ID_AA64DFR0_EL1_DEBUGVER_SHIFT 0
2667#define AARCH64_ID_AA64DFR0_EL1_DEBUGVER_MASK 0xfU
2668#define AARCH64_ID_AA64DFR0_EL1_DEBUGVER_GET( _reg ) \
2669 ( ( ( _reg ) >> 0 ) & 0xfU )
2671#define AARCH64_ID_AA64DFR0_EL1_TRACEVER( _val ) ( ( _val ) << 4 )
2672#define AARCH64_ID_AA64DFR0_EL1_TRACEVER_SHIFT 4
2673#define AARCH64_ID_AA64DFR0_EL1_TRACEVER_MASK 0xf0U
2674#define AARCH64_ID_AA64DFR0_EL1_TRACEVER_GET( _reg ) \
2675 ( ( ( _reg ) >> 4 ) & 0xfU )
2677#define AARCH64_ID_AA64DFR0_EL1_PMUVER( _val ) ( ( _val ) << 8 )
2678#define AARCH64_ID_AA64DFR0_EL1_PMUVER_SHIFT 8
2679#define AARCH64_ID_AA64DFR0_EL1_PMUVER_MASK 0xf00U
2680#define AARCH64_ID_AA64DFR0_EL1_PMUVER_GET( _reg ) \
2681 ( ( ( _reg ) >> 8 ) & 0xfU )
2683#define AARCH64_ID_AA64DFR0_EL1_BRPS( _val ) ( ( _val ) << 12 )
2684#define AARCH64_ID_AA64DFR0_EL1_BRPS_SHIFT 12
2685#define AARCH64_ID_AA64DFR0_EL1_BRPS_MASK 0xf000U
2686#define AARCH64_ID_AA64DFR0_EL1_BRPS_GET( _reg ) \
2687 ( ( ( _reg ) >> 12 ) & 0xfU )
2689#define AARCH64_ID_AA64DFR0_EL1_WRPS( _val ) ( ( _val ) << 20 )
2690#define AARCH64_ID_AA64DFR0_EL1_WRPS_SHIFT 20
2691#define AARCH64_ID_AA64DFR0_EL1_WRPS_MASK 0xf00000U
2692#define AARCH64_ID_AA64DFR0_EL1_WRPS_GET( _reg ) \
2693 ( ( ( _reg ) >> 20 ) & 0xfU )
2695#define AARCH64_ID_AA64DFR0_EL1_CTX_CMPS( _val ) ( ( _val ) << 28 )
2696#define AARCH64_ID_AA64DFR0_EL1_CTX_CMPS_SHIFT 28
2697#define AARCH64_ID_AA64DFR0_EL1_CTX_CMPS_MASK 0xf0000000U
2698#define AARCH64_ID_AA64DFR0_EL1_CTX_CMPS_GET( _reg ) \
2699 ( ( ( _reg ) >> 28 ) & 0xfU )
2701#define AARCH64_ID_AA64DFR0_EL1_PMSVER( _val ) ( ( _val ) << 32 )
2702#define AARCH64_ID_AA64DFR0_EL1_PMSVER_SHIFT 32
2703#define AARCH64_ID_AA64DFR0_EL1_PMSVER_MASK 0xf00000000ULL
2704#define AARCH64_ID_AA64DFR0_EL1_PMSVER_GET( _reg ) \
2705 ( ( ( _reg ) >> 32 ) & 0xfULL )
2707#define AARCH64_ID_AA64DFR0_EL1_DOUBLELOCK( _val ) ( ( _val ) << 36 )
2708#define AARCH64_ID_AA64DFR0_EL1_DOUBLELOCK_SHIFT 36
2709#define AARCH64_ID_AA64DFR0_EL1_DOUBLELOCK_MASK 0xf000000000ULL
2710#define AARCH64_ID_AA64DFR0_EL1_DOUBLELOCK_GET( _reg ) \
2711 ( ( ( _reg ) >> 36 ) & 0xfULL )
2713#define AARCH64_ID_AA64DFR0_EL1_TRACEFILT( _val ) ( ( _val ) << 40 )
2714#define AARCH64_ID_AA64DFR0_EL1_TRACEFILT_SHIFT 40
2715#define AARCH64_ID_AA64DFR0_EL1_TRACEFILT_MASK 0xf0000000000ULL
2716#define AARCH64_ID_AA64DFR0_EL1_TRACEFILT_GET( _reg ) \
2717 ( ( ( _reg ) >> 40 ) & 0xfULL )
2719#define AARCH64_ID_AA64DFR0_EL1_MTPMU( _val ) ( ( _val ) << 48 )
2720#define AARCH64_ID_AA64DFR0_EL1_MTPMU_SHIFT 48
2721#define AARCH64_ID_AA64DFR0_EL1_MTPMU_MASK 0xf000000000000ULL
2722#define AARCH64_ID_AA64DFR0_EL1_MTPMU_GET( _reg ) \
2723 ( ( ( _reg ) >> 48 ) & 0xfULL )
2725static inline uint64_t _AArch64_Read_id_aa64dfr0_el1(
void )
2730 "mrs %0, ID_AA64DFR0_EL1" :
"=&r" ( value ) : :
"memory"
2738static inline uint64_t _AArch64_Read_id_aa64dfr1_el1(
void )
2743 "mrs %0, ID_AA64DFR1_EL1" :
"=&r" ( value ) : :
"memory"
2751#define AARCH64_ID_AA64ISAR0_EL1_AES( _val ) ( ( _val ) << 4 )
2752#define AARCH64_ID_AA64ISAR0_EL1_AES_SHIFT 4
2753#define AARCH64_ID_AA64ISAR0_EL1_AES_MASK 0xf0U
2754#define AARCH64_ID_AA64ISAR0_EL1_AES_GET( _reg ) \
2755 ( ( ( _reg ) >> 4 ) & 0xfU )
2757#define AARCH64_ID_AA64ISAR0_EL1_SHA1( _val ) ( ( _val ) << 8 )
2758#define AARCH64_ID_AA64ISAR0_EL1_SHA1_SHIFT 8
2759#define AARCH64_ID_AA64ISAR0_EL1_SHA1_MASK 0xf00U
2760#define AARCH64_ID_AA64ISAR0_EL1_SHA1_GET( _reg ) \
2761 ( ( ( _reg ) >> 8 ) & 0xfU )
2763#define AARCH64_ID_AA64ISAR0_EL1_SHA2( _val ) ( ( _val ) << 12 )
2764#define AARCH64_ID_AA64ISAR0_EL1_SHA2_SHIFT 12
2765#define AARCH64_ID_AA64ISAR0_EL1_SHA2_MASK 0xf000U
2766#define AARCH64_ID_AA64ISAR0_EL1_SHA2_GET( _reg ) \
2767 ( ( ( _reg ) >> 12 ) & 0xfU )
2769#define AARCH64_ID_AA64ISAR0_EL1_CRC32( _val ) ( ( _val ) << 16 )
2770#define AARCH64_ID_AA64ISAR0_EL1_CRC32_SHIFT 16
2771#define AARCH64_ID_AA64ISAR0_EL1_CRC32_MASK 0xf0000U
2772#define AARCH64_ID_AA64ISAR0_EL1_CRC32_GET( _reg ) \
2773 ( ( ( _reg ) >> 16 ) & 0xfU )
2775#define AARCH64_ID_AA64ISAR0_EL1_ATOMIC( _val ) ( ( _val ) << 20 )
2776#define AARCH64_ID_AA64ISAR0_EL1_ATOMIC_SHIFT 20
2777#define AARCH64_ID_AA64ISAR0_EL1_ATOMIC_MASK 0xf00000U
2778#define AARCH64_ID_AA64ISAR0_EL1_ATOMIC_GET( _reg ) \
2779 ( ( ( _reg ) >> 20 ) & 0xfU )
2781#define AARCH64_ID_AA64ISAR0_EL1_RDM( _val ) ( ( _val ) << 28 )
2782#define AARCH64_ID_AA64ISAR0_EL1_RDM_SHIFT 28
2783#define AARCH64_ID_AA64ISAR0_EL1_RDM_MASK 0xf0000000U
2784#define AARCH64_ID_AA64ISAR0_EL1_RDM_GET( _reg ) \
2785 ( ( ( _reg ) >> 28 ) & 0xfU )
2787#define AARCH64_ID_AA64ISAR0_EL1_SHA3( _val ) ( ( _val ) << 32 )
2788#define AARCH64_ID_AA64ISAR0_EL1_SHA3_SHIFT 32
2789#define AARCH64_ID_AA64ISAR0_EL1_SHA3_MASK 0xf00000000ULL
2790#define AARCH64_ID_AA64ISAR0_EL1_SHA3_GET( _reg ) \
2791 ( ( ( _reg ) >> 32 ) & 0xfULL )
2793#define AARCH64_ID_AA64ISAR0_EL1_SM3( _val ) ( ( _val ) << 36 )
2794#define AARCH64_ID_AA64ISAR0_EL1_SM3_SHIFT 36
2795#define AARCH64_ID_AA64ISAR0_EL1_SM3_MASK 0xf000000000ULL
2796#define AARCH64_ID_AA64ISAR0_EL1_SM3_GET( _reg ) \
2797 ( ( ( _reg ) >> 36 ) & 0xfULL )
2799#define AARCH64_ID_AA64ISAR0_EL1_SM4( _val ) ( ( _val ) << 40 )
2800#define AARCH64_ID_AA64ISAR0_EL1_SM4_SHIFT 40
2801#define AARCH64_ID_AA64ISAR0_EL1_SM4_MASK 0xf0000000000ULL
2802#define AARCH64_ID_AA64ISAR0_EL1_SM4_GET( _reg ) \
2803 ( ( ( _reg ) >> 40 ) & 0xfULL )
2805#define AARCH64_ID_AA64ISAR0_EL1_DP( _val ) ( ( _val ) << 44 )
2806#define AARCH64_ID_AA64ISAR0_EL1_DP_SHIFT 44
2807#define AARCH64_ID_AA64ISAR0_EL1_DP_MASK 0xf00000000000ULL
2808#define AARCH64_ID_AA64ISAR0_EL1_DP_GET( _reg ) \
2809 ( ( ( _reg ) >> 44 ) & 0xfULL )
2811#define AARCH64_ID_AA64ISAR0_EL1_FHM( _val ) ( ( _val ) << 48 )
2812#define AARCH64_ID_AA64ISAR0_EL1_FHM_SHIFT 48
2813#define AARCH64_ID_AA64ISAR0_EL1_FHM_MASK 0xf000000000000ULL
2814#define AARCH64_ID_AA64ISAR0_EL1_FHM_GET( _reg ) \
2815 ( ( ( _reg ) >> 48 ) & 0xfULL )
2817#define AARCH64_ID_AA64ISAR0_EL1_TS( _val ) ( ( _val ) << 52 )
2818#define AARCH64_ID_AA64ISAR0_EL1_TS_SHIFT 52
2819#define AARCH64_ID_AA64ISAR0_EL1_TS_MASK 0xf0000000000000ULL
2820#define AARCH64_ID_AA64ISAR0_EL1_TS_GET( _reg ) \
2821 ( ( ( _reg ) >> 52 ) & 0xfULL )
2823#define AARCH64_ID_AA64ISAR0_EL1_TLB( _val ) ( ( _val ) << 56 )
2824#define AARCH64_ID_AA64ISAR0_EL1_TLB_SHIFT 56
2825#define AARCH64_ID_AA64ISAR0_EL1_TLB_MASK 0xf00000000000000ULL
2826#define AARCH64_ID_AA64ISAR0_EL1_TLB_GET( _reg ) \
2827 ( ( ( _reg ) >> 56 ) & 0xfULL )
2829#define AARCH64_ID_AA64ISAR0_EL1_RNDR( _val ) ( ( _val ) << 60 )
2830#define AARCH64_ID_AA64ISAR0_EL1_RNDR_SHIFT 60
2831#define AARCH64_ID_AA64ISAR0_EL1_RNDR_MASK 0xf000000000000000ULL
2832#define AARCH64_ID_AA64ISAR0_EL1_RNDR_GET( _reg ) \
2833 ( ( ( _reg ) >> 60 ) & 0xfULL )
2835static inline uint64_t _AArch64_Read_id_aa64isar0_el1(
void )
2840 "mrs %0, ID_AA64ISAR0_EL1" :
"=&r" ( value ) : :
"memory"
2848#define AARCH64_ID_AA64ISAR1_EL1_DPB( _val ) ( ( _val ) << 0 )
2849#define AARCH64_ID_AA64ISAR1_EL1_DPB_SHIFT 0
2850#define AARCH64_ID_AA64ISAR1_EL1_DPB_MASK 0xfU
2851#define AARCH64_ID_AA64ISAR1_EL1_DPB_GET( _reg ) \
2852 ( ( ( _reg ) >> 0 ) & 0xfU )
2854#define AARCH64_ID_AA64ISAR1_EL1_APA( _val ) ( ( _val ) << 4 )
2855#define AARCH64_ID_AA64ISAR1_EL1_APA_SHIFT 4
2856#define AARCH64_ID_AA64ISAR1_EL1_APA_MASK 0xf0U
2857#define AARCH64_ID_AA64ISAR1_EL1_APA_GET( _reg ) \
2858 ( ( ( _reg ) >> 4 ) & 0xfU )
2860#define AARCH64_ID_AA64ISAR1_EL1_API( _val ) ( ( _val ) << 8 )
2861#define AARCH64_ID_AA64ISAR1_EL1_API_SHIFT 8
2862#define AARCH64_ID_AA64ISAR1_EL1_API_MASK 0xf00U
2863#define AARCH64_ID_AA64ISAR1_EL1_API_GET( _reg ) \
2864 ( ( ( _reg ) >> 8 ) & 0xfU )
2866#define AARCH64_ID_AA64ISAR1_EL1_JSCVT( _val ) ( ( _val ) << 12 )
2867#define AARCH64_ID_AA64ISAR1_EL1_JSCVT_SHIFT 12
2868#define AARCH64_ID_AA64ISAR1_EL1_JSCVT_MASK 0xf000U
2869#define AARCH64_ID_AA64ISAR1_EL1_JSCVT_GET( _reg ) \
2870 ( ( ( _reg ) >> 12 ) & 0xfU )
2872#define AARCH64_ID_AA64ISAR1_EL1_FCMA( _val ) ( ( _val ) << 16 )
2873#define AARCH64_ID_AA64ISAR1_EL1_FCMA_SHIFT 16
2874#define AARCH64_ID_AA64ISAR1_EL1_FCMA_MASK 0xf0000U
2875#define AARCH64_ID_AA64ISAR1_EL1_FCMA_GET( _reg ) \
2876 ( ( ( _reg ) >> 16 ) & 0xfU )
2878#define AARCH64_ID_AA64ISAR1_EL1_LRCPC( _val ) ( ( _val ) << 20 )
2879#define AARCH64_ID_AA64ISAR1_EL1_LRCPC_SHIFT 20
2880#define AARCH64_ID_AA64ISAR1_EL1_LRCPC_MASK 0xf00000U
2881#define AARCH64_ID_AA64ISAR1_EL1_LRCPC_GET( _reg ) \
2882 ( ( ( _reg ) >> 20 ) & 0xfU )
2884#define AARCH64_ID_AA64ISAR1_EL1_GPA( _val ) ( ( _val ) << 24 )
2885#define AARCH64_ID_AA64ISAR1_EL1_GPA_SHIFT 24
2886#define AARCH64_ID_AA64ISAR1_EL1_GPA_MASK 0xf000000U
2887#define AARCH64_ID_AA64ISAR1_EL1_GPA_GET( _reg ) \
2888 ( ( ( _reg ) >> 24 ) & 0xfU )
2890#define AARCH64_ID_AA64ISAR1_EL1_GPI( _val ) ( ( _val ) << 28 )
2891#define AARCH64_ID_AA64ISAR1_EL1_GPI_SHIFT 28
2892#define AARCH64_ID_AA64ISAR1_EL1_GPI_MASK 0xf0000000U
2893#define AARCH64_ID_AA64ISAR1_EL1_GPI_GET( _reg ) \
2894 ( ( ( _reg ) >> 28 ) & 0xfU )
2896#define AARCH64_ID_AA64ISAR1_EL1_FRINTTS( _val ) ( ( _val ) << 32 )
2897#define AARCH64_ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32
2898#define AARCH64_ID_AA64ISAR1_EL1_FRINTTS_MASK 0xf00000000ULL
2899#define AARCH64_ID_AA64ISAR1_EL1_FRINTTS_GET( _reg ) \
2900 ( ( ( _reg ) >> 32 ) & 0xfULL )
2902#define AARCH64_ID_AA64ISAR1_EL1_SB( _val ) ( ( _val ) << 36 )
2903#define AARCH64_ID_AA64ISAR1_EL1_SB_SHIFT 36
2904#define AARCH64_ID_AA64ISAR1_EL1_SB_MASK 0xf000000000ULL
2905#define AARCH64_ID_AA64ISAR1_EL1_SB_GET( _reg ) \
2906 ( ( ( _reg ) >> 36 ) & 0xfULL )
2908#define AARCH64_ID_AA64ISAR1_EL1_SPECRES( _val ) ( ( _val ) << 40 )
2909#define AARCH64_ID_AA64ISAR1_EL1_SPECRES_SHIFT 40
2910#define AARCH64_ID_AA64ISAR1_EL1_SPECRES_MASK 0xf0000000000ULL
2911#define AARCH64_ID_AA64ISAR1_EL1_SPECRES_GET( _reg ) \
2912 ( ( ( _reg ) >> 40 ) & 0xfULL )
2914#define AARCH64_ID_AA64ISAR1_EL1_BF16( _val ) ( ( _val ) << 44 )
2915#define AARCH64_ID_AA64ISAR1_EL1_BF16_SHIFT 44
2916#define AARCH64_ID_AA64ISAR1_EL1_BF16_MASK 0xf00000000000ULL
2917#define AARCH64_ID_AA64ISAR1_EL1_BF16_GET( _reg ) \
2918 ( ( ( _reg ) >> 44 ) & 0xfULL )
2920#define AARCH64_ID_AA64ISAR1_EL1_DGH( _val ) ( ( _val ) << 48 )
2921#define AARCH64_ID_AA64ISAR1_EL1_DGH_SHIFT 48
2922#define AARCH64_ID_AA64ISAR1_EL1_DGH_MASK 0xf000000000000ULL
2923#define AARCH64_ID_AA64ISAR1_EL1_DGH_GET( _reg ) \
2924 ( ( ( _reg ) >> 48 ) & 0xfULL )
2926#define AARCH64_ID_AA64ISAR1_EL1_I8MM( _val ) ( ( _val ) << 52 )
2927#define AARCH64_ID_AA64ISAR1_EL1_I8MM_SHIFT 52
2928#define AARCH64_ID_AA64ISAR1_EL1_I8MM_MASK 0xf0000000000000ULL
2929#define AARCH64_ID_AA64ISAR1_EL1_I8MM_GET( _reg ) \
2930 ( ( ( _reg ) >> 52 ) & 0xfULL )
2932static inline uint64_t _AArch64_Read_id_aa64isar1_el1(
void )
2937 "mrs %0, ID_AA64ISAR1_EL1" :
"=&r" ( value ) : :
"memory"
2945#define AARCH64_ID_AA64MMFR0_EL1_PARANGE( _val ) ( ( _val ) << 0 )
2946#define AARCH64_ID_AA64MMFR0_EL1_PARANGE_SHIFT 0
2947#define AARCH64_ID_AA64MMFR0_EL1_PARANGE_MASK 0xfU
2948#define AARCH64_ID_AA64MMFR0_EL1_PARANGE_GET( _reg ) \
2949 ( ( ( _reg ) >> 0 ) & 0xfU )
2951#define AARCH64_ID_AA64MMFR0_EL1_ASIDBITS( _val ) ( ( _val ) << 4 )
2952#define AARCH64_ID_AA64MMFR0_EL1_ASIDBITS_SHIFT 4
2953#define AARCH64_ID_AA64MMFR0_EL1_ASIDBITS_MASK 0xf0U
2954#define AARCH64_ID_AA64MMFR0_EL1_ASIDBITS_GET( _reg ) \
2955 ( ( ( _reg ) >> 4 ) & 0xfU )
2957#define AARCH64_ID_AA64MMFR0_EL1_BIGEND( _val ) ( ( _val ) << 8 )
2958#define AARCH64_ID_AA64MMFR0_EL1_BIGEND_SHIFT 8
2959#define AARCH64_ID_AA64MMFR0_EL1_BIGEND_MASK 0xf00U
2960#define AARCH64_ID_AA64MMFR0_EL1_BIGEND_GET( _reg ) \
2961 ( ( ( _reg ) >> 8 ) & 0xfU )
2963#define AARCH64_ID_AA64MMFR0_EL1_SNSMEM( _val ) ( ( _val ) << 12 )
2964#define AARCH64_ID_AA64MMFR0_EL1_SNSMEM_SHIFT 12
2965#define AARCH64_ID_AA64MMFR0_EL1_SNSMEM_MASK 0xf000U
2966#define AARCH64_ID_AA64MMFR0_EL1_SNSMEM_GET( _reg ) \
2967 ( ( ( _reg ) >> 12 ) & 0xfU )
2969#define AARCH64_ID_AA64MMFR0_EL1_BIGENDEL0( _val ) ( ( _val ) << 16 )
2970#define AARCH64_ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT 16
2971#define AARCH64_ID_AA64MMFR0_EL1_BIGENDEL0_MASK 0xf0000U
2972#define AARCH64_ID_AA64MMFR0_EL1_BIGENDEL0_GET( _reg ) \
2973 ( ( ( _reg ) >> 16 ) & 0xfU )
2975#define AARCH64_ID_AA64MMFR0_EL1_TGRAN16( _val ) ( ( _val ) << 20 )
2976#define AARCH64_ID_AA64MMFR0_EL1_TGRAN16_SHIFT 20
2977#define AARCH64_ID_AA64MMFR0_EL1_TGRAN16_MASK 0xf00000U
2978#define AARCH64_ID_AA64MMFR0_EL1_TGRAN16_GET( _reg ) \
2979 ( ( ( _reg ) >> 20 ) & 0xfU )
2981#define AARCH64_ID_AA64MMFR0_EL1_TGRAN64( _val ) ( ( _val ) << 24 )
2982#define AARCH64_ID_AA64MMFR0_EL1_TGRAN64_SHIFT 24
2983#define AARCH64_ID_AA64MMFR0_EL1_TGRAN64_MASK 0xf000000U
2984#define AARCH64_ID_AA64MMFR0_EL1_TGRAN64_GET( _reg ) \
2985 ( ( ( _reg ) >> 24 ) & 0xfU )
2987#define AARCH64_ID_AA64MMFR0_EL1_TGRAN4( _val ) ( ( _val ) << 28 )
2988#define AARCH64_ID_AA64MMFR0_EL1_TGRAN4_SHIFT 28
2989#define AARCH64_ID_AA64MMFR0_EL1_TGRAN4_MASK 0xf0000000U
2990#define AARCH64_ID_AA64MMFR0_EL1_TGRAN4_GET( _reg ) \
2991 ( ( ( _reg ) >> 28 ) & 0xfU )
2993#define AARCH64_ID_AA64MMFR0_EL1_TGRAN16_2( _val ) ( ( _val ) << 32 )
2994#define AARCH64_ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT 32
2995#define AARCH64_ID_AA64MMFR0_EL1_TGRAN16_2_MASK 0xf00000000ULL
2996#define AARCH64_ID_AA64MMFR0_EL1_TGRAN16_2_GET( _reg ) \
2997 ( ( ( _reg ) >> 32 ) & 0xfULL )
2999#define AARCH64_ID_AA64MMFR0_EL1_TGRAN64_2( _val ) ( ( _val ) << 36 )
3000#define AARCH64_ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT 36
3001#define AARCH64_ID_AA64MMFR0_EL1_TGRAN64_2_MASK 0xf000000000ULL
3002#define AARCH64_ID_AA64MMFR0_EL1_TGRAN64_2_GET( _reg ) \
3003 ( ( ( _reg ) >> 36 ) & 0xfULL )
3005#define AARCH64_ID_AA64MMFR0_EL1_TGRAN4_2( _val ) ( ( _val ) << 40 )
3006#define AARCH64_ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT 40
3007#define AARCH64_ID_AA64MMFR0_EL1_TGRAN4_2_MASK 0xf0000000000ULL
3008#define AARCH64_ID_AA64MMFR0_EL1_TGRAN4_2_GET( _reg ) \
3009 ( ( ( _reg ) >> 40 ) & 0xfULL )
3011#define AARCH64_ID_AA64MMFR0_EL1_EXS( _val ) ( ( _val ) << 44 )
3012#define AARCH64_ID_AA64MMFR0_EL1_EXS_SHIFT 44
3013#define AARCH64_ID_AA64MMFR0_EL1_EXS_MASK 0xf00000000000ULL
3014#define AARCH64_ID_AA64MMFR0_EL1_EXS_GET( _reg ) \
3015 ( ( ( _reg ) >> 44 ) & 0xfULL )
3017#define AARCH64_ID_AA64MMFR0_EL1_FGT( _val ) ( ( _val ) << 56 )
3018#define AARCH64_ID_AA64MMFR0_EL1_FGT_SHIFT 56
3019#define AARCH64_ID_AA64MMFR0_EL1_FGT_MASK 0xf00000000000000ULL
3020#define AARCH64_ID_AA64MMFR0_EL1_FGT_GET( _reg ) \
3021 ( ( ( _reg ) >> 56 ) & 0xfULL )
3023#define AARCH64_ID_AA64MMFR0_EL1_ECV( _val ) ( ( _val ) << 60 )
3024#define AARCH64_ID_AA64MMFR0_EL1_ECV_SHIFT 60
3025#define AARCH64_ID_AA64MMFR0_EL1_ECV_MASK 0xf000000000000000ULL
3026#define AARCH64_ID_AA64MMFR0_EL1_ECV_GET( _reg ) \
3027 ( ( ( _reg ) >> 60 ) & 0xfULL )
3029static inline uint64_t _AArch64_Read_id_aa64mmfr0_el1(
void )
3034 "mrs %0, ID_AA64MMFR0_EL1" :
"=&r" ( value ) : :
"memory"
3042#define AARCH64_ID_AA64MMFR1_EL1_HAFDBS( _val ) ( ( _val ) << 0 )
3043#define AARCH64_ID_AA64MMFR1_EL1_HAFDBS_SHIFT 0
3044#define AARCH64_ID_AA64MMFR1_EL1_HAFDBS_MASK 0xfU
3045#define AARCH64_ID_AA64MMFR1_EL1_HAFDBS_GET( _reg ) \
3046 ( ( ( _reg ) >> 0 ) & 0xfU )
3048#define AARCH64_ID_AA64MMFR1_EL1_VMIDBITS( _val ) ( ( _val ) << 4 )
3049#define AARCH64_ID_AA64MMFR1_EL1_VMIDBITS_SHIFT 4
3050#define AARCH64_ID_AA64MMFR1_EL1_VMIDBITS_MASK 0xf0U
3051#define AARCH64_ID_AA64MMFR1_EL1_VMIDBITS_GET( _reg ) \
3052 ( ( ( _reg ) >> 4 ) & 0xfU )
3054#define AARCH64_ID_AA64MMFR1_EL1_VH( _val ) ( ( _val ) << 8 )
3055#define AARCH64_ID_AA64MMFR1_EL1_VH_SHIFT 8
3056#define AARCH64_ID_AA64MMFR1_EL1_VH_MASK 0xf00U
3057#define AARCH64_ID_AA64MMFR1_EL1_VH_GET( _reg ) \
3058 ( ( ( _reg ) >> 8 ) & 0xfU )
3060#define AARCH64_ID_AA64MMFR1_EL1_HPDS( _val ) ( ( _val ) << 12 )
3061#define AARCH64_ID_AA64MMFR1_EL1_HPDS_SHIFT 12
3062#define AARCH64_ID_AA64MMFR1_EL1_HPDS_MASK 0xf000U
3063#define AARCH64_ID_AA64MMFR1_EL1_HPDS_GET( _reg ) \
3064 ( ( ( _reg ) >> 12 ) & 0xfU )
3066#define AARCH64_ID_AA64MMFR1_EL1_LO( _val ) ( ( _val ) << 16 )
3067#define AARCH64_ID_AA64MMFR1_EL1_LO_SHIFT 16
3068#define AARCH64_ID_AA64MMFR1_EL1_LO_MASK 0xf0000U
3069#define AARCH64_ID_AA64MMFR1_EL1_LO_GET( _reg ) \
3070 ( ( ( _reg ) >> 16 ) & 0xfU )
3072#define AARCH64_ID_AA64MMFR1_EL1_PAN( _val ) ( ( _val ) << 20 )
3073#define AARCH64_ID_AA64MMFR1_EL1_PAN_SHIFT 20
3074#define AARCH64_ID_AA64MMFR1_EL1_PAN_MASK 0xf00000U
3075#define AARCH64_ID_AA64MMFR1_EL1_PAN_GET( _reg ) \
3076 ( ( ( _reg ) >> 20 ) & 0xfU )
3078#define AARCH64_ID_AA64MMFR1_EL1_SPECSEI( _val ) ( ( _val ) << 24 )
3079#define AARCH64_ID_AA64MMFR1_EL1_SPECSEI_SHIFT 24
3080#define AARCH64_ID_AA64MMFR1_EL1_SPECSEI_MASK 0xf000000U
3081#define AARCH64_ID_AA64MMFR1_EL1_SPECSEI_GET( _reg ) \
3082 ( ( ( _reg ) >> 24 ) & 0xfU )
3084#define AARCH64_ID_AA64MMFR1_EL1_XNX( _val ) ( ( _val ) << 28 )
3085#define AARCH64_ID_AA64MMFR1_EL1_XNX_SHIFT 28
3086#define AARCH64_ID_AA64MMFR1_EL1_XNX_MASK 0xf0000000U
3087#define AARCH64_ID_AA64MMFR1_EL1_XNX_GET( _reg ) \
3088 ( ( ( _reg ) >> 28 ) & 0xfU )
3090#define AARCH64_ID_AA64MMFR1_EL1_TWED( _val ) ( ( _val ) << 32 )
3091#define AARCH64_ID_AA64MMFR1_EL1_TWED_SHIFT 32
3092#define AARCH64_ID_AA64MMFR1_EL1_TWED_MASK 0xf00000000ULL
3093#define AARCH64_ID_AA64MMFR1_EL1_TWED_GET( _reg ) \
3094 ( ( ( _reg ) >> 32 ) & 0xfULL )
3096#define AARCH64_ID_AA64MMFR1_EL1_ETS( _val ) ( ( _val ) << 36 )
3097#define AARCH64_ID_AA64MMFR1_EL1_ETS_SHIFT 36
3098#define AARCH64_ID_AA64MMFR1_EL1_ETS_MASK 0xf000000000ULL
3099#define AARCH64_ID_AA64MMFR1_EL1_ETS_GET( _reg ) \
3100 ( ( ( _reg ) >> 36 ) & 0xfULL )
3102static inline uint64_t _AArch64_Read_id_aa64mmfr1_el1(
void )
3107 "mrs %0, ID_AA64MMFR1_EL1" :
"=&r" ( value ) : :
"memory"
3115#define AARCH64_ID_AA64MMFR2_EL1_CNP( _val ) ( ( _val ) << 0 )
3116#define AARCH64_ID_AA64MMFR2_EL1_CNP_SHIFT 0
3117#define AARCH64_ID_AA64MMFR2_EL1_CNP_MASK 0xfU
3118#define AARCH64_ID_AA64MMFR2_EL1_CNP_GET( _reg ) \
3119 ( ( ( _reg ) >> 0 ) & 0xfU )
3121#define AARCH64_ID_AA64MMFR2_EL1_UAO( _val ) ( ( _val ) << 4 )
3122#define AARCH64_ID_AA64MMFR2_EL1_UAO_SHIFT 4
3123#define AARCH64_ID_AA64MMFR2_EL1_UAO_MASK 0xf0U
3124#define AARCH64_ID_AA64MMFR2_EL1_UAO_GET( _reg ) \
3125 ( ( ( _reg ) >> 4 ) & 0xfU )
3127#define AARCH64_ID_AA64MMFR2_EL1_LSM( _val ) ( ( _val ) << 8 )
3128#define AARCH64_ID_AA64MMFR2_EL1_LSM_SHIFT 8
3129#define AARCH64_ID_AA64MMFR2_EL1_LSM_MASK 0xf00U
3130#define AARCH64_ID_AA64MMFR2_EL1_LSM_GET( _reg ) \
3131 ( ( ( _reg ) >> 8 ) & 0xfU )
3133#define AARCH64_ID_AA64MMFR2_EL1_IESB( _val ) ( ( _val ) << 12 )
3134#define AARCH64_ID_AA64MMFR2_EL1_IESB_SHIFT 12
3135#define AARCH64_ID_AA64MMFR2_EL1_IESB_MASK 0xf000U
3136#define AARCH64_ID_AA64MMFR2_EL1_IESB_GET( _reg ) \
3137 ( ( ( _reg ) >> 12 ) & 0xfU )
3139#define AARCH64_ID_AA64MMFR2_EL1_VARANGE( _val ) ( ( _val ) << 16 )
3140#define AARCH64_ID_AA64MMFR2_EL1_VARANGE_SHIFT 16
3141#define AARCH64_ID_AA64MMFR2_EL1_VARANGE_MASK 0xf0000U
3142#define AARCH64_ID_AA64MMFR2_EL1_VARANGE_GET( _reg ) \
3143 ( ( ( _reg ) >> 16 ) & 0xfU )
3145#define AARCH64_ID_AA64MMFR2_EL1_CCIDX( _val ) ( ( _val ) << 20 )
3146#define AARCH64_ID_AA64MMFR2_EL1_CCIDX_SHIFT 20
3147#define AARCH64_ID_AA64MMFR2_EL1_CCIDX_MASK 0xf00000U
3148#define AARCH64_ID_AA64MMFR2_EL1_CCIDX_GET( _reg ) \
3149 ( ( ( _reg ) >> 20 ) & 0xfU )
3151#define AARCH64_ID_AA64MMFR2_EL1_NV( _val ) ( ( _val ) << 24 )
3152#define AARCH64_ID_AA64MMFR2_EL1_NV_SHIFT 24
3153#define AARCH64_ID_AA64MMFR2_EL1_NV_MASK 0xf000000U
3154#define AARCH64_ID_AA64MMFR2_EL1_NV_GET( _reg ) \
3155 ( ( ( _reg ) >> 24 ) & 0xfU )
3157#define AARCH64_ID_AA64MMFR2_EL1_ST( _val ) ( ( _val ) << 28 )
3158#define AARCH64_ID_AA64MMFR2_EL1_ST_SHIFT 28
3159#define AARCH64_ID_AA64MMFR2_EL1_ST_MASK 0xf0000000U
3160#define AARCH64_ID_AA64MMFR2_EL1_ST_GET( _reg ) \
3161 ( ( ( _reg ) >> 28 ) & 0xfU )
3163#define AARCH64_ID_AA64MMFR2_EL1_AT( _val ) ( ( _val ) << 32 )
3164#define AARCH64_ID_AA64MMFR2_EL1_AT_SHIFT 32
3165#define AARCH64_ID_AA64MMFR2_EL1_AT_MASK 0xf00000000ULL
3166#define AARCH64_ID_AA64MMFR2_EL1_AT_GET( _reg ) \
3167 ( ( ( _reg ) >> 32 ) & 0xfULL )
3169#define AARCH64_ID_AA64MMFR2_EL1_IDS( _val ) ( ( _val ) << 36 )
3170#define AARCH64_ID_AA64MMFR2_EL1_IDS_SHIFT 36
3171#define AARCH64_ID_AA64MMFR2_EL1_IDS_MASK 0xf000000000ULL
3172#define AARCH64_ID_AA64MMFR2_EL1_IDS_GET( _reg ) \
3173 ( ( ( _reg ) >> 36 ) & 0xfULL )
3175#define AARCH64_ID_AA64MMFR2_EL1_FWB( _val ) ( ( _val ) << 40 )
3176#define AARCH64_ID_AA64MMFR2_EL1_FWB_SHIFT 40
3177#define AARCH64_ID_AA64MMFR2_EL1_FWB_MASK 0xf0000000000ULL
3178#define AARCH64_ID_AA64MMFR2_EL1_FWB_GET( _reg ) \
3179 ( ( ( _reg ) >> 40 ) & 0xfULL )
3181#define AARCH64_ID_AA64MMFR2_EL1_TTL( _val ) ( ( _val ) << 48 )
3182#define AARCH64_ID_AA64MMFR2_EL1_TTL_SHIFT 48
3183#define AARCH64_ID_AA64MMFR2_EL1_TTL_MASK 0xf000000000000ULL
3184#define AARCH64_ID_AA64MMFR2_EL1_TTL_GET( _reg ) \
3185 ( ( ( _reg ) >> 48 ) & 0xfULL )
3187#define AARCH64_ID_AA64MMFR2_EL1_BBM( _val ) ( ( _val ) << 52 )
3188#define AARCH64_ID_AA64MMFR2_EL1_BBM_SHIFT 52
3189#define AARCH64_ID_AA64MMFR2_EL1_BBM_MASK 0xf0000000000000ULL
3190#define AARCH64_ID_AA64MMFR2_EL1_BBM_GET( _reg ) \
3191 ( ( ( _reg ) >> 52 ) & 0xfULL )
3193#define AARCH64_ID_AA64MMFR2_EL1_EVT( _val ) ( ( _val ) << 56 )
3194#define AARCH64_ID_AA64MMFR2_EL1_EVT_SHIFT 56
3195#define AARCH64_ID_AA64MMFR2_EL1_EVT_MASK 0xf00000000000000ULL
3196#define AARCH64_ID_AA64MMFR2_EL1_EVT_GET( _reg ) \
3197 ( ( ( _reg ) >> 56 ) & 0xfULL )
3199#define AARCH64_ID_AA64MMFR2_EL1_E0PD( _val ) ( ( _val ) << 60 )
3200#define AARCH64_ID_AA64MMFR2_EL1_E0PD_SHIFT 60
3201#define AARCH64_ID_AA64MMFR2_EL1_E0PD_MASK 0xf000000000000000ULL
3202#define AARCH64_ID_AA64MMFR2_EL1_E0PD_GET( _reg ) \
3203 ( ( ( _reg ) >> 60 ) & 0xfULL )
3205static inline uint64_t _AArch64_Read_id_aa64mmfr2_el1(
void )
3210 "mrs %0, ID_AA64MMFR2_EL1" :
"=&r" ( value ) : :
"memory"
3218#define AARCH64_ID_AA64PFR0_EL1_EL0( _val ) ( ( _val ) << 0 )
3219#define AARCH64_ID_AA64PFR0_EL1_EL0_SHIFT 0
3220#define AARCH64_ID_AA64PFR0_EL1_EL0_MASK 0xfU
3221#define AARCH64_ID_AA64PFR0_EL1_EL0_GET( _reg ) \
3222 ( ( ( _reg ) >> 0 ) & 0xfU )
3224#define AARCH64_ID_AA64PFR0_EL1_EL1( _val ) ( ( _val ) << 4 )
3225#define AARCH64_ID_AA64PFR0_EL1_EL1_SHIFT 4
3226#define AARCH64_ID_AA64PFR0_EL1_EL1_MASK 0xf0U
3227#define AARCH64_ID_AA64PFR0_EL1_EL1_GET( _reg ) \
3228 ( ( ( _reg ) >> 4 ) & 0xfU )
3230#define AARCH64_ID_AA64PFR0_EL1_EL2( _val ) ( ( _val ) << 8 )
3231#define AARCH64_ID_AA64PFR0_EL1_EL2_SHIFT 8
3232#define AARCH64_ID_AA64PFR0_EL1_EL2_MASK 0xf00U
3233#define AARCH64_ID_AA64PFR0_EL1_EL2_GET( _reg ) \
3234 ( ( ( _reg ) >> 8 ) & 0xfU )
3236#define AARCH64_ID_AA64PFR0_EL1_EL3( _val ) ( ( _val ) << 12 )
3237#define AARCH64_ID_AA64PFR0_EL1_EL3_SHIFT 12
3238#define AARCH64_ID_AA64PFR0_EL1_EL3_MASK 0xf000U
3239#define AARCH64_ID_AA64PFR0_EL1_EL3_GET( _reg ) \
3240 ( ( ( _reg ) >> 12 ) & 0xfU )
3242#define AARCH64_ID_AA64PFR0_EL1_FP( _val ) ( ( _val ) << 16 )
3243#define AARCH64_ID_AA64PFR0_EL1_FP_SHIFT 16
3244#define AARCH64_ID_AA64PFR0_EL1_FP_MASK 0xf0000U
3245#define AARCH64_ID_AA64PFR0_EL1_FP_GET( _reg ) \
3246 ( ( ( _reg ) >> 16 ) & 0xfU )
3248#define AARCH64_ID_AA64PFR0_EL1_ADVSIMD( _val ) ( ( _val ) << 20 )
3249#define AARCH64_ID_AA64PFR0_EL1_ADVSIMD_SHIFT 20
3250#define AARCH64_ID_AA64PFR0_EL1_ADVSIMD_MASK 0xf00000U
3251#define AARCH64_ID_AA64PFR0_EL1_ADVSIMD_GET( _reg ) \
3252 ( ( ( _reg ) >> 20 ) & 0xfU )
3254#define AARCH64_ID_AA64PFR0_EL1_GIC( _val ) ( ( _val ) << 24 )
3255#define AARCH64_ID_AA64PFR0_EL1_GIC_SHIFT 24
3256#define AARCH64_ID_AA64PFR0_EL1_GIC_MASK 0xf000000U
3257#define AARCH64_ID_AA64PFR0_EL1_GIC_GET( _reg ) \
3258 ( ( ( _reg ) >> 24 ) & 0xfU )
3260#define AARCH64_ID_AA64PFR0_EL1_RAS( _val ) ( ( _val ) << 28 )
3261#define AARCH64_ID_AA64PFR0_EL1_RAS_SHIFT 28
3262#define AARCH64_ID_AA64PFR0_EL1_RAS_MASK 0xf0000000U
3263#define AARCH64_ID_AA64PFR0_EL1_RAS_GET( _reg ) \
3264 ( ( ( _reg ) >> 28 ) & 0xfU )
3266#define AARCH64_ID_AA64PFR0_EL1_SVE( _val ) ( ( _val ) << 32 )
3267#define AARCH64_ID_AA64PFR0_EL1_SVE_SHIFT 32
3268#define AARCH64_ID_AA64PFR0_EL1_SVE_MASK 0xf00000000ULL
3269#define AARCH64_ID_AA64PFR0_EL1_SVE_GET( _reg ) \
3270 ( ( ( _reg ) >> 32 ) & 0xfULL )
3272#define AARCH64_ID_AA64PFR0_EL1_SEL2( _val ) ( ( _val ) << 36 )
3273#define AARCH64_ID_AA64PFR0_EL1_SEL2_SHIFT 36
3274#define AARCH64_ID_AA64PFR0_EL1_SEL2_MASK 0xf000000000ULL
3275#define AARCH64_ID_AA64PFR0_EL1_SEL2_GET( _reg ) \
3276 ( ( ( _reg ) >> 36 ) & 0xfULL )
3278#define AARCH64_ID_AA64PFR0_EL1_MPAM( _val ) ( ( _val ) << 40 )
3279#define AARCH64_ID_AA64PFR0_EL1_MPAM_SHIFT 40
3280#define AARCH64_ID_AA64PFR0_EL1_MPAM_MASK 0xf0000000000ULL
3281#define AARCH64_ID_AA64PFR0_EL1_MPAM_GET( _reg ) \
3282 ( ( ( _reg ) >> 40 ) & 0xfULL )
3284#define AARCH64_ID_AA64PFR0_EL1_AMU( _val ) ( ( _val ) << 44 )
3285#define AARCH64_ID_AA64PFR0_EL1_AMU_SHIFT 44
3286#define AARCH64_ID_AA64PFR0_EL1_AMU_MASK 0xf00000000000ULL
3287#define AARCH64_ID_AA64PFR0_EL1_AMU_GET( _reg ) \
3288 ( ( ( _reg ) >> 44 ) & 0xfULL )
3290#define AARCH64_ID_AA64PFR0_EL1_DIT( _val ) ( ( _val ) << 48 )
3291#define AARCH64_ID_AA64PFR0_EL1_DIT_SHIFT 48
3292#define AARCH64_ID_AA64PFR0_EL1_DIT_MASK 0xf000000000000ULL
3293#define AARCH64_ID_AA64PFR0_EL1_DIT_GET( _reg ) \
3294 ( ( ( _reg ) >> 48 ) & 0xfULL )
3296#define AARCH64_ID_AA64PFR0_EL1_CSV2( _val ) ( ( _val ) << 56 )
3297#define AARCH64_ID_AA64PFR0_EL1_CSV2_SHIFT 56
3298#define AARCH64_ID_AA64PFR0_EL1_CSV2_MASK 0xf00000000000000ULL
3299#define AARCH64_ID_AA64PFR0_EL1_CSV2_GET( _reg ) \
3300 ( ( ( _reg ) >> 56 ) & 0xfULL )
3302#define AARCH64_ID_AA64PFR0_EL1_CSV3( _val ) ( ( _val ) << 60 )
3303#define AARCH64_ID_AA64PFR0_EL1_CSV3_SHIFT 60
3304#define AARCH64_ID_AA64PFR0_EL1_CSV3_MASK 0xf000000000000000ULL
3305#define AARCH64_ID_AA64PFR0_EL1_CSV3_GET( _reg ) \
3306 ( ( ( _reg ) >> 60 ) & 0xfULL )
3308static inline uint64_t _AArch64_Read_id_aa64pfr0_el1(
void )
3313 "mrs %0, ID_AA64PFR0_EL1" :
"=&r" ( value ) : :
"memory"
3321#define AARCH64_ID_AA64PFR1_EL1_BT( _val ) ( ( _val ) << 0 )
3322#define AARCH64_ID_AA64PFR1_EL1_BT_SHIFT 0
3323#define AARCH64_ID_AA64PFR1_EL1_BT_MASK 0xfU
3324#define AARCH64_ID_AA64PFR1_EL1_BT_GET( _reg ) \
3325 ( ( ( _reg ) >> 0 ) & 0xfU )
3327#define AARCH64_ID_AA64PFR1_EL1_SSBS( _val ) ( ( _val ) << 4 )
3328#define AARCH64_ID_AA64PFR1_EL1_SSBS_SHIFT 4
3329#define AARCH64_ID_AA64PFR1_EL1_SSBS_MASK 0xf0U
3330#define AARCH64_ID_AA64PFR1_EL1_SSBS_GET( _reg ) \
3331 ( ( ( _reg ) >> 4 ) & 0xfU )
3333#define AARCH64_ID_AA64PFR1_EL1_MTE( _val ) ( ( _val ) << 8 )
3334#define AARCH64_ID_AA64PFR1_EL1_MTE_SHIFT 8
3335#define AARCH64_ID_AA64PFR1_EL1_MTE_MASK 0xf00U
3336#define AARCH64_ID_AA64PFR1_EL1_MTE_GET( _reg ) \
3337 ( ( ( _reg ) >> 8 ) & 0xfU )
3339#define AARCH64_ID_AA64PFR1_EL1_RAS_FRAC( _val ) ( ( _val ) << 12 )
3340#define AARCH64_ID_AA64PFR1_EL1_RAS_FRAC_SHIFT 12
3341#define AARCH64_ID_AA64PFR1_EL1_RAS_FRAC_MASK 0xf000U
3342#define AARCH64_ID_AA64PFR1_EL1_RAS_FRAC_GET( _reg ) \
3343 ( ( ( _reg ) >> 12 ) & 0xfU )
3345#define AARCH64_ID_AA64PFR1_EL1_MPAM_FRAC( _val ) ( ( _val ) << 16 )
3346#define AARCH64_ID_AA64PFR1_EL1_MPAM_FRAC_SHIFT 16
3347#define AARCH64_ID_AA64PFR1_EL1_MPAM_FRAC_MASK 0xf0000U
3348#define AARCH64_ID_AA64PFR1_EL1_MPAM_FRAC_GET( _reg ) \
3349 ( ( ( _reg ) >> 16 ) & 0xfU )
3351static inline uint64_t _AArch64_Read_id_aa64pfr1_el1(
void )
3356 "mrs %0, ID_AA64PFR1_EL1" :
"=&r" ( value ) : :
"memory"
3364static inline uint64_t _AArch64_Read_id_afr0_el1(
void )
3369 "mrs %0, ID_AFR0_EL1" :
"=&r" ( value ) : :
"memory"
3377#define AARCH64_ID_DFR0_EL1_COPDBG( _val ) ( ( _val ) << 0 )
3378#define AARCH64_ID_DFR0_EL1_COPDBG_SHIFT 0
3379#define AARCH64_ID_DFR0_EL1_COPDBG_MASK 0xfU
3380#define AARCH64_ID_DFR0_EL1_COPDBG_GET( _reg ) \
3381 ( ( ( _reg ) >> 0 ) & 0xfU )
3383#define AARCH64_ID_DFR0_EL1_COPSDBG( _val ) ( ( _val ) << 4 )
3384#define AARCH64_ID_DFR0_EL1_COPSDBG_SHIFT 4
3385#define AARCH64_ID_DFR0_EL1_COPSDBG_MASK 0xf0U
3386#define AARCH64_ID_DFR0_EL1_COPSDBG_GET( _reg ) \
3387 ( ( ( _reg ) >> 4 ) & 0xfU )
3389#define AARCH64_ID_DFR0_EL1_MMAPDBG( _val ) ( ( _val ) << 8 )
3390#define AARCH64_ID_DFR0_EL1_MMAPDBG_SHIFT 8
3391#define AARCH64_ID_DFR0_EL1_MMAPDBG_MASK 0xf00U
3392#define AARCH64_ID_DFR0_EL1_MMAPDBG_GET( _reg ) \
3393 ( ( ( _reg ) >> 8 ) & 0xfU )
3395#define AARCH64_ID_DFR0_EL1_COPTRC( _val ) ( ( _val ) << 12 )
3396#define AARCH64_ID_DFR0_EL1_COPTRC_SHIFT 12
3397#define AARCH64_ID_DFR0_EL1_COPTRC_MASK 0xf000U
3398#define AARCH64_ID_DFR0_EL1_COPTRC_GET( _reg ) \
3399 ( ( ( _reg ) >> 12 ) & 0xfU )
3401#define AARCH64_ID_DFR0_EL1_MMAPTRC( _val ) ( ( _val ) << 16 )
3402#define AARCH64_ID_DFR0_EL1_MMAPTRC_SHIFT 16
3403#define AARCH64_ID_DFR0_EL1_MMAPTRC_MASK 0xf0000U
3404#define AARCH64_ID_DFR0_EL1_MMAPTRC_GET( _reg ) \
3405 ( ( ( _reg ) >> 16 ) & 0xfU )
3407#define AARCH64_ID_DFR0_EL1_MPROFDBG( _val ) ( ( _val ) << 20 )
3408#define AARCH64_ID_DFR0_EL1_MPROFDBG_SHIFT 20
3409#define AARCH64_ID_DFR0_EL1_MPROFDBG_MASK 0xf00000U
3410#define AARCH64_ID_DFR0_EL1_MPROFDBG_GET( _reg ) \
3411 ( ( ( _reg ) >> 20 ) & 0xfU )
3413#define AARCH64_ID_DFR0_EL1_PERFMON( _val ) ( ( _val ) << 24 )
3414#define AARCH64_ID_DFR0_EL1_PERFMON_SHIFT 24
3415#define AARCH64_ID_DFR0_EL1_PERFMON_MASK 0xf000000U
3416#define AARCH64_ID_DFR0_EL1_PERFMON_GET( _reg ) \
3417 ( ( ( _reg ) >> 24 ) & 0xfU )
3419#define AARCH64_ID_DFR0_EL1_TRACEFILT( _val ) ( ( _val ) << 28 )
3420#define AARCH64_ID_DFR0_EL1_TRACEFILT_SHIFT 28
3421#define AARCH64_ID_DFR0_EL1_TRACEFILT_MASK 0xf0000000U
3422#define AARCH64_ID_DFR0_EL1_TRACEFILT_GET( _reg ) \
3423 ( ( ( _reg ) >> 28 ) & 0xfU )
3425static inline uint64_t _AArch64_Read_id_dfr0_el1(
void )
3430 "mrs %0, ID_DFR0_EL1" :
"=&r" ( value ) : :
"memory"
3438#define AARCH64_ID_DFR1_EL1_MTPMU( _val ) ( ( _val ) << 0 )
3439#define AARCH64_ID_DFR1_EL1_MTPMU_SHIFT 0
3440#define AARCH64_ID_DFR1_EL1_MTPMU_MASK 0xfU
3441#define AARCH64_ID_DFR1_EL1_MTPMU_GET( _reg ) \
3442 ( ( ( _reg ) >> 0 ) & 0xfU )
3444static inline uint64_t _AArch64_Read_id_dfr1_el1(
void )
3449 "mrs %0, ID_DFR1_EL1" :
"=&r" ( value ) : :
"memory"
3457#define AARCH64_ID_ISAR0_EL1_SWAP( _val ) ( ( _val ) << 0 )
3458#define AARCH64_ID_ISAR0_EL1_SWAP_SHIFT 0
3459#define AARCH64_ID_ISAR0_EL1_SWAP_MASK 0xfU
3460#define AARCH64_ID_ISAR0_EL1_SWAP_GET( _reg ) \
3461 ( ( ( _reg ) >> 0 ) & 0xfU )
3463#define AARCH64_ID_ISAR0_EL1_BITCOUNT( _val ) ( ( _val ) << 4 )
3464#define AARCH64_ID_ISAR0_EL1_BITCOUNT_SHIFT 4
3465#define AARCH64_ID_ISAR0_EL1_BITCOUNT_MASK 0xf0U
3466#define AARCH64_ID_ISAR0_EL1_BITCOUNT_GET( _reg ) \
3467 ( ( ( _reg ) >> 4 ) & 0xfU )
3469#define AARCH64_ID_ISAR0_EL1_BITFIELD( _val ) ( ( _val ) << 8 )
3470#define AARCH64_ID_ISAR0_EL1_BITFIELD_SHIFT 8
3471#define AARCH64_ID_ISAR0_EL1_BITFIELD_MASK 0xf00U
3472#define AARCH64_ID_ISAR0_EL1_BITFIELD_GET( _reg ) \
3473 ( ( ( _reg ) >> 8 ) & 0xfU )
3475#define AARCH64_ID_ISAR0_EL1_CMPBRANCH( _val ) ( ( _val ) << 12 )
3476#define AARCH64_ID_ISAR0_EL1_CMPBRANCH_SHIFT 12
3477#define AARCH64_ID_ISAR0_EL1_CMPBRANCH_MASK 0xf000U
3478#define AARCH64_ID_ISAR0_EL1_CMPBRANCH_GET( _reg ) \
3479 ( ( ( _reg ) >> 12 ) & 0xfU )
3481#define AARCH64_ID_ISAR0_EL1_COPROC( _val ) ( ( _val ) << 16 )
3482#define AARCH64_ID_ISAR0_EL1_COPROC_SHIFT 16
3483#define AARCH64_ID_ISAR0_EL1_COPROC_MASK 0xf0000U
3484#define AARCH64_ID_ISAR0_EL1_COPROC_GET( _reg ) \
3485 ( ( ( _reg ) >> 16 ) & 0xfU )
3487#define AARCH64_ID_ISAR0_EL1_DEBUG( _val ) ( ( _val ) << 20 )
3488#define AARCH64_ID_ISAR0_EL1_DEBUG_SHIFT 20
3489#define AARCH64_ID_ISAR0_EL1_DEBUG_MASK 0xf00000U
3490#define AARCH64_ID_ISAR0_EL1_DEBUG_GET( _reg ) \
3491 ( ( ( _reg ) >> 20 ) & 0xfU )
3493#define AARCH64_ID_ISAR0_EL1_DIVIDE( _val ) ( ( _val ) << 24 )
3494#define AARCH64_ID_ISAR0_EL1_DIVIDE_SHIFT 24
3495#define AARCH64_ID_ISAR0_EL1_DIVIDE_MASK 0xf000000U
3496#define AARCH64_ID_ISAR0_EL1_DIVIDE_GET( _reg ) \
3497 ( ( ( _reg ) >> 24 ) & 0xfU )
3499static inline uint64_t _AArch64_Read_id_isar0_el1(
void )
3504 "mrs %0, ID_ISAR0_EL1" :
"=&r" ( value ) : :
"memory"
3512#define AARCH64_ID_ISAR1_EL1_ENDIAN( _val ) ( ( _val ) << 0 )
3513#define AARCH64_ID_ISAR1_EL1_ENDIAN_SHIFT 0
3514#define AARCH64_ID_ISAR1_EL1_ENDIAN_MASK 0xfU
3515#define AARCH64_ID_ISAR1_EL1_ENDIAN_GET( _reg ) \
3516 ( ( ( _reg ) >> 0 ) & 0xfU )
3518#define AARCH64_ID_ISAR1_EL1_EXCEPT( _val ) ( ( _val ) << 4 )
3519#define AARCH64_ID_ISAR1_EL1_EXCEPT_SHIFT 4
3520#define AARCH64_ID_ISAR1_EL1_EXCEPT_MASK 0xf0U
3521#define AARCH64_ID_ISAR1_EL1_EXCEPT_GET( _reg ) \
3522 ( ( ( _reg ) >> 4 ) & 0xfU )
3524#define AARCH64_ID_ISAR1_EL1_EXCEPT_AR( _val ) ( ( _val ) << 8 )
3525#define AARCH64_ID_ISAR1_EL1_EXCEPT_AR_SHIFT 8
3526#define AARCH64_ID_ISAR1_EL1_EXCEPT_AR_MASK 0xf00U
3527#define AARCH64_ID_ISAR1_EL1_EXCEPT_AR_GET( _reg ) \
3528 ( ( ( _reg ) >> 8 ) & 0xfU )
3530#define AARCH64_ID_ISAR1_EL1_EXTEND( _val ) ( ( _val ) << 12 )
3531#define AARCH64_ID_ISAR1_EL1_EXTEND_SHIFT 12
3532#define AARCH64_ID_ISAR1_EL1_EXTEND_MASK 0xf000U
3533#define AARCH64_ID_ISAR1_EL1_EXTEND_GET( _reg ) \
3534 ( ( ( _reg ) >> 12 ) & 0xfU )
3536#define AARCH64_ID_ISAR1_EL1_IFTHEN( _val ) ( ( _val ) << 16 )
3537#define AARCH64_ID_ISAR1_EL1_IFTHEN_SHIFT 16
3538#define AARCH64_ID_ISAR1_EL1_IFTHEN_MASK 0xf0000U
3539#define AARCH64_ID_ISAR1_EL1_IFTHEN_GET( _reg ) \
3540 ( ( ( _reg ) >> 16 ) & 0xfU )
3542#define AARCH64_ID_ISAR1_EL1_IMMEDIATE( _val ) ( ( _val ) << 20 )
3543#define AARCH64_ID_ISAR1_EL1_IMMEDIATE_SHIFT 20
3544#define AARCH64_ID_ISAR1_EL1_IMMEDIATE_MASK 0xf00000U
3545#define AARCH64_ID_ISAR1_EL1_IMMEDIATE_GET( _reg ) \
3546 ( ( ( _reg ) >> 20 ) & 0xfU )
3548#define AARCH64_ID_ISAR1_EL1_INTERWORK( _val ) ( ( _val ) << 24 )
3549#define AARCH64_ID_ISAR1_EL1_INTERWORK_SHIFT 24
3550#define AARCH64_ID_ISAR1_EL1_INTERWORK_MASK 0xf000000U
3551#define AARCH64_ID_ISAR1_EL1_INTERWORK_GET( _reg ) \
3552 ( ( ( _reg ) >> 24 ) & 0xfU )
3554#define AARCH64_ID_ISAR1_EL1_JAZELLE( _val ) ( ( _val ) << 28 )
3555#define AARCH64_ID_ISAR1_EL1_JAZELLE_SHIFT 28
3556#define AARCH64_ID_ISAR1_EL1_JAZELLE_MASK 0xf0000000U
3557#define AARCH64_ID_ISAR1_EL1_JAZELLE_GET( _reg ) \
3558 ( ( ( _reg ) >> 28 ) & 0xfU )
3560static inline uint64_t _AArch64_Read_id_isar1_el1(
void )
3565 "mrs %0, ID_ISAR1_EL1" :
"=&r" ( value ) : :
"memory"
3573#define AARCH64_ID_ISAR2_EL1_LOADSTORE( _val ) ( ( _val ) << 0 )
3574#define AARCH64_ID_ISAR2_EL1_LOADSTORE_SHIFT 0
3575#define AARCH64_ID_ISAR2_EL1_LOADSTORE_MASK 0xfU
3576#define AARCH64_ID_ISAR2_EL1_LOADSTORE_GET( _reg ) \
3577 ( ( ( _reg ) >> 0 ) & 0xfU )
3579#define AARCH64_ID_ISAR2_EL1_MEMHINT( _val ) ( ( _val ) << 4 )
3580#define AARCH64_ID_ISAR2_EL1_MEMHINT_SHIFT 4
3581#define AARCH64_ID_ISAR2_EL1_MEMHINT_MASK 0xf0U
3582#define AARCH64_ID_ISAR2_EL1_MEMHINT_GET( _reg ) \
3583 ( ( ( _reg ) >> 4 ) & 0xfU )
3585#define AARCH64_ID_ISAR2_EL1_MULTIACCESSINT( _val ) ( ( _val ) << 8 )
3586#define AARCH64_ID_ISAR2_EL1_MULTIACCESSINT_SHIFT 8
3587#define AARCH64_ID_ISAR2_EL1_MULTIACCESSINT_MASK 0xf00U
3588#define AARCH64_ID_ISAR2_EL1_MULTIACCESSINT_GET( _reg ) \
3589 ( ( ( _reg ) >> 8 ) & 0xfU )
3591#define AARCH64_ID_ISAR2_EL1_MULT( _val ) ( ( _val ) << 12 )
3592#define AARCH64_ID_ISAR2_EL1_MULT_SHIFT 12
3593#define AARCH64_ID_ISAR2_EL1_MULT_MASK 0xf000U
3594#define AARCH64_ID_ISAR2_EL1_MULT_GET( _reg ) \
3595 ( ( ( _reg ) >> 12 ) & 0xfU )
3597#define AARCH64_ID_ISAR2_EL1_MULTS( _val ) ( ( _val ) << 16 )
3598#define AARCH64_ID_ISAR2_EL1_MULTS_SHIFT 16
3599#define AARCH64_ID_ISAR2_EL1_MULTS_MASK 0xf0000U
3600#define AARCH64_ID_ISAR2_EL1_MULTS_GET( _reg ) \
3601 ( ( ( _reg ) >> 16 ) & 0xfU )
3603#define AARCH64_ID_ISAR2_EL1_MULTU( _val ) ( ( _val ) << 20 )
3604#define AARCH64_ID_ISAR2_EL1_MULTU_SHIFT 20
3605#define AARCH64_ID_ISAR2_EL1_MULTU_MASK 0xf00000U
3606#define AARCH64_ID_ISAR2_EL1_MULTU_GET( _reg ) \
3607 ( ( ( _reg ) >> 20 ) & 0xfU )
3609#define AARCH64_ID_ISAR2_EL1_PSR_AR( _val ) ( ( _val ) << 24 )
3610#define AARCH64_ID_ISAR2_EL1_PSR_AR_SHIFT 24
3611#define AARCH64_ID_ISAR2_EL1_PSR_AR_MASK 0xf000000U
3612#define AARCH64_ID_ISAR2_EL1_PSR_AR_GET( _reg ) \
3613 ( ( ( _reg ) >> 24 ) & 0xfU )
3615#define AARCH64_ID_ISAR2_EL1_REVERSAL( _val ) ( ( _val ) << 28 )
3616#define AARCH64_ID_ISAR2_EL1_REVERSAL_SHIFT 28
3617#define AARCH64_ID_ISAR2_EL1_REVERSAL_MASK 0xf0000000U
3618#define AARCH64_ID_ISAR2_EL1_REVERSAL_GET( _reg ) \
3619 ( ( ( _reg ) >> 28 ) & 0xfU )
3621static inline uint64_t _AArch64_Read_id_isar2_el1(
void )
3626 "mrs %0, ID_ISAR2_EL1" :
"=&r" ( value ) : :
"memory"
3634#define AARCH64_ID_ISAR3_EL1_SATURATE( _val ) ( ( _val ) << 0 )
3635#define AARCH64_ID_ISAR3_EL1_SATURATE_SHIFT 0
3636#define AARCH64_ID_ISAR3_EL1_SATURATE_MASK 0xfU
3637#define AARCH64_ID_ISAR3_EL1_SATURATE_GET( _reg ) \
3638 ( ( ( _reg ) >> 0 ) & 0xfU )
3640#define AARCH64_ID_ISAR3_EL1_SIMD( _val ) ( ( _val ) << 4 )
3641#define AARCH64_ID_ISAR3_EL1_SIMD_SHIFT 4
3642#define AARCH64_ID_ISAR3_EL1_SIMD_MASK 0xf0U
3643#define AARCH64_ID_ISAR3_EL1_SIMD_GET( _reg ) \
3644 ( ( ( _reg ) >> 4 ) & 0xfU )
3646#define AARCH64_ID_ISAR3_EL1_SVC( _val ) ( ( _val ) << 8 )
3647#define AARCH64_ID_ISAR3_EL1_SVC_SHIFT 8
3648#define AARCH64_ID_ISAR3_EL1_SVC_MASK 0xf00U
3649#define AARCH64_ID_ISAR3_EL1_SVC_GET( _reg ) \
3650 ( ( ( _reg ) >> 8 ) & 0xfU )
3652#define AARCH64_ID_ISAR3_EL1_SYNCHPRIM( _val ) ( ( _val ) << 12 )
3653#define AARCH64_ID_ISAR3_EL1_SYNCHPRIM_SHIFT 12
3654#define AARCH64_ID_ISAR3_EL1_SYNCHPRIM_MASK 0xf000U
3655#define AARCH64_ID_ISAR3_EL1_SYNCHPRIM_GET( _reg ) \
3656 ( ( ( _reg ) >> 12 ) & 0xfU )
3658#define AARCH64_ID_ISAR3_EL1_TABBRANCH( _val ) ( ( _val ) << 16 )
3659#define AARCH64_ID_ISAR3_EL1_TABBRANCH_SHIFT 16
3660#define AARCH64_ID_ISAR3_EL1_TABBRANCH_MASK 0xf0000U
3661#define AARCH64_ID_ISAR3_EL1_TABBRANCH_GET( _reg ) \
3662 ( ( ( _reg ) >> 16 ) & 0xfU )
3664#define AARCH64_ID_ISAR3_EL1_T32COPY( _val ) ( ( _val ) << 20 )
3665#define AARCH64_ID_ISAR3_EL1_T32COPY_SHIFT 20
3666#define AARCH64_ID_ISAR3_EL1_T32COPY_MASK 0xf00000U
3667#define AARCH64_ID_ISAR3_EL1_T32COPY_GET( _reg ) \
3668 ( ( ( _reg ) >> 20 ) & 0xfU )
3670#define AARCH64_ID_ISAR3_EL1_TRUENOP( _val ) ( ( _val ) << 24 )
3671#define AARCH64_ID_ISAR3_EL1_TRUENOP_SHIFT 24
3672#define AARCH64_ID_ISAR3_EL1_TRUENOP_MASK 0xf000000U
3673#define AARCH64_ID_ISAR3_EL1_TRUENOP_GET( _reg ) \
3674 ( ( ( _reg ) >> 24 ) & 0xfU )
3676#define AARCH64_ID_ISAR3_EL1_T32EE( _val ) ( ( _val ) << 28 )
3677#define AARCH64_ID_ISAR3_EL1_T32EE_SHIFT 28
3678#define AARCH64_ID_ISAR3_EL1_T32EE_MASK 0xf0000000U
3679#define AARCH64_ID_ISAR3_EL1_T32EE_GET( _reg ) \
3680 ( ( ( _reg ) >> 28 ) & 0xfU )
3682static inline uint64_t _AArch64_Read_id_isar3_el1(
void )
3687 "mrs %0, ID_ISAR3_EL1" :
"=&r" ( value ) : :
"memory"
3695#define AARCH64_ID_ISAR4_EL1_UNPRIV( _val ) ( ( _val ) << 0 )
3696#define AARCH64_ID_ISAR4_EL1_UNPRIV_SHIFT 0
3697#define AARCH64_ID_ISAR4_EL1_UNPRIV_MASK 0xfU
3698#define AARCH64_ID_ISAR4_EL1_UNPRIV_GET( _reg ) \
3699 ( ( ( _reg ) >> 0 ) & 0xfU )
3701#define AARCH64_ID_ISAR4_EL1_WITHSHIFTS( _val ) ( ( _val ) << 4 )
3702#define AARCH64_ID_ISAR4_EL1_WITHSHIFTS_SHIFT 4
3703#define AARCH64_ID_ISAR4_EL1_WITHSHIFTS_MASK 0xf0U
3704#define AARCH64_ID_ISAR4_EL1_WITHSHIFTS_GET( _reg ) \
3705 ( ( ( _reg ) >> 4 ) & 0xfU )
3707#define AARCH64_ID_ISAR4_EL1_WRITEBACK( _val ) ( ( _val ) << 8 )
3708#define AARCH64_ID_ISAR4_EL1_WRITEBACK_SHIFT 8
3709#define AARCH64_ID_ISAR4_EL1_WRITEBACK_MASK 0xf00U
3710#define AARCH64_ID_ISAR4_EL1_WRITEBACK_GET( _reg ) \
3711 ( ( ( _reg ) >> 8 ) & 0xfU )
3713#define AARCH64_ID_ISAR4_EL1_SMC( _val ) ( ( _val ) << 12 )
3714#define AARCH64_ID_ISAR4_EL1_SMC_SHIFT 12
3715#define AARCH64_ID_ISAR4_EL1_SMC_MASK 0xf000U
3716#define AARCH64_ID_ISAR4_EL1_SMC_GET( _reg ) \
3717 ( ( ( _reg ) >> 12 ) & 0xfU )
3719#define AARCH64_ID_ISAR4_EL1_BARRIER( _val ) ( ( _val ) << 16 )
3720#define AARCH64_ID_ISAR4_EL1_BARRIER_SHIFT 16
3721#define AARCH64_ID_ISAR4_EL1_BARRIER_MASK 0xf0000U
3722#define AARCH64_ID_ISAR4_EL1_BARRIER_GET( _reg ) \
3723 ( ( ( _reg ) >> 16 ) & 0xfU )
3725#define AARCH64_ID_ISAR4_EL1_SYNCHPRIM_FRAC( _val ) ( ( _val ) << 20 )
3726#define AARCH64_ID_ISAR4_EL1_SYNCHPRIM_FRAC_SHIFT 20
3727#define AARCH64_ID_ISAR4_EL1_SYNCHPRIM_FRAC_MASK 0xf00000U
3728#define AARCH64_ID_ISAR4_EL1_SYNCHPRIM_FRAC_GET( _reg ) \
3729 ( ( ( _reg ) >> 20 ) & 0xfU )
3731#define AARCH64_ID_ISAR4_EL1_PSR_M( _val ) ( ( _val ) << 24 )
3732#define AARCH64_ID_ISAR4_EL1_PSR_M_SHIFT 24
3733#define AARCH64_ID_ISAR4_EL1_PSR_M_MASK 0xf000000U
3734#define AARCH64_ID_ISAR4_EL1_PSR_M_GET( _reg ) \
3735 ( ( ( _reg ) >> 24 ) & 0xfU )
3737#define AARCH64_ID_ISAR4_EL1_SWP_FRAC( _val ) ( ( _val ) << 28 )
3738#define AARCH64_ID_ISAR4_EL1_SWP_FRAC_SHIFT 28
3739#define AARCH64_ID_ISAR4_EL1_SWP_FRAC_MASK 0xf0000000U
3740#define AARCH64_ID_ISAR4_EL1_SWP_FRAC_GET( _reg ) \
3741 ( ( ( _reg ) >> 28 ) & 0xfU )
3743static inline uint64_t _AArch64_Read_id_isar4_el1(
void )
3748 "mrs %0, ID_ISAR4_EL1" :
"=&r" ( value ) : :
"memory"
3756#define AARCH64_ID_ISAR5_EL1_SEVL( _val ) ( ( _val ) << 0 )
3757#define AARCH64_ID_ISAR5_EL1_SEVL_SHIFT 0
3758#define AARCH64_ID_ISAR5_EL1_SEVL_MASK 0xfU
3759#define AARCH64_ID_ISAR5_EL1_SEVL_GET( _reg ) \
3760 ( ( ( _reg ) >> 0 ) & 0xfU )
3762#define AARCH64_ID_ISAR5_EL1_AES( _val ) ( ( _val ) << 4 )
3763#define AARCH64_ID_ISAR5_EL1_AES_SHIFT 4
3764#define AARCH64_ID_ISAR5_EL1_AES_MASK 0xf0U
3765#define AARCH64_ID_ISAR5_EL1_AES_GET( _reg ) \
3766 ( ( ( _reg ) >> 4 ) & 0xfU )
3768#define AARCH64_ID_ISAR5_EL1_SHA1( _val ) ( ( _val ) << 8 )
3769#define AARCH64_ID_ISAR5_EL1_SHA1_SHIFT 8
3770#define AARCH64_ID_ISAR5_EL1_SHA1_MASK 0xf00U
3771#define AARCH64_ID_ISAR5_EL1_SHA1_GET( _reg ) \
3772 ( ( ( _reg ) >> 8 ) & 0xfU )
3774#define AARCH64_ID_ISAR5_EL1_SHA2( _val ) ( ( _val ) << 12 )
3775#define AARCH64_ID_ISAR5_EL1_SHA2_SHIFT 12
3776#define AARCH64_ID_ISAR5_EL1_SHA2_MASK 0xf000U
3777#define AARCH64_ID_ISAR5_EL1_SHA2_GET( _reg ) \
3778 ( ( ( _reg ) >> 12 ) & 0xfU )
3780#define AARCH64_ID_ISAR5_EL1_CRC32( _val ) ( ( _val ) << 16 )
3781#define AARCH64_ID_ISAR5_EL1_CRC32_SHIFT 16
3782#define AARCH64_ID_ISAR5_EL1_CRC32_MASK 0xf0000U
3783#define AARCH64_ID_ISAR5_EL1_CRC32_GET( _reg ) \
3784 ( ( ( _reg ) >> 16 ) & 0xfU )
3786#define AARCH64_ID_ISAR5_EL1_RDM( _val ) ( ( _val ) << 24 )
3787#define AARCH64_ID_ISAR5_EL1_RDM_SHIFT 24
3788#define AARCH64_ID_ISAR5_EL1_RDM_MASK 0xf000000U
3789#define AARCH64_ID_ISAR5_EL1_RDM_GET( _reg ) \
3790 ( ( ( _reg ) >> 24 ) & 0xfU )
3792#define AARCH64_ID_ISAR5_EL1_VCMA( _val ) ( ( _val ) << 28 )
3793#define AARCH64_ID_ISAR5_EL1_VCMA_SHIFT 28
3794#define AARCH64_ID_ISAR5_EL1_VCMA_MASK 0xf0000000U
3795#define AARCH64_ID_ISAR5_EL1_VCMA_GET( _reg ) \
3796 ( ( ( _reg ) >> 28 ) & 0xfU )
3798static inline uint64_t _AArch64_Read_id_isar5_el1(
void )
3803 "mrs %0, ID_ISAR5_EL1" :
"=&r" ( value ) : :
"memory"
3811#define AARCH64_ID_ISAR6_EL1_JSCVT( _val ) ( ( _val ) << 0 )
3812#define AARCH64_ID_ISAR6_EL1_JSCVT_SHIFT 0
3813#define AARCH64_ID_ISAR6_EL1_JSCVT_MASK 0xfU
3814#define AARCH64_ID_ISAR6_EL1_JSCVT_GET( _reg ) \
3815 ( ( ( _reg ) >> 0 ) & 0xfU )
3817#define AARCH64_ID_ISAR6_EL1_DP( _val ) ( ( _val ) << 4 )
3818#define AARCH64_ID_ISAR6_EL1_DP_SHIFT 4
3819#define AARCH64_ID_ISAR6_EL1_DP_MASK 0xf0U
3820#define AARCH64_ID_ISAR6_EL1_DP_GET( _reg ) \
3821 ( ( ( _reg ) >> 4 ) & 0xfU )
3823#define AARCH64_ID_ISAR6_EL1_FHM( _val ) ( ( _val ) << 8 )
3824#define AARCH64_ID_ISAR6_EL1_FHM_SHIFT 8
3825#define AARCH64_ID_ISAR6_EL1_FHM_MASK 0xf00U
3826#define AARCH64_ID_ISAR6_EL1_FHM_GET( _reg ) \
3827 ( ( ( _reg ) >> 8 ) & 0xfU )
3829#define AARCH64_ID_ISAR6_EL1_SB( _val ) ( ( _val ) << 12 )
3830#define AARCH64_ID_ISAR6_EL1_SB_SHIFT 12
3831#define AARCH64_ID_ISAR6_EL1_SB_MASK 0xf000U
3832#define AARCH64_ID_ISAR6_EL1_SB_GET( _reg ) \
3833 ( ( ( _reg ) >> 12 ) & 0xfU )
3835#define AARCH64_ID_ISAR6_EL1_SPECRES( _val ) ( ( _val ) << 16 )
3836#define AARCH64_ID_ISAR6_EL1_SPECRES_SHIFT 16
3837#define AARCH64_ID_ISAR6_EL1_SPECRES_MASK 0xf0000U
3838#define AARCH64_ID_ISAR6_EL1_SPECRES_GET( _reg ) \
3839 ( ( ( _reg ) >> 16 ) & 0xfU )
3841#define AARCH64_ID_ISAR6_EL1_BF16( _val ) ( ( _val ) << 20 )
3842#define AARCH64_ID_ISAR6_EL1_BF16_SHIFT 20
3843#define AARCH64_ID_ISAR6_EL1_BF16_MASK 0xf00000U
3844#define AARCH64_ID_ISAR6_EL1_BF16_GET( _reg ) \
3845 ( ( ( _reg ) >> 20 ) & 0xfU )
3847#define AARCH64_ID_ISAR6_EL1_I8MM( _val ) ( ( _val ) << 24 )
3848#define AARCH64_ID_ISAR6_EL1_I8MM_SHIFT 24
3849#define AARCH64_ID_ISAR6_EL1_I8MM_MASK 0xf000000U
3850#define AARCH64_ID_ISAR6_EL1_I8MM_GET( _reg ) \
3851 ( ( ( _reg ) >> 24 ) & 0xfU )
3853static inline uint64_t _AArch64_Read_id_isar6_el1(
void )
3858 "mrs %0, ID_ISAR6_EL1" :
"=&r" ( value ) : :
"memory"
3866#define AARCH64_ID_MMFR0_EL1_VMSA( _val ) ( ( _val ) << 0 )
3867#define AARCH64_ID_MMFR0_EL1_VMSA_SHIFT 0
3868#define AARCH64_ID_MMFR0_EL1_VMSA_MASK 0xfU
3869#define AARCH64_ID_MMFR0_EL1_VMSA_GET( _reg ) \
3870 ( ( ( _reg ) >> 0 ) & 0xfU )
3872#define AARCH64_ID_MMFR0_EL1_PMSA( _val ) ( ( _val ) << 4 )
3873#define AARCH64_ID_MMFR0_EL1_PMSA_SHIFT 4
3874#define AARCH64_ID_MMFR0_EL1_PMSA_MASK 0xf0U
3875#define AARCH64_ID_MMFR0_EL1_PMSA_GET( _reg ) \
3876 ( ( ( _reg ) >> 4 ) & 0xfU )
3878#define AARCH64_ID_MMFR0_EL1_OUTERSHR( _val ) ( ( _val ) << 8 )
3879#define AARCH64_ID_MMFR0_EL1_OUTERSHR_SHIFT 8
3880#define AARCH64_ID_MMFR0_EL1_OUTERSHR_MASK 0xf00U
3881#define AARCH64_ID_MMFR0_EL1_OUTERSHR_GET( _reg ) \
3882 ( ( ( _reg ) >> 8 ) & 0xfU )
3884#define AARCH64_ID_MMFR0_EL1_SHARELVL( _val ) ( ( _val ) << 12 )
3885#define AARCH64_ID_MMFR0_EL1_SHARELVL_SHIFT 12
3886#define AARCH64_ID_MMFR0_EL1_SHARELVL_MASK 0xf000U
3887#define AARCH64_ID_MMFR0_EL1_SHARELVL_GET( _reg ) \
3888 ( ( ( _reg ) >> 12 ) & 0xfU )
3890#define AARCH64_ID_MMFR0_EL1_TCM( _val ) ( ( _val ) << 16 )
3891#define AARCH64_ID_MMFR0_EL1_TCM_SHIFT 16
3892#define AARCH64_ID_MMFR0_EL1_TCM_MASK 0xf0000U
3893#define AARCH64_ID_MMFR0_EL1_TCM_GET( _reg ) \
3894 ( ( ( _reg ) >> 16 ) & 0xfU )
3896#define AARCH64_ID_MMFR0_EL1_AUXREG( _val ) ( ( _val ) << 20 )
3897#define AARCH64_ID_MMFR0_EL1_AUXREG_SHIFT 20
3898#define AARCH64_ID_MMFR0_EL1_AUXREG_MASK 0xf00000U
3899#define AARCH64_ID_MMFR0_EL1_AUXREG_GET( _reg ) \
3900 ( ( ( _reg ) >> 20 ) & 0xfU )
3902#define AARCH64_ID_MMFR0_EL1_FCSE( _val ) ( ( _val ) << 24 )
3903#define AARCH64_ID_MMFR0_EL1_FCSE_SHIFT 24
3904#define AARCH64_ID_MMFR0_EL1_FCSE_MASK 0xf000000U
3905#define AARCH64_ID_MMFR0_EL1_FCSE_GET( _reg ) \
3906 ( ( ( _reg ) >> 24 ) & 0xfU )
3908#define AARCH64_ID_MMFR0_EL1_INNERSHR( _val ) ( ( _val ) << 28 )
3909#define AARCH64_ID_MMFR0_EL1_INNERSHR_SHIFT 28
3910#define AARCH64_ID_MMFR0_EL1_INNERSHR_MASK 0xf0000000U
3911#define AARCH64_ID_MMFR0_EL1_INNERSHR_GET( _reg ) \
3912 ( ( ( _reg ) >> 28 ) & 0xfU )
3914static inline uint64_t _AArch64_Read_id_mmfr0_el1(
void )
3919 "mrs %0, ID_MMFR0_EL1" :
"=&r" ( value ) : :
"memory"
3927#define AARCH64_ID_MMFR1_EL1_L1HVDVA( _val ) ( ( _val ) << 0 )
3928#define AARCH64_ID_MMFR1_EL1_L1HVDVA_SHIFT 0
3929#define AARCH64_ID_MMFR1_EL1_L1HVDVA_MASK 0xfU
3930#define AARCH64_ID_MMFR1_EL1_L1HVDVA_GET( _reg ) \
3931 ( ( ( _reg ) >> 0 ) & 0xfU )
3933#define AARCH64_ID_MMFR1_EL1_L1UNIVA( _val ) ( ( _val ) << 4 )
3934#define AARCH64_ID_MMFR1_EL1_L1UNIVA_SHIFT 4
3935#define AARCH64_ID_MMFR1_EL1_L1UNIVA_MASK 0xf0U
3936#define AARCH64_ID_MMFR1_EL1_L1UNIVA_GET( _reg ) \
3937 ( ( ( _reg ) >> 4 ) & 0xfU )
3939#define AARCH64_ID_MMFR1_EL1_L1HVDSW( _val ) ( ( _val ) << 8 )
3940#define AARCH64_ID_MMFR1_EL1_L1HVDSW_SHIFT 8
3941#define AARCH64_ID_MMFR1_EL1_L1HVDSW_MASK 0xf00U
3942#define AARCH64_ID_MMFR1_EL1_L1HVDSW_GET( _reg ) \
3943 ( ( ( _reg ) >> 8 ) & 0xfU )
3945#define AARCH64_ID_MMFR1_EL1_L1UNISW( _val ) ( ( _val ) << 12 )
3946#define AARCH64_ID_MMFR1_EL1_L1UNISW_SHIFT 12
3947#define AARCH64_ID_MMFR1_EL1_L1UNISW_MASK 0xf000U
3948#define AARCH64_ID_MMFR1_EL1_L1UNISW_GET( _reg ) \
3949 ( ( ( _reg ) >> 12 ) & 0xfU )
3951#define AARCH64_ID_MMFR1_EL1_L1HVD( _val ) ( ( _val ) << 16 )
3952#define AARCH64_ID_MMFR1_EL1_L1HVD_SHIFT 16
3953#define AARCH64_ID_MMFR1_EL1_L1HVD_MASK 0xf0000U
3954#define AARCH64_ID_MMFR1_EL1_L1HVD_GET( _reg ) \
3955 ( ( ( _reg ) >> 16 ) & 0xfU )
3957#define AARCH64_ID_MMFR1_EL1_L1UNI( _val ) ( ( _val ) << 20 )
3958#define AARCH64_ID_MMFR1_EL1_L1UNI_SHIFT 20
3959#define AARCH64_ID_MMFR1_EL1_L1UNI_MASK 0xf00000U
3960#define AARCH64_ID_MMFR1_EL1_L1UNI_GET( _reg ) \
3961 ( ( ( _reg ) >> 20 ) & 0xfU )
3963#define AARCH64_ID_MMFR1_EL1_L1TSTCLN( _val ) ( ( _val ) << 24 )
3964#define AARCH64_ID_MMFR1_EL1_L1TSTCLN_SHIFT 24
3965#define AARCH64_ID_MMFR1_EL1_L1TSTCLN_MASK 0xf000000U
3966#define AARCH64_ID_MMFR1_EL1_L1TSTCLN_GET( _reg ) \
3967 ( ( ( _reg ) >> 24 ) & 0xfU )
3969#define AARCH64_ID_MMFR1_EL1_BPRED( _val ) ( ( _val ) << 28 )
3970#define AARCH64_ID_MMFR1_EL1_BPRED_SHIFT 28
3971#define AARCH64_ID_MMFR1_EL1_BPRED_MASK 0xf0000000U
3972#define AARCH64_ID_MMFR1_EL1_BPRED_GET( _reg ) \
3973 ( ( ( _reg ) >> 28 ) & 0xfU )
3975static inline uint64_t _AArch64_Read_id_mmfr1_el1(
void )
3980 "mrs %0, ID_MMFR1_EL1" :
"=&r" ( value ) : :
"memory"
3988#define AARCH64_ID_MMFR2_EL1_L1HVDFG( _val ) ( ( _val ) << 0 )
3989#define AARCH64_ID_MMFR2_EL1_L1HVDFG_SHIFT 0
3990#define AARCH64_ID_MMFR2_EL1_L1HVDFG_MASK 0xfU
3991#define AARCH64_ID_MMFR2_EL1_L1HVDFG_GET( _reg ) \
3992 ( ( ( _reg ) >> 0 ) & 0xfU )
3994#define AARCH64_ID_MMFR2_EL1_L1HVDBG( _val ) ( ( _val ) << 4 )
3995#define AARCH64_ID_MMFR2_EL1_L1HVDBG_SHIFT 4
3996#define AARCH64_ID_MMFR2_EL1_L1HVDBG_MASK 0xf0U
3997#define AARCH64_ID_MMFR2_EL1_L1HVDBG_GET( _reg ) \
3998 ( ( ( _reg ) >> 4 ) & 0xfU )
4000#define AARCH64_ID_MMFR2_EL1_L1HVDRNG( _val ) ( ( _val ) << 8 )
4001#define AARCH64_ID_MMFR2_EL1_L1HVDRNG_SHIFT 8
4002#define AARCH64_ID_MMFR2_EL1_L1HVDRNG_MASK 0xf00U
4003#define AARCH64_ID_MMFR2_EL1_L1HVDRNG_GET( _reg ) \
4004 ( ( ( _reg ) >> 8 ) & 0xfU )
4006#define AARCH64_ID_MMFR2_EL1_HVDTLB( _val ) ( ( _val ) << 12 )
4007#define AARCH64_ID_MMFR2_EL1_HVDTLB_SHIFT 12
4008#define AARCH64_ID_MMFR2_EL1_HVDTLB_MASK 0xf000U
4009#define AARCH64_ID_MMFR2_EL1_HVDTLB_GET( _reg ) \
4010 ( ( ( _reg ) >> 12 ) & 0xfU )
4012#define AARCH64_ID_MMFR2_EL1_UNITLB( _val ) ( ( _val ) << 16 )
4013#define AARCH64_ID_MMFR2_EL1_UNITLB_SHIFT 16
4014#define AARCH64_ID_MMFR2_EL1_UNITLB_MASK 0xf0000U
4015#define AARCH64_ID_MMFR2_EL1_UNITLB_GET( _reg ) \
4016 ( ( ( _reg ) >> 16 ) & 0xfU )
4018#define AARCH64_ID_MMFR2_EL1_MEMBARR( _val ) ( ( _val ) << 20 )
4019#define AARCH64_ID_MMFR2_EL1_MEMBARR_SHIFT 20
4020#define AARCH64_ID_MMFR2_EL1_MEMBARR_MASK 0xf00000U
4021#define AARCH64_ID_MMFR2_EL1_MEMBARR_GET( _reg ) \
4022 ( ( ( _reg ) >> 20 ) & 0xfU )
4024#define AARCH64_ID_MMFR2_EL1_WFISTALL( _val ) ( ( _val ) << 24 )
4025#define AARCH64_ID_MMFR2_EL1_WFISTALL_SHIFT 24
4026#define AARCH64_ID_MMFR2_EL1_WFISTALL_MASK 0xf000000U
4027#define AARCH64_ID_MMFR2_EL1_WFISTALL_GET( _reg ) \
4028 ( ( ( _reg ) >> 24 ) & 0xfU )
4030#define AARCH64_ID_MMFR2_EL1_HWACCFLG( _val ) ( ( _val ) << 28 )
4031#define AARCH64_ID_MMFR2_EL1_HWACCFLG_SHIFT 28
4032#define AARCH64_ID_MMFR2_EL1_HWACCFLG_MASK 0xf0000000U
4033#define AARCH64_ID_MMFR2_EL1_HWACCFLG_GET( _reg ) \
4034 ( ( ( _reg ) >> 28 ) & 0xfU )
4036static inline uint64_t _AArch64_Read_id_mmfr2_el1(
void )
4041 "mrs %0, ID_MMFR2_EL1" :
"=&r" ( value ) : :
"memory"
4049#define AARCH64_ID_MMFR3_EL1_CMAINTVA( _val ) ( ( _val ) << 0 )
4050#define AARCH64_ID_MMFR3_EL1_CMAINTVA_SHIFT 0
4051#define AARCH64_ID_MMFR3_EL1_CMAINTVA_MASK 0xfU
4052#define AARCH64_ID_MMFR3_EL1_CMAINTVA_GET( _reg ) \
4053 ( ( ( _reg ) >> 0 ) & 0xfU )
4055#define AARCH64_ID_MMFR3_EL1_CMAINTSW( _val ) ( ( _val ) << 4 )
4056#define AARCH64_ID_MMFR3_EL1_CMAINTSW_SHIFT 4
4057#define AARCH64_ID_MMFR3_EL1_CMAINTSW_MASK 0xf0U
4058#define AARCH64_ID_MMFR3_EL1_CMAINTSW_GET( _reg ) \
4059 ( ( ( _reg ) >> 4 ) & 0xfU )
4061#define AARCH64_ID_MMFR3_EL1_BPMAINT( _val ) ( ( _val ) << 8 )
4062#define AARCH64_ID_MMFR3_EL1_BPMAINT_SHIFT 8
4063#define AARCH64_ID_MMFR3_EL1_BPMAINT_MASK 0xf00U
4064#define AARCH64_ID_MMFR3_EL1_BPMAINT_GET( _reg ) \
4065 ( ( ( _reg ) >> 8 ) & 0xfU )
4067#define AARCH64_ID_MMFR3_EL1_MAINTBCST( _val ) ( ( _val ) << 12 )
4068#define AARCH64_ID_MMFR3_EL1_MAINTBCST_SHIFT 12
4069#define AARCH64_ID_MMFR3_EL1_MAINTBCST_MASK 0xf000U
4070#define AARCH64_ID_MMFR3_EL1_MAINTBCST_GET( _reg ) \
4071 ( ( ( _reg ) >> 12 ) & 0xfU )
4073#define AARCH64_ID_MMFR3_EL1_PAN( _val ) ( ( _val ) << 16 )
4074#define AARCH64_ID_MMFR3_EL1_PAN_SHIFT 16
4075#define AARCH64_ID_MMFR3_EL1_PAN_MASK 0xf0000U
4076#define AARCH64_ID_MMFR3_EL1_PAN_GET( _reg ) \
4077 ( ( ( _reg ) >> 16 ) & 0xfU )
4079#define AARCH64_ID_MMFR3_EL1_COHWALK( _val ) ( ( _val ) << 20 )
4080#define AARCH64_ID_MMFR3_EL1_COHWALK_SHIFT 20
4081#define AARCH64_ID_MMFR3_EL1_COHWALK_MASK 0xf00000U
4082#define AARCH64_ID_MMFR3_EL1_COHWALK_GET( _reg ) \
4083 ( ( ( _reg ) >> 20 ) & 0xfU )
4085#define AARCH64_ID_MMFR3_EL1_CMEMSZ( _val ) ( ( _val ) << 24 )
4086#define AARCH64_ID_MMFR3_EL1_CMEMSZ_SHIFT 24
4087#define AARCH64_ID_MMFR3_EL1_CMEMSZ_MASK 0xf000000U
4088#define AARCH64_ID_MMFR3_EL1_CMEMSZ_GET( _reg ) \
4089 ( ( ( _reg ) >> 24 ) & 0xfU )
4091#define AARCH64_ID_MMFR3_EL1_SUPERSEC( _val ) ( ( _val ) << 28 )
4092#define AARCH64_ID_MMFR3_EL1_SUPERSEC_SHIFT 28
4093#define AARCH64_ID_MMFR3_EL1_SUPERSEC_MASK 0xf0000000U
4094#define AARCH64_ID_MMFR3_EL1_SUPERSEC_GET( _reg ) \
4095 ( ( ( _reg ) >> 28 ) & 0xfU )
4097static inline uint64_t _AArch64_Read_id_mmfr3_el1(
void )
4102 "mrs %0, ID_MMFR3_EL1" :
"=&r" ( value ) : :
"memory"
4110#define AARCH64_ID_MMFR4_EL1_SPECSEI( _val ) ( ( _val ) << 0 )
4111#define AARCH64_ID_MMFR4_EL1_SPECSEI_SHIFT 0
4112#define AARCH64_ID_MMFR4_EL1_SPECSEI_MASK 0xfU
4113#define AARCH64_ID_MMFR4_EL1_SPECSEI_GET( _reg ) \
4114 ( ( ( _reg ) >> 0 ) & 0xfU )
4116#define AARCH64_ID_MMFR4_EL1_AC2( _val ) ( ( _val ) << 4 )
4117#define AARCH64_ID_MMFR4_EL1_AC2_SHIFT 4
4118#define AARCH64_ID_MMFR4_EL1_AC2_MASK 0xf0U
4119#define AARCH64_ID_MMFR4_EL1_AC2_GET( _reg ) \
4120 ( ( ( _reg ) >> 4 ) & 0xfU )
4122#define AARCH64_ID_MMFR4_EL1_XNX( _val ) ( ( _val ) << 8 )
4123#define AARCH64_ID_MMFR4_EL1_XNX_SHIFT 8
4124#define AARCH64_ID_MMFR4_EL1_XNX_MASK 0xf00U
4125#define AARCH64_ID_MMFR4_EL1_XNX_GET( _reg ) \
4126 ( ( ( _reg ) >> 8 ) & 0xfU )
4128#define AARCH64_ID_MMFR4_EL1_CNP( _val ) ( ( _val ) << 12 )
4129#define AARCH64_ID_MMFR4_EL1_CNP_SHIFT 12
4130#define AARCH64_ID_MMFR4_EL1_CNP_MASK 0xf000U
4131#define AARCH64_ID_MMFR4_EL1_CNP_GET( _reg ) \
4132 ( ( ( _reg ) >> 12 ) & 0xfU )
4134#define AARCH64_ID_MMFR4_EL1_HPDS( _val ) ( ( _val ) << 16 )
4135#define AARCH64_ID_MMFR4_EL1_HPDS_SHIFT 16
4136#define AARCH64_ID_MMFR4_EL1_HPDS_MASK 0xf0000U
4137#define AARCH64_ID_MMFR4_EL1_HPDS_GET( _reg ) \
4138 ( ( ( _reg ) >> 16 ) & 0xfU )
4140#define AARCH64_ID_MMFR4_EL1_LSM( _val ) ( ( _val ) << 20 )
4141#define AARCH64_ID_MMFR4_EL1_LSM_SHIFT 20
4142#define AARCH64_ID_MMFR4_EL1_LSM_MASK 0xf00000U
4143#define AARCH64_ID_MMFR4_EL1_LSM_GET( _reg ) \
4144 ( ( ( _reg ) >> 20 ) & 0xfU )
4146#define AARCH64_ID_MMFR4_EL1_CCIDX( _val ) ( ( _val ) << 24 )
4147#define AARCH64_ID_MMFR4_EL1_CCIDX_SHIFT 24
4148#define AARCH64_ID_MMFR4_EL1_CCIDX_MASK 0xf000000U
4149#define AARCH64_ID_MMFR4_EL1_CCIDX_GET( _reg ) \
4150 ( ( ( _reg ) >> 24 ) & 0xfU )
4152#define AARCH64_ID_MMFR4_EL1_EVT( _val ) ( ( _val ) << 28 )
4153#define AARCH64_ID_MMFR4_EL1_EVT_SHIFT 28
4154#define AARCH64_ID_MMFR4_EL1_EVT_MASK 0xf0000000U
4155#define AARCH64_ID_MMFR4_EL1_EVT_GET( _reg ) \
4156 ( ( ( _reg ) >> 28 ) & 0xfU )
4158static inline uint64_t _AArch64_Read_id_mmfr4_el1(
void )
4163 "mrs %0, ID_MMFR4_EL1" :
"=&r" ( value ) : :
"memory"
4171#define AARCH64_ID_MMFR5_EL1_ETS( _val ) ( ( _val ) << 0 )
4172#define AARCH64_ID_MMFR5_EL1_ETS_SHIFT 0
4173#define AARCH64_ID_MMFR5_EL1_ETS_MASK 0xfU
4174#define AARCH64_ID_MMFR5_EL1_ETS_GET( _reg ) \
4175 ( ( ( _reg ) >> 0 ) & 0xfU )
4177static inline uint64_t _AArch64_Read_id_mmfr5_el1(
void )
4182 "mrs %0, ID_MMFR5_EL1" :
"=&r" ( value ) : :
"memory"
4190#define AARCH64_ID_PFR0_EL1_STATE0( _val ) ( ( _val ) << 0 )
4191#define AARCH64_ID_PFR0_EL1_STATE0_SHIFT 0
4192#define AARCH64_ID_PFR0_EL1_STATE0_MASK 0xfU
4193#define AARCH64_ID_PFR0_EL1_STATE0_GET( _reg ) \
4194 ( ( ( _reg ) >> 0 ) & 0xfU )
4196#define AARCH64_ID_PFR0_EL1_STATE1( _val ) ( ( _val ) << 4 )
4197#define AARCH64_ID_PFR0_EL1_STATE1_SHIFT 4
4198#define AARCH64_ID_PFR0_EL1_STATE1_MASK 0xf0U
4199#define AARCH64_ID_PFR0_EL1_STATE1_GET( _reg ) \
4200 ( ( ( _reg ) >> 4 ) & 0xfU )
4202#define AARCH64_ID_PFR0_EL1_STATE2( _val ) ( ( _val ) << 8 )
4203#define AARCH64_ID_PFR0_EL1_STATE2_SHIFT 8
4204#define AARCH64_ID_PFR0_EL1_STATE2_MASK 0xf00U
4205#define AARCH64_ID_PFR0_EL1_STATE2_GET( _reg ) \
4206 ( ( ( _reg ) >> 8 ) & 0xfU )
4208#define AARCH64_ID_PFR0_EL1_STATE3( _val ) ( ( _val ) << 12 )
4209#define AARCH64_ID_PFR0_EL1_STATE3_SHIFT 12
4210#define AARCH64_ID_PFR0_EL1_STATE3_MASK 0xf000U
4211#define AARCH64_ID_PFR0_EL1_STATE3_GET( _reg ) \
4212 ( ( ( _reg ) >> 12 ) & 0xfU )
4214#define AARCH64_ID_PFR0_EL1_CSV2( _val ) ( ( _val ) << 16 )
4215#define AARCH64_ID_PFR0_EL1_CSV2_SHIFT 16
4216#define AARCH64_ID_PFR0_EL1_CSV2_MASK 0xf0000U
4217#define AARCH64_ID_PFR0_EL1_CSV2_GET( _reg ) \
4218 ( ( ( _reg ) >> 16 ) & 0xfU )
4220#define AARCH64_ID_PFR0_EL1_AMU( _val ) ( ( _val ) << 20 )
4221#define AARCH64_ID_PFR0_EL1_AMU_SHIFT 20
4222#define AARCH64_ID_PFR0_EL1_AMU_MASK 0xf00000U
4223#define AARCH64_ID_PFR0_EL1_AMU_GET( _reg ) \
4224 ( ( ( _reg ) >> 20 ) & 0xfU )
4226#define AARCH64_ID_PFR0_EL1_DIT( _val ) ( ( _val ) << 24 )
4227#define AARCH64_ID_PFR0_EL1_DIT_SHIFT 24
4228#define AARCH64_ID_PFR0_EL1_DIT_MASK 0xf000000U
4229#define AARCH64_ID_PFR0_EL1_DIT_GET( _reg ) \
4230 ( ( ( _reg ) >> 24 ) & 0xfU )
4232#define AARCH64_ID_PFR0_EL1_RAS( _val ) ( ( _val ) << 28 )
4233#define AARCH64_ID_PFR0_EL1_RAS_SHIFT 28
4234#define AARCH64_ID_PFR0_EL1_RAS_MASK 0xf0000000U
4235#define AARCH64_ID_PFR0_EL1_RAS_GET( _reg ) \
4236 ( ( ( _reg ) >> 28 ) & 0xfU )
4238static inline uint64_t _AArch64_Read_id_pfr0_el1(
void )
4243 "mrs %0, ID_PFR0_EL1" :
"=&r" ( value ) : :
"memory"
4251#define AARCH64_ID_PFR1_EL1_PROGMOD( _val ) ( ( _val ) << 0 )
4252#define AARCH64_ID_PFR1_EL1_PROGMOD_SHIFT 0
4253#define AARCH64_ID_PFR1_EL1_PROGMOD_MASK 0xfU
4254#define AARCH64_ID_PFR1_EL1_PROGMOD_GET( _reg ) \
4255 ( ( ( _reg ) >> 0 ) & 0xfU )
4257#define AARCH64_ID_PFR1_EL1_SECURITY( _val ) ( ( _val ) << 4 )
4258#define AARCH64_ID_PFR1_EL1_SECURITY_SHIFT 4
4259#define AARCH64_ID_PFR1_EL1_SECURITY_MASK 0xf0U
4260#define AARCH64_ID_PFR1_EL1_SECURITY_GET( _reg ) \
4261 ( ( ( _reg ) >> 4 ) & 0xfU )
4263#define AARCH64_ID_PFR1_EL1_MPROGMOD( _val ) ( ( _val ) << 8 )
4264#define AARCH64_ID_PFR1_EL1_MPROGMOD_SHIFT 8
4265#define AARCH64_ID_PFR1_EL1_MPROGMOD_MASK 0xf00U
4266#define AARCH64_ID_PFR1_EL1_MPROGMOD_GET( _reg ) \
4267 ( ( ( _reg ) >> 8 ) & 0xfU )
4269#define AARCH64_ID_PFR1_EL1_VIRTUALIZATION( _val ) ( ( _val ) << 12 )
4270#define AARCH64_ID_PFR1_EL1_VIRTUALIZATION_SHIFT 12
4271#define AARCH64_ID_PFR1_EL1_VIRTUALIZATION_MASK 0xf000U
4272#define AARCH64_ID_PFR1_EL1_VIRTUALIZATION_GET( _reg ) \
4273 ( ( ( _reg ) >> 12 ) & 0xfU )
4275#define AARCH64_ID_PFR1_EL1_GENTIMER( _val ) ( ( _val ) << 16 )
4276#define AARCH64_ID_PFR1_EL1_GENTIMER_SHIFT 16
4277#define AARCH64_ID_PFR1_EL1_GENTIMER_MASK 0xf0000U
4278#define AARCH64_ID_PFR1_EL1_GENTIMER_GET( _reg ) \
4279 ( ( ( _reg ) >> 16 ) & 0xfU )
4281#define AARCH64_ID_PFR1_EL1_SEC_FRAC( _val ) ( ( _val ) << 20 )
4282#define AARCH64_ID_PFR1_EL1_SEC_FRAC_SHIFT 20
4283#define AARCH64_ID_PFR1_EL1_SEC_FRAC_MASK 0xf00000U
4284#define AARCH64_ID_PFR1_EL1_SEC_FRAC_GET( _reg ) \
4285 ( ( ( _reg ) >> 20 ) & 0xfU )
4287#define AARCH64_ID_PFR1_EL1_VIRT_FRAC( _val ) ( ( _val ) << 24 )
4288#define AARCH64_ID_PFR1_EL1_VIRT_FRAC_SHIFT 24
4289#define AARCH64_ID_PFR1_EL1_VIRT_FRAC_MASK 0xf000000U
4290#define AARCH64_ID_PFR1_EL1_VIRT_FRAC_GET( _reg ) \
4291 ( ( ( _reg ) >> 24 ) & 0xfU )
4293#define AARCH64_ID_PFR1_EL1_GIC( _val ) ( ( _val ) << 28 )
4294#define AARCH64_ID_PFR1_EL1_GIC_SHIFT 28
4295#define AARCH64_ID_PFR1_EL1_GIC_MASK 0xf0000000U
4296#define AARCH64_ID_PFR1_EL1_GIC_GET( _reg ) \
4297 ( ( ( _reg ) >> 28 ) & 0xfU )
4299static inline uint64_t _AArch64_Read_id_pfr1_el1(
void )
4304 "mrs %0, ID_PFR1_EL1" :
"=&r" ( value ) : :
"memory"
4312#define AARCH64_ID_PFR2_EL1_CSV3( _val ) ( ( _val ) << 0 )
4313#define AARCH64_ID_PFR2_EL1_CSV3_SHIFT 0
4314#define AARCH64_ID_PFR2_EL1_CSV3_MASK 0xfU
4315#define AARCH64_ID_PFR2_EL1_CSV3_GET( _reg ) \
4316 ( ( ( _reg ) >> 0 ) & 0xfU )
4318#define AARCH64_ID_PFR2_EL1_SSBS( _val ) ( ( _val ) << 4 )
4319#define AARCH64_ID_PFR2_EL1_SSBS_SHIFT 4
4320#define AARCH64_ID_PFR2_EL1_SSBS_MASK 0xf0U
4321#define AARCH64_ID_PFR2_EL1_SSBS_GET( _reg ) \
4322 ( ( ( _reg ) >> 4 ) & 0xfU )
4324#define AARCH64_ID_PFR2_EL1_RAS_FRAC( _val ) ( ( _val ) << 8 )
4325#define AARCH64_ID_PFR2_EL1_RAS_FRAC_SHIFT 8
4326#define AARCH64_ID_PFR2_EL1_RAS_FRAC_MASK 0xf00U
4327#define AARCH64_ID_PFR2_EL1_RAS_FRAC_GET( _reg ) \
4328 ( ( ( _reg ) >> 8 ) & 0xfU )
4330static inline uint64_t _AArch64_Read_id_pfr2_el1(
void )
4335 "mrs %0, ID_PFR2_EL1" :
"=&r" ( value ) : :
"memory"
4343#define AARCH64_IFSR32_EL2_FS_3_0( _val ) ( ( _val ) << 0 )
4344#define AARCH64_IFSR32_EL2_FS_3_0_SHIFT 0
4345#define AARCH64_IFSR32_EL2_FS_3_0_MASK 0xfU
4346#define AARCH64_IFSR32_EL2_FS_3_0_GET( _reg ) \
4347 ( ( ( _reg ) >> 0 ) & 0xfU )
4349#define AARCH64_IFSR32_EL2_STATUS( _val ) ( ( _val ) << 0 )
4350#define AARCH64_IFSR32_EL2_STATUS_SHIFT 0
4351#define AARCH64_IFSR32_EL2_STATUS_MASK 0x3fU
4352#define AARCH64_IFSR32_EL2_STATUS_GET( _reg ) \
4353 ( ( ( _reg ) >> 0 ) & 0x3fU )
4355#define AARCH64_IFSR32_EL2_LPAE 0x200U
4357#define AARCH64_IFSR32_EL2_FS_4 0x400U
4359#define AARCH64_IFSR32_EL2_EXT 0x1000U
4361#define AARCH64_IFSR32_EL2_FNV 0x10000U
4363static inline uint64_t _AArch64_Read_ifsr32_el2(
void )
4368 "mrs %0, IFSR32_EL2" :
"=&r" ( value ) : :
"memory"
4374static inline void _AArch64_Write_ifsr32_el2( uint64_t value )
4377 "msr IFSR32_EL2, %0" : :
"r" ( value ) :
"memory"
4383#define AARCH64_ISR_EL1_F 0x40U
4385#define AARCH64_ISR_EL1_I 0x80U
4387#define AARCH64_ISR_EL1_A 0x100U
4389static inline uint64_t _AArch64_Read_isr_el1(
void )
4394 "mrs %0, ISR_EL1" :
"=&r" ( value ) : :
"memory"
4402#define AARCH64_LORC_EL1_EN 0x1U
4404#define AARCH64_LORC_EL1_DS( _val ) ( ( _val ) << 2 )
4405#define AARCH64_LORC_EL1_DS_SHIFT 2
4406#define AARCH64_LORC_EL1_DS_MASK 0x3fcU
4407#define AARCH64_LORC_EL1_DS_GET( _reg ) \
4408 ( ( ( _reg ) >> 2 ) & 0xffU )
4410static inline uint64_t _AArch64_Read_lorc_el1(
void )
4415 "mrs %0, LORC_EL1" :
"=&r" ( value ) : :
"memory"
4421static inline void _AArch64_Write_lorc_el1( uint64_t value )
4424 "msr LORC_EL1, %0" : :
"r" ( value ) :
"memory"
4430#define AARCH64_LOREA_EL1_EA_47_16( _val ) ( ( _val ) << 16 )
4431#define AARCH64_LOREA_EL1_EA_47_16_SHIFT 16
4432#define AARCH64_LOREA_EL1_EA_47_16_MASK 0xffffffff0000ULL
4433#define AARCH64_LOREA_EL1_EA_47_16_GET( _reg ) \
4434 ( ( ( _reg ) >> 16 ) & 0xffffffffULL )
4436#define AARCH64_LOREA_EL1_EA_51_48( _val ) ( ( _val ) << 48 )
4437#define AARCH64_LOREA_EL1_EA_51_48_SHIFT 48
4438#define AARCH64_LOREA_EL1_EA_51_48_MASK 0xf000000000000ULL
4439#define AARCH64_LOREA_EL1_EA_51_48_GET( _reg ) \
4440 ( ( ( _reg ) >> 48 ) & 0xfULL )
4442static inline uint64_t _AArch64_Read_lorea_el1(
void )
4447 "mrs %0, LOREA_EL1" :
"=&r" ( value ) : :
"memory"
4453static inline void _AArch64_Write_lorea_el1( uint64_t value )
4456 "msr LOREA_EL1, %0" : :
"r" ( value ) :
"memory"
4462#define AARCH64_LORID_EL1_LR( _val ) ( ( _val ) << 0 )
4463#define AARCH64_LORID_EL1_LR_SHIFT 0
4464#define AARCH64_LORID_EL1_LR_MASK 0xffU
4465#define AARCH64_LORID_EL1_LR_GET( _reg ) \
4466 ( ( ( _reg ) >> 0 ) & 0xffU )
4468#define AARCH64_LORID_EL1_LD( _val ) ( ( _val ) << 16 )
4469#define AARCH64_LORID_EL1_LD_SHIFT 16
4470#define AARCH64_LORID_EL1_LD_MASK 0xff0000U
4471#define AARCH64_LORID_EL1_LD_GET( _reg ) \
4472 ( ( ( _reg ) >> 16 ) & 0xffU )
4474static inline uint64_t _AArch64_Read_lorid_el1(
void )
4479 "mrs %0, LORID_EL1" :
"=&r" ( value ) : :
"memory"
4487#define AARCH64_LORN_EL1_NUM( _val ) ( ( _val ) << 0 )
4488#define AARCH64_LORN_EL1_NUM_SHIFT 0
4489#define AARCH64_LORN_EL1_NUM_MASK 0xffU
4490#define AARCH64_LORN_EL1_NUM_GET( _reg ) \
4491 ( ( ( _reg ) >> 0 ) & 0xffU )
4493static inline uint64_t _AArch64_Read_lorn_el1(
void )
4498 "mrs %0, LORN_EL1" :
"=&r" ( value ) : :
"memory"
4504static inline void _AArch64_Write_lorn_el1( uint64_t value )
4507 "msr LORN_EL1, %0" : :
"r" ( value ) :
"memory"
4513#define AARCH64_LORSA_EL1_VALID 0x1U
4515#define AARCH64_LORSA_EL1_SA_47_16( _val ) ( ( _val ) << 16 )
4516#define AARCH64_LORSA_EL1_SA_47_16_SHIFT 16
4517#define AARCH64_LORSA_EL1_SA_47_16_MASK 0xffffffff0000ULL
4518#define AARCH64_LORSA_EL1_SA_47_16_GET( _reg ) \
4519 ( ( ( _reg ) >> 16 ) & 0xffffffffULL )
4521#define AARCH64_LORSA_EL1_SA_51_48( _val ) ( ( _val ) << 48 )
4522#define AARCH64_LORSA_EL1_SA_51_48_SHIFT 48
4523#define AARCH64_LORSA_EL1_SA_51_48_MASK 0xf000000000000ULL
4524#define AARCH64_LORSA_EL1_SA_51_48_GET( _reg ) \
4525 ( ( ( _reg ) >> 48 ) & 0xfULL )
4527static inline uint64_t _AArch64_Read_lorsa_el1(
void )
4532 "mrs %0, LORSA_EL1" :
"=&r" ( value ) : :
"memory"
4538static inline void _AArch64_Write_lorsa_el1( uint64_t value )
4541 "msr LORSA_EL1, %0" : :
"r" ( value ) :
"memory"
4547#define AARCH64_MAIR_EL1_ATTR0( _val ) ( ( _val ) << 0 )
4548#define AARCH64_MAIR_EL1_ATTR1( _val ) ( ( _val ) << 8 )
4549#define AARCH64_MAIR_EL1_ATTR2( _val ) ( ( _val ) << 16 )
4550#define AARCH64_MAIR_EL1_ATTR3( _val ) ( ( _val ) << 24 )
4551#define AARCH64_MAIR_EL1_ATTR4( _val ) ( ( _val ) << 32 )
4552#define AARCH64_MAIR_EL1_ATTR5( _val ) ( ( _val ) << 40 )
4553#define AARCH64_MAIR_EL1_ATTR6( _val ) ( ( _val ) << 48 )
4554#define AARCH64_MAIR_EL1_ATTR7( _val ) ( ( _val ) << 56 )
4556static inline uint64_t _AArch64_Read_mair_el1(
void )
4561 "mrs %0, MAIR_EL1" :
"=&r" ( value ) : :
"memory"
4567static inline void _AArch64_Write_mair_el1( uint64_t value )
4570 "msr MAIR_EL1, %0" : :
"r" ( value ) :
"memory"
4576static inline uint64_t _AArch64_Read_mair_el2(
void )
4581 "mrs %0, MAIR_EL2" :
"=&r" ( value ) : :
"memory"
4587static inline void _AArch64_Write_mair_el2( uint64_t value )
4590 "msr MAIR_EL2, %0" : :
"r" ( value ) :
"memory"
4596static inline uint64_t _AArch64_Read_mair_el3(
void )
4601 "mrs %0, MAIR_EL3" :
"=&r" ( value ) : :
"memory"
4607static inline void _AArch64_Write_mair_el3( uint64_t value )
4610 "msr MAIR_EL3, %0" : :
"r" ( value ) :
"memory"
4616#define AARCH64_MIDR_EL1_REVISION( _val ) ( ( _val ) << 0 )
4617#define AARCH64_MIDR_EL1_REVISION_SHIFT 0
4618#define AARCH64_MIDR_EL1_REVISION_MASK 0xfU
4619#define AARCH64_MIDR_EL1_REVISION_GET( _reg ) \
4620 ( ( ( _reg ) >> 0 ) & 0xfU )
4622#define AARCH64_MIDR_EL1_PARTNUM( _val ) ( ( _val ) << 4 )
4623#define AARCH64_MIDR_EL1_PARTNUM_SHIFT 4
4624#define AARCH64_MIDR_EL1_PARTNUM_MASK 0xfff0U
4625#define AARCH64_MIDR_EL1_PARTNUM_GET( _reg ) \
4626 ( ( ( _reg ) >> 4 ) & 0xfffU )
4628#define AARCH64_MIDR_EL1_ARCHITECTURE( _val ) ( ( _val ) << 16 )
4629#define AARCH64_MIDR_EL1_ARCHITECTURE_SHIFT 16
4630#define AARCH64_MIDR_EL1_ARCHITECTURE_MASK 0xf0000U
4631#define AARCH64_MIDR_EL1_ARCHITECTURE_GET( _reg ) \
4632 ( ( ( _reg ) >> 16 ) & 0xfU )
4634#define AARCH64_MIDR_EL1_VARIANT( _val ) ( ( _val ) << 20 )
4635#define AARCH64_MIDR_EL1_VARIANT_SHIFT 20
4636#define AARCH64_MIDR_EL1_VARIANT_MASK 0xf00000U
4637#define AARCH64_MIDR_EL1_VARIANT_GET( _reg ) \
4638 ( ( ( _reg ) >> 20 ) & 0xfU )
4640#define AARCH64_MIDR_EL1_IMPLEMENTER( _val ) ( ( _val ) << 24 )
4641#define AARCH64_MIDR_EL1_IMPLEMENTER_SHIFT 24
4642#define AARCH64_MIDR_EL1_IMPLEMENTER_MASK 0xff000000U
4643#define AARCH64_MIDR_EL1_IMPLEMENTER_GET( _reg ) \
4644 ( ( ( _reg ) >> 24 ) & 0xffU )
4646static inline uint64_t _AArch64_Read_midr_el1(
void )
4651 "mrs %0, MIDR_EL1" :
"=&r" ( value ) : :
"memory"
4659#define AARCH64_MPIDR_EL1_AFF0( _val ) ( ( _val ) << 0 )
4660#define AARCH64_MPIDR_EL1_AFF0_SHIFT 0
4661#define AARCH64_MPIDR_EL1_AFF0_MASK 0xffU
4662#define AARCH64_MPIDR_EL1_AFF0_GET( _reg ) \
4663 ( ( ( _reg ) >> 0 ) & 0xffU )
4665#define AARCH64_MPIDR_EL1_AFF1( _val ) ( ( _val ) << 8 )
4666#define AARCH64_MPIDR_EL1_AFF1_SHIFT 8
4667#define AARCH64_MPIDR_EL1_AFF1_MASK 0xff00U
4668#define AARCH64_MPIDR_EL1_AFF1_GET( _reg ) \
4669 ( ( ( _reg ) >> 8 ) & 0xffU )
4671#define AARCH64_MPIDR_EL1_AFF2( _val ) ( ( _val ) << 16 )
4672#define AARCH64_MPIDR_EL1_AFF2_SHIFT 16
4673#define AARCH64_MPIDR_EL1_AFF2_MASK 0xff0000U
4674#define AARCH64_MPIDR_EL1_AFF2_GET( _reg ) \
4675 ( ( ( _reg ) >> 16 ) & 0xffU )
4677#define AARCH64_MPIDR_EL1_MT 0x1000000U
4679#define AARCH64_MPIDR_EL1_U 0x40000000U
4681#define AARCH64_MPIDR_EL1_AFF3( _val ) ( ( _val ) << 32 )
4682#define AARCH64_MPIDR_EL1_AFF3_SHIFT 32
4683#define AARCH64_MPIDR_EL1_AFF3_MASK 0xff00000000ULL
4684#define AARCH64_MPIDR_EL1_AFF3_GET( _reg ) \
4685 ( ( ( _reg ) >> 32 ) & 0xffULL )
4687static inline uint64_t _AArch64_Read_mpidr_el1(
void )
4692 "mrs %0, MPIDR_EL1" :
"=&r" ( value ) : :
"memory"
4700#define AARCH64_MVFR0_EL1_SIMDREG( _val ) ( ( _val ) << 0 )
4701#define AARCH64_MVFR0_EL1_SIMDREG_SHIFT 0
4702#define AARCH64_MVFR0_EL1_SIMDREG_MASK 0xfU
4703#define AARCH64_MVFR0_EL1_SIMDREG_GET( _reg ) \
4704 ( ( ( _reg ) >> 0 ) & 0xfU )
4706#define AARCH64_MVFR0_EL1_FPSP( _val ) ( ( _val ) << 4 )
4707#define AARCH64_MVFR0_EL1_FPSP_SHIFT 4
4708#define AARCH64_MVFR0_EL1_FPSP_MASK 0xf0U
4709#define AARCH64_MVFR0_EL1_FPSP_GET( _reg ) \
4710 ( ( ( _reg ) >> 4 ) & 0xfU )
4712#define AARCH64_MVFR0_EL1_FPDP( _val ) ( ( _val ) << 8 )
4713#define AARCH64_MVFR0_EL1_FPDP_SHIFT 8
4714#define AARCH64_MVFR0_EL1_FPDP_MASK 0xf00U
4715#define AARCH64_MVFR0_EL1_FPDP_GET( _reg ) \
4716 ( ( ( _reg ) >> 8 ) & 0xfU )
4718#define AARCH64_MVFR0_EL1_FPTRAP( _val ) ( ( _val ) << 12 )
4719#define AARCH64_MVFR0_EL1_FPTRAP_SHIFT 12
4720#define AARCH64_MVFR0_EL1_FPTRAP_MASK 0xf000U
4721#define AARCH64_MVFR0_EL1_FPTRAP_GET( _reg ) \
4722 ( ( ( _reg ) >> 12 ) & 0xfU )
4724#define AARCH64_MVFR0_EL1_FPDIVIDE( _val ) ( ( _val ) << 16 )
4725#define AARCH64_MVFR0_EL1_FPDIVIDE_SHIFT 16
4726#define AARCH64_MVFR0_EL1_FPDIVIDE_MASK 0xf0000U
4727#define AARCH64_MVFR0_EL1_FPDIVIDE_GET( _reg ) \
4728 ( ( ( _reg ) >> 16 ) & 0xfU )
4730#define AARCH64_MVFR0_EL1_FPSQRT( _val ) ( ( _val ) << 20 )
4731#define AARCH64_MVFR0_EL1_FPSQRT_SHIFT 20
4732#define AARCH64_MVFR0_EL1_FPSQRT_MASK 0xf00000U
4733#define AARCH64_MVFR0_EL1_FPSQRT_GET( _reg ) \
4734 ( ( ( _reg ) >> 20 ) & 0xfU )
4736#define AARCH64_MVFR0_EL1_FPSHVEC( _val ) ( ( _val ) << 24 )
4737#define AARCH64_MVFR0_EL1_FPSHVEC_SHIFT 24
4738#define AARCH64_MVFR0_EL1_FPSHVEC_MASK 0xf000000U
4739#define AARCH64_MVFR0_EL1_FPSHVEC_GET( _reg ) \
4740 ( ( ( _reg ) >> 24 ) & 0xfU )
4742#define AARCH64_MVFR0_EL1_FPROUND( _val ) ( ( _val ) << 28 )
4743#define AARCH64_MVFR0_EL1_FPROUND_SHIFT 28
4744#define AARCH64_MVFR0_EL1_FPROUND_MASK 0xf0000000U
4745#define AARCH64_MVFR0_EL1_FPROUND_GET( _reg ) \
4746 ( ( ( _reg ) >> 28 ) & 0xfU )
4748static inline uint64_t _AArch64_Read_mvfr0_el1(
void )
4753 "mrs %0, MVFR0_EL1" :
"=&r" ( value ) : :
"memory"
4761#define AARCH64_MVFR1_EL1_FPFTZ( _val ) ( ( _val ) << 0 )
4762#define AARCH64_MVFR1_EL1_FPFTZ_SHIFT 0
4763#define AARCH64_MVFR1_EL1_FPFTZ_MASK 0xfU
4764#define AARCH64_MVFR1_EL1_FPFTZ_GET( _reg ) \
4765 ( ( ( _reg ) >> 0 ) & 0xfU )
4767#define AARCH64_MVFR1_EL1_FPDNAN( _val ) ( ( _val ) << 4 )
4768#define AARCH64_MVFR1_EL1_FPDNAN_SHIFT 4
4769#define AARCH64_MVFR1_EL1_FPDNAN_MASK 0xf0U
4770#define AARCH64_MVFR1_EL1_FPDNAN_GET( _reg ) \
4771 ( ( ( _reg ) >> 4 ) & 0xfU )
4773#define AARCH64_MVFR1_EL1_SIMDLS( _val ) ( ( _val ) << 8 )
4774#define AARCH64_MVFR1_EL1_SIMDLS_SHIFT 8
4775#define AARCH64_MVFR1_EL1_SIMDLS_MASK 0xf00U
4776#define AARCH64_MVFR1_EL1_SIMDLS_GET( _reg ) \
4777 ( ( ( _reg ) >> 8 ) & 0xfU )
4779#define AARCH64_MVFR1_EL1_SIMDINT( _val ) ( ( _val ) << 12 )
4780#define AARCH64_MVFR1_EL1_SIMDINT_SHIFT 12
4781#define AARCH64_MVFR1_EL1_SIMDINT_MASK 0xf000U
4782#define AARCH64_MVFR1_EL1_SIMDINT_GET( _reg ) \
4783 ( ( ( _reg ) >> 12 ) & 0xfU )
4785#define AARCH64_MVFR1_EL1_SIMDSP( _val ) ( ( _val ) << 16 )
4786#define AARCH64_MVFR1_EL1_SIMDSP_SHIFT 16
4787#define AARCH64_MVFR1_EL1_SIMDSP_MASK 0xf0000U
4788#define AARCH64_MVFR1_EL1_SIMDSP_GET( _reg ) \
4789 ( ( ( _reg ) >> 16 ) & 0xfU )
4791#define AARCH64_MVFR1_EL1_SIMDHP( _val ) ( ( _val ) << 20 )
4792#define AARCH64_MVFR1_EL1_SIMDHP_SHIFT 20
4793#define AARCH64_MVFR1_EL1_SIMDHP_MASK 0xf00000U
4794#define AARCH64_MVFR1_EL1_SIMDHP_GET( _reg ) \
4795 ( ( ( _reg ) >> 20 ) & 0xfU )
4797#define AARCH64_MVFR1_EL1_FPHP( _val ) ( ( _val ) << 24 )
4798#define AARCH64_MVFR1_EL1_FPHP_SHIFT 24
4799#define AARCH64_MVFR1_EL1_FPHP_MASK 0xf000000U
4800#define AARCH64_MVFR1_EL1_FPHP_GET( _reg ) \
4801 ( ( ( _reg ) >> 24 ) & 0xfU )
4803#define AARCH64_MVFR1_EL1_SIMDFMAC( _val ) ( ( _val ) << 28 )
4804#define AARCH64_MVFR1_EL1_SIMDFMAC_SHIFT 28
4805#define AARCH64_MVFR1_EL1_SIMDFMAC_MASK 0xf0000000U
4806#define AARCH64_MVFR1_EL1_SIMDFMAC_GET( _reg ) \
4807 ( ( ( _reg ) >> 28 ) & 0xfU )
4809static inline uint64_t _AArch64_Read_mvfr1_el1(
void )
4814 "mrs %0, MVFR1_EL1" :
"=&r" ( value ) : :
"memory"
4822#define AARCH64_MVFR2_EL1_SIMDMISC( _val ) ( ( _val ) << 0 )
4823#define AARCH64_MVFR2_EL1_SIMDMISC_SHIFT 0
4824#define AARCH64_MVFR2_EL1_SIMDMISC_MASK 0xfU
4825#define AARCH64_MVFR2_EL1_SIMDMISC_GET( _reg ) \
4826 ( ( ( _reg ) >> 0 ) & 0xfU )
4828#define AARCH64_MVFR2_EL1_FPMISC( _val ) ( ( _val ) << 4 )
4829#define AARCH64_MVFR2_EL1_FPMISC_SHIFT 4
4830#define AARCH64_MVFR2_EL1_FPMISC_MASK 0xf0U
4831#define AARCH64_MVFR2_EL1_FPMISC_GET( _reg ) \
4832 ( ( ( _reg ) >> 4 ) & 0xfU )
4834static inline uint64_t _AArch64_Read_mvfr2_el1(
void )
4839 "mrs %0, MVFR2_EL1" :
"=&r" ( value ) : :
"memory"
4847#define AARCH64_PAR_EL1_F 0x1U
4849#define AARCH64_PAR_EL1_FST( _val ) ( ( _val ) << 1 )
4850#define AARCH64_PAR_EL1_FST_SHIFT 1
4851#define AARCH64_PAR_EL1_FST_MASK 0x7eU
4852#define AARCH64_PAR_EL1_FST_GET( _reg ) \
4853 ( ( ( _reg ) >> 1 ) & 0x3fU )
4855#define AARCH64_PAR_EL1_SH( _val ) ( ( _val ) << 7 )
4856#define AARCH64_PAR_EL1_SH_SHIFT 7
4857#define AARCH64_PAR_EL1_SH_MASK 0x180U
4858#define AARCH64_PAR_EL1_SH_GET( _reg ) \
4859 ( ( ( _reg ) >> 7 ) & 0x3U )
4861#define AARCH64_PAR_EL1_PTW 0x100U
4863#define AARCH64_PAR_EL1_NS 0x200U
4865#define AARCH64_PAR_EL1_S 0x200U
4867#define AARCH64_PAR_EL1_PA_47_12( _val ) ( ( _val ) << 12 )
4868#define AARCH64_PAR_EL1_PA_47_12_SHIFT 12
4869#define AARCH64_PAR_EL1_PA_47_12_MASK 0xfffffffff000ULL
4870#define AARCH64_PAR_EL1_PA_47_12_GET( _reg ) \
4871 ( ( ( _reg ) >> 12 ) & 0xfffffffffULL )
4873#define AARCH64_PAR_EL1_PA_51_48( _val ) ( ( _val ) << 48 )
4874#define AARCH64_PAR_EL1_PA_51_48_SHIFT 48
4875#define AARCH64_PAR_EL1_PA_51_48_MASK 0xf000000000000ULL
4876#define AARCH64_PAR_EL1_PA_51_48_GET( _reg ) \
4877 ( ( ( _reg ) >> 48 ) & 0xfULL )
4879#define AARCH64_PAR_EL1_ATTR( _val ) ( ( _val ) << 56 )
4880#define AARCH64_PAR_EL1_ATTR_SHIFT 56
4881#define AARCH64_PAR_EL1_ATTR_MASK 0xff00000000000000ULL
4882#define AARCH64_PAR_EL1_ATTR_GET( _reg ) \
4883 ( ( ( _reg ) >> 56 ) & 0xffULL )
4885static inline uint64_t _AArch64_Read_par_el1(
void )
4890 "mrs %0, PAR_EL1" :
"=&r" ( value ) : :
"memory"
4896static inline void _AArch64_Write_par_el1( uint64_t value )
4899 "msr PAR_EL1, %0" : :
"r" ( value ) :
"memory"
4905static inline uint64_t _AArch64_Read_revidr_el1(
void )
4910 "mrs %0, REVIDR_EL1" :
"=&r" ( value ) : :
"memory"
4918#define AARCH64_RGSR_EL1_TAG( _val ) ( ( _val ) << 0 )
4919#define AARCH64_RGSR_EL1_TAG_SHIFT 0
4920#define AARCH64_RGSR_EL1_TAG_MASK 0xfU
4921#define AARCH64_RGSR_EL1_TAG_GET( _reg ) \
4922 ( ( ( _reg ) >> 0 ) & 0xfU )
4924#define AARCH64_RGSR_EL1_SEED( _val ) ( ( _val ) << 8 )
4925#define AARCH64_RGSR_EL1_SEED_SHIFT 8
4926#define AARCH64_RGSR_EL1_SEED_MASK 0xffff00U
4927#define AARCH64_RGSR_EL1_SEED_GET( _reg ) \
4928 ( ( ( _reg ) >> 8 ) & 0xffffU )
4930static inline uint64_t _AArch64_Read_rgsr_el1(
void )
4935 "mrs %0, RGSR_EL1" :
"=&r" ( value ) : :
"memory"
4941static inline void _AArch64_Write_rgsr_el1( uint64_t value )
4944 "msr RGSR_EL1, %0" : :
"r" ( value ) :
"memory"
4950#define AARCH64_RMR_EL1_AA64 0x1U
4952#define AARCH64_RMR_EL1_RR 0x2U
4954static inline uint64_t _AArch64_Read_rmr_el1(
void )
4959 "mrs %0, RMR_EL1" :
"=&r" ( value ) : :
"memory"
4965static inline void _AArch64_Write_rmr_el1( uint64_t value )
4968 "msr RMR_EL1, %0" : :
"r" ( value ) :
"memory"
4974#define AARCH64_RMR_EL2_AA64 0x1U
4976#define AARCH64_RMR_EL2_RR 0x2U
4978static inline uint64_t _AArch64_Read_rmr_el2(
void )
4983 "mrs %0, RMR_EL2" :
"=&r" ( value ) : :
"memory"
4989static inline void _AArch64_Write_rmr_el2( uint64_t value )
4992 "msr RMR_EL2, %0" : :
"r" ( value ) :
"memory"
4998#define AARCH64_RMR_EL3_AA64 0x1U
5000#define AARCH64_RMR_EL3_RR 0x2U
5002static inline uint64_t _AArch64_Read_rmr_el3(
void )
5007 "mrs %0, RMR_EL3" :
"=&r" ( value ) : :
"memory"
5013static inline void _AArch64_Write_rmr_el3( uint64_t value )
5016 "msr RMR_EL3, %0" : :
"r" ( value ) :
"memory"
5022static inline uint64_t _AArch64_Read_rndr(
void )
5027 "mrs %0, RNDR" :
"=&r" ( value ) : :
"memory"
5035static inline uint64_t _AArch64_Read_rndrrs(
void )
5040 "mrs %0, RNDRRS" :
"=&r" ( value ) : :
"memory"
5048static inline uint64_t _AArch64_Read_rvbar_el1(
void )
5053 "mrs %0, RVBAR_EL1" :
"=&r" ( value ) : :
"memory"
5061static inline uint64_t _AArch64_Read_rvbar_el2(
void )
5066 "mrs %0, RVBAR_EL2" :
"=&r" ( value ) : :
"memory"
5074static inline uint64_t _AArch64_Read_rvbar_el3(
void )
5079 "mrs %0, RVBAR_EL3" :
"=&r" ( value ) : :
"memory"
5087#define AARCH64_SCR_EL3_NS 0x1U
5089#define AARCH64_SCR_EL3_IRQ 0x2U
5091#define AARCH64_SCR_EL3_FIQ 0x4U
5093#define AARCH64_SCR_EL3_EA 0x8U
5095#define AARCH64_SCR_EL3_SMD 0x80U
5097#define AARCH64_SCR_EL3_HCE 0x100U
5099#define AARCH64_SCR_EL3_SIF 0x200U
5101#define AARCH64_SCR_EL3_RW 0x400U
5103#define AARCH64_SCR_EL3_ST 0x800U
5105#define AARCH64_SCR_EL3_TWI 0x1000U
5107#define AARCH64_SCR_EL3_TWE 0x2000U
5109#define AARCH64_SCR_EL3_TLOR 0x4000U
5111#define AARCH64_SCR_EL3_TERR 0x8000U
5113#define AARCH64_SCR_EL3_APK 0x10000U
5115#define AARCH64_SCR_EL3_API 0x20000U
5117#define AARCH64_SCR_EL3_EEL2 0x40000U
5119#define AARCH64_SCR_EL3_EASE 0x80000U
5121#define AARCH64_SCR_EL3_NMEA 0x100000U
5123#define AARCH64_SCR_EL3_FIEN 0x200000U
5125#define AARCH64_SCR_EL3_ENSCXT 0x2000000U
5127#define AARCH64_SCR_EL3_ATA 0x4000000U
5129#define AARCH64_SCR_EL3_FGTEN 0x8000000U
5131#define AARCH64_SCR_EL3_ECVEN 0x10000000U
5133#define AARCH64_SCR_EL3_TWEDEN 0x20000000U
5135#define AARCH64_SCR_EL3_TWEDEL( _val ) ( ( _val ) << 30 )
5136#define AARCH64_SCR_EL3_TWEDEL_SHIFT 30
5137#define AARCH64_SCR_EL3_TWEDEL_MASK 0x3c0000000ULL
5138#define AARCH64_SCR_EL3_TWEDEL_GET( _reg ) \
5139 ( ( ( _reg ) >> 30 ) & 0xfULL )
5141#define AARCH64_SCR_EL3_AMVOFFEN 0x800000000ULL
5143static inline uint64_t _AArch64_Read_scr_el3(
void )
5148 "mrs %0, SCR_EL3" :
"=&r" ( value ) : :
"memory"
5154static inline void _AArch64_Write_scr_el3( uint64_t value )
5157 "msr SCR_EL3, %0" : :
"r" ( value ) :
"memory"
5163#define AARCH64_SCTLR_EL1_M 0x1U
5165#define AARCH64_SCTLR_EL1_A 0x2U
5167#define AARCH64_SCTLR_EL1_C 0x4U
5169#define AARCH64_SCTLR_EL1_SA 0x8U
5171#define AARCH64_SCTLR_EL1_SA0 0x10U
5173#define AARCH64_SCTLR_EL1_CP15BEN 0x20U
5175#define AARCH64_SCTLR_EL1_NAA 0x40U
5177#define AARCH64_SCTLR_EL1_ITD 0x80U
5179#define AARCH64_SCTLR_EL1_SED 0x100U
5181#define AARCH64_SCTLR_EL1_UMA 0x200U
5183#define AARCH64_SCTLR_EL1_ENRCTX 0x400U
5185#define AARCH64_SCTLR_EL1_EOS 0x800U
5187#define AARCH64_SCTLR_EL1_I 0x1000U
5189#define AARCH64_SCTLR_EL1_ENDB 0x2000U
5191#define AARCH64_SCTLR_EL1_DZE 0x4000U
5193#define AARCH64_SCTLR_EL1_UCT 0x8000U
5195#define AARCH64_SCTLR_EL1_NTWI 0x10000U
5197#define AARCH64_SCTLR_EL1_NTWE 0x40000U
5199#define AARCH64_SCTLR_EL1_WXN 0x80000U
5201#define AARCH64_SCTLR_EL1_TSCXT 0x100000U
5203#define AARCH64_SCTLR_EL1_IESB 0x200000U
5205#define AARCH64_SCTLR_EL1_EIS 0x400000U
5207#define AARCH64_SCTLR_EL1_SPAN 0x800000U
5209#define AARCH64_SCTLR_EL1_E0E 0x1000000U
5211#define AARCH64_SCTLR_EL1_EE 0x2000000U
5213#define AARCH64_SCTLR_EL1_UCI 0x4000000U
5215#define AARCH64_SCTLR_EL1_ENDA 0x8000000U
5217#define AARCH64_SCTLR_EL1_NTLSMD 0x10000000U
5219#define AARCH64_SCTLR_EL1_LSMAOE 0x20000000U
5221#define AARCH64_SCTLR_EL1_ENIB 0x40000000U
5223#define AARCH64_SCTLR_EL1_ENIA 0x80000000U
5225#define AARCH64_SCTLR_EL1_BT0 0x800000000ULL
5227#define AARCH64_SCTLR_EL1_BT1 0x1000000000ULL
5229#define AARCH64_SCTLR_EL1_ITFSB 0x2000000000ULL
5231#define AARCH64_SCTLR_EL1_TCF0( _val ) ( ( _val ) << 38 )
5232#define AARCH64_SCTLR_EL1_TCF0_SHIFT 38
5233#define AARCH64_SCTLR_EL1_TCF0_MASK 0xc000000000ULL
5234#define AARCH64_SCTLR_EL1_TCF0_GET( _reg ) \
5235 ( ( ( _reg ) >> 38 ) & 0x3ULL )
5237#define AARCH64_SCTLR_EL1_TCF( _val ) ( ( _val ) << 40 )
5238#define AARCH64_SCTLR_EL1_TCF_SHIFT 40
5239#define AARCH64_SCTLR_EL1_TCF_MASK 0x30000000000ULL
5240#define AARCH64_SCTLR_EL1_TCF_GET( _reg ) \
5241 ( ( ( _reg ) >> 40 ) & 0x3ULL )
5243#define AARCH64_SCTLR_EL1_ATA0 0x40000000000ULL
5245#define AARCH64_SCTLR_EL1_ATA 0x80000000000ULL
5247#define AARCH64_SCTLR_EL1_DSSBS 0x100000000000ULL
5249#define AARCH64_SCTLR_EL1_TWEDEN 0x200000000000ULL
5251#define AARCH64_SCTLR_EL1_TWEDEL( _val ) ( ( _val ) << 46 )
5252#define AARCH64_SCTLR_EL1_TWEDEL_SHIFT 46
5253#define AARCH64_SCTLR_EL1_TWEDEL_MASK 0x3c00000000000ULL
5254#define AARCH64_SCTLR_EL1_TWEDEL_GET( _reg ) \
5255 ( ( ( _reg ) >> 46 ) & 0xfULL )
5257static inline uint64_t _AArch64_Read_sctlr_el1(
void )
5262 "mrs %0, SCTLR_EL1" :
"=&r" ( value ) : :
"memory"
5268static inline void _AArch64_Write_sctlr_el1( uint64_t value )
5271 "msr SCTLR_EL1, %0" : :
"r" ( value ) :
"memory"
5277#define AARCH64_SCTLR_EL2_M 0x1U
5279#define AARCH64_SCTLR_EL2_A 0x2U
5281#define AARCH64_SCTLR_EL2_C 0x4U
5283#define AARCH64_SCTLR_EL2_SA 0x8U
5285#define AARCH64_SCTLR_EL2_SA0 0x10U
5287#define AARCH64_SCTLR_EL2_CP15BEN 0x20U
5289#define AARCH64_SCTLR_EL2_NAA 0x40U
5291#define AARCH64_SCTLR_EL2_ITD 0x80U
5293#define AARCH64_SCTLR_EL2_SED 0x100U
5295#define AARCH64_SCTLR_EL2_ENRCTX 0x400U
5297#define AARCH64_SCTLR_EL2_EOS 0x800U
5299#define AARCH64_SCTLR_EL2_I 0x1000U
5301#define AARCH64_SCTLR_EL2_ENDB 0x2000U
5303#define AARCH64_SCTLR_EL2_DZE 0x4000U
5305#define AARCH64_SCTLR_EL2_UCT 0x8000U
5307#define AARCH64_SCTLR_EL2_NTWI 0x10000U
5309#define AARCH64_SCTLR_EL2_NTWE 0x40000U
5311#define AARCH64_SCTLR_EL2_WXN 0x80000U
5313#define AARCH64_SCTLR_EL2_TSCXT 0x100000U
5315#define AARCH64_SCTLR_EL2_IESB 0x200000U
5317#define AARCH64_SCTLR_EL2_EIS 0x400000U
5319#define AARCH64_SCTLR_EL2_SPAN 0x800000U
5321#define AARCH64_SCTLR_EL2_E0E 0x1000000U
5323#define AARCH64_SCTLR_EL2_EE 0x2000000U
5325#define AARCH64_SCTLR_EL2_UCI 0x4000000U
5327#define AARCH64_SCTLR_EL2_ENDA 0x8000000U
5329#define AARCH64_SCTLR_EL2_NTLSMD 0x10000000U
5331#define AARCH64_SCTLR_EL2_LSMAOE 0x20000000U
5333#define AARCH64_SCTLR_EL2_ENIB 0x40000000U
5335#define AARCH64_SCTLR_EL2_ENIA 0x80000000U
5337#define AARCH64_SCTLR_EL2_BT0 0x800000000ULL
5339#define AARCH64_SCTLR_EL2_BT 0x1000000000ULL
5341#define AARCH64_SCTLR_EL2_BT1 0x1000000000ULL
5343#define AARCH64_SCTLR_EL2_ITFSB 0x2000000000ULL
5345#define AARCH64_SCTLR_EL2_TCF0( _val ) ( ( _val ) << 38 )
5346#define AARCH64_SCTLR_EL2_TCF0_SHIFT 38
5347#define AARCH64_SCTLR_EL2_TCF0_MASK 0xc000000000ULL
5348#define AARCH64_SCTLR_EL2_TCF0_GET( _reg ) \
5349 ( ( ( _reg ) >> 38 ) & 0x3ULL )
5351#define AARCH64_SCTLR_EL2_TCF( _val ) ( ( _val ) << 40 )
5352#define AARCH64_SCTLR_EL2_TCF_SHIFT 40
5353#define AARCH64_SCTLR_EL2_TCF_MASK 0x30000000000ULL
5354#define AARCH64_SCTLR_EL2_TCF_GET( _reg ) \
5355 ( ( ( _reg ) >> 40 ) & 0x3ULL )
5357#define AARCH64_SCTLR_EL2_ATA0 0x40000000000ULL
5359#define AARCH64_SCTLR_EL2_ATA 0x80000000000ULL
5361#define AARCH64_SCTLR_EL2_DSSBS 0x100000000000ULL
5363#define AARCH64_SCTLR_EL2_TWEDEN 0x200000000000ULL
5365#define AARCH64_SCTLR_EL2_TWEDEL( _val ) ( ( _val ) << 46 )
5366#define AARCH64_SCTLR_EL2_TWEDEL_SHIFT 46
5367#define AARCH64_SCTLR_EL2_TWEDEL_MASK 0x3c00000000000ULL
5368#define AARCH64_SCTLR_EL2_TWEDEL_GET( _reg ) \
5369 ( ( ( _reg ) >> 46 ) & 0xfULL )
5371static inline uint64_t _AArch64_Read_sctlr_el2(
void )
5376 "mrs %0, SCTLR_EL2" :
"=&r" ( value ) : :
"memory"
5382static inline void _AArch64_Write_sctlr_el2( uint64_t value )
5385 "msr SCTLR_EL2, %0" : :
"r" ( value ) :
"memory"
5391#define AARCH64_SCTLR_EL3_M 0x1U
5393#define AARCH64_SCTLR_EL3_A 0x2U
5395#define AARCH64_SCTLR_EL3_C 0x4U
5397#define AARCH64_SCTLR_EL3_SA 0x8U
5399#define AARCH64_SCTLR_EL3_NAA 0x40U
5401#define AARCH64_SCTLR_EL3_EOS 0x800U
5403#define AARCH64_SCTLR_EL3_I 0x1000U
5405#define AARCH64_SCTLR_EL3_ENDB 0x2000U
5407#define AARCH64_SCTLR_EL3_WXN 0x80000U
5409#define AARCH64_SCTLR_EL3_IESB 0x200000U
5411#define AARCH64_SCTLR_EL3_EIS 0x400000U
5413#define AARCH64_SCTLR_EL3_EE 0x2000000U
5415#define AARCH64_SCTLR_EL3_ENDA 0x8000000U
5417#define AARCH64_SCTLR_EL3_ENIB 0x40000000U
5419#define AARCH64_SCTLR_EL3_ENIA 0x80000000U
5421#define AARCH64_SCTLR_EL3_BT 0x1000000000ULL
5423#define AARCH64_SCTLR_EL3_ITFSB 0x2000000000ULL
5425#define AARCH64_SCTLR_EL3_TCF( _val ) ( ( _val ) << 40 )
5426#define AARCH64_SCTLR_EL3_TCF_SHIFT 40
5427#define AARCH64_SCTLR_EL3_TCF_MASK 0x30000000000ULL
5428#define AARCH64_SCTLR_EL3_TCF_GET( _reg ) \
5429 ( ( ( _reg ) >> 40 ) & 0x3ULL )
5431#define AARCH64_SCTLR_EL3_ATA 0x80000000000ULL
5433#define AARCH64_SCTLR_EL3_DSSBS 0x100000000000ULL
5435static inline uint64_t _AArch64_Read_sctlr_el3(
void )
5440 "mrs %0, SCTLR_EL3" :
"=&r" ( value ) : :
"memory"
5446static inline void _AArch64_Write_sctlr_el3( uint64_t value )
5449 "msr SCTLR_EL3, %0" : :
"r" ( value ) :
"memory"
5455static inline uint64_t _AArch64_Read_scxtnum_el0(
void )
5460 "mrs %0, SCXTNUM_EL0" :
"=&r" ( value ) : :
"memory"
5466static inline void _AArch64_Write_scxtnum_el0( uint64_t value )
5469 "msr SCXTNUM_EL0, %0" : :
"r" ( value ) :
"memory"
5475static inline uint64_t _AArch64_Read_scxtnum_el1(
void )
5480 "mrs %0, SCXTNUM_EL1" :
"=&r" ( value ) : :
"memory"
5486static inline void _AArch64_Write_scxtnum_el1( uint64_t value )
5489 "msr SCXTNUM_EL1, %0" : :
"r" ( value ) :
"memory"
5495static inline uint64_t _AArch64_Read_scxtnum_el2(
void )
5500 "mrs %0, SCXTNUM_EL2" :
"=&r" ( value ) : :
"memory"
5506static inline void _AArch64_Write_scxtnum_el2( uint64_t value )
5509 "msr SCXTNUM_EL2, %0" : :
"r" ( value ) :
"memory"
5515static inline uint64_t _AArch64_Read_scxtnum_el3(
void )
5520 "mrs %0, SCXTNUM_EL3" :
"=&r" ( value ) : :
"memory"
5526static inline void _AArch64_Write_scxtnum_el3( uint64_t value )
5529 "msr SCXTNUM_EL3, %0" : :
"r" ( value ) :
"memory"
5535#define AARCH64_TCR_EL1_T0SZ( _val ) ( ( _val ) << 0 )
5536#define AARCH64_TCR_EL1_T0SZ_SHIFT 0
5537#define AARCH64_TCR_EL1_T0SZ_MASK 0x3fU
5538#define AARCH64_TCR_EL1_T0SZ_GET( _reg ) \
5539 ( ( ( _reg ) >> 0 ) & 0x3fU )
5541#define AARCH64_TCR_EL1_EPD0 0x80U
5543#define AARCH64_TCR_EL1_IRGN0( _val ) ( ( _val ) << 8 )
5544#define AARCH64_TCR_EL1_IRGN0_SHIFT 8
5545#define AARCH64_TCR_EL1_IRGN0_MASK 0x300U
5546#define AARCH64_TCR_EL1_IRGN0_GET( _reg ) \
5547 ( ( ( _reg ) >> 8 ) & 0x3U )
5549#define AARCH64_TCR_EL1_ORGN0( _val ) ( ( _val ) << 10 )
5550#define AARCH64_TCR_EL1_ORGN0_SHIFT 10
5551#define AARCH64_TCR_EL1_ORGN0_MASK 0xc00U
5552#define AARCH64_TCR_EL1_ORGN0_GET( _reg ) \
5553 ( ( ( _reg ) >> 10 ) & 0x3U )
5555#define AARCH64_TCR_EL1_SH0( _val ) ( ( _val ) << 12 )
5556#define AARCH64_TCR_EL1_SH0_SHIFT 12
5557#define AARCH64_TCR_EL1_SH0_MASK 0x3000U
5558#define AARCH64_TCR_EL1_SH0_GET( _reg ) \
5559 ( ( ( _reg ) >> 12 ) & 0x3U )
5561#define AARCH64_TCR_EL1_TG0( _val ) ( ( _val ) << 14 )
5562#define AARCH64_TCR_EL1_TG0_SHIFT 14
5563#define AARCH64_TCR_EL1_TG0_MASK 0xc000U
5564#define AARCH64_TCR_EL1_TG0_GET( _reg ) \
5565 ( ( ( _reg ) >> 14 ) & 0x3U )
5567#define AARCH64_TCR_EL1_T1SZ( _val ) ( ( _val ) << 16 )
5568#define AARCH64_TCR_EL1_T1SZ_SHIFT 16
5569#define AARCH64_TCR_EL1_T1SZ_MASK 0x3f0000U
5570#define AARCH64_TCR_EL1_T1SZ_GET( _reg ) \
5571 ( ( ( _reg ) >> 16 ) & 0x3fU )
5573#define AARCH64_TCR_EL1_A1 0x400000U
5575#define AARCH64_TCR_EL1_EPD1 0x800000U
5577#define AARCH64_TCR_EL1_IRGN1( _val ) ( ( _val ) << 24 )
5578#define AARCH64_TCR_EL1_IRGN1_SHIFT 24
5579#define AARCH64_TCR_EL1_IRGN1_MASK 0x3000000U
5580#define AARCH64_TCR_EL1_IRGN1_GET( _reg ) \
5581 ( ( ( _reg ) >> 24 ) & 0x3U )
5583#define AARCH64_TCR_EL1_ORGN1( _val ) ( ( _val ) << 26 )
5584#define AARCH64_TCR_EL1_ORGN1_SHIFT 26
5585#define AARCH64_TCR_EL1_ORGN1_MASK 0xc000000U
5586#define AARCH64_TCR_EL1_ORGN1_GET( _reg ) \
5587 ( ( ( _reg ) >> 26 ) & 0x3U )
5589#define AARCH64_TCR_EL1_SH1( _val ) ( ( _val ) << 28 )
5590#define AARCH64_TCR_EL1_SH1_SHIFT 28
5591#define AARCH64_TCR_EL1_SH1_MASK 0x30000000U
5592#define AARCH64_TCR_EL1_SH1_GET( _reg ) \
5593 ( ( ( _reg ) >> 28 ) & 0x3U )
5595#define AARCH64_TCR_EL1_TG1( _val ) ( ( _val ) << 30 )
5596#define AARCH64_TCR_EL1_TG1_SHIFT 30
5597#define AARCH64_TCR_EL1_TG1_MASK 0xc0000000U
5598#define AARCH64_TCR_EL1_TG1_GET( _reg ) \
5599 ( ( ( _reg ) >> 30 ) & 0x3U )
5601#define AARCH64_TCR_EL1_IPS( _val ) ( ( _val ) << 32 )
5602#define AARCH64_TCR_EL1_IPS_SHIFT 32
5603#define AARCH64_TCR_EL1_IPS_MASK 0x700000000ULL
5604#define AARCH64_TCR_EL1_IPS_GET( _reg ) \
5605 ( ( ( _reg ) >> 32 ) & 0x7ULL )
5607#define AARCH64_TCR_EL1_AS 0x1000000000ULL
5609#define AARCH64_TCR_EL1_TBI0 0x2000000000ULL
5611#define AARCH64_TCR_EL1_TBI1 0x4000000000ULL
5613#define AARCH64_TCR_EL1_HA 0x8000000000ULL
5615#define AARCH64_TCR_EL1_HD 0x10000000000ULL
5617#define AARCH64_TCR_EL1_HPD0 0x20000000000ULL
5619#define AARCH64_TCR_EL1_HPD1 0x40000000000ULL
5621#define AARCH64_TCR_EL1_HWU059 0x80000000000ULL
5623#define AARCH64_TCR_EL1_HWU060 0x100000000000ULL
5625#define AARCH64_TCR_EL1_HWU061 0x200000000000ULL
5627#define AARCH64_TCR_EL1_HWU062 0x400000000000ULL
5629#define AARCH64_TCR_EL1_HWU159 0x800000000000ULL
5631#define AARCH64_TCR_EL1_HWU160 0x1000000000000ULL
5633#define AARCH64_TCR_EL1_HWU161 0x2000000000000ULL
5635#define AARCH64_TCR_EL1_HWU162 0x4000000000000ULL
5637#define AARCH64_TCR_EL1_TBID0 0x8000000000000ULL
5639#define AARCH64_TCR_EL1_TBID1 0x10000000000000ULL
5641#define AARCH64_TCR_EL1_NFD0 0x20000000000000ULL
5643#define AARCH64_TCR_EL1_NFD1 0x40000000000000ULL
5645#define AARCH64_TCR_EL1_E0PD0 0x80000000000000ULL
5647#define AARCH64_TCR_EL1_E0PD1 0x100000000000000ULL
5649#define AARCH64_TCR_EL1_TCMA0 0x200000000000000ULL
5651#define AARCH64_TCR_EL1_TCMA1 0x400000000000000ULL
5653static inline uint64_t _AArch64_Read_tcr_el1(
void )
5658 "mrs %0, TCR_EL1" :
"=&r" ( value ) : :
"memory"
5664static inline void _AArch64_Write_tcr_el1( uint64_t value )
5667 "msr TCR_EL1, %0" : :
"r" ( value ) :
"memory"
5673#define AARCH64_TCR_EL2_T0SZ( _val ) ( ( _val ) << 0 )
5674#define AARCH64_TCR_EL2_T0SZ_SHIFT 0
5675#define AARCH64_TCR_EL2_T0SZ_MASK 0x3fU
5676#define AARCH64_TCR_EL2_T0SZ_GET( _reg ) \
5677 ( ( ( _reg ) >> 0 ) & 0x3fU )
5679#define AARCH64_TCR_EL2_EPD0 0x80U
5681#define AARCH64_TCR_EL2_IRGN0( _val ) ( ( _val ) << 8 )
5682#define AARCH64_TCR_EL2_IRGN0_SHIFT 8
5683#define AARCH64_TCR_EL2_IRGN0_MASK 0x300U
5684#define AARCH64_TCR_EL2_IRGN0_GET( _reg ) \
5685 ( ( ( _reg ) >> 8 ) & 0x3U )
5687#define AARCH64_TCR_EL2_ORGN0( _val ) ( ( _val ) << 10 )
5688#define AARCH64_TCR_EL2_ORGN0_SHIFT 10
5689#define AARCH64_TCR_EL2_ORGN0_MASK 0xc00U
5690#define AARCH64_TCR_EL2_ORGN0_GET( _reg ) \
5691 ( ( ( _reg ) >> 10 ) & 0x3U )
5693#define AARCH64_TCR_EL2_SH0( _val ) ( ( _val ) << 12 )
5694#define AARCH64_TCR_EL2_SH0_SHIFT 12
5695#define AARCH64_TCR_EL2_SH0_MASK 0x3000U
5696#define AARCH64_TCR_EL2_SH0_GET( _reg ) \
5697 ( ( ( _reg ) >> 12 ) & 0x3U )
5699#define AARCH64_TCR_EL2_TG0( _val ) ( ( _val ) << 14 )
5700#define AARCH64_TCR_EL2_TG0_SHIFT 14
5701#define AARCH64_TCR_EL2_TG0_MASK 0xc000U
5702#define AARCH64_TCR_EL2_TG0_GET( _reg ) \
5703 ( ( ( _reg ) >> 14 ) & 0x3U )
5705#define AARCH64_TCR_EL2_PS( _val ) ( ( _val ) << 16 )
5706#define AARCH64_TCR_EL2_PS_SHIFT 16
5707#define AARCH64_TCR_EL2_PS_MASK 0x70000U
5708#define AARCH64_TCR_EL2_PS_GET( _reg ) \
5709 ( ( ( _reg ) >> 16 ) & 0x7U )
5711#define AARCH64_TCR_EL2_T1SZ( _val ) ( ( _val ) << 16 )
5712#define AARCH64_TCR_EL2_T1SZ_SHIFT 16
5713#define AARCH64_TCR_EL2_T1SZ_MASK 0x3f0000U
5714#define AARCH64_TCR_EL2_T1SZ_GET( _reg ) \
5715 ( ( ( _reg ) >> 16 ) & 0x3fU )
5717#define AARCH64_TCR_EL2_TBI 0x100000U
5719#define AARCH64_TCR_EL2_HA_0 0x200000U
5721#define AARCH64_TCR_EL2_A1 0x400000U
5723#define AARCH64_TCR_EL2_HD_0 0x400000U
5725#define AARCH64_TCR_EL2_EPD1 0x800000U
5727#define AARCH64_TCR_EL2_HPD 0x1000000U
5729#define AARCH64_TCR_EL2_IRGN1( _val ) ( ( _val ) << 24 )
5730#define AARCH64_TCR_EL2_IRGN1_SHIFT 24
5731#define AARCH64_TCR_EL2_IRGN1_MASK 0x3000000U
5732#define AARCH64_TCR_EL2_IRGN1_GET( _reg ) \
5733 ( ( ( _reg ) >> 24 ) & 0x3U )
5735#define AARCH64_TCR_EL2_HWU59 0x2000000U
5737#define AARCH64_TCR_EL2_HWU60 0x4000000U
5739#define AARCH64_TCR_EL2_ORGN1( _val ) ( ( _val ) << 26 )
5740#define AARCH64_TCR_EL2_ORGN1_SHIFT 26
5741#define AARCH64_TCR_EL2_ORGN1_MASK 0xc000000U
5742#define AARCH64_TCR_EL2_ORGN1_GET( _reg ) \
5743 ( ( ( _reg ) >> 26 ) & 0x3U )
5745#define AARCH64_TCR_EL2_HWU61 0x8000000U
5747#define AARCH64_TCR_EL2_HWU62 0x10000000U
5749#define AARCH64_TCR_EL2_SH1( _val ) ( ( _val ) << 28 )
5750#define AARCH64_TCR_EL2_SH1_SHIFT 28
5751#define AARCH64_TCR_EL2_SH1_MASK 0x30000000U
5752#define AARCH64_TCR_EL2_SH1_GET( _reg ) \
5753 ( ( ( _reg ) >> 28 ) & 0x3U )
5755#define AARCH64_TCR_EL2_TBID 0x20000000U
5757#define AARCH64_TCR_EL2_TCMA 0x40000000U
5759#define AARCH64_TCR_EL2_TG1( _val ) ( ( _val ) << 30 )
5760#define AARCH64_TCR_EL2_TG1_SHIFT 30
5761#define AARCH64_TCR_EL2_TG1_MASK 0xc0000000U
5762#define AARCH64_TCR_EL2_TG1_GET( _reg ) \
5763 ( ( ( _reg ) >> 30 ) & 0x3U )
5765#define AARCH64_TCR_EL2_IPS( _val ) ( ( _val ) << 32 )
5766#define AARCH64_TCR_EL2_IPS_SHIFT 32
5767#define AARCH64_TCR_EL2_IPS_MASK 0x700000000ULL
5768#define AARCH64_TCR_EL2_IPS_GET( _reg ) \
5769 ( ( ( _reg ) >> 32 ) & 0x7ULL )
5771#define AARCH64_TCR_EL2_AS 0x1000000000ULL
5773#define AARCH64_TCR_EL2_TBI0 0x2000000000ULL
5775#define AARCH64_TCR_EL2_TBI1 0x4000000000ULL
5777#define AARCH64_TCR_EL2_HA_1 0x8000000000ULL
5779#define AARCH64_TCR_EL2_HD_1 0x10000000000ULL
5781#define AARCH64_TCR_EL2_HPD0 0x20000000000ULL
5783#define AARCH64_TCR_EL2_HPD1 0x40000000000ULL
5785#define AARCH64_TCR_EL2_HWU059 0x80000000000ULL
5787#define AARCH64_TCR_EL2_HWU060 0x100000000000ULL
5789#define AARCH64_TCR_EL2_HWU061 0x200000000000ULL
5791#define AARCH64_TCR_EL2_HWU062 0x400000000000ULL
5793#define AARCH64_TCR_EL2_HWU159 0x800000000000ULL
5795#define AARCH64_TCR_EL2_HWU160 0x1000000000000ULL
5797#define AARCH64_TCR_EL2_HWU161 0x2000000000000ULL
5799#define AARCH64_TCR_EL2_HWU162 0x4000000000000ULL
5801#define AARCH64_TCR_EL2_TBID0 0x8000000000000ULL
5803#define AARCH64_TCR_EL2_TBID1 0x10000000000000ULL
5805#define AARCH64_TCR_EL2_NFD0 0x20000000000000ULL
5807#define AARCH64_TCR_EL2_NFD1 0x40000000000000ULL
5809#define AARCH64_TCR_EL2_E0PD0 0x80000000000000ULL
5811#define AARCH64_TCR_EL2_E0PD1 0x100000000000000ULL
5813#define AARCH64_TCR_EL2_TCMA0 0x200000000000000ULL
5815#define AARCH64_TCR_EL2_TCMA1 0x400000000000000ULL
5817static inline uint64_t _AArch64_Read_tcr_el2(
void )
5822 "mrs %0, TCR_EL2" :
"=&r" ( value ) : :
"memory"
5828static inline void _AArch64_Write_tcr_el2( uint64_t value )
5831 "msr TCR_EL2, %0" : :
"r" ( value ) :
"memory"
5837#define AARCH64_TCR_EL3_T0SZ( _val ) ( ( _val ) << 0 )
5838#define AARCH64_TCR_EL3_T0SZ_SHIFT 0
5839#define AARCH64_TCR_EL3_T0SZ_MASK 0x3fU
5840#define AARCH64_TCR_EL3_T0SZ_GET( _reg ) \
5841 ( ( ( _reg ) >> 0 ) & 0x3fU )
5843#define AARCH64_TCR_EL3_IRGN0( _val ) ( ( _val ) << 8 )
5844#define AARCH64_TCR_EL3_IRGN0_SHIFT 8
5845#define AARCH64_TCR_EL3_IRGN0_MASK 0x300U
5846#define AARCH64_TCR_EL3_IRGN0_GET( _reg ) \
5847 ( ( ( _reg ) >> 8 ) & 0x3U )
5849#define AARCH64_TCR_EL3_ORGN0( _val ) ( ( _val ) << 10 )
5850#define AARCH64_TCR_EL3_ORGN0_SHIFT 10
5851#define AARCH64_TCR_EL3_ORGN0_MASK 0xc00U
5852#define AARCH64_TCR_EL3_ORGN0_GET( _reg ) \
5853 ( ( ( _reg ) >> 10 ) & 0x3U )
5855#define AARCH64_TCR_EL3_SH0( _val ) ( ( _val ) << 12 )
5856#define AARCH64_TCR_EL3_SH0_SHIFT 12
5857#define AARCH64_TCR_EL3_SH0_MASK 0x3000U
5858#define AARCH64_TCR_EL3_SH0_GET( _reg ) \
5859 ( ( ( _reg ) >> 12 ) & 0x3U )
5861#define AARCH64_TCR_EL3_TG0( _val ) ( ( _val ) << 14 )
5862#define AARCH64_TCR_EL3_TG0_SHIFT 14
5863#define AARCH64_TCR_EL3_TG0_MASK 0xc000U
5864#define AARCH64_TCR_EL3_TG0_GET( _reg ) \
5865 ( ( ( _reg ) >> 14 ) & 0x3U )
5867#define AARCH64_TCR_EL3_PS( _val ) ( ( _val ) << 16 )
5868#define AARCH64_TCR_EL3_PS_SHIFT 16
5869#define AARCH64_TCR_EL3_PS_MASK 0x70000U
5870#define AARCH64_TCR_EL3_PS_GET( _reg ) \
5871 ( ( ( _reg ) >> 16 ) & 0x7U )
5873#define AARCH64_TCR_EL3_TBI 0x100000U
5875#define AARCH64_TCR_EL3_HA 0x200000U
5877#define AARCH64_TCR_EL3_HD 0x400000U
5879#define AARCH64_TCR_EL3_HPD 0x1000000U
5881#define AARCH64_TCR_EL3_HWU59 0x2000000U
5883#define AARCH64_TCR_EL3_HWU60 0x4000000U
5885#define AARCH64_TCR_EL3_HWU61 0x8000000U
5887#define AARCH64_TCR_EL3_HWU62 0x10000000U
5889#define AARCH64_TCR_EL3_TBID 0x20000000U
5891#define AARCH64_TCR_EL3_TCMA 0x40000000U
5893static inline uint64_t _AArch64_Read_tcr_el3(
void )
5898 "mrs %0, TCR_EL3" :
"=&r" ( value ) : :
"memory"
5904static inline void _AArch64_Write_tcr_el3( uint64_t value )
5907 "msr TCR_EL3, %0" : :
"r" ( value ) :
"memory"
5913#define AARCH64_TFSRE0_EL1_TF0 0x1U
5915#define AARCH64_TFSRE0_EL1_TF1 0x2U
5917static inline uint64_t _AArch64_Read_tfsre0_el1(
void )
5922 "mrs %0, TFSRE0_EL1" :
"=&r" ( value ) : :
"memory"
5928static inline void _AArch64_Write_tfsre0_el1( uint64_t value )
5931 "msr TFSRE0_EL1, %0" : :
"r" ( value ) :
"memory"
5937#define AARCH64_TFSR_EL1_TF0 0x1U
5939#define AARCH64_TFSR_EL1_TF1 0x2U
5941static inline uint64_t _AArch64_Read_tfsr_el1(
void )
5946 "mrs %0, TFSR_EL1" :
"=&r" ( value ) : :
"memory"
5952static inline void _AArch64_Write_tfsr_el1( uint64_t value )
5955 "msr TFSR_EL1, %0" : :
"r" ( value ) :
"memory"
5961#define AARCH64_TFSR_EL2_TF0 0x1U
5963#define AARCH64_TFSR_EL2_TF1 0x2U
5965static inline uint64_t _AArch64_Read_tfsr_el2(
void )
5970 "mrs %0, TFSR_EL2" :
"=&r" ( value ) : :
"memory"
5976static inline void _AArch64_Write_tfsr_el2( uint64_t value )
5979 "msr TFSR_EL2, %0" : :
"r" ( value ) :
"memory"
5985#define AARCH64_TFSR_EL3_TF0 0x1U
5987static inline uint64_t _AArch64_Read_tfsr_el3(
void )
5992 "mrs %0, TFSR_EL3" :
"=&r" ( value ) : :
"memory"
5998static inline void _AArch64_Write_tfsr_el3( uint64_t value )
6001 "msr TFSR_EL3, %0" : :
"r" ( value ) :
"memory"
6007static inline uint64_t _AArch64_Read_tpidr_el0(
void )
6012 "mrs %0, TPIDR_EL0" :
"=&r" ( value ) : :
"memory"
6018static inline void _AArch64_Write_tpidr_el0( uint64_t value )
6021 "msr TPIDR_EL0, %0" : :
"r" ( value ) :
"memory"
6027static inline uint64_t _AArch64_Read_tpidr_el1(
void )
6032 "mrs %0, TPIDR_EL1" :
"=&r" ( value ) : :
"memory"
6038static inline void _AArch64_Write_tpidr_el1( uint64_t value )
6041 "msr TPIDR_EL1, %0" : :
"r" ( value ) :
"memory"
6047static inline uint64_t _AArch64_Read_tpidr_el2(
void )
6052 "mrs %0, TPIDR_EL2" :
"=&r" ( value ) : :
"memory"
6058static inline void _AArch64_Write_tpidr_el2( uint64_t value )
6061 "msr TPIDR_EL2, %0" : :
"r" ( value ) :
"memory"
6067static inline uint64_t _AArch64_Read_tpidr_el3(
void )
6072 "mrs %0, TPIDR_EL3" :
"=&r" ( value ) : :
"memory"
6078static inline void _AArch64_Write_tpidr_el3( uint64_t value )
6081 "msr TPIDR_EL3, %0" : :
"r" ( value ) :
"memory"
6087static inline uint64_t _AArch64_Read_tpidrro_el0(
void )
6092 "mrs %0, TPIDRRO_EL0" :
"=&r" ( value ) : :
"memory"
6098static inline void _AArch64_Write_tpidrro_el0( uint64_t value )
6101 "msr TPIDRRO_EL0, %0" : :
"r" ( value ) :
"memory"
6107#define AARCH64_TTBR0_EL1_CNP 0x1U
6109#define AARCH64_TTBR0_EL1_BADDR( _val ) ( ( _val ) << 1 )
6110#define AARCH64_TTBR0_EL1_BADDR_SHIFT 1
6111#define AARCH64_TTBR0_EL1_BADDR_MASK 0xfffffffffffeULL
6112#define AARCH64_TTBR0_EL1_BADDR_GET( _reg ) \
6113 ( ( ( _reg ) >> 1 ) & 0x7fffffffffffULL )
6115#define AARCH64_TTBR0_EL1_ASID( _val ) ( ( _val ) << 48 )
6116#define AARCH64_TTBR0_EL1_ASID_SHIFT 48
6117#define AARCH64_TTBR0_EL1_ASID_MASK 0xffff000000000000ULL
6118#define AARCH64_TTBR0_EL1_ASID_GET( _reg ) \
6119 ( ( ( _reg ) >> 48 ) & 0xffffULL )
6121static inline uint64_t _AArch64_Read_ttbr0_el1(
void )
6126 "mrs %0, TTBR0_EL1" :
"=&r" ( value ) : :
"memory"
6132static inline void _AArch64_Write_ttbr0_el1( uint64_t value )
6135 "msr TTBR0_EL1, %0" : :
"r" ( value ) :
"memory"
6141#define AARCH64_TTBR0_EL2_CNP 0x1U
6143#define AARCH64_TTBR0_EL2_BADDR( _val ) ( ( _val ) << 1 )
6144#define AARCH64_TTBR0_EL2_BADDR_SHIFT 1
6145#define AARCH64_TTBR0_EL2_BADDR_MASK 0xfffffffffffeULL
6146#define AARCH64_TTBR0_EL2_BADDR_GET( _reg ) \
6147 ( ( ( _reg ) >> 1 ) & 0x7fffffffffffULL )
6149#define AARCH64_TTBR0_EL2_ASID( _val ) ( ( _val ) << 48 )
6150#define AARCH64_TTBR0_EL2_ASID_SHIFT 48
6151#define AARCH64_TTBR0_EL2_ASID_MASK 0xffff000000000000ULL
6152#define AARCH64_TTBR0_EL2_ASID_GET( _reg ) \
6153 ( ( ( _reg ) >> 48 ) & 0xffffULL )
6155static inline uint64_t _AArch64_Read_ttbr0_el2(
void )
6160 "mrs %0, TTBR0_EL2" :
"=&r" ( value ) : :
"memory"
6166static inline void _AArch64_Write_ttbr0_el2( uint64_t value )
6169 "msr TTBR0_EL2, %0" : :
"r" ( value ) :
"memory"
6175#define AARCH64_TTBR0_EL3_CNP 0x1U
6177#define AARCH64_TTBR0_EL3_BADDR( _val ) ( ( _val ) << 1 )
6178#define AARCH64_TTBR0_EL3_BADDR_SHIFT 1
6179#define AARCH64_TTBR0_EL3_BADDR_MASK 0xfffffffffffeULL
6180#define AARCH64_TTBR0_EL3_BADDR_GET( _reg ) \
6181 ( ( ( _reg ) >> 1 ) & 0x7fffffffffffULL )
6183static inline uint64_t _AArch64_Read_ttbr0_el3(
void )
6188 "mrs %0, TTBR0_EL3" :
"=&r" ( value ) : :
"memory"
6194static inline void _AArch64_Write_ttbr0_el3( uint64_t value )
6197 "msr TTBR0_EL3, %0" : :
"r" ( value ) :
"memory"
6203#define AARCH64_TTBR1_EL1_CNP 0x1U
6205#define AARCH64_TTBR1_EL1_BADDR( _val ) ( ( _val ) << 1 )
6206#define AARCH64_TTBR1_EL1_BADDR_SHIFT 1
6207#define AARCH64_TTBR1_EL1_BADDR_MASK 0xfffffffffffeULL
6208#define AARCH64_TTBR1_EL1_BADDR_GET( _reg ) \
6209 ( ( ( _reg ) >> 1 ) & 0x7fffffffffffULL )
6211#define AARCH64_TTBR1_EL1_ASID( _val ) ( ( _val ) << 48 )
6212#define AARCH64_TTBR1_EL1_ASID_SHIFT 48
6213#define AARCH64_TTBR1_EL1_ASID_MASK 0xffff000000000000ULL
6214#define AARCH64_TTBR1_EL1_ASID_GET( _reg ) \
6215 ( ( ( _reg ) >> 48 ) & 0xffffULL )
6217static inline uint64_t _AArch64_Read_ttbr1_el1(
void )
6222 "mrs %0, TTBR1_EL1" :
"=&r" ( value ) : :
"memory"
6228static inline void _AArch64_Write_ttbr1_el1( uint64_t value )
6231 "msr TTBR1_EL1, %0" : :
"r" ( value ) :
"memory"
6237#define AARCH64_TTBR1_EL2_CNP 0x1U
6239#define AARCH64_TTBR1_EL2_BADDR( _val ) ( ( _val ) << 1 )
6240#define AARCH64_TTBR1_EL2_BADDR_SHIFT 1
6241#define AARCH64_TTBR1_EL2_BADDR_MASK 0xfffffffffffeULL
6242#define AARCH64_TTBR1_EL2_BADDR_GET( _reg ) \
6243 ( ( ( _reg ) >> 1 ) & 0x7fffffffffffULL )
6245#define AARCH64_TTBR1_EL2_ASID( _val ) ( ( _val ) << 48 )
6246#define AARCH64_TTBR1_EL2_ASID_SHIFT 48
6247#define AARCH64_TTBR1_EL2_ASID_MASK 0xffff000000000000ULL
6248#define AARCH64_TTBR1_EL2_ASID_GET( _reg ) \
6249 ( ( ( _reg ) >> 48 ) & 0xffffULL )
6251static inline uint64_t _AArch64_Read_ttbr1_el2(
void )
6256 "mrs %0, TTBR1_EL2" :
"=&r" ( value ) : :
"memory"
6262static inline void _AArch64_Write_ttbr1_el2( uint64_t value )
6265 "msr TTBR1_EL2, %0" : :
"r" ( value ) :
"memory"
6271static inline uint64_t _AArch64_Read_vbar_el1(
void )
6276 "mrs %0, VBAR_EL1" :
"=&r" ( value ) : :
"memory"
6282static inline void _AArch64_Write_vbar_el1( uint64_t value )
6285 "msr VBAR_EL1, %0" : :
"r" ( value ) :
"memory"
6291static inline uint64_t _AArch64_Read_vbar_el2(
void )
6296 "mrs %0, VBAR_EL2" :
"=&r" ( value ) : :
"memory"
6302static inline void _AArch64_Write_vbar_el2( uint64_t value )
6305 "msr VBAR_EL2, %0" : :
"r" ( value ) :
"memory"
6311static inline uint64_t _AArch64_Read_vbar_el3(
void )
6316 "mrs %0, VBAR_EL3" :
"=&r" ( value ) : :
"memory"
6322static inline void _AArch64_Write_vbar_el3( uint64_t value )
6325 "msr VBAR_EL3, %0" : :
"r" ( value ) :
"memory"
6331#define AARCH64_VMPIDR_EL2_AFF0( _val ) ( ( _val ) << 0 )
6332#define AARCH64_VMPIDR_EL2_AFF0_SHIFT 0
6333#define AARCH64_VMPIDR_EL2_AFF0_MASK 0xffU
6334#define AARCH64_VMPIDR_EL2_AFF0_GET( _reg ) \
6335 ( ( ( _reg ) >> 0 ) & 0xffU )
6337#define AARCH64_VMPIDR_EL2_AFF1( _val ) ( ( _val ) << 8 )
6338#define AARCH64_VMPIDR_EL2_AFF1_SHIFT 8
6339#define AARCH64_VMPIDR_EL2_AFF1_MASK 0xff00U
6340#define AARCH64_VMPIDR_EL2_AFF1_GET( _reg ) \
6341 ( ( ( _reg ) >> 8 ) & 0xffU )
6343#define AARCH64_VMPIDR_EL2_AFF2( _val ) ( ( _val ) << 16 )
6344#define AARCH64_VMPIDR_EL2_AFF2_SHIFT 16
6345#define AARCH64_VMPIDR_EL2_AFF2_MASK 0xff0000U
6346#define AARCH64_VMPIDR_EL2_AFF2_GET( _reg ) \
6347 ( ( ( _reg ) >> 16 ) & 0xffU )
6349#define AARCH64_VMPIDR_EL2_MT 0x1000000U
6351#define AARCH64_VMPIDR_EL2_U 0x40000000U
6353#define AARCH64_VMPIDR_EL2_AFF3( _val ) ( ( _val ) << 32 )
6354#define AARCH64_VMPIDR_EL2_AFF3_SHIFT 32
6355#define AARCH64_VMPIDR_EL2_AFF3_MASK 0xff00000000ULL
6356#define AARCH64_VMPIDR_EL2_AFF3_GET( _reg ) \
6357 ( ( ( _reg ) >> 32 ) & 0xffULL )
6359static inline uint64_t _AArch64_Read_vmpidr_el2(
void )
6364 "mrs %0, VMPIDR_EL2" :
"=&r" ( value ) : :
"memory"
6370static inline void _AArch64_Write_vmpidr_el2( uint64_t value )
6373 "msr VMPIDR_EL2, %0" : :
"r" ( value ) :
"memory"
6379#define AARCH64_VNCR_EL2_BADDR( _val ) ( ( _val ) << 12 )
6380#define AARCH64_VNCR_EL2_BADDR_SHIFT 12
6381#define AARCH64_VNCR_EL2_BADDR_MASK 0x1ffffffffff000ULL
6382#define AARCH64_VNCR_EL2_BADDR_GET( _reg ) \
6383 ( ( ( _reg ) >> 12 ) & 0x1ffffffffffULL )
6385#define AARCH64_VNCR_EL2_RESS( _val ) ( ( _val ) << 53 )
6386#define AARCH64_VNCR_EL2_RESS_SHIFT 53
6387#define AARCH64_VNCR_EL2_RESS_MASK 0xffe0000000000000ULL
6388#define AARCH64_VNCR_EL2_RESS_GET( _reg ) \
6389 ( ( ( _reg ) >> 53 ) & 0x7ffULL )
6391static inline uint64_t _AArch64_Read_vncr_el2(
void )
6396 "mrs %0, VNCR_EL2" :
"=&r" ( value ) : :
"memory"
6402static inline void _AArch64_Write_vncr_el2( uint64_t value )
6405 "msr VNCR_EL2, %0" : :
"r" ( value ) :
"memory"
6411#define AARCH64_VPIDR_EL2_REVISION( _val ) ( ( _val ) << 0 )
6412#define AARCH64_VPIDR_EL2_REVISION_SHIFT 0
6413#define AARCH64_VPIDR_EL2_REVISION_MASK 0xfU
6414#define AARCH64_VPIDR_EL2_REVISION_GET( _reg ) \
6415 ( ( ( _reg ) >> 0 ) & 0xfU )
6417#define AARCH64_VPIDR_EL2_PARTNUM( _val ) ( ( _val ) << 4 )
6418#define AARCH64_VPIDR_EL2_PARTNUM_SHIFT 4
6419#define AARCH64_VPIDR_EL2_PARTNUM_MASK 0xfff0U
6420#define AARCH64_VPIDR_EL2_PARTNUM_GET( _reg ) \
6421 ( ( ( _reg ) >> 4 ) & 0xfffU )
6423#define AARCH64_VPIDR_EL2_ARCHITECTURE( _val ) ( ( _val ) << 16 )
6424#define AARCH64_VPIDR_EL2_ARCHITECTURE_SHIFT 16
6425#define AARCH64_VPIDR_EL2_ARCHITECTURE_MASK 0xf0000U
6426#define AARCH64_VPIDR_EL2_ARCHITECTURE_GET( _reg ) \
6427 ( ( ( _reg ) >> 16 ) & 0xfU )
6429#define AARCH64_VPIDR_EL2_VARIANT( _val ) ( ( _val ) << 20 )
6430#define AARCH64_VPIDR_EL2_VARIANT_SHIFT 20
6431#define AARCH64_VPIDR_EL2_VARIANT_MASK 0xf00000U
6432#define AARCH64_VPIDR_EL2_VARIANT_GET( _reg ) \
6433 ( ( ( _reg ) >> 20 ) & 0xfU )
6435#define AARCH64_VPIDR_EL2_IMPLEMENTER( _val ) ( ( _val ) << 24 )
6436#define AARCH64_VPIDR_EL2_IMPLEMENTER_SHIFT 24
6437#define AARCH64_VPIDR_EL2_IMPLEMENTER_MASK 0xff000000U
6438#define AARCH64_VPIDR_EL2_IMPLEMENTER_GET( _reg ) \
6439 ( ( ( _reg ) >> 24 ) & 0xffU )
6441static inline uint64_t _AArch64_Read_vpidr_el2(
void )
6446 "mrs %0, VPIDR_EL2" :
"=&r" ( value ) : :
"memory"
6452static inline void _AArch64_Write_vpidr_el2( uint64_t value )
6455 "msr VPIDR_EL2, %0" : :
"r" ( value ) :
"memory"
6461#define AARCH64_VSTCR_EL2_T0SZ( _val ) ( ( _val ) << 0 )
6462#define AARCH64_VSTCR_EL2_T0SZ_SHIFT 0
6463#define AARCH64_VSTCR_EL2_T0SZ_MASK 0x3fU
6464#define AARCH64_VSTCR_EL2_T0SZ_GET( _reg ) \
6465 ( ( ( _reg ) >> 0 ) & 0x3fU )
6467#define AARCH64_VSTCR_EL2_SL0( _val ) ( ( _val ) << 6 )
6468#define AARCH64_VSTCR_EL2_SL0_SHIFT 6
6469#define AARCH64_VSTCR_EL2_SL0_MASK 0xc0U
6470#define AARCH64_VSTCR_EL2_SL0_GET( _reg ) \
6471 ( ( ( _reg ) >> 6 ) & 0x3U )
6473#define AARCH64_VSTCR_EL2_TG0( _val ) ( ( _val ) << 14 )
6474#define AARCH64_VSTCR_EL2_TG0_SHIFT 14
6475#define AARCH64_VSTCR_EL2_TG0_MASK 0xc000U
6476#define AARCH64_VSTCR_EL2_TG0_GET( _reg ) \
6477 ( ( ( _reg ) >> 14 ) & 0x3U )
6479#define AARCH64_VSTCR_EL2_SW 0x20000000U
6481#define AARCH64_VSTCR_EL2_SA 0x40000000U
6483static inline uint64_t _AArch64_Read_vstcr_el2(
void )
6488 "mrs %0, VSTCR_EL2" :
"=&r" ( value ) : :
"memory"
6494static inline void _AArch64_Write_vstcr_el2( uint64_t value )
6497 "msr VSTCR_EL2, %0" : :
"r" ( value ) :
"memory"
6503#define AARCH64_VSTTBR_EL2_CNP 0x1U
6505#define AARCH64_VSTTBR_EL2_BADDR( _val ) ( ( _val ) << 1 )
6506#define AARCH64_VSTTBR_EL2_BADDR_SHIFT 1
6507#define AARCH64_VSTTBR_EL2_BADDR_MASK 0xfffffffffffeULL
6508#define AARCH64_VSTTBR_EL2_BADDR_GET( _reg ) \
6509 ( ( ( _reg ) >> 1 ) & 0x7fffffffffffULL )
6511static inline uint64_t _AArch64_Read_vsttbr_el2(
void )
6516 "mrs %0, VSTTBR_EL2" :
"=&r" ( value ) : :
"memory"
6522static inline void _AArch64_Write_vsttbr_el2( uint64_t value )
6525 "msr VSTTBR_EL2, %0" : :
"r" ( value ) :
"memory"
6531#define AARCH64_VTCR_EL2_T0SZ( _val ) ( ( _val ) << 0 )
6532#define AARCH64_VTCR_EL2_T0SZ_SHIFT 0
6533#define AARCH64_VTCR_EL2_T0SZ_MASK 0x3fU
6534#define AARCH64_VTCR_EL2_T0SZ_GET( _reg ) \
6535 ( ( ( _reg ) >> 0 ) & 0x3fU )
6537#define AARCH64_VTCR_EL2_SL0( _val ) ( ( _val ) << 6 )
6538#define AARCH64_VTCR_EL2_SL0_SHIFT 6
6539#define AARCH64_VTCR_EL2_SL0_MASK 0xc0U
6540#define AARCH64_VTCR_EL2_SL0_GET( _reg ) \
6541 ( ( ( _reg ) >> 6 ) & 0x3U )
6543#define AARCH64_VTCR_EL2_IRGN0( _val ) ( ( _val ) << 8 )
6544#define AARCH64_VTCR_EL2_IRGN0_SHIFT 8
6545#define AARCH64_VTCR_EL2_IRGN0_MASK 0x300U
6546#define AARCH64_VTCR_EL2_IRGN0_GET( _reg ) \
6547 ( ( ( _reg ) >> 8 ) & 0x3U )
6549#define AARCH64_VTCR_EL2_ORGN0( _val ) ( ( _val ) << 10 )
6550#define AARCH64_VTCR_EL2_ORGN0_SHIFT 10
6551#define AARCH64_VTCR_EL2_ORGN0_MASK 0xc00U
6552#define AARCH64_VTCR_EL2_ORGN0_GET( _reg ) \
6553 ( ( ( _reg ) >> 10 ) & 0x3U )
6555#define AARCH64_VTCR_EL2_SH0( _val ) ( ( _val ) << 12 )
6556#define AARCH64_VTCR_EL2_SH0_SHIFT 12
6557#define AARCH64_VTCR_EL2_SH0_MASK 0x3000U
6558#define AARCH64_VTCR_EL2_SH0_GET( _reg ) \
6559 ( ( ( _reg ) >> 12 ) & 0x3U )
6561#define AARCH64_VTCR_EL2_TG0( _val ) ( ( _val ) << 14 )
6562#define AARCH64_VTCR_EL2_TG0_SHIFT 14
6563#define AARCH64_VTCR_EL2_TG0_MASK 0xc000U
6564#define AARCH64_VTCR_EL2_TG0_GET( _reg ) \
6565 ( ( ( _reg ) >> 14 ) & 0x3U )
6567#define AARCH64_VTCR_EL2_PS( _val ) ( ( _val ) << 16 )
6568#define AARCH64_VTCR_EL2_PS_SHIFT 16
6569#define AARCH64_VTCR_EL2_PS_MASK 0x70000U
6570#define AARCH64_VTCR_EL2_PS_GET( _reg ) \
6571 ( ( ( _reg ) >> 16 ) & 0x7U )
6573#define AARCH64_VTCR_EL2_VS 0x80000U
6575#define AARCH64_VTCR_EL2_HA 0x200000U
6577#define AARCH64_VTCR_EL2_HD 0x400000U
6579#define AARCH64_VTCR_EL2_HWU59 0x2000000U
6581#define AARCH64_VTCR_EL2_HWU60 0x4000000U
6583#define AARCH64_VTCR_EL2_HWU61 0x8000000U
6585#define AARCH64_VTCR_EL2_HWU62 0x10000000U
6587#define AARCH64_VTCR_EL2_NSW 0x20000000U
6589#define AARCH64_VTCR_EL2_NSA 0x40000000U
6591static inline uint64_t _AArch64_Read_vtcr_el2(
void )
6596 "mrs %0, VTCR_EL2" :
"=&r" ( value ) : :
"memory"
6602static inline void _AArch64_Write_vtcr_el2( uint64_t value )
6605 "msr VTCR_EL2, %0" : :
"r" ( value ) :
"memory"
6611#define AARCH64_VTTBR_EL2_CNP 0x1U
6613#define AARCH64_VTTBR_EL2_BADDR( _val ) ( ( _val ) << 1 )
6614#define AARCH64_VTTBR_EL2_BADDR_SHIFT 1
6615#define AARCH64_VTTBR_EL2_BADDR_MASK 0xfffffffffffeULL
6616#define AARCH64_VTTBR_EL2_BADDR_GET( _reg ) \
6617 ( ( ( _reg ) >> 1 ) & 0x7fffffffffffULL )
6619#define AARCH64_VTTBR_EL2_VMID_7_0( _val ) ( ( _val ) << 48 )
6620#define AARCH64_VTTBR_EL2_VMID_7_0_SHIFT 48
6621#define AARCH64_VTTBR_EL2_VMID_7_0_MASK 0xff000000000000ULL
6622#define AARCH64_VTTBR_EL2_VMID_7_0_GET( _reg ) \
6623 ( ( ( _reg ) >> 48 ) & 0xffULL )
6625#define AARCH64_VTTBR_EL2_VMID_15_8( _val ) ( ( _val ) << 56 )
6626#define AARCH64_VTTBR_EL2_VMID_15_8_SHIFT 56
6627#define AARCH64_VTTBR_EL2_VMID_15_8_MASK 0xff00000000000000ULL
6628#define AARCH64_VTTBR_EL2_VMID_15_8_GET( _reg ) \
6629 ( ( ( _reg ) >> 56 ) & 0xffULL )
6631static inline uint64_t _AArch64_Read_vttbr_el2(
void )
6636 "mrs %0, VTTBR_EL2" :
"=&r" ( value ) : :
"memory"
6642static inline void _AArch64_Write_vttbr_el2( uint64_t value )
6645 "msr VTTBR_EL2, %0" : :
"r" ( value ) :
"memory"
6651#define AARCH64_DBGAUTHSTATUS_EL1_NSID( _val ) ( ( _val ) << 0 )
6652#define AARCH64_DBGAUTHSTATUS_EL1_NSID_SHIFT 0
6653#define AARCH64_DBGAUTHSTATUS_EL1_NSID_MASK 0x3U
6654#define AARCH64_DBGAUTHSTATUS_EL1_NSID_GET( _reg ) \
6655 ( ( ( _reg ) >> 0 ) & 0x3U )
6657#define AARCH64_DBGAUTHSTATUS_EL1_NSNID( _val ) ( ( _val ) << 2 )
6658#define AARCH64_DBGAUTHSTATUS_EL1_NSNID_SHIFT 2
6659#define AARCH64_DBGAUTHSTATUS_EL1_NSNID_MASK 0xcU
6660#define AARCH64_DBGAUTHSTATUS_EL1_NSNID_GET( _reg ) \
6661 ( ( ( _reg ) >> 2 ) & 0x3U )
6663#define AARCH64_DBGAUTHSTATUS_EL1_SID( _val ) ( ( _val ) << 4 )
6664#define AARCH64_DBGAUTHSTATUS_EL1_SID_SHIFT 4
6665#define AARCH64_DBGAUTHSTATUS_EL1_SID_MASK 0x30U
6666#define AARCH64_DBGAUTHSTATUS_EL1_SID_GET( _reg ) \
6667 ( ( ( _reg ) >> 4 ) & 0x3U )
6669#define AARCH64_DBGAUTHSTATUS_EL1_SNID( _val ) ( ( _val ) << 6 )
6670#define AARCH64_DBGAUTHSTATUS_EL1_SNID_SHIFT 6
6671#define AARCH64_DBGAUTHSTATUS_EL1_SNID_MASK 0xc0U
6672#define AARCH64_DBGAUTHSTATUS_EL1_SNID_GET( _reg ) \
6673 ( ( ( _reg ) >> 6 ) & 0x3U )
6675static inline uint64_t _AArch64_Read_dbgauthstatus_el1(
void )
6680 "mrs %0, DBGAUTHSTATUS_EL1" :
"=&r" ( value ) : :
"memory"
6688#define AARCH64_DBGBCR_N_EL1_E 0x1U
6690#define AARCH64_DBGBCR_N_EL1_PMC( _val ) ( ( _val ) << 1 )
6691#define AARCH64_DBGBCR_N_EL1_PMC_SHIFT 1
6692#define AARCH64_DBGBCR_N_EL1_PMC_MASK 0x6U
6693#define AARCH64_DBGBCR_N_EL1_PMC_GET( _reg ) \
6694 ( ( ( _reg ) >> 1 ) & 0x3U )
6696#define AARCH64_DBGBCR_N_EL1_BAS( _val ) ( ( _val ) << 5 )
6697#define AARCH64_DBGBCR_N_EL1_BAS_SHIFT 5
6698#define AARCH64_DBGBCR_N_EL1_BAS_MASK 0x1e0U
6699#define AARCH64_DBGBCR_N_EL1_BAS_GET( _reg ) \
6700 ( ( ( _reg ) >> 5 ) & 0xfU )
6702#define AARCH64_DBGBCR_N_EL1_HMC 0x2000U
6704#define AARCH64_DBGBCR_N_EL1_SSC( _val ) ( ( _val ) << 14 )
6705#define AARCH64_DBGBCR_N_EL1_SSC_SHIFT 14
6706#define AARCH64_DBGBCR_N_EL1_SSC_MASK 0xc000U
6707#define AARCH64_DBGBCR_N_EL1_SSC_GET( _reg ) \
6708 ( ( ( _reg ) >> 14 ) & 0x3U )
6710#define AARCH64_DBGBCR_N_EL1_LBN( _val ) ( ( _val ) << 16 )
6711#define AARCH64_DBGBCR_N_EL1_LBN_SHIFT 16
6712#define AARCH64_DBGBCR_N_EL1_LBN_MASK 0xf0000U
6713#define AARCH64_DBGBCR_N_EL1_LBN_GET( _reg ) \
6714 ( ( ( _reg ) >> 16 ) & 0xfU )
6716#define AARCH64_DBGBCR_N_EL1_BT( _val ) ( ( _val ) << 20 )
6717#define AARCH64_DBGBCR_N_EL1_BT_SHIFT 20
6718#define AARCH64_DBGBCR_N_EL1_BT_MASK 0xf00000U
6719#define AARCH64_DBGBCR_N_EL1_BT_GET( _reg ) \
6720 ( ( ( _reg ) >> 20 ) & 0xfU )
6722static inline uint64_t _AArch64_Read_dbgbcr0_el1(
void )
6727 "mrs %0, DBGBCR0_EL1" :
"=&r" ( value ) : :
"memory"
6733static inline void _AArch64_Write_dbgbcr0_el1( uint64_t value )
6736 "msr DBGBCR0_EL1, %0" : :
"r" ( value ) :
"memory"
6740static inline uint64_t _AArch64_Read_dbgbcr1_el1(
void )
6745 "mrs %0, DBGBCR1_EL1" :
"=&r" ( value ) : :
"memory"
6751static inline void _AArch64_Write_dbgbcr1_el1( uint64_t value )
6754 "msr DBGBCR1_EL1, %0" : :
"r" ( value ) :
"memory"
6758static inline uint64_t _AArch64_Read_dbgbcr2_el1(
void )
6763 "mrs %0, DBGBCR2_EL1" :
"=&r" ( value ) : :
"memory"
6769static inline void _AArch64_Write_dbgbcr2_el1( uint64_t value )
6772 "msr DBGBCR2_EL1, %0" : :
"r" ( value ) :
"memory"
6776static inline uint64_t _AArch64_Read_dbgbcr3_el1(
void )
6781 "mrs %0, DBGBCR3_EL1" :
"=&r" ( value ) : :
"memory"
6787static inline void _AArch64_Write_dbgbcr3_el1( uint64_t value )
6790 "msr DBGBCR3_EL1, %0" : :
"r" ( value ) :
"memory"
6794static inline uint64_t _AArch64_Read_dbgbcr4_el1(
void )
6799 "mrs %0, DBGBCR4_EL1" :
"=&r" ( value ) : :
"memory"
6805static inline void _AArch64_Write_dbgbcr4_el1( uint64_t value )
6808 "msr DBGBCR4_EL1, %0" : :
"r" ( value ) :
"memory"
6812static inline uint64_t _AArch64_Read_dbgbcr5_el1(
void )
6817 "mrs %0, DBGBCR5_EL1" :
"=&r" ( value ) : :
"memory"
6823static inline void _AArch64_Write_dbgbcr5_el1( uint64_t value )
6826 "msr DBGBCR5_EL1, %0" : :
"r" ( value ) :
"memory"
6830static inline uint64_t _AArch64_Read_dbgbcr6_el1(
void )
6835 "mrs %0, DBGBCR6_EL1" :
"=&r" ( value ) : :
"memory"
6841static inline void _AArch64_Write_dbgbcr6_el1( uint64_t value )
6844 "msr DBGBCR6_EL1, %0" : :
"r" ( value ) :
"memory"
6848static inline uint64_t _AArch64_Read_dbgbcr7_el1(
void )
6853 "mrs %0, DBGBCR7_EL1" :
"=&r" ( value ) : :
"memory"
6859static inline void _AArch64_Write_dbgbcr7_el1( uint64_t value )
6862 "msr DBGBCR7_EL1, %0" : :
"r" ( value ) :
"memory"
6866static inline uint64_t _AArch64_Read_dbgbcr8_el1(
void )
6871 "mrs %0, DBGBCR8_EL1" :
"=&r" ( value ) : :
"memory"
6877static inline void _AArch64_Write_dbgbcr8_el1( uint64_t value )
6880 "msr DBGBCR8_EL1, %0" : :
"r" ( value ) :
"memory"
6884static inline uint64_t _AArch64_Read_dbgbcr9_el1(
void )
6889 "mrs %0, DBGBCR9_EL1" :
"=&r" ( value ) : :
"memory"
6895static inline void _AArch64_Write_dbgbcr9_el1( uint64_t value )
6898 "msr DBGBCR9_EL1, %0" : :
"r" ( value ) :
"memory"
6902static inline uint64_t _AArch64_Read_dbgbcr10_el1(
void )
6907 "mrs %0, DBGBCR10_EL1" :
"=&r" ( value ) : :
"memory"
6913static inline void _AArch64_Write_dbgbcr10_el1( uint64_t value )
6916 "msr DBGBCR10_EL1, %0" : :
"r" ( value ) :
"memory"
6920static inline uint64_t _AArch64_Read_dbgbcr11_el1(
void )
6925 "mrs %0, DBGBCR11_EL1" :
"=&r" ( value ) : :
"memory"
6931static inline void _AArch64_Write_dbgbcr11_el1( uint64_t value )
6934 "msr DBGBCR11_EL1, %0" : :
"r" ( value ) :
"memory"
6938static inline uint64_t _AArch64_Read_dbgbcr12_el1(
void )
6943 "mrs %0, DBGBCR12_EL1" :
"=&r" ( value ) : :
"memory"
6949static inline void _AArch64_Write_dbgbcr12_el1( uint64_t value )
6952 "msr DBGBCR12_EL1, %0" : :
"r" ( value ) :
"memory"
6956static inline uint64_t _AArch64_Read_dbgbcr13_el1(
void )
6961 "mrs %0, DBGBCR13_EL1" :
"=&r" ( value ) : :
"memory"
6967static inline void _AArch64_Write_dbgbcr13_el1( uint64_t value )
6970 "msr DBGBCR13_EL1, %0" : :
"r" ( value ) :
"memory"
6974static inline uint64_t _AArch64_Read_dbgbcr14_el1(
void )
6979 "mrs %0, DBGBCR14_EL1" :
"=&r" ( value ) : :
"memory"
6985static inline void _AArch64_Write_dbgbcr14_el1( uint64_t value )
6988 "msr DBGBCR14_EL1, %0" : :
"r" ( value ) :
"memory"
6992static inline uint64_t _AArch64_Read_dbgbcr15_el1(
void )
6997 "mrs %0, DBGBCR15_EL1" :
"=&r" ( value ) : :
"memory"
7003static inline void _AArch64_Write_dbgbcr15_el1( uint64_t value )
7006 "msr DBGBCR15_EL1, %0" : :
"r" ( value ) :
"memory"
7012#define AARCH64_DBGBVR_N_EL1_CONTEXTID( _val ) ( ( _val ) << 0 )
7013#define AARCH64_DBGBVR_N_EL1_CONTEXTID_SHIFT 0
7014#define AARCH64_DBGBVR_N_EL1_CONTEXTID_MASK 0xffffffffU
7015#define AARCH64_DBGBVR_N_EL1_CONTEXTID_GET( _reg ) \
7016 ( ( ( _reg ) >> 0 ) & 0xffffffffU )
7018#define AARCH64_DBGBVR_N_EL1_VA_48_2( _val ) ( ( _val ) << 2 )
7019#define AARCH64_DBGBVR_N_EL1_VA_48_2_SHIFT 2
7020#define AARCH64_DBGBVR_N_EL1_VA_48_2_MASK 0x1fffffffffffcULL
7021#define AARCH64_DBGBVR_N_EL1_VA_48_2_GET( _reg ) \
7022 ( ( ( _reg ) >> 2 ) & 0x7fffffffffffULL )
7024#define AARCH64_DBGBVR_N_EL1_VMID_7_0( _val ) ( ( _val ) << 32 )
7025#define AARCH64_DBGBVR_N_EL1_VMID_7_0_SHIFT 32
7026#define AARCH64_DBGBVR_N_EL1_VMID_7_0_MASK 0xff00000000ULL
7027#define AARCH64_DBGBVR_N_EL1_VMID_7_0_GET( _reg ) \
7028 ( ( ( _reg ) >> 32 ) & 0xffULL )
7030#define AARCH64_DBGBVR_N_EL1_CONTEXTID2( _val ) ( ( _val ) << 32 )
7031#define AARCH64_DBGBVR_N_EL1_CONTEXTID2_SHIFT 32
7032#define AARCH64_DBGBVR_N_EL1_CONTEXTID2_MASK 0xffffffff00000000ULL
7033#define AARCH64_DBGBVR_N_EL1_CONTEXTID2_GET( _reg ) \
7034 ( ( ( _reg ) >> 32 ) & 0xffffffffULL )
7036#define AARCH64_DBGBVR_N_EL1_VMID_15_8( _val ) ( ( _val ) << 40 )
7037#define AARCH64_DBGBVR_N_EL1_VMID_15_8_SHIFT 40
7038#define AARCH64_DBGBVR_N_EL1_VMID_15_8_MASK 0xff0000000000ULL
7039#define AARCH64_DBGBVR_N_EL1_VMID_15_8_GET( _reg ) \
7040 ( ( ( _reg ) >> 40 ) & 0xffULL )
7042#define AARCH64_DBGBVR_N_EL1_VA_52_49( _val ) ( ( _val ) << 49 )
7043#define AARCH64_DBGBVR_N_EL1_VA_52_49_SHIFT 49
7044#define AARCH64_DBGBVR_N_EL1_VA_52_49_MASK 0x1e000000000000ULL
7045#define AARCH64_DBGBVR_N_EL1_VA_52_49_GET( _reg ) \
7046 ( ( ( _reg ) >> 49 ) & 0xfULL )
7048#define AARCH64_DBGBVR_N_EL1_RESS_14_4( _val ) ( ( _val ) << 53 )
7049#define AARCH64_DBGBVR_N_EL1_RESS_14_4_SHIFT 53
7050#define AARCH64_DBGBVR_N_EL1_RESS_14_4_MASK 0xffe0000000000000ULL
7051#define AARCH64_DBGBVR_N_EL1_RESS_14_4_GET( _reg ) \
7052 ( ( ( _reg ) >> 53 ) & 0x7ffULL )
7054static inline uint64_t _AArch64_Read_dbgbvr0_el1(
void )
7059 "mrs %0, DBGBVR0_EL1" :
"=&r" ( value ) : :
"memory"
7065static inline void _AArch64_Write_dbgbvr0_el1( uint64_t value )
7068 "msr DBGBVR0_EL1, %0" : :
"r" ( value ) :
"memory"
7072static inline uint64_t _AArch64_Read_dbgbvr1_el1(
void )
7077 "mrs %0, DBGBVR1_EL1" :
"=&r" ( value ) : :
"memory"
7083static inline void _AArch64_Write_dbgbvr1_el1( uint64_t value )
7086 "msr DBGBVR1_EL1, %0" : :
"r" ( value ) :
"memory"
7090static inline uint64_t _AArch64_Read_dbgbvr2_el1(
void )
7095 "mrs %0, DBGBVR2_EL1" :
"=&r" ( value ) : :
"memory"
7101static inline void _AArch64_Write_dbgbvr2_el1( uint64_t value )
7104 "msr DBGBVR2_EL1, %0" : :
"r" ( value ) :
"memory"
7108static inline uint64_t _AArch64_Read_dbgbvr3_el1(
void )
7113 "mrs %0, DBGBVR3_EL1" :
"=&r" ( value ) : :
"memory"
7119static inline void _AArch64_Write_dbgbvr3_el1( uint64_t value )
7122 "msr DBGBVR3_EL1, %0" : :
"r" ( value ) :
"memory"
7126static inline uint64_t _AArch64_Read_dbgbvr4_el1(
void )
7131 "mrs %0, DBGBVR4_EL1" :
"=&r" ( value ) : :
"memory"
7137static inline void _AArch64_Write_dbgbvr4_el1( uint64_t value )
7140 "msr DBGBVR4_EL1, %0" : :
"r" ( value ) :
"memory"
7144static inline uint64_t _AArch64_Read_dbgbvr5_el1(
void )
7149 "mrs %0, DBGBVR5_EL1" :
"=&r" ( value ) : :
"memory"
7155static inline void _AArch64_Write_dbgbvr5_el1( uint64_t value )
7158 "msr DBGBVR5_EL1, %0" : :
"r" ( value ) :
"memory"
7162static inline uint64_t _AArch64_Read_dbgbvr6_el1(
void )
7167 "mrs %0, DBGBVR6_EL1" :
"=&r" ( value ) : :
"memory"
7173static inline void _AArch64_Write_dbgbvr6_el1( uint64_t value )
7176 "msr DBGBVR6_EL1, %0" : :
"r" ( value ) :
"memory"
7180static inline uint64_t _AArch64_Read_dbgbvr7_el1(
void )
7185 "mrs %0, DBGBVR7_EL1" :
"=&r" ( value ) : :
"memory"
7191static inline void _AArch64_Write_dbgbvr7_el1( uint64_t value )
7194 "msr DBGBVR7_EL1, %0" : :
"r" ( value ) :
"memory"
7198static inline uint64_t _AArch64_Read_dbgbvr8_el1(
void )
7203 "mrs %0, DBGBVR8_EL1" :
"=&r" ( value ) : :
"memory"
7209static inline void _AArch64_Write_dbgbvr8_el1( uint64_t value )
7212 "msr DBGBVR8_EL1, %0" : :
"r" ( value ) :
"memory"
7216static inline uint64_t _AArch64_Read_dbgbvr9_el1(
void )
7221 "mrs %0, DBGBVR9_EL1" :
"=&r" ( value ) : :
"memory"
7227static inline void _AArch64_Write_dbgbvr9_el1( uint64_t value )
7230 "msr DBGBVR9_EL1, %0" : :
"r" ( value ) :
"memory"
7234static inline uint64_t _AArch64_Read_dbgbvr10_el1(
void )
7239 "mrs %0, DBGBVR10_EL1" :
"=&r" ( value ) : :
"memory"
7245static inline void _AArch64_Write_dbgbvr10_el1( uint64_t value )
7248 "msr DBGBVR10_EL1, %0" : :
"r" ( value ) :
"memory"
7252static inline uint64_t _AArch64_Read_dbgbvr11_el1(
void )
7257 "mrs %0, DBGBVR11_EL1" :
"=&r" ( value ) : :
"memory"
7263static inline void _AArch64_Write_dbgbvr11_el1( uint64_t value )
7266 "msr DBGBVR11_EL1, %0" : :
"r" ( value ) :
"memory"
7270static inline uint64_t _AArch64_Read_dbgbvr12_el1(
void )
7275 "mrs %0, DBGBVR12_EL1" :
"=&r" ( value ) : :
"memory"
7281static inline void _AArch64_Write_dbgbvr12_el1( uint64_t value )
7284 "msr DBGBVR12_EL1, %0" : :
"r" ( value ) :
"memory"
7288static inline uint64_t _AArch64_Read_dbgbvr13_el1(
void )
7293 "mrs %0, DBGBVR13_EL1" :
"=&r" ( value ) : :
"memory"
7299static inline void _AArch64_Write_dbgbvr13_el1( uint64_t value )
7302 "msr DBGBVR13_EL1, %0" : :
"r" ( value ) :
"memory"
7306static inline uint64_t _AArch64_Read_dbgbvr14_el1(
void )
7311 "mrs %0, DBGBVR14_EL1" :
"=&r" ( value ) : :
"memory"
7317static inline void _AArch64_Write_dbgbvr14_el1( uint64_t value )
7320 "msr DBGBVR14_EL1, %0" : :
"r" ( value ) :
"memory"
7324static inline uint64_t _AArch64_Read_dbgbvr15_el1(
void )
7329 "mrs %0, DBGBVR15_EL1" :
"=&r" ( value ) : :
"memory"
7335static inline void _AArch64_Write_dbgbvr15_el1( uint64_t value )
7338 "msr DBGBVR15_EL1, %0" : :
"r" ( value ) :
"memory"
7344#define AARCH64_DBGCLAIMCLR_EL1_CLAIM( _val ) ( ( _val ) << 0 )
7345#define AARCH64_DBGCLAIMCLR_EL1_CLAIM_SHIFT 0
7346#define AARCH64_DBGCLAIMCLR_EL1_CLAIM_MASK 0xffU
7347#define AARCH64_DBGCLAIMCLR_EL1_CLAIM_GET( _reg ) \
7348 ( ( ( _reg ) >> 0 ) & 0xffU )
7350static inline uint64_t _AArch64_Read_dbgclaimclr_el1(
void )
7355 "mrs %0, DBGCLAIMCLR_EL1" :
"=&r" ( value ) : :
"memory"
7361static inline void _AArch64_Write_dbgclaimclr_el1( uint64_t value )
7364 "msr DBGCLAIMCLR_EL1, %0" : :
"r" ( value ) :
"memory"
7370#define AARCH64_DBGCLAIMSET_EL1_CLAIM( _val ) ( ( _val ) << 0 )
7371#define AARCH64_DBGCLAIMSET_EL1_CLAIM_SHIFT 0
7372#define AARCH64_DBGCLAIMSET_EL1_CLAIM_MASK 0xffU
7373#define AARCH64_DBGCLAIMSET_EL1_CLAIM_GET( _reg ) \
7374 ( ( ( _reg ) >> 0 ) & 0xffU )
7376static inline uint64_t _AArch64_Read_dbgclaimset_el1(
void )
7381 "mrs %0, DBGCLAIMSET_EL1" :
"=&r" ( value ) : :
"memory"
7387static inline void _AArch64_Write_dbgclaimset_el1( uint64_t value )
7390 "msr DBGCLAIMSET_EL1, %0" : :
"r" ( value ) :
"memory"
7396#define AARCH64_DBGDTR_EL0_LOWWORD( _val ) ( ( _val ) << 0 )
7397#define AARCH64_DBGDTR_EL0_LOWWORD_SHIFT 0
7398#define AARCH64_DBGDTR_EL0_LOWWORD_MASK 0xffffffffU
7399#define AARCH64_DBGDTR_EL0_LOWWORD_GET( _reg ) \
7400 ( ( ( _reg ) >> 0 ) & 0xffffffffU )
7402#define AARCH64_DBGDTR_EL0_HIGHWORD( _val ) ( ( _val ) << 32 )
7403#define AARCH64_DBGDTR_EL0_HIGHWORD_SHIFT 32
7404#define AARCH64_DBGDTR_EL0_HIGHWORD_MASK 0xffffffff00000000ULL
7405#define AARCH64_DBGDTR_EL0_HIGHWORD_GET( _reg ) \
7406 ( ( ( _reg ) >> 32 ) & 0xffffffffULL )
7408static inline uint64_t _AArch64_Read_dbgdtr_el0(
void )
7413 "mrs %0, DBGDTR_EL0" :
"=&r" ( value ) : :
"memory"
7419static inline void _AArch64_Write_dbgdtr_el0( uint64_t value )
7422 "msr DBGDTR_EL0, %0" : :
"r" ( value ) :
"memory"
7428static inline uint64_t _AArch64_Read_dbgdtrrx_el0(
void )
7433 "mrs %0, DBGDTRRX_EL0" :
"=&r" ( value ) : :
"memory"
7441static inline void _AArch64_Write_dbgdtrtx_el0( uint64_t value )
7444 "msr DBGDTRTX_EL0, %0" : :
"r" ( value ) :
"memory"
7450#define AARCH64_DBGPRCR_EL1_CORENPDRQ 0x1U
7452static inline uint64_t _AArch64_Read_dbgprcr_el1(
void )
7457 "mrs %0, DBGPRCR_EL1" :
"=&r" ( value ) : :
"memory"
7463static inline void _AArch64_Write_dbgprcr_el1( uint64_t value )
7466 "msr DBGPRCR_EL1, %0" : :
"r" ( value ) :
"memory"
7472#define AARCH64_DBGVCR32_EL2_SU 0x2U
7474#define AARCH64_DBGVCR32_EL2_U 0x2U
7476#define AARCH64_DBGVCR32_EL2_S 0x4U
7478#define AARCH64_DBGVCR32_EL2_SS 0x4U
7480#define AARCH64_DBGVCR32_EL2_P 0x8U
7482#define AARCH64_DBGVCR32_EL2_SP 0x8U
7484#define AARCH64_DBGVCR32_EL2_D 0x10U
7486#define AARCH64_DBGVCR32_EL2_SD 0x10U
7488#define AARCH64_DBGVCR32_EL2_I 0x40U
7490#define AARCH64_DBGVCR32_EL2_SI 0x40U
7492#define AARCH64_DBGVCR32_EL2_F 0x80U
7494#define AARCH64_DBGVCR32_EL2_SF 0x80U
7496#define AARCH64_DBGVCR32_EL2_NSU 0x2000000U
7498#define AARCH64_DBGVCR32_EL2_NSS 0x4000000U
7500#define AARCH64_DBGVCR32_EL2_NSP 0x8000000U
7502#define AARCH64_DBGVCR32_EL2_NSD 0x10000000U
7504#define AARCH64_DBGVCR32_EL2_NSI 0x40000000U
7506#define AARCH64_DBGVCR32_EL2_NSF 0x80000000U
7508static inline uint64_t _AArch64_Read_dbgvcr32_el2(
void )
7513 "mrs %0, DBGVCR32_EL2" :
"=&r" ( value ) : :
"memory"
7519static inline void _AArch64_Write_dbgvcr32_el2( uint64_t value )
7522 "msr DBGVCR32_EL2, %0" : :
"r" ( value ) :
"memory"
7528#define AARCH64_DBGWCR_N_EL1_E 0x1U
7530#define AARCH64_DBGWCR_N_EL1_PAC( _val ) ( ( _val ) << 1 )
7531#define AARCH64_DBGWCR_N_EL1_PAC_SHIFT 1
7532#define AARCH64_DBGWCR_N_EL1_PAC_MASK 0x6U
7533#define AARCH64_DBGWCR_N_EL1_PAC_GET( _reg ) \
7534 ( ( ( _reg ) >> 1 ) & 0x3U )
7536#define AARCH64_DBGWCR_N_EL1_LSC( _val ) ( ( _val ) << 3 )
7537#define AARCH64_DBGWCR_N_EL1_LSC_SHIFT 3
7538#define AARCH64_DBGWCR_N_EL1_LSC_MASK 0x18U
7539#define AARCH64_DBGWCR_N_EL1_LSC_GET( _reg ) \
7540 ( ( ( _reg ) >> 3 ) & 0x3U )
7542#define AARCH64_DBGWCR_N_EL1_BAS( _val ) ( ( _val ) << 5 )
7543#define AARCH64_DBGWCR_N_EL1_BAS_SHIFT 5
7544#define AARCH64_DBGWCR_N_EL1_BAS_MASK 0x1fe0U
7545#define AARCH64_DBGWCR_N_EL1_BAS_GET( _reg ) \
7546 ( ( ( _reg ) >> 5 ) & 0xffU )
7548#define AARCH64_DBGWCR_N_EL1_HMC 0x2000U
7550#define AARCH64_DBGWCR_N_EL1_SSC( _val ) ( ( _val ) << 14 )
7551#define AARCH64_DBGWCR_N_EL1_SSC_SHIFT 14
7552#define AARCH64_DBGWCR_N_EL1_SSC_MASK 0xc000U
7553#define AARCH64_DBGWCR_N_EL1_SSC_GET( _reg ) \
7554 ( ( ( _reg ) >> 14 ) & 0x3U )
7556#define AARCH64_DBGWCR_N_EL1_LBN( _val ) ( ( _val ) << 16 )
7557#define AARCH64_DBGWCR_N_EL1_LBN_SHIFT 16
7558#define AARCH64_DBGWCR_N_EL1_LBN_MASK 0xf0000U
7559#define AARCH64_DBGWCR_N_EL1_LBN_GET( _reg ) \
7560 ( ( ( _reg ) >> 16 ) & 0xfU )
7562#define AARCH64_DBGWCR_N_EL1_WT 0x100000U
7564#define AARCH64_DBGWCR_N_EL1_MASK( _val ) ( ( _val ) << 24 )
7565#define AARCH64_DBGWCR_N_EL1_MASK_SHIFT 24
7566#define AARCH64_DBGWCR_N_EL1_MASK_MASK 0x1f000000U
7567#define AARCH64_DBGWCR_N_EL1_MASK_GET( _reg ) \
7568 ( ( ( _reg ) >> 24 ) & 0x1fU )
7570static inline uint64_t _AArch64_Read_dbgwcr0_el1(
void )
7575 "mrs %0, DBGWCR0_EL1" :
"=&r" ( value ) : :
"memory"
7581static inline void _AArch64_Write_dbgwcr0_el1( uint64_t value )
7584 "msr DBGWCR0_EL1, %0" : :
"r" ( value ) :
"memory"
7588static inline uint64_t _AArch64_Read_dbgwcr1_el1(
void )
7593 "mrs %0, DBGWCR1_EL1" :
"=&r" ( value ) : :
"memory"
7599static inline void _AArch64_Write_dbgwcr1_el1( uint64_t value )
7602 "msr DBGWCR1_EL1, %0" : :
"r" ( value ) :
"memory"
7606static inline uint64_t _AArch64_Read_dbgwcr2_el1(
void )
7611 "mrs %0, DBGWCR2_EL1" :
"=&r" ( value ) : :
"memory"
7617static inline void _AArch64_Write_dbgwcr2_el1( uint64_t value )
7620 "msr DBGWCR2_EL1, %0" : :
"r" ( value ) :
"memory"
7624static inline uint64_t _AArch64_Read_dbgwcr3_el1(
void )
7629 "mrs %0, DBGWCR3_EL1" :
"=&r" ( value ) : :
"memory"
7635static inline void _AArch64_Write_dbgwcr3_el1( uint64_t value )
7638 "msr DBGWCR3_EL1, %0" : :
"r" ( value ) :
"memory"
7642static inline uint64_t _AArch64_Read_dbgwcr4_el1(
void )
7647 "mrs %0, DBGWCR4_EL1" :
"=&r" ( value ) : :
"memory"
7653static inline void _AArch64_Write_dbgwcr4_el1( uint64_t value )
7656 "msr DBGWCR4_EL1, %0" : :
"r" ( value ) :
"memory"
7660static inline uint64_t _AArch64_Read_dbgwcr5_el1(
void )
7665 "mrs %0, DBGWCR5_EL1" :
"=&r" ( value ) : :
"memory"
7671static inline void _AArch64_Write_dbgwcr5_el1( uint64_t value )
7674 "msr DBGWCR5_EL1, %0" : :
"r" ( value ) :
"memory"
7678static inline uint64_t _AArch64_Read_dbgwcr6_el1(
void )
7683 "mrs %0, DBGWCR6_EL1" :
"=&r" ( value ) : :
"memory"
7689static inline void _AArch64_Write_dbgwcr6_el1( uint64_t value )
7692 "msr DBGWCR6_EL1, %0" : :
"r" ( value ) :
"memory"
7696static inline uint64_t _AArch64_Read_dbgwcr7_el1(
void )
7701 "mrs %0, DBGWCR7_EL1" :
"=&r" ( value ) : :
"memory"
7707static inline void _AArch64_Write_dbgwcr7_el1( uint64_t value )
7710 "msr DBGWCR7_EL1, %0" : :
"r" ( value ) :
"memory"
7714static inline uint64_t _AArch64_Read_dbgwcr8_el1(
void )
7719 "mrs %0, DBGWCR8_EL1" :
"=&r" ( value ) : :
"memory"
7725static inline void _AArch64_Write_dbgwcr8_el1( uint64_t value )
7728 "msr DBGWCR8_EL1, %0" : :
"r" ( value ) :
"memory"
7732static inline uint64_t _AArch64_Read_dbgwcr9_el1(
void )
7737 "mrs %0, DBGWCR9_EL1" :
"=&r" ( value ) : :
"memory"
7743static inline void _AArch64_Write_dbgwcr9_el1( uint64_t value )
7746 "msr DBGWCR9_EL1, %0" : :
"r" ( value ) :
"memory"
7750static inline uint64_t _AArch64_Read_dbgwcr10_el1(
void )
7755 "mrs %0, DBGWCR10_EL1" :
"=&r" ( value ) : :
"memory"
7761static inline void _AArch64_Write_dbgwcr10_el1( uint64_t value )
7764 "msr DBGWCR10_EL1, %0" : :
"r" ( value ) :
"memory"
7768static inline uint64_t _AArch64_Read_dbgwcr11_el1(
void )
7773 "mrs %0, DBGWCR11_EL1" :
"=&r" ( value ) : :
"memory"
7779static inline void _AArch64_Write_dbgwcr11_el1( uint64_t value )
7782 "msr DBGWCR11_EL1, %0" : :
"r" ( value ) :
"memory"
7786static inline uint64_t _AArch64_Read_dbgwcr12_el1(
void )
7791 "mrs %0, DBGWCR12_EL1" :
"=&r" ( value ) : :
"memory"
7797static inline void _AArch64_Write_dbgwcr12_el1( uint64_t value )
7800 "msr DBGWCR12_EL1, %0" : :
"r" ( value ) :
"memory"
7804static inline uint64_t _AArch64_Read_dbgwcr13_el1(
void )
7809 "mrs %0, DBGWCR13_EL1" :
"=&r" ( value ) : :
"memory"
7815static inline void _AArch64_Write_dbgwcr13_el1( uint64_t value )
7818 "msr DBGWCR13_EL1, %0" : :
"r" ( value ) :
"memory"
7822static inline uint64_t _AArch64_Read_dbgwcr14_el1(
void )
7827 "mrs %0, DBGWCR14_EL1" :
"=&r" ( value ) : :
"memory"
7833static inline void _AArch64_Write_dbgwcr14_el1( uint64_t value )
7836 "msr DBGWCR14_EL1, %0" : :
"r" ( value ) :
"memory"
7840static inline uint64_t _AArch64_Read_dbgwcr15_el1(
void )
7845 "mrs %0, DBGWCR15_EL1" :
"=&r" ( value ) : :
"memory"
7851static inline void _AArch64_Write_dbgwcr15_el1( uint64_t value )
7854 "msr DBGWCR15_EL1, %0" : :
"r" ( value ) :
"memory"
7860#define AARCH64_DBGWVR_N_EL1_VA_48_2( _val ) ( ( _val ) << 2 )
7861#define AARCH64_DBGWVR_N_EL1_VA_48_2_SHIFT 2
7862#define AARCH64_DBGWVR_N_EL1_VA_48_2_MASK 0x1fffffffffffcULL
7863#define AARCH64_DBGWVR_N_EL1_VA_48_2_GET( _reg ) \
7864 ( ( ( _reg ) >> 2 ) & 0x7fffffffffffULL )
7866#define AARCH64_DBGWVR_N_EL1_VA_52_49( _val ) ( ( _val ) << 49 )
7867#define AARCH64_DBGWVR_N_EL1_VA_52_49_SHIFT 49
7868#define AARCH64_DBGWVR_N_EL1_VA_52_49_MASK 0x1e000000000000ULL
7869#define AARCH64_DBGWVR_N_EL1_VA_52_49_GET( _reg ) \
7870 ( ( ( _reg ) >> 49 ) & 0xfULL )
7872#define AARCH64_DBGWVR_N_EL1_RESS_14_4( _val ) ( ( _val ) << 53 )
7873#define AARCH64_DBGWVR_N_EL1_RESS_14_4_SHIFT 53
7874#define AARCH64_DBGWVR_N_EL1_RESS_14_4_MASK 0xffe0000000000000ULL
7875#define AARCH64_DBGWVR_N_EL1_RESS_14_4_GET( _reg ) \
7876 ( ( ( _reg ) >> 53 ) & 0x7ffULL )
7878static inline uint64_t _AArch64_Read_dbgwvr0_el1(
void )
7883 "mrs %0, DBGWVR0_EL1" :
"=&r" ( value ) : :
"memory"
7889static inline void _AArch64_Write_dbgwvr0_el1( uint64_t value )
7892 "msr DBGWVR0_EL1, %0" : :
"r" ( value ) :
"memory"
7896static inline uint64_t _AArch64_Read_dbgwvr1_el1(
void )
7901 "mrs %0, DBGWVR1_EL1" :
"=&r" ( value ) : :
"memory"
7907static inline void _AArch64_Write_dbgwvr1_el1( uint64_t value )
7910 "msr DBGWVR1_EL1, %0" : :
"r" ( value ) :
"memory"
7914static inline uint64_t _AArch64_Read_dbgwvr2_el1(
void )
7919 "mrs %0, DBGWVR2_EL1" :
"=&r" ( value ) : :
"memory"
7925static inline void _AArch64_Write_dbgwvr2_el1( uint64_t value )
7928 "msr DBGWVR2_EL1, %0" : :
"r" ( value ) :
"memory"
7932static inline uint64_t _AArch64_Read_dbgwvr3_el1(
void )
7937 "mrs %0, DBGWVR3_EL1" :
"=&r" ( value ) : :
"memory"
7943static inline void _AArch64_Write_dbgwvr3_el1( uint64_t value )
7946 "msr DBGWVR3_EL1, %0" : :
"r" ( value ) :
"memory"
7950static inline uint64_t _AArch64_Read_dbgwvr4_el1(
void )
7955 "mrs %0, DBGWVR4_EL1" :
"=&r" ( value ) : :
"memory"
7961static inline void _AArch64_Write_dbgwvr4_el1( uint64_t value )
7964 "msr DBGWVR4_EL1, %0" : :
"r" ( value ) :
"memory"
7968static inline uint64_t _AArch64_Read_dbgwvr5_el1(
void )
7973 "mrs %0, DBGWVR5_EL1" :
"=&r" ( value ) : :
"memory"
7979static inline void _AArch64_Write_dbgwvr5_el1( uint64_t value )
7982 "msr DBGWVR5_EL1, %0" : :
"r" ( value ) :
"memory"
7986static inline uint64_t _AArch64_Read_dbgwvr6_el1(
void )
7991 "mrs %0, DBGWVR6_EL1" :
"=&r" ( value ) : :
"memory"
7997static inline void _AArch64_Write_dbgwvr6_el1( uint64_t value )
8000 "msr DBGWVR6_EL1, %0" : :
"r" ( value ) :
"memory"
8004static inline uint64_t _AArch64_Read_dbgwvr7_el1(
void )
8009 "mrs %0, DBGWVR7_EL1" :
"=&r" ( value ) : :
"memory"
8015static inline void _AArch64_Write_dbgwvr7_el1( uint64_t value )
8018 "msr DBGWVR7_EL1, %0" : :
"r" ( value ) :
"memory"
8022static inline uint64_t _AArch64_Read_dbgwvr8_el1(
void )
8027 "mrs %0, DBGWVR8_EL1" :
"=&r" ( value ) : :
"memory"
8033static inline void _AArch64_Write_dbgwvr8_el1( uint64_t value )
8036 "msr DBGWVR8_EL1, %0" : :
"r" ( value ) :
"memory"
8040static inline uint64_t _AArch64_Read_dbgwvr9_el1(
void )
8045 "mrs %0, DBGWVR9_EL1" :
"=&r" ( value ) : :
"memory"
8051static inline void _AArch64_Write_dbgwvr9_el1( uint64_t value )
8054 "msr DBGWVR9_EL1, %0" : :
"r" ( value ) :
"memory"
8058static inline uint64_t _AArch64_Read_dbgwvr10_el1(
void )
8063 "mrs %0, DBGWVR10_EL1" :
"=&r" ( value ) : :
"memory"
8069static inline void _AArch64_Write_dbgwvr10_el1( uint64_t value )
8072 "msr DBGWVR10_EL1, %0" : :
"r" ( value ) :
"memory"
8076static inline uint64_t _AArch64_Read_dbgwvr11_el1(
void )
8081 "mrs %0, DBGWVR11_EL1" :
"=&r" ( value ) : :
"memory"
8087static inline void _AArch64_Write_dbgwvr11_el1( uint64_t value )
8090 "msr DBGWVR11_EL1, %0" : :
"r" ( value ) :
"memory"
8094static inline uint64_t _AArch64_Read_dbgwvr12_el1(
void )
8099 "mrs %0, DBGWVR12_EL1" :
"=&r" ( value ) : :
"memory"
8105static inline void _AArch64_Write_dbgwvr12_el1( uint64_t value )
8108 "msr DBGWVR12_EL1, %0" : :
"r" ( value ) :
"memory"
8112static inline uint64_t _AArch64_Read_dbgwvr13_el1(
void )
8117 "mrs %0, DBGWVR13_EL1" :
"=&r" ( value ) : :
"memory"
8123static inline void _AArch64_Write_dbgwvr13_el1( uint64_t value )
8126 "msr DBGWVR13_EL1, %0" : :
"r" ( value ) :
"memory"
8130static inline uint64_t _AArch64_Read_dbgwvr14_el1(
void )
8135 "mrs %0, DBGWVR14_EL1" :
"=&r" ( value ) : :
"memory"
8141static inline void _AArch64_Write_dbgwvr14_el1( uint64_t value )
8144 "msr DBGWVR14_EL1, %0" : :
"r" ( value ) :
"memory"
8148static inline uint64_t _AArch64_Read_dbgwvr15_el1(
void )
8153 "mrs %0, DBGWVR15_EL1" :
"=&r" ( value ) : :
"memory"
8159static inline void _AArch64_Write_dbgwvr15_el1( uint64_t value )
8162 "msr DBGWVR15_EL1, %0" : :
"r" ( value ) :
"memory"
8168static inline uint64_t _AArch64_Read_dlr_el0(
void )
8173 "mrs %0, DLR_EL0" :
"=&r" ( value ) : :
"memory"
8179static inline void _AArch64_Write_dlr_el0( uint64_t value )
8182 "msr DLR_EL0, %0" : :
"r" ( value ) :
"memory"
8188#define AARCH64_DSPSR_EL0_M_3_0( _val ) ( ( _val ) << 0 )
8189#define AARCH64_DSPSR_EL0_M_3_0_SHIFT 0
8190#define AARCH64_DSPSR_EL0_M_3_0_MASK 0xfU
8191#define AARCH64_DSPSR_EL0_M_3_0_GET( _reg ) \
8192 ( ( ( _reg ) >> 0 ) & 0xfU )
8194#define AARCH64_DSPSR_EL0_M_4 0x10U
8196#define AARCH64_DSPSR_EL0_T 0x20U
8198#define AARCH64_DSPSR_EL0_F 0x40U
8200#define AARCH64_DSPSR_EL0_I 0x80U
8202#define AARCH64_DSPSR_EL0_A 0x100U
8204#define AARCH64_DSPSR_EL0_D 0x200U
8206#define AARCH64_DSPSR_EL0_E 0x200U
8208#define AARCH64_DSPSR_EL0_BTYPE( _val ) ( ( _val ) << 10 )
8209#define AARCH64_DSPSR_EL0_BTYPE_SHIFT 10
8210#define AARCH64_DSPSR_EL0_BTYPE_MASK 0xc00U
8211#define AARCH64_DSPSR_EL0_BTYPE_GET( _reg ) \
8212 ( ( ( _reg ) >> 10 ) & 0x3U )
8214#define AARCH64_DSPSR_EL0_IT_7_2( _val ) ( ( _val ) << 10 )
8215#define AARCH64_DSPSR_EL0_IT_7_2_SHIFT 10
8216#define AARCH64_DSPSR_EL0_IT_7_2_MASK 0xfc00U
8217#define AARCH64_DSPSR_EL0_IT_7_2_GET( _reg ) \
8218 ( ( ( _reg ) >> 10 ) & 0x3fU )
8220#define AARCH64_DSPSR_EL0_SSBS_0 0x1000U
8222#define AARCH64_DSPSR_EL0_GE( _val ) ( ( _val ) << 16 )
8223#define AARCH64_DSPSR_EL0_GE_SHIFT 16
8224#define AARCH64_DSPSR_EL0_GE_MASK 0xf0000U
8225#define AARCH64_DSPSR_EL0_GE_GET( _reg ) \
8226 ( ( ( _reg ) >> 16 ) & 0xfU )
8228#define AARCH64_DSPSR_EL0_IL 0x100000U
8230#define AARCH64_DSPSR_EL0_SS 0x200000U
8232#define AARCH64_DSPSR_EL0_PAN 0x400000U
8234#define AARCH64_DSPSR_EL0_SSBS_1 0x800000U
8236#define AARCH64_DSPSR_EL0_UAO 0x800000U
8238#define AARCH64_DSPSR_EL0_DIT 0x1000000U
8240#define AARCH64_DSPSR_EL0_TCO 0x2000000U
8242#define AARCH64_DSPSR_EL0_IT_1_0( _val ) ( ( _val ) << 25 )
8243#define AARCH64_DSPSR_EL0_IT_1_0_SHIFT 25
8244#define AARCH64_DSPSR_EL0_IT_1_0_MASK 0x6000000U
8245#define AARCH64_DSPSR_EL0_IT_1_0_GET( _reg ) \
8246 ( ( ( _reg ) >> 25 ) & 0x3U )
8248#define AARCH64_DSPSR_EL0_Q 0x8000000U
8250#define AARCH64_DSPSR_EL0_V 0x10000000U
8252#define AARCH64_DSPSR_EL0_C 0x20000000U
8254#define AARCH64_DSPSR_EL0_Z 0x40000000U
8256#define AARCH64_DSPSR_EL0_N 0x80000000U
8258static inline uint64_t _AArch64_Read_dspsr_el0(
void )
8263 "mrs %0, DSPSR_EL0" :
"=&r" ( value ) : :
"memory"
8269static inline void _AArch64_Write_dspsr_el0( uint64_t value )
8272 "msr DSPSR_EL0, %0" : :
"r" ( value ) :
"memory"
8278#define AARCH64_MDCCINT_EL1_TX 0x20000000U
8280#define AARCH64_MDCCINT_EL1_RX 0x40000000U
8282static inline uint64_t _AArch64_Read_mdccint_el1(
void )
8287 "mrs %0, MDCCINT_EL1" :
"=&r" ( value ) : :
"memory"
8293static inline void _AArch64_Write_mdccint_el1( uint64_t value )
8296 "msr MDCCINT_EL1, %0" : :
"r" ( value ) :
"memory"
8302#define AARCH64_MDCCSR_EL0_TXFULL 0x20000000U
8304#define AARCH64_MDCCSR_EL0_RXFULL 0x40000000U
8306static inline uint64_t _AArch64_Read_mdccsr_el0(
void )
8311 "mrs %0, MDCCSR_EL0" :
"=&r" ( value ) : :
"memory"
8319#define AARCH64_MDCR_EL2_HPMN( _val ) ( ( _val ) << 0 )
8320#define AARCH64_MDCR_EL2_HPMN_SHIFT 0
8321#define AARCH64_MDCR_EL2_HPMN_MASK 0x1fU
8322#define AARCH64_MDCR_EL2_HPMN_GET( _reg ) \
8323 ( ( ( _reg ) >> 0 ) & 0x1fU )
8325#define AARCH64_MDCR_EL2_TPMCR 0x20U
8327#define AARCH64_MDCR_EL2_TPM 0x40U
8329#define AARCH64_MDCR_EL2_HPME 0x80U
8331#define AARCH64_MDCR_EL2_TDE 0x100U
8333#define AARCH64_MDCR_EL2_TDA 0x200U
8335#define AARCH64_MDCR_EL2_TDOSA 0x400U
8337#define AARCH64_MDCR_EL2_TDRA 0x800U
8339#define AARCH64_MDCR_EL2_E2PB( _val ) ( ( _val ) << 12 )
8340#define AARCH64_MDCR_EL2_E2PB_SHIFT 12
8341#define AARCH64_MDCR_EL2_E2PB_MASK 0x3000U
8342#define AARCH64_MDCR_EL2_E2PB_GET( _reg ) \
8343 ( ( ( _reg ) >> 12 ) & 0x3U )
8345#define AARCH64_MDCR_EL2_TPMS 0x4000U
8347#define AARCH64_MDCR_EL2_HPMD 0x20000U
8349#define AARCH64_MDCR_EL2_TTRF 0x80000U
8351#define AARCH64_MDCR_EL2_HCCD 0x800000U
8353#define AARCH64_MDCR_EL2_HLP 0x4000000U
8355#define AARCH64_MDCR_EL2_TDCC 0x8000000U
8357#define AARCH64_MDCR_EL2_MTPME 0x10000000U
8359static inline uint64_t _AArch64_Read_mdcr_el2(
void )
8364 "mrs %0, MDCR_EL2" :
"=&r" ( value ) : :
"memory"
8370static inline void _AArch64_Write_mdcr_el2( uint64_t value )
8373 "msr MDCR_EL2, %0" : :
"r" ( value ) :
"memory"
8379#define AARCH64_MDCR_EL3_TPM 0x40U
8381#define AARCH64_MDCR_EL3_TDA 0x200U
8383#define AARCH64_MDCR_EL3_TDOSA 0x400U
8385#define AARCH64_MDCR_EL3_NSPB( _val ) ( ( _val ) << 12 )
8386#define AARCH64_MDCR_EL3_NSPB_SHIFT 12
8387#define AARCH64_MDCR_EL3_NSPB_MASK 0x3000U
8388#define AARCH64_MDCR_EL3_NSPB_GET( _reg ) \
8389 ( ( ( _reg ) >> 12 ) & 0x3U )
8391#define AARCH64_MDCR_EL3_SPD32( _val ) ( ( _val ) << 14 )
8392#define AARCH64_MDCR_EL3_SPD32_SHIFT 14
8393#define AARCH64_MDCR_EL3_SPD32_MASK 0xc000U
8394#define AARCH64_MDCR_EL3_SPD32_GET( _reg ) \
8395 ( ( ( _reg ) >> 14 ) & 0x3U )
8397#define AARCH64_MDCR_EL3_SDD 0x10000U
8399#define AARCH64_MDCR_EL3_SPME 0x20000U
8401#define AARCH64_MDCR_EL3_STE 0x40000U
8403#define AARCH64_MDCR_EL3_TTRF 0x80000U
8405#define AARCH64_MDCR_EL3_EDAD 0x100000U
8407#define AARCH64_MDCR_EL3_EPMAD 0x200000U
8409#define AARCH64_MDCR_EL3_SCCD 0x800000U
8411#define AARCH64_MDCR_EL3_TDCC 0x8000000U
8413#define AARCH64_MDCR_EL3_MTPME 0x10000000U
8415static inline uint64_t _AArch64_Read_mdcr_el3(
void )
8420 "mrs %0, MDCR_EL3" :
"=&r" ( value ) : :
"memory"
8426static inline void _AArch64_Write_mdcr_el3( uint64_t value )
8429 "msr MDCR_EL3, %0" : :
"r" ( value ) :
"memory"
8435#define AARCH64_MDRAR_EL1_VALID( _val ) ( ( _val ) << 0 )
8436#define AARCH64_MDRAR_EL1_VALID_SHIFT 0
8437#define AARCH64_MDRAR_EL1_VALID_MASK 0x3U
8438#define AARCH64_MDRAR_EL1_VALID_GET( _reg ) \
8439 ( ( ( _reg ) >> 0 ) & 0x3U )
8441#define AARCH64_MDRAR_EL1_ROMADDR_47_12( _val ) ( ( _val ) << 12 )
8442#define AARCH64_MDRAR_EL1_ROMADDR_47_12_SHIFT 12
8443#define AARCH64_MDRAR_EL1_ROMADDR_47_12_MASK 0xfffffffff000ULL
8444#define AARCH64_MDRAR_EL1_ROMADDR_47_12_GET( _reg ) \
8445 ( ( ( _reg ) >> 12 ) & 0xfffffffffULL )
8447#define AARCH64_MDRAR_EL1_ROMADDR_51_48( _val ) ( ( _val ) << 48 )
8448#define AARCH64_MDRAR_EL1_ROMADDR_51_48_SHIFT 48
8449#define AARCH64_MDRAR_EL1_ROMADDR_51_48_MASK 0xf000000000000ULL
8450#define AARCH64_MDRAR_EL1_ROMADDR_51_48_GET( _reg ) \
8451 ( ( ( _reg ) >> 48 ) & 0xfULL )
8453static inline uint64_t _AArch64_Read_mdrar_el1(
void )
8458 "mrs %0, MDRAR_EL1" :
"=&r" ( value ) : :
"memory"
8466#define AARCH64_MDSCR_EL1_SS 0x1U
8468#define AARCH64_MDSCR_EL1_ERR 0x40U
8470#define AARCH64_MDSCR_EL1_TDCC 0x1000U
8472#define AARCH64_MDSCR_EL1_KDE 0x2000U
8474#define AARCH64_MDSCR_EL1_HDE 0x4000U
8476#define AARCH64_MDSCR_EL1_MDE 0x8000U
8478#define AARCH64_MDSCR_EL1_SC2 0x80000U
8480#define AARCH64_MDSCR_EL1_TDA 0x200000U
8482#define AARCH64_MDSCR_EL1_INTDIS( _val ) ( ( _val ) << 22 )
8483#define AARCH64_MDSCR_EL1_INTDIS_SHIFT 22
8484#define AARCH64_MDSCR_EL1_INTDIS_MASK 0xc00000U
8485#define AARCH64_MDSCR_EL1_INTDIS_GET( _reg ) \
8486 ( ( ( _reg ) >> 22 ) & 0x3U )
8488#define AARCH64_MDSCR_EL1_TXU 0x4000000U
8490#define AARCH64_MDSCR_EL1_RXO 0x8000000U
8492#define AARCH64_MDSCR_EL1_TXFULL 0x20000000U
8494#define AARCH64_MDSCR_EL1_RXFULL 0x40000000U
8496#define AARCH64_MDSCR_EL1_TFO 0x80000000U
8498static inline uint64_t _AArch64_Read_mdscr_el1(
void )
8503 "mrs %0, MDSCR_EL1" :
"=&r" ( value ) : :
"memory"
8509static inline void _AArch64_Write_mdscr_el1( uint64_t value )
8512 "msr MDSCR_EL1, %0" : :
"r" ( value ) :
"memory"
8518#define AARCH64_OSDLR_EL1_DLK 0x1U
8520static inline uint64_t _AArch64_Read_osdlr_el1(
void )
8525 "mrs %0, OSDLR_EL1" :
"=&r" ( value ) : :
"memory"
8531static inline void _AArch64_Write_osdlr_el1( uint64_t value )
8534 "msr OSDLR_EL1, %0" : :
"r" ( value ) :
"memory"
8540static inline uint64_t _AArch64_Read_osdtrrx_el1(
void )
8545 "mrs %0, OSDTRRX_EL1" :
"=&r" ( value ) : :
"memory"
8551static inline void _AArch64_Write_osdtrrx_el1( uint64_t value )
8554 "msr OSDTRRX_EL1, %0" : :
"r" ( value ) :
"memory"
8560static inline uint64_t _AArch64_Read_osdtrtx_el1(
void )
8565 "mrs %0, OSDTRTX_EL1" :
"=&r" ( value ) : :
"memory"
8571static inline void _AArch64_Write_osdtrtx_el1( uint64_t value )
8574 "msr OSDTRTX_EL1, %0" : :
"r" ( value ) :
"memory"
8580#define AARCH64_OSECCR_EL1_EDECCR( _val ) ( ( _val ) << 0 )
8581#define AARCH64_OSECCR_EL1_EDECCR_SHIFT 0
8582#define AARCH64_OSECCR_EL1_EDECCR_MASK 0xffffffffU
8583#define AARCH64_OSECCR_EL1_EDECCR_GET( _reg ) \
8584 ( ( ( _reg ) >> 0 ) & 0xffffffffU )
8586static inline uint64_t _AArch64_Read_oseccr_el1(
void )
8591 "mrs %0, OSECCR_EL1" :
"=&r" ( value ) : :
"memory"
8597static inline void _AArch64_Write_oseccr_el1( uint64_t value )
8600 "msr OSECCR_EL1, %0" : :
"r" ( value ) :
"memory"
8606#define AARCH64_OSLAR_EL1_OSLK 0x1U
8608static inline void _AArch64_Write_oslar_el1( uint64_t value )
8611 "msr OSLAR_EL1, %0" : :
"r" ( value ) :
"memory"
8617#define AARCH64_OSLSR_EL1_OSLM_0 0x1U
8619#define AARCH64_OSLSR_EL1_OSLK 0x2U
8621#define AARCH64_OSLSR_EL1_NTT 0x4U
8623#define AARCH64_OSLSR_EL1_OSLM_1 0x8U
8625static inline uint64_t _AArch64_Read_oslsr_el1(
void )
8630 "mrs %0, OSLSR_EL1" :
"=&r" ( value ) : :
"memory"
8638#define AARCH64_SDER32_EL2_SUIDEN 0x1U
8640#define AARCH64_SDER32_EL2_SUNIDEN 0x2U
8642static inline uint64_t _AArch64_Read_sder32_el2(
void )
8647 "mrs %0, SDER32_EL2" :
"=&r" ( value ) : :
"memory"
8653static inline void _AArch64_Write_sder32_el2( uint64_t value )
8656 "msr SDER32_EL2, %0" : :
"r" ( value ) :
"memory"
8662#define AARCH64_SDER32_EL3_SUIDEN 0x1U
8664#define AARCH64_SDER32_EL3_SUNIDEN 0x2U
8666static inline uint64_t _AArch64_Read_sder32_el3(
void )
8671 "mrs %0, SDER32_EL3" :
"=&r" ( value ) : :
"memory"
8677static inline void _AArch64_Write_sder32_el3( uint64_t value )
8680 "msr SDER32_EL3, %0" : :
"r" ( value ) :
"memory"
8686#define AARCH64_TRFCR_EL1_E0TRE 0x1U
8688#define AARCH64_TRFCR_EL1_E1TRE 0x2U
8690#define AARCH64_TRFCR_EL1_TS( _val ) ( ( _val ) << 5 )
8691#define AARCH64_TRFCR_EL1_TS_SHIFT 5
8692#define AARCH64_TRFCR_EL1_TS_MASK 0x60U
8693#define AARCH64_TRFCR_EL1_TS_GET( _reg ) \
8694 ( ( ( _reg ) >> 5 ) & 0x3U )
8696static inline uint64_t _AArch64_Read_trfcr_el1(
void )
8701 "mrs %0, TRFCR_EL1" :
"=&r" ( value ) : :
"memory"
8707static inline void _AArch64_Write_trfcr_el1( uint64_t value )
8710 "msr TRFCR_EL1, %0" : :
"r" ( value ) :
"memory"
8716#define AARCH64_TRFCR_EL2_E0HTRE 0x1U
8718#define AARCH64_TRFCR_EL2_E2TRE 0x2U
8720#define AARCH64_TRFCR_EL2_CX 0x8U
8722#define AARCH64_TRFCR_EL2_TS( _val ) ( ( _val ) << 5 )
8723#define AARCH64_TRFCR_EL2_TS_SHIFT 5
8724#define AARCH64_TRFCR_EL2_TS_MASK 0x60U
8725#define AARCH64_TRFCR_EL2_TS_GET( _reg ) \
8726 ( ( ( _reg ) >> 5 ) & 0x3U )
8728static inline uint64_t _AArch64_Read_trfcr_el2(
void )
8733 "mrs %0, TRFCR_EL2" :
"=&r" ( value ) : :
"memory"
8739static inline void _AArch64_Write_trfcr_el2( uint64_t value )
8742 "msr TRFCR_EL2, %0" : :
"r" ( value ) :
"memory"
8748#define AARCH64_PMCCFILTR_EL0_SH 0x1000000U
8750#define AARCH64_PMCCFILTR_EL0_M 0x4000000U
8752#define AARCH64_PMCCFILTR_EL0_NSH 0x8000000U
8754#define AARCH64_PMCCFILTR_EL0_NSU 0x10000000U
8756#define AARCH64_PMCCFILTR_EL0_NSK 0x20000000U
8758#define AARCH64_PMCCFILTR_EL0_U 0x40000000U
8760#define AARCH64_PMCCFILTR_EL0_P 0x80000000U
8762static inline uint64_t _AArch64_Read_pmccfiltr_el0(
void )
8767 "mrs %0, PMCCFILTR_EL0" :
"=&r" ( value ) : :
"memory"
8773static inline void _AArch64_Write_pmccfiltr_el0( uint64_t value )
8776 "msr PMCCFILTR_EL0, %0" : :
"r" ( value ) :
"memory"
8782static inline uint64_t _AArch64_Read_pmccntr_el0(
void )
8787 "mrs %0, PMCCNTR_EL0" :
"=&r" ( value ) : :
"memory"
8793static inline void _AArch64_Write_pmccntr_el0( uint64_t value )
8796 "msr PMCCNTR_EL0, %0" : :
"r" ( value ) :
"memory"
8802static inline uint64_t _AArch64_Read_pmceid0_el0(
void )
8807 "mrs %0, PMCEID0_EL0" :
"=&r" ( value ) : :
"memory"
8815static inline uint64_t _AArch64_Read_pmceid1_el0(
void )
8820 "mrs %0, PMCEID1_EL0" :
"=&r" ( value ) : :
"memory"
8828#define AARCH64_PMCNTENCLR_EL0_C 0x80000000U
8830static inline uint64_t _AArch64_Read_pmcntenclr_el0(
void )
8835 "mrs %0, PMCNTENCLR_EL0" :
"=&r" ( value ) : :
"memory"
8841static inline void _AArch64_Write_pmcntenclr_el0( uint64_t value )
8844 "msr PMCNTENCLR_EL0, %0" : :
"r" ( value ) :
"memory"
8850#define AARCH64_PMCNTENSET_EL0_C 0x80000000U
8852static inline uint64_t _AArch64_Read_pmcntenset_el0(
void )
8857 "mrs %0, PMCNTENSET_EL0" :
"=&r" ( value ) : :
"memory"
8863static inline void _AArch64_Write_pmcntenset_el0( uint64_t value )
8866 "msr PMCNTENSET_EL0, %0" : :
"r" ( value ) :
"memory"
8872#define AARCH64_PMCR_EL0_E 0x1U
8874#define AARCH64_PMCR_EL0_P 0x2U
8876#define AARCH64_PMCR_EL0_C 0x4U
8878#define AARCH64_PMCR_EL0_D 0x8U
8880#define AARCH64_PMCR_EL0_X 0x10U
8882#define AARCH64_PMCR_EL0_DP 0x20U
8884#define AARCH64_PMCR_EL0_LC 0x40U
8886#define AARCH64_PMCR_EL0_LP 0x80U
8888#define AARCH64_PMCR_EL0_N( _val ) ( ( _val ) << 11 )
8889#define AARCH64_PMCR_EL0_N_SHIFT 11
8890#define AARCH64_PMCR_EL0_N_MASK 0xf800U
8891#define AARCH64_PMCR_EL0_N_GET( _reg ) \
8892 ( ( ( _reg ) >> 11 ) & 0x1fU )
8894#define AARCH64_PMCR_EL0_IDCODE( _val ) ( ( _val ) << 16 )
8895#define AARCH64_PMCR_EL0_IDCODE_SHIFT 16
8896#define AARCH64_PMCR_EL0_IDCODE_MASK 0xff0000U
8897#define AARCH64_PMCR_EL0_IDCODE_GET( _reg ) \
8898 ( ( ( _reg ) >> 16 ) & 0xffU )
8900#define AARCH64_PMCR_EL0_IMP( _val ) ( ( _val ) << 24 )
8901#define AARCH64_PMCR_EL0_IMP_SHIFT 24
8902#define AARCH64_PMCR_EL0_IMP_MASK 0xff000000U
8903#define AARCH64_PMCR_EL0_IMP_GET( _reg ) \
8904 ( ( ( _reg ) >> 24 ) & 0xffU )
8906static inline uint64_t _AArch64_Read_pmcr_el0(
void )
8911 "mrs %0, PMCR_EL0" :
"=&r" ( value ) : :
"memory"
8917static inline void _AArch64_Write_pmcr_el0( uint64_t value )
8920 "msr PMCR_EL0, %0" : :
"r" ( value ) :
"memory"
8926static inline uint64_t _AArch64_Read_pmevcntr_n_el0(
void )
8931 "mrs %0, PMEVCNTR_N_EL0" :
"=&r" ( value ) : :
"memory"
8937static inline void _AArch64_Write_pmevcntr_n_el0( uint64_t value )
8940 "msr PMEVCNTR_N_EL0, %0" : :
"r" ( value ) :
"memory"
8946#define AARCH64_PMEVTYPER_N_EL0_EVTCOUNT_9_0( _val ) ( ( _val ) << 0 )
8947#define AARCH64_PMEVTYPER_N_EL0_EVTCOUNT_9_0_SHIFT 0
8948#define AARCH64_PMEVTYPER_N_EL0_EVTCOUNT_9_0_MASK 0x3ffU
8949#define AARCH64_PMEVTYPER_N_EL0_EVTCOUNT_9_0_GET( _reg ) \
8950 ( ( ( _reg ) >> 0 ) & 0x3ffU )
8952#define AARCH64_PMEVTYPER_N_EL0_EVTCOUNT_15_10( _val ) ( ( _val ) << 10 )
8953#define AARCH64_PMEVTYPER_N_EL0_EVTCOUNT_15_10_SHIFT 10
8954#define AARCH64_PMEVTYPER_N_EL0_EVTCOUNT_15_10_MASK 0xfc00U
8955#define AARCH64_PMEVTYPER_N_EL0_EVTCOUNT_15_10_GET( _reg ) \
8956 ( ( ( _reg ) >> 10 ) & 0x3fU )
8958#define AARCH64_PMEVTYPER_N_EL0_SH 0x1000000U
8960#define AARCH64_PMEVTYPER_N_EL0_MT 0x2000000U
8962#define AARCH64_PMEVTYPER_N_EL0_M 0x4000000U
8964#define AARCH64_PMEVTYPER_N_EL0_NSH 0x8000000U
8966#define AARCH64_PMEVTYPER_N_EL0_NSU 0x10000000U
8968#define AARCH64_PMEVTYPER_N_EL0_NSK 0x20000000U
8970#define AARCH64_PMEVTYPER_N_EL0_U 0x40000000U
8972#define AARCH64_PMEVTYPER_N_EL0_P 0x80000000U
8974static inline uint64_t _AArch64_Read_pmevtyper_n_el0(
void )
8979 "mrs %0, PMEVTYPER_N_EL0" :
"=&r" ( value ) : :
"memory"
8985static inline void _AArch64_Write_pmevtyper_n_el0( uint64_t value )
8988 "msr PMEVTYPER_N_EL0, %0" : :
"r" ( value ) :
"memory"
8994#define AARCH64_PMINTENCLR_EL1_C 0x80000000U
8996static inline uint64_t _AArch64_Read_pmintenclr_el1(
void )
9001 "mrs %0, PMINTENCLR_EL1" :
"=&r" ( value ) : :
"memory"
9007static inline void _AArch64_Write_pmintenclr_el1( uint64_t value )
9010 "msr PMINTENCLR_EL1, %0" : :
"r" ( value ) :
"memory"
9016#define AARCH64_PMINTENSET_EL1_C 0x80000000U
9018static inline uint64_t _AArch64_Read_pmintenset_el1(
void )
9023 "mrs %0, PMINTENSET_EL1" :
"=&r" ( value ) : :
"memory"
9029static inline void _AArch64_Write_pmintenset_el1( uint64_t value )
9032 "msr PMINTENSET_EL1, %0" : :
"r" ( value ) :
"memory"
9038#define AARCH64_PMMIR_EL1_SLOTS( _val ) ( ( _val ) << 0 )
9039#define AARCH64_PMMIR_EL1_SLOTS_SHIFT 0
9040#define AARCH64_PMMIR_EL1_SLOTS_MASK 0xffU
9041#define AARCH64_PMMIR_EL1_SLOTS_GET( _reg ) \
9042 ( ( ( _reg ) >> 0 ) & 0xffU )
9044static inline uint64_t _AArch64_Read_pmmir_el1(
void )
9049 "mrs %0, PMMIR_EL1" :
"=&r" ( value ) : :
"memory"
9057#define AARCH64_PMOVSCLR_EL0_C 0x80000000U
9059static inline uint64_t _AArch64_Read_pmovsclr_el0(
void )
9064 "mrs %0, PMOVSCLR_EL0" :
"=&r" ( value ) : :
"memory"
9070static inline void _AArch64_Write_pmovsclr_el0( uint64_t value )
9073 "msr PMOVSCLR_EL0, %0" : :
"r" ( value ) :
"memory"
9079#define AARCH64_PMOVSSET_EL0_C 0x80000000U
9081static inline uint64_t _AArch64_Read_pmovsset_el0(
void )
9086 "mrs %0, PMOVSSET_EL0" :
"=&r" ( value ) : :
"memory"
9092static inline void _AArch64_Write_pmovsset_el0( uint64_t value )
9095 "msr PMOVSSET_EL0, %0" : :
"r" ( value ) :
"memory"
9101#define AARCH64_PMSELR_EL0_SEL( _val ) ( ( _val ) << 0 )
9102#define AARCH64_PMSELR_EL0_SEL_SHIFT 0
9103#define AARCH64_PMSELR_EL0_SEL_MASK 0x1fU
9104#define AARCH64_PMSELR_EL0_SEL_GET( _reg ) \
9105 ( ( ( _reg ) >> 0 ) & 0x1fU )
9107static inline uint64_t _AArch64_Read_pmselr_el0(
void )
9112 "mrs %0, PMSELR_EL0" :
"=&r" ( value ) : :
"memory"
9118static inline void _AArch64_Write_pmselr_el0( uint64_t value )
9121 "msr PMSELR_EL0, %0" : :
"r" ( value ) :
"memory"
9127static inline void _AArch64_Write_pmswinc_el0( uint64_t value )
9130 "msr PMSWINC_EL0, %0" : :
"r" ( value ) :
"memory"
9136#define AARCH64_PMUSERENR_EL0_EN 0x1U
9138#define AARCH64_PMUSERENR_EL0_SW 0x2U
9140#define AARCH64_PMUSERENR_EL0_CR 0x4U
9142#define AARCH64_PMUSERENR_EL0_ER 0x8U
9144static inline uint64_t _AArch64_Read_pmuserenr_el0(
void )
9149 "mrs %0, PMUSERENR_EL0" :
"=&r" ( value ) : :
"memory"
9155static inline void _AArch64_Write_pmuserenr_el0( uint64_t value )
9158 "msr PMUSERENR_EL0, %0" : :
"r" ( value ) :
"memory"
9164#define AARCH64_PMXEVCNTR_EL0_PMEVCNTR_N( _val ) ( ( _val ) << 0 )
9165#define AARCH64_PMXEVCNTR_EL0_PMEVCNTR_N_SHIFT 0
9166#define AARCH64_PMXEVCNTR_EL0_PMEVCNTR_N_MASK 0xffffffffU
9167#define AARCH64_PMXEVCNTR_EL0_PMEVCNTR_N_GET( _reg ) \
9168 ( ( ( _reg ) >> 0 ) & 0xffffffffU )
9170static inline uint64_t _AArch64_Read_pmxevcntr_el0(
void )
9175 "mrs %0, PMXEVCNTR_EL0" :
"=&r" ( value ) : :
"memory"
9181static inline void _AArch64_Write_pmxevcntr_el0( uint64_t value )
9184 "msr PMXEVCNTR_EL0, %0" : :
"r" ( value ) :
"memory"
9190static inline uint64_t _AArch64_Read_pmxevtyper_el0(
void )
9195 "mrs %0, PMXEVTYPER_EL0" :
"=&r" ( value ) : :
"memory"
9201static inline void _AArch64_Write_pmxevtyper_el0( uint64_t value )
9204 "msr PMXEVTYPER_EL0, %0" : :
"r" ( value ) :
"memory"
9210#define AARCH64_AMCFGR_EL0_N( _val ) ( ( _val ) << 0 )
9211#define AARCH64_AMCFGR_EL0_N_SHIFT 0
9212#define AARCH64_AMCFGR_EL0_N_MASK 0xffU
9213#define AARCH64_AMCFGR_EL0_N_GET( _reg ) \
9214 ( ( ( _reg ) >> 0 ) & 0xffU )
9216#define AARCH64_AMCFGR_EL0_SIZE( _val ) ( ( _val ) << 8 )
9217#define AARCH64_AMCFGR_EL0_SIZE_SHIFT 8
9218#define AARCH64_AMCFGR_EL0_SIZE_MASK 0x3f00U
9219#define AARCH64_AMCFGR_EL0_SIZE_GET( _reg ) \
9220 ( ( ( _reg ) >> 8 ) & 0x3fU )
9222#define AARCH64_AMCFGR_EL0_HDBG 0x1000000U
9224#define AARCH64_AMCFGR_EL0_NCG( _val ) ( ( _val ) << 28 )
9225#define AARCH64_AMCFGR_EL0_NCG_SHIFT 28
9226#define AARCH64_AMCFGR_EL0_NCG_MASK 0xf0000000U
9227#define AARCH64_AMCFGR_EL0_NCG_GET( _reg ) \
9228 ( ( ( _reg ) >> 28 ) & 0xfU )
9230static inline uint64_t _AArch64_Read_amcfgr_el0(
void )
9235 "mrs %0, AMCFGR_EL0" :
"=&r" ( value ) : :
"memory"
9243static inline uint64_t _AArch64_Read_amcg1idr_el0(
void )
9248 "mrs %0, AMCG1IDR_EL0" :
"=&r" ( value ) : :
"memory"
9256#define AARCH64_AMCGCR_EL0_CG0NC( _val ) ( ( _val ) << 0 )
9257#define AARCH64_AMCGCR_EL0_CG0NC_SHIFT 0
9258#define AARCH64_AMCGCR_EL0_CG0NC_MASK 0xffU
9259#define AARCH64_AMCGCR_EL0_CG0NC_GET( _reg ) \
9260 ( ( ( _reg ) >> 0 ) & 0xffU )
9262#define AARCH64_AMCGCR_EL0_CG1NC( _val ) ( ( _val ) << 8 )
9263#define AARCH64_AMCGCR_EL0_CG1NC_SHIFT 8
9264#define AARCH64_AMCGCR_EL0_CG1NC_MASK 0xff00U
9265#define AARCH64_AMCGCR_EL0_CG1NC_GET( _reg ) \
9266 ( ( ( _reg ) >> 8 ) & 0xffU )
9268static inline uint64_t _AArch64_Read_amcgcr_el0(
void )
9273 "mrs %0, AMCGCR_EL0" :
"=&r" ( value ) : :
"memory"
9281static inline uint64_t _AArch64_Read_amcntenclr0_el0(
void )
9286 "mrs %0, AMCNTENCLR0_EL0" :
"=&r" ( value ) : :
"memory"
9292static inline void _AArch64_Write_amcntenclr0_el0( uint64_t value )
9295 "msr AMCNTENCLR0_EL0, %0" : :
"r" ( value ) :
"memory"
9301static inline uint64_t _AArch64_Read_amcntenclr1_el0(
void )
9306 "mrs %0, AMCNTENCLR1_EL0" :
"=&r" ( value ) : :
"memory"
9312static inline void _AArch64_Write_amcntenclr1_el0( uint64_t value )
9315 "msr AMCNTENCLR1_EL0, %0" : :
"r" ( value ) :
"memory"
9321static inline uint64_t _AArch64_Read_amcntenset0_el0(
void )
9326 "mrs %0, AMCNTENSET0_EL0" :
"=&r" ( value ) : :
"memory"
9332static inline void _AArch64_Write_amcntenset0_el0( uint64_t value )
9335 "msr AMCNTENSET0_EL0, %0" : :
"r" ( value ) :
"memory"
9341static inline uint64_t _AArch64_Read_amcntenset1_el0(
void )
9346 "mrs %0, AMCNTENSET1_EL0" :
"=&r" ( value ) : :
"memory"
9352static inline void _AArch64_Write_amcntenset1_el0( uint64_t value )
9355 "msr AMCNTENSET1_EL0, %0" : :
"r" ( value ) :
"memory"
9361#define AARCH64_AMCR_EL0_HDBG 0x400U
9363#define AARCH64_AMCR_EL0_CG1RZ 0x20000U
9365static inline uint64_t _AArch64_Read_amcr_el0(
void )
9370 "mrs %0, AMCR_EL0" :
"=&r" ( value ) : :
"memory"
9376static inline void _AArch64_Write_amcr_el0( uint64_t value )
9379 "msr AMCR_EL0, %0" : :
"r" ( value ) :
"memory"
9385static inline uint64_t _AArch64_Read_amevcntr0_n_el0(
void )
9390 "mrs %0, AMEVCNTR0_N_EL0" :
"=&r" ( value ) : :
"memory"
9396static inline void _AArch64_Write_amevcntr0_n_el0( uint64_t value )
9399 "msr AMEVCNTR0_N_EL0, %0" : :
"r" ( value ) :
"memory"
9405static inline uint64_t _AArch64_Read_amevcntr1_n_el0(
void )
9410 "mrs %0, AMEVCNTR1_N_EL0" :
"=&r" ( value ) : :
"memory"
9416static inline void _AArch64_Write_amevcntr1_n_el0( uint64_t value )
9419 "msr AMEVCNTR1_N_EL0, %0" : :
"r" ( value ) :
"memory"
9425static inline uint64_t _AArch64_Read_amevcntvoff0_n_el2(
void )
9430 "mrs %0, AMEVCNTVOFF0_N_EL2" :
"=&r" ( value ) : :
"memory"
9436static inline void _AArch64_Write_amevcntvoff0_n_el2( uint64_t value )
9439 "msr AMEVCNTVOFF0_N_EL2, %0" : :
"r" ( value ) :
"memory"
9445static inline uint64_t _AArch64_Read_amevcntvoff1_n_el2(
void )
9450 "mrs %0, AMEVCNTVOFF1_N_EL2" :
"=&r" ( value ) : :
"memory"
9456static inline void _AArch64_Write_amevcntvoff1_n_el2( uint64_t value )
9459 "msr AMEVCNTVOFF1_N_EL2, %0" : :
"r" ( value ) :
"memory"
9465#define AARCH64_AMEVTYPER0_N_EL0_EVTCOUNT( _val ) ( ( _val ) << 0 )
9466#define AARCH64_AMEVTYPER0_N_EL0_EVTCOUNT_SHIFT 0
9467#define AARCH64_AMEVTYPER0_N_EL0_EVTCOUNT_MASK 0xffffU
9468#define AARCH64_AMEVTYPER0_N_EL0_EVTCOUNT_GET( _reg ) \
9469 ( ( ( _reg ) >> 0 ) & 0xffffU )
9471static inline uint64_t _AArch64_Read_amevtyper0_n_el0(
void )
9476 "mrs %0, AMEVTYPER0_N_EL0" :
"=&r" ( value ) : :
"memory"
9484#define AARCH64_AMEVTYPER1_N_EL0_EVTCOUNT( _val ) ( ( _val ) << 0 )
9485#define AARCH64_AMEVTYPER1_N_EL0_EVTCOUNT_SHIFT 0
9486#define AARCH64_AMEVTYPER1_N_EL0_EVTCOUNT_MASK 0xffffU
9487#define AARCH64_AMEVTYPER1_N_EL0_EVTCOUNT_GET( _reg ) \
9488 ( ( ( _reg ) >> 0 ) & 0xffffU )
9490static inline uint64_t _AArch64_Read_amevtyper1_n_el0(
void )
9495 "mrs %0, AMEVTYPER1_N_EL0" :
"=&r" ( value ) : :
"memory"
9501static inline void _AArch64_Write_amevtyper1_n_el0( uint64_t value )
9504 "msr AMEVTYPER1_N_EL0, %0" : :
"r" ( value ) :
"memory"
9510#define AARCH64_AMUSERENR_EL0_EN 0x1U
9512static inline uint64_t _AArch64_Read_amuserenr_el0(
void )
9517 "mrs %0, AMUSERENR_EL0" :
"=&r" ( value ) : :
"memory"
9523static inline void _AArch64_Write_amuserenr_el0( uint64_t value )
9526 "msr AMUSERENR_EL0, %0" : :
"r" ( value ) :
"memory"
9532#define AARCH64_PMBIDR_EL1_ALIGN( _val ) ( ( _val ) << 0 )
9533#define AARCH64_PMBIDR_EL1_ALIGN_SHIFT 0
9534#define AARCH64_PMBIDR_EL1_ALIGN_MASK 0xfU
9535#define AARCH64_PMBIDR_EL1_ALIGN_GET( _reg ) \
9536 ( ( ( _reg ) >> 0 ) & 0xfU )
9538#define AARCH64_PMBIDR_EL1_P 0x10U
9540#define AARCH64_PMBIDR_EL1_F 0x20U
9542static inline uint64_t _AArch64_Read_pmbidr_el1(
void )
9547 "mrs %0, PMBIDR_EL1" :
"=&r" ( value ) : :
"memory"
9555#define AARCH64_PMBLIMITR_EL1_E 0x1U
9557#define AARCH64_PMBLIMITR_EL1_FM( _val ) ( ( _val ) << 1 )
9558#define AARCH64_PMBLIMITR_EL1_FM_SHIFT 1
9559#define AARCH64_PMBLIMITR_EL1_FM_MASK 0x6U
9560#define AARCH64_PMBLIMITR_EL1_FM_GET( _reg ) \
9561 ( ( ( _reg ) >> 1 ) & 0x3U )
9563#define AARCH64_PMBLIMITR_EL1_LIMIT( _val ) ( ( _val ) << 12 )
9564#define AARCH64_PMBLIMITR_EL1_LIMIT_SHIFT 12
9565#define AARCH64_PMBLIMITR_EL1_LIMIT_MASK 0xfffffffffffff000ULL
9566#define AARCH64_PMBLIMITR_EL1_LIMIT_GET( _reg ) \
9567 ( ( ( _reg ) >> 12 ) & 0xfffffffffffffULL )
9569static inline uint64_t _AArch64_Read_pmblimitr_el1(
void )
9574 "mrs %0, PMBLIMITR_EL1" :
"=&r" ( value ) : :
"memory"
9580static inline void _AArch64_Write_pmblimitr_el1( uint64_t value )
9583 "msr PMBLIMITR_EL1, %0" : :
"r" ( value ) :
"memory"
9589static inline uint64_t _AArch64_Read_pmbptr_el1(
void )
9594 "mrs %0, PMBPTR_EL1" :
"=&r" ( value ) : :
"memory"
9600static inline void _AArch64_Write_pmbptr_el1( uint64_t value )
9603 "msr PMBPTR_EL1, %0" : :
"r" ( value ) :
"memory"
9609#define AARCH64_PMBSR_EL1_BSC( _val ) ( ( _val ) << 0 )
9610#define AARCH64_PMBSR_EL1_BSC_SHIFT 0
9611#define AARCH64_PMBSR_EL1_BSC_MASK 0x3fU
9612#define AARCH64_PMBSR_EL1_BSC_GET( _reg ) \
9613 ( ( ( _reg ) >> 0 ) & 0x3fU )
9615#define AARCH64_PMBSR_EL1_FSC( _val ) ( ( _val ) << 0 )
9616#define AARCH64_PMBSR_EL1_FSC_SHIFT 0
9617#define AARCH64_PMBSR_EL1_FSC_MASK 0x3fU
9618#define AARCH64_PMBSR_EL1_FSC_GET( _reg ) \
9619 ( ( ( _reg ) >> 0 ) & 0x3fU )
9621#define AARCH64_PMBSR_EL1_MSS( _val ) ( ( _val ) << 0 )
9622#define AARCH64_PMBSR_EL1_MSS_SHIFT 0
9623#define AARCH64_PMBSR_EL1_MSS_MASK 0xffffU
9624#define AARCH64_PMBSR_EL1_MSS_GET( _reg ) \
9625 ( ( ( _reg ) >> 0 ) & 0xffffU )
9627#define AARCH64_PMBSR_EL1_COLL 0x10000U
9629#define AARCH64_PMBSR_EL1_S 0x20000U
9631#define AARCH64_PMBSR_EL1_EA 0x40000U
9633#define AARCH64_PMBSR_EL1_DL 0x80000U
9635#define AARCH64_PMBSR_EL1_EC( _val ) ( ( _val ) << 26 )
9636#define AARCH64_PMBSR_EL1_EC_SHIFT 26
9637#define AARCH64_PMBSR_EL1_EC_MASK 0xfc000000U
9638#define AARCH64_PMBSR_EL1_EC_GET( _reg ) \
9639 ( ( ( _reg ) >> 26 ) & 0x3fU )
9641static inline uint64_t _AArch64_Read_pmbsr_el1(
void )
9646 "mrs %0, PMBSR_EL1" :
"=&r" ( value ) : :
"memory"
9652static inline void _AArch64_Write_pmbsr_el1( uint64_t value )
9655 "msr PMBSR_EL1, %0" : :
"r" ( value ) :
"memory"
9661#define AARCH64_PMSCR_EL1_E0SPE 0x1U
9663#define AARCH64_PMSCR_EL1_E1SPE 0x2U
9665#define AARCH64_PMSCR_EL1_CX 0x8U
9667#define AARCH64_PMSCR_EL1_PA 0x10U
9669#define AARCH64_PMSCR_EL1_TS 0x20U
9671#define AARCH64_PMSCR_EL1_PCT( _val ) ( ( _val ) << 6 )
9672#define AARCH64_PMSCR_EL1_PCT_SHIFT 6
9673#define AARCH64_PMSCR_EL1_PCT_MASK 0xc0U
9674#define AARCH64_PMSCR_EL1_PCT_GET( _reg ) \
9675 ( ( ( _reg ) >> 6 ) & 0x3U )
9677static inline uint64_t _AArch64_Read_pmscr_el1(
void )
9682 "mrs %0, PMSCR_EL1" :
"=&r" ( value ) : :
"memory"
9688static inline void _AArch64_Write_pmscr_el1( uint64_t value )
9691 "msr PMSCR_EL1, %0" : :
"r" ( value ) :
"memory"
9697#define AARCH64_PMSCR_EL2_E0HSPE 0x1U
9699#define AARCH64_PMSCR_EL2_E2SPE 0x2U
9701#define AARCH64_PMSCR_EL2_CX 0x8U
9703#define AARCH64_PMSCR_EL2_PA 0x10U
9705#define AARCH64_PMSCR_EL2_TS 0x20U
9707#define AARCH64_PMSCR_EL2_PCT( _val ) ( ( _val ) << 6 )
9708#define AARCH64_PMSCR_EL2_PCT_SHIFT 6
9709#define AARCH64_PMSCR_EL2_PCT_MASK 0xc0U
9710#define AARCH64_PMSCR_EL2_PCT_GET( _reg ) \
9711 ( ( ( _reg ) >> 6 ) & 0x3U )
9713static inline uint64_t _AArch64_Read_pmscr_el2(
void )
9718 "mrs %0, PMSCR_EL2" :
"=&r" ( value ) : :
"memory"
9724static inline void _AArch64_Write_pmscr_el2( uint64_t value )
9727 "msr PMSCR_EL2, %0" : :
"r" ( value ) :
"memory"
9733#define AARCH64_PMSEVFR_EL1_E_1 0x2U
9735#define AARCH64_PMSEVFR_EL1_E_3 0x8U
9737#define AARCH64_PMSEVFR_EL1_E_5 0x20U
9739#define AARCH64_PMSEVFR_EL1_E_7 0x80U
9741#define AARCH64_PMSEVFR_EL1_E_11 0x800U
9743#define AARCH64_PMSEVFR_EL1_E_12 0x1000U
9745#define AARCH64_PMSEVFR_EL1_E_13 0x2000U
9747#define AARCH64_PMSEVFR_EL1_E_14 0x4000U
9749#define AARCH64_PMSEVFR_EL1_E_15 0x8000U
9751#define AARCH64_PMSEVFR_EL1_E_17 0x20000U
9753#define AARCH64_PMSEVFR_EL1_E_18 0x40000U
9755#define AARCH64_PMSEVFR_EL1_E_24 0x1000000U
9757#define AARCH64_PMSEVFR_EL1_E_25 0x2000000U
9759#define AARCH64_PMSEVFR_EL1_E_26 0x4000000U
9761#define AARCH64_PMSEVFR_EL1_E_27 0x8000000U
9763#define AARCH64_PMSEVFR_EL1_E_28 0x10000000U
9765#define AARCH64_PMSEVFR_EL1_E_29 0x20000000U
9767#define AARCH64_PMSEVFR_EL1_E_30 0x40000000U
9769#define AARCH64_PMSEVFR_EL1_E_31 0x80000000U
9771#define AARCH64_PMSEVFR_EL1_E_48 0x1000000000000ULL
9773#define AARCH64_PMSEVFR_EL1_E_49 0x2000000000000ULL
9775#define AARCH64_PMSEVFR_EL1_E_50 0x4000000000000ULL
9777#define AARCH64_PMSEVFR_EL1_E_51 0x8000000000000ULL
9779#define AARCH64_PMSEVFR_EL1_E_52 0x10000000000000ULL
9781#define AARCH64_PMSEVFR_EL1_E_53 0x20000000000000ULL
9783#define AARCH64_PMSEVFR_EL1_E_54 0x40000000000000ULL
9785#define AARCH64_PMSEVFR_EL1_E_55 0x80000000000000ULL
9787#define AARCH64_PMSEVFR_EL1_E_56 0x100000000000000ULL
9789#define AARCH64_PMSEVFR_EL1_E_57 0x200000000000000ULL
9791#define AARCH64_PMSEVFR_EL1_E_58 0x400000000000000ULL
9793#define AARCH64_PMSEVFR_EL1_E_59 0x800000000000000ULL
9795#define AARCH64_PMSEVFR_EL1_E_60 0x1000000000000000ULL
9797#define AARCH64_PMSEVFR_EL1_E_61 0x2000000000000000ULL
9799#define AARCH64_PMSEVFR_EL1_E_62 0x4000000000000000ULL
9801#define AARCH64_PMSEVFR_EL1_E_63 0x8000000000000000ULL
9803static inline uint64_t _AArch64_Read_pmsevfr_el1(
void )
9808 "mrs %0, PMSEVFR_EL1" :
"=&r" ( value ) : :
"memory"
9814static inline void _AArch64_Write_pmsevfr_el1( uint64_t value )
9817 "msr PMSEVFR_EL1, %0" : :
"r" ( value ) :
"memory"
9823#define AARCH64_PMSFCR_EL1_FE 0x1U
9825#define AARCH64_PMSFCR_EL1_FT 0x2U
9827#define AARCH64_PMSFCR_EL1_FL 0x4U
9829#define AARCH64_PMSFCR_EL1_B 0x10000U
9831#define AARCH64_PMSFCR_EL1_LD 0x20000U
9833#define AARCH64_PMSFCR_EL1_ST 0x40000U
9835static inline uint64_t _AArch64_Read_pmsfcr_el1(
void )
9840 "mrs %0, PMSFCR_EL1" :
"=&r" ( value ) : :
"memory"
9846static inline void _AArch64_Write_pmsfcr_el1( uint64_t value )
9849 "msr PMSFCR_EL1, %0" : :
"r" ( value ) :
"memory"
9855#define AARCH64_PMSICR_EL1_COUNT( _val ) ( ( _val ) << 0 )
9856#define AARCH64_PMSICR_EL1_COUNT_SHIFT 0
9857#define AARCH64_PMSICR_EL1_COUNT_MASK 0xffffffffU
9858#define AARCH64_PMSICR_EL1_COUNT_GET( _reg ) \
9859 ( ( ( _reg ) >> 0 ) & 0xffffffffU )
9861#define AARCH64_PMSICR_EL1_ECOUNT( _val ) ( ( _val ) << 56 )
9862#define AARCH64_PMSICR_EL1_ECOUNT_SHIFT 56
9863#define AARCH64_PMSICR_EL1_ECOUNT_MASK 0xff00000000000000ULL
9864#define AARCH64_PMSICR_EL1_ECOUNT_GET( _reg ) \
9865 ( ( ( _reg ) >> 56 ) & 0xffULL )
9867static inline uint64_t _AArch64_Read_pmsicr_el1(
void )
9872 "mrs %0, PMSICR_EL1" :
"=&r" ( value ) : :
"memory"
9878static inline void _AArch64_Write_pmsicr_el1( uint64_t value )
9881 "msr PMSICR_EL1, %0" : :
"r" ( value ) :
"memory"
9887#define AARCH64_PMSIDR_EL1_FE 0x1U
9889#define AARCH64_PMSIDR_EL1_FT 0x2U
9891#define AARCH64_PMSIDR_EL1_FL 0x4U
9893#define AARCH64_PMSIDR_EL1_ARCHINST 0x8U
9895#define AARCH64_PMSIDR_EL1_LDS 0x10U
9897#define AARCH64_PMSIDR_EL1_ERND 0x20U
9899#define AARCH64_PMSIDR_EL1_INTERVAL( _val ) ( ( _val ) << 8 )
9900#define AARCH64_PMSIDR_EL1_INTERVAL_SHIFT 8
9901#define AARCH64_PMSIDR_EL1_INTERVAL_MASK 0xf00U
9902#define AARCH64_PMSIDR_EL1_INTERVAL_GET( _reg ) \
9903 ( ( ( _reg ) >> 8 ) & 0xfU )
9905#define AARCH64_PMSIDR_EL1_MAXSIZE( _val ) ( ( _val ) << 12 )
9906#define AARCH64_PMSIDR_EL1_MAXSIZE_SHIFT 12
9907#define AARCH64_PMSIDR_EL1_MAXSIZE_MASK 0xf000U
9908#define AARCH64_PMSIDR_EL1_MAXSIZE_GET( _reg ) \
9909 ( ( ( _reg ) >> 12 ) & 0xfU )
9911#define AARCH64_PMSIDR_EL1_COUNTSIZE( _val ) ( ( _val ) << 16 )
9912#define AARCH64_PMSIDR_EL1_COUNTSIZE_SHIFT 16
9913#define AARCH64_PMSIDR_EL1_COUNTSIZE_MASK 0xf0000U
9914#define AARCH64_PMSIDR_EL1_COUNTSIZE_GET( _reg ) \
9915 ( ( ( _reg ) >> 16 ) & 0xfU )
9917static inline uint64_t _AArch64_Read_pmsidr_el1(
void )
9922 "mrs %0, PMSIDR_EL1" :
"=&r" ( value ) : :
"memory"
9930#define AARCH64_PMSIRR_EL1_RND 0x1U
9932#define AARCH64_PMSIRR_EL1_INTERVAL( _val ) ( ( _val ) << 8 )
9933#define AARCH64_PMSIRR_EL1_INTERVAL_SHIFT 8
9934#define AARCH64_PMSIRR_EL1_INTERVAL_MASK 0xffffff00U
9935#define AARCH64_PMSIRR_EL1_INTERVAL_GET( _reg ) \
9936 ( ( ( _reg ) >> 8 ) & 0xffffffU )
9938static inline uint64_t _AArch64_Read_pmsirr_el1(
void )
9943 "mrs %0, PMSIRR_EL1" :
"=&r" ( value ) : :
"memory"
9949static inline void _AArch64_Write_pmsirr_el1( uint64_t value )
9952 "msr PMSIRR_EL1, %0" : :
"r" ( value ) :
"memory"
9958#define AARCH64_PMSLATFR_EL1_MINLAT( _val ) ( ( _val ) << 0 )
9959#define AARCH64_PMSLATFR_EL1_MINLAT_SHIFT 0
9960#define AARCH64_PMSLATFR_EL1_MINLAT_MASK 0xfffU
9961#define AARCH64_PMSLATFR_EL1_MINLAT_GET( _reg ) \
9962 ( ( ( _reg ) >> 0 ) & 0xfffU )
9964static inline uint64_t _AArch64_Read_pmslatfr_el1(
void )
9969 "mrs %0, PMSLATFR_EL1" :
"=&r" ( value ) : :
"memory"
9975static inline void _AArch64_Write_pmslatfr_el1( uint64_t value )
9978 "msr PMSLATFR_EL1, %0" : :
"r" ( value ) :
"memory"
9984#define AARCH64_DISR_EL1_DFSC( _val ) ( ( _val ) << 0 )
9985#define AARCH64_DISR_EL1_DFSC_SHIFT 0
9986#define AARCH64_DISR_EL1_DFSC_MASK 0x3fU
9987#define AARCH64_DISR_EL1_DFSC_GET( _reg ) \
9988 ( ( ( _reg ) >> 0 ) & 0x3fU )
9990#define AARCH64_DISR_EL1_ISS( _val ) ( ( _val ) << 0 )
9991#define AARCH64_DISR_EL1_ISS_SHIFT 0
9992#define AARCH64_DISR_EL1_ISS_MASK 0xffffffU
9993#define AARCH64_DISR_EL1_ISS_GET( _reg ) \
9994 ( ( ( _reg ) >> 0 ) & 0xffffffU )
9996#define AARCH64_DISR_EL1_EA 0x200U
9998#define AARCH64_DISR_EL1_AET( _val ) ( ( _val ) << 10 )
9999#define AARCH64_DISR_EL1_AET_SHIFT 10
10000#define AARCH64_DISR_EL1_AET_MASK 0x1c00U
10001#define AARCH64_DISR_EL1_AET_GET( _reg ) \
10002 ( ( ( _reg ) >> 10 ) & 0x7U )
10004#define AARCH64_DISR_EL1_IDS 0x1000000U
10006#define AARCH64_DISR_EL1_A 0x80000000U
10008static inline uint64_t _AArch64_Read_disr_el1(
void )
10013 "mrs %0, DISR_EL1" :
"=&r" ( value ) : :
"memory"
10019static inline void _AArch64_Write_disr_el1( uint64_t value )
10022 "msr DISR_EL1, %0" : :
"r" ( value ) :
"memory"
10028#define AARCH64_ERRIDR_EL1_NUM( _val ) ( ( _val ) << 0 )
10029#define AARCH64_ERRIDR_EL1_NUM_SHIFT 0
10030#define AARCH64_ERRIDR_EL1_NUM_MASK 0xffffU
10031#define AARCH64_ERRIDR_EL1_NUM_GET( _reg ) \
10032 ( ( ( _reg ) >> 0 ) & 0xffffU )
10034static inline uint64_t _AArch64_Read_erridr_el1(
void )
10039 "mrs %0, ERRIDR_EL1" :
"=&r" ( value ) : :
"memory"
10047#define AARCH64_ERRSELR_EL1_SEL( _val ) ( ( _val ) << 0 )
10048#define AARCH64_ERRSELR_EL1_SEL_SHIFT 0
10049#define AARCH64_ERRSELR_EL1_SEL_MASK 0xffffU
10050#define AARCH64_ERRSELR_EL1_SEL_GET( _reg ) \
10051 ( ( ( _reg ) >> 0 ) & 0xffffU )
10053static inline uint64_t _AArch64_Read_errselr_el1(
void )
10058 "mrs %0, ERRSELR_EL1" :
"=&r" ( value ) : :
"memory"
10064static inline void _AArch64_Write_errselr_el1( uint64_t value )
10067 "msr ERRSELR_EL1, %0" : :
"r" ( value ) :
"memory"
10073static inline uint64_t _AArch64_Read_erxaddr_el1(
void )
10078 "mrs %0, ERXADDR_EL1" :
"=&r" ( value ) : :
"memory"
10084static inline void _AArch64_Write_erxaddr_el1( uint64_t value )
10087 "msr ERXADDR_EL1, %0" : :
"r" ( value ) :
"memory"
10093static inline uint64_t _AArch64_Read_erxctlr_el1(
void )
10098 "mrs %0, ERXCTLR_EL1" :
"=&r" ( value ) : :
"memory"
10104static inline void _AArch64_Write_erxctlr_el1( uint64_t value )
10107 "msr ERXCTLR_EL1, %0" : :
"r" ( value ) :
"memory"
10113static inline uint64_t _AArch64_Read_erxfr_el1(
void )
10118 "mrs %0, ERXFR_EL1" :
"=&r" ( value ) : :
"memory"
10126static inline uint64_t _AArch64_Read_erxmisc0_el1(
void )
10131 "mrs %0, ERXMISC0_EL1" :
"=&r" ( value ) : :
"memory"
10137static inline void _AArch64_Write_erxmisc0_el1( uint64_t value )
10140 "msr ERXMISC0_EL1, %0" : :
"r" ( value ) :
"memory"
10146static inline uint64_t _AArch64_Read_erxmisc1_el1(
void )
10151 "mrs %0, ERXMISC1_EL1" :
"=&r" ( value ) : :
"memory"
10157static inline void _AArch64_Write_erxmisc1_el1( uint64_t value )
10160 "msr ERXMISC1_EL1, %0" : :
"r" ( value ) :
"memory"
10166static inline uint64_t _AArch64_Read_erxmisc2_el1(
void )
10171 "mrs %0, ERXMISC2_EL1" :
"=&r" ( value ) : :
"memory"
10177static inline void _AArch64_Write_erxmisc2_el1( uint64_t value )
10180 "msr ERXMISC2_EL1, %0" : :
"r" ( value ) :
"memory"
10186static inline uint64_t _AArch64_Read_erxmisc3_el1(
void )
10191 "mrs %0, ERXMISC3_EL1" :
"=&r" ( value ) : :
"memory"
10197static inline void _AArch64_Write_erxmisc3_el1( uint64_t value )
10200 "msr ERXMISC3_EL1, %0" : :
"r" ( value ) :
"memory"
10206static inline uint64_t _AArch64_Read_erxpfgcdn_el1(
void )
10211 "mrs %0, ERXPFGCDN_EL1" :
"=&r" ( value ) : :
"memory"
10217static inline void _AArch64_Write_erxpfgcdn_el1( uint64_t value )
10220 "msr ERXPFGCDN_EL1, %0" : :
"r" ( value ) :
"memory"
10226static inline uint64_t _AArch64_Read_erxpfgctl_el1(
void )
10231 "mrs %0, ERXPFGCTL_EL1" :
"=&r" ( value ) : :
"memory"
10237static inline void _AArch64_Write_erxpfgctl_el1( uint64_t value )
10240 "msr ERXPFGCTL_EL1, %0" : :
"r" ( value ) :
"memory"
10246static inline uint64_t _AArch64_Read_erxpfgf_el1(
void )
10251 "mrs %0, ERXPFGF_EL1" :
"=&r" ( value ) : :
"memory"
10259static inline uint64_t _AArch64_Read_erxstatus_el1(
void )
10264 "mrs %0, ERXSTATUS_EL1" :
"=&r" ( value ) : :
"memory"
10270static inline void _AArch64_Write_erxstatus_el1( uint64_t value )
10273 "msr ERXSTATUS_EL1, %0" : :
"r" ( value ) :
"memory"
10279#define AARCH64_VDISR_EL2_FS_3_0( _val ) ( ( _val ) << 0 )
10280#define AARCH64_VDISR_EL2_FS_3_0_SHIFT 0
10281#define AARCH64_VDISR_EL2_FS_3_0_MASK 0xfU
10282#define AARCH64_VDISR_EL2_FS_3_0_GET( _reg ) \
10283 ( ( ( _reg ) >> 0 ) & 0xfU )
10285#define AARCH64_VDISR_EL2_STATUS( _val ) ( ( _val ) << 0 )
10286#define AARCH64_VDISR_EL2_STATUS_SHIFT 0
10287#define AARCH64_VDISR_EL2_STATUS_MASK 0x3fU
10288#define AARCH64_VDISR_EL2_STATUS_GET( _reg ) \
10289 ( ( ( _reg ) >> 0 ) & 0x3fU )
10291#define AARCH64_VDISR_EL2_ISS( _val ) ( ( _val ) << 0 )
10292#define AARCH64_VDISR_EL2_ISS_SHIFT 0
10293#define AARCH64_VDISR_EL2_ISS_MASK 0xffffffU
10294#define AARCH64_VDISR_EL2_ISS_GET( _reg ) \
10295 ( ( ( _reg ) >> 0 ) & 0xffffffU )
10297#define AARCH64_VDISR_EL2_LPAE 0x200U
10299#define AARCH64_VDISR_EL2_FS_4 0x400U
10301#define AARCH64_VDISR_EL2_EXT 0x1000U
10303#define AARCH64_VDISR_EL2_AET( _val ) ( ( _val ) << 14 )
10304#define AARCH64_VDISR_EL2_AET_SHIFT 14
10305#define AARCH64_VDISR_EL2_AET_MASK 0xc000U
10306#define AARCH64_VDISR_EL2_AET_GET( _reg ) \
10307 ( ( ( _reg ) >> 14 ) & 0x3U )
10309#define AARCH64_VDISR_EL2_IDS 0x1000000U
10311#define AARCH64_VDISR_EL2_A 0x80000000U
10313static inline uint64_t _AArch64_Read_vdisr_el2(
void )
10318 "mrs %0, VDISR_EL2" :
"=&r" ( value ) : :
"memory"
10324static inline void _AArch64_Write_vdisr_el2( uint64_t value )
10327 "msr VDISR_EL2, %0" : :
"r" ( value ) :
"memory"
10333#define AARCH64_VSESR_EL2_ISS( _val ) ( ( _val ) << 0 )
10334#define AARCH64_VSESR_EL2_ISS_SHIFT 0
10335#define AARCH64_VSESR_EL2_ISS_MASK 0xffffffU
10336#define AARCH64_VSESR_EL2_ISS_GET( _reg ) \
10337 ( ( ( _reg ) >> 0 ) & 0xffffffU )
10339#define AARCH64_VSESR_EL2_EXT 0x1000U
10341#define AARCH64_VSESR_EL2_AET( _val ) ( ( _val ) << 14 )
10342#define AARCH64_VSESR_EL2_AET_SHIFT 14
10343#define AARCH64_VSESR_EL2_AET_MASK 0xc000U
10344#define AARCH64_VSESR_EL2_AET_GET( _reg ) \
10345 ( ( ( _reg ) >> 14 ) & 0x3U )
10347#define AARCH64_VSESR_EL2_IDS 0x1000000U
10349static inline uint64_t _AArch64_Read_vsesr_el2(
void )
10354 "mrs %0, VSESR_EL2" :
"=&r" ( value ) : :
"memory"
10360static inline void _AArch64_Write_vsesr_el2( uint64_t value )
10363 "msr VSESR_EL2, %0" : :
"r" ( value ) :
"memory"
10369static inline uint64_t _AArch64_Read_cntfrq_el0(
void )
10374 "mrs %0, CNTFRQ_EL0" :
"=&r" ( value ) : :
"memory"
10380static inline void _AArch64_Write_cntfrq_el0( uint64_t value )
10383 "msr CNTFRQ_EL0, %0" : :
"r" ( value ) :
"memory"
10389#define AARCH64_CNTHCTL_EL2_EL0PCTEN 0x1U
10391#define AARCH64_CNTHCTL_EL2_EL1PCTEN_0 0x1U
10393#define AARCH64_CNTHCTL_EL2_EL0VCTEN 0x2U
10395#define AARCH64_CNTHCTL_EL2_EL1PCEN 0x2U
10397#define AARCH64_CNTHCTL_EL2_EVNTEN 0x4U
10399#define AARCH64_CNTHCTL_EL2_EVNTDIR 0x8U
10401#define AARCH64_CNTHCTL_EL2_EVNTI( _val ) ( ( _val ) << 4 )
10402#define AARCH64_CNTHCTL_EL2_EVNTI_SHIFT 4
10403#define AARCH64_CNTHCTL_EL2_EVNTI_MASK 0xf0U
10404#define AARCH64_CNTHCTL_EL2_EVNTI_GET( _reg ) \
10405 ( ( ( _reg ) >> 4 ) & 0xfU )
10407#define AARCH64_CNTHCTL_EL2_EL0VTEN 0x100U
10409#define AARCH64_CNTHCTL_EL2_EL0PTEN 0x200U
10411#define AARCH64_CNTHCTL_EL2_EL1PCTEN_1 0x400U
10413#define AARCH64_CNTHCTL_EL2_EL1PTEN 0x800U
10415#define AARCH64_CNTHCTL_EL2_ECV 0x1000U
10417#define AARCH64_CNTHCTL_EL2_EL1TVT 0x2000U
10419#define AARCH64_CNTHCTL_EL2_EL1TVCT 0x4000U
10421#define AARCH64_CNTHCTL_EL2_EL1NVPCT 0x8000U
10423#define AARCH64_CNTHCTL_EL2_EL1NVVCT 0x10000U
10425#define AARCH64_CNTHCTL_EL2_EVNTIS 0x20000U
10427static inline uint64_t _AArch64_Read_cnthctl_el2(
void )
10432 "mrs %0, CNTHCTL_EL2" :
"=&r" ( value ) : :
"memory"
10438static inline void _AArch64_Write_cnthctl_el2( uint64_t value )
10441 "msr CNTHCTL_EL2, %0" : :
"r" ( value ) :
"memory"
10447#define AARCH64_CNTHP_CTL_EL2_ENABLE 0x1U
10449#define AARCH64_CNTHP_CTL_EL2_IMASK 0x2U
10451#define AARCH64_CNTHP_CTL_EL2_ISTATUS 0x4U
10453static inline uint64_t _AArch64_Read_cnthp_ctl_el2(
void )
10458 "mrs %0, CNTHP_CTL_EL2" :
"=&r" ( value ) : :
"memory"
10464static inline void _AArch64_Write_cnthp_ctl_el2( uint64_t value )
10467 "msr CNTHP_CTL_EL2, %0" : :
"r" ( value ) :
"memory"
10473static inline uint64_t _AArch64_Read_cnthp_cval_el2(
void )
10478 "mrs %0, CNTHP_CVAL_EL2" :
"=&r" ( value ) : :
"memory"
10484static inline void _AArch64_Write_cnthp_cval_el2( uint64_t value )
10487 "msr CNTHP_CVAL_EL2, %0" : :
"r" ( value ) :
"memory"
10493#define AARCH64_CNTHP_TVAL_EL2_TIMERVALUE( _val ) ( ( _val ) << 0 )
10494#define AARCH64_CNTHP_TVAL_EL2_TIMERVALUE_SHIFT 0
10495#define AARCH64_CNTHP_TVAL_EL2_TIMERVALUE_MASK 0xffffffffU
10496#define AARCH64_CNTHP_TVAL_EL2_TIMERVALUE_GET( _reg ) \
10497 ( ( ( _reg ) >> 0 ) & 0xffffffffU )
10499static inline uint64_t _AArch64_Read_cnthp_tval_el2(
void )
10504 "mrs %0, CNTHP_TVAL_EL2" :
"=&r" ( value ) : :
"memory"
10510static inline void _AArch64_Write_cnthp_tval_el2( uint64_t value )
10513 "msr CNTHP_TVAL_EL2, %0" : :
"r" ( value ) :
"memory"
10519#define AARCH64_CNTHPS_CTL_EL2_ENABLE 0x1U
10521#define AARCH64_CNTHPS_CTL_EL2_IMASK 0x2U
10523#define AARCH64_CNTHPS_CTL_EL2_ISTATUS 0x4U
10525static inline uint64_t _AArch64_Read_cnthps_ctl_el2(
void )
10530 "mrs %0, CNTHPS_CTL_EL2" :
"=&r" ( value ) : :
"memory"
10536static inline void _AArch64_Write_cnthps_ctl_el2( uint64_t value )
10539 "msr CNTHPS_CTL_EL2, %0" : :
"r" ( value ) :
"memory"
10545static inline uint64_t _AArch64_Read_cnthps_cval_el2(
void )
10550 "mrs %0, CNTHPS_CVAL_EL2" :
"=&r" ( value ) : :
"memory"
10556static inline void _AArch64_Write_cnthps_cval_el2( uint64_t value )
10559 "msr CNTHPS_CVAL_EL2, %0" : :
"r" ( value ) :
"memory"
10565#define AARCH64_CNTHPS_TVAL_EL2_TIMERVALUE( _val ) ( ( _val ) << 0 )
10566#define AARCH64_CNTHPS_TVAL_EL2_TIMERVALUE_SHIFT 0
10567#define AARCH64_CNTHPS_TVAL_EL2_TIMERVALUE_MASK 0xffffffffU
10568#define AARCH64_CNTHPS_TVAL_EL2_TIMERVALUE_GET( _reg ) \
10569 ( ( ( _reg ) >> 0 ) & 0xffffffffU )
10571static inline uint64_t _AArch64_Read_cnthps_tval_el2(
void )
10576 "mrs %0, CNTHPS_TVAL_EL2" :
"=&r" ( value ) : :
"memory"
10582static inline void _AArch64_Write_cnthps_tval_el2( uint64_t value )
10585 "msr CNTHPS_TVAL_EL2, %0" : :
"r" ( value ) :
"memory"
10591#define AARCH64_CNTHV_CTL_EL2_ENABLE 0x1U
10593#define AARCH64_CNTHV_CTL_EL2_IMASK 0x2U
10595#define AARCH64_CNTHV_CTL_EL2_ISTATUS 0x4U
10597static inline uint64_t _AArch64_Read_cnthv_ctl_el2(
void )
10602 "mrs %0, CNTHV_CTL_EL2" :
"=&r" ( value ) : :
"memory"
10608static inline void _AArch64_Write_cnthv_ctl_el2( uint64_t value )
10611 "msr CNTHV_CTL_EL2, %0" : :
"r" ( value ) :
"memory"
10617static inline uint64_t _AArch64_Read_cnthv_cval_el2(
void )
10622 "mrs %0, CNTHV_CVAL_EL2" :
"=&r" ( value ) : :
"memory"
10628static inline void _AArch64_Write_cnthv_cval_el2( uint64_t value )
10631 "msr CNTHV_CVAL_EL2, %0" : :
"r" ( value ) :
"memory"
10637#define AARCH64_CNTHV_TVAL_EL2_TIMERVALUE( _val ) ( ( _val ) << 0 )
10638#define AARCH64_CNTHV_TVAL_EL2_TIMERVALUE_SHIFT 0
10639#define AARCH64_CNTHV_TVAL_EL2_TIMERVALUE_MASK 0xffffffffU
10640#define AARCH64_CNTHV_TVAL_EL2_TIMERVALUE_GET( _reg ) \
10641 ( ( ( _reg ) >> 0 ) & 0xffffffffU )
10643static inline uint64_t _AArch64_Read_cnthv_tval_el2(
void )
10648 "mrs %0, CNTHV_TVAL_EL2" :
"=&r" ( value ) : :
"memory"
10654static inline void _AArch64_Write_cnthv_tval_el2( uint64_t value )
10657 "msr CNTHV_TVAL_EL2, %0" : :
"r" ( value ) :
"memory"
10663#define AARCH64_CNTHVS_CTL_EL2_ENABLE 0x1U
10665#define AARCH64_CNTHVS_CTL_EL2_IMASK 0x2U
10667#define AARCH64_CNTHVS_CTL_EL2_ISTATUS 0x4U
10669static inline uint64_t _AArch64_Read_cnthvs_ctl_el2(
void )
10674 "mrs %0, CNTHVS_CTL_EL2" :
"=&r" ( value ) : :
"memory"
10680static inline void _AArch64_Write_cnthvs_ctl_el2( uint64_t value )
10683 "msr CNTHVS_CTL_EL2, %0" : :
"r" ( value ) :
"memory"
10689static inline uint64_t _AArch64_Read_cnthvs_cval_el2(
void )
10694 "mrs %0, CNTHVS_CVAL_EL2" :
"=&r" ( value ) : :
"memory"
10700static inline void _AArch64_Write_cnthvs_cval_el2( uint64_t value )
10703 "msr CNTHVS_CVAL_EL2, %0" : :
"r" ( value ) :
"memory"
10709#define AARCH64_CNTHVS_TVAL_EL2_TIMERVALUE( _val ) ( ( _val ) << 0 )
10710#define AARCH64_CNTHVS_TVAL_EL2_TIMERVALUE_SHIFT 0
10711#define AARCH64_CNTHVS_TVAL_EL2_TIMERVALUE_MASK 0xffffffffU
10712#define AARCH64_CNTHVS_TVAL_EL2_TIMERVALUE_GET( _reg ) \
10713 ( ( ( _reg ) >> 0 ) & 0xffffffffU )
10715static inline uint64_t _AArch64_Read_cnthvs_tval_el2(
void )
10720 "mrs %0, CNTHVS_TVAL_EL2" :
"=&r" ( value ) : :
"memory"
10726static inline void _AArch64_Write_cnthvs_tval_el2( uint64_t value )
10729 "msr CNTHVS_TVAL_EL2, %0" : :
"r" ( value ) :
"memory"
10735#define AARCH64_CNTKCTL_EL1_EL0PCTEN 0x1U
10737#define AARCH64_CNTKCTL_EL1_EL0VCTEN 0x2U
10739#define AARCH64_CNTKCTL_EL1_EVNTEN 0x4U
10741#define AARCH64_CNTKCTL_EL1_EVNTDIR 0x8U
10743#define AARCH64_CNTKCTL_EL1_EVNTI( _val ) ( ( _val ) << 4 )
10744#define AARCH64_CNTKCTL_EL1_EVNTI_SHIFT 4
10745#define AARCH64_CNTKCTL_EL1_EVNTI_MASK 0xf0U
10746#define AARCH64_CNTKCTL_EL1_EVNTI_GET( _reg ) \
10747 ( ( ( _reg ) >> 4 ) & 0xfU )
10749#define AARCH64_CNTKCTL_EL1_EL0VTEN 0x100U
10751#define AARCH64_CNTKCTL_EL1_EL0PTEN 0x200U
10753#define AARCH64_CNTKCTL_EL1_EVNTIS 0x20000U
10755static inline uint64_t _AArch64_Read_cntkctl_el1(
void )
10760 "mrs %0, CNTKCTL_EL1" :
"=&r" ( value ) : :
"memory"
10766static inline void _AArch64_Write_cntkctl_el1( uint64_t value )
10769 "msr CNTKCTL_EL1, %0" : :
"r" ( value ) :
"memory"
10775#define AARCH64_CNTP_CTL_EL0_ENABLE 0x1U
10777#define AARCH64_CNTP_CTL_EL0_IMASK 0x2U
10779#define AARCH64_CNTP_CTL_EL0_ISTATUS 0x4U
10781static inline uint64_t _AArch64_Read_cntp_ctl_el0(
void )
10786 "mrs %0, CNTP_CTL_EL0" :
"=&r" ( value ) : :
"memory"
10792static inline void _AArch64_Write_cntp_ctl_el0( uint64_t value )
10795 "msr CNTP_CTL_EL0, %0" : :
"r" ( value ) :
"memory"
10801static inline uint64_t _AArch64_Read_cntp_cval_el0(
void )
10806 "mrs %0, CNTP_CVAL_EL0" :
"=&r" ( value ) : :
"memory"
10812static inline void _AArch64_Write_cntp_cval_el0( uint64_t value )
10815 "msr CNTP_CVAL_EL0, %0" : :
"r" ( value ) :
"memory"
10821#define AARCH64_CNTP_TVAL_EL0_TIMERVALUE( _val ) ( ( _val ) << 0 )
10822#define AARCH64_CNTP_TVAL_EL0_TIMERVALUE_SHIFT 0
10823#define AARCH64_CNTP_TVAL_EL0_TIMERVALUE_MASK 0xffffffffU
10824#define AARCH64_CNTP_TVAL_EL0_TIMERVALUE_GET( _reg ) \
10825 ( ( ( _reg ) >> 0 ) & 0xffffffffU )
10827static inline uint64_t _AArch64_Read_cntp_tval_el0(
void )
10832 "mrs %0, CNTP_TVAL_EL0" :
"=&r" ( value ) : :
"memory"
10838static inline void _AArch64_Write_cntp_tval_el0( uint64_t value )
10841 "msr CNTP_TVAL_EL0, %0" : :
"r" ( value ) :
"memory"
10847static inline uint64_t _AArch64_Read_cntpctss_el0(
void )
10852 "mrs %0, CNTPCTSS_EL0" :
"=&r" ( value ) : :
"memory"
10860static inline uint64_t _AArch64_Read_cntpct_el0(
void )
10865 "mrs %0, CNTPCT_EL0" :
"=&r" ( value ) : :
"memory"
10873#define AARCH64_CNTPS_CTL_EL1_ENABLE 0x1U
10875#define AARCH64_CNTPS_CTL_EL1_IMASK 0x2U
10877#define AARCH64_CNTPS_CTL_EL1_ISTATUS 0x4U
10879static inline uint64_t _AArch64_Read_cntps_ctl_el1(
void )
10884 "mrs %0, CNTPS_CTL_EL1" :
"=&r" ( value ) : :
"memory"
10890static inline void _AArch64_Write_cntps_ctl_el1( uint64_t value )
10893 "msr CNTPS_CTL_EL1, %0" : :
"r" ( value ) :
"memory"
10899static inline uint64_t _AArch64_Read_cntpoff_el2(
void )
10904 "mrs %0, CNTPOFF_EL2" :
"=&r" ( value ) : :
"memory"
10910static inline void _AArch64_Write_cntpoff_el2( uint64_t value )
10913 "msr CNTPOFF_EL2, %0" : :
"r" ( value ) :
"memory"
10919static inline uint64_t _AArch64_Read_cntps_cval_el1(
void )
10924 "mrs %0, CNTPS_CVAL_EL1" :
"=&r" ( value ) : :
"memory"
10930static inline void _AArch64_Write_cntps_cval_el1( uint64_t value )
10933 "msr CNTPS_CVAL_EL1, %0" : :
"r" ( value ) :
"memory"
10939#define AARCH64_CNTPS_TVAL_EL1_TIMERVALUE( _val ) ( ( _val ) << 0 )
10940#define AARCH64_CNTPS_TVAL_EL1_TIMERVALUE_SHIFT 0
10941#define AARCH64_CNTPS_TVAL_EL1_TIMERVALUE_MASK 0xffffffffU
10942#define AARCH64_CNTPS_TVAL_EL1_TIMERVALUE_GET( _reg ) \
10943 ( ( ( _reg ) >> 0 ) & 0xffffffffU )
10945static inline uint64_t _AArch64_Read_cntps_tval_el1(
void )
10950 "mrs %0, CNTPS_TVAL_EL1" :
"=&r" ( value ) : :
"memory"
10956static inline void _AArch64_Write_cntps_tval_el1( uint64_t value )
10959 "msr CNTPS_TVAL_EL1, %0" : :
"r" ( value ) :
"memory"
10965#define AARCH64_CNTV_CTL_EL0_ENABLE 0x1U
10967#define AARCH64_CNTV_CTL_EL0_IMASK 0x2U
10969#define AARCH64_CNTV_CTL_EL0_ISTATUS 0x4U
10971static inline uint64_t _AArch64_Read_cntv_ctl_el0(
void )
10976 "mrs %0, CNTV_CTL_EL0" :
"=&r" ( value ) : :
"memory"
10982static inline void _AArch64_Write_cntv_ctl_el0( uint64_t value )
10985 "msr CNTV_CTL_EL0, %0" : :
"r" ( value ) :
"memory"
10991static inline uint64_t _AArch64_Read_cntv_cval_el0(
void )
10996 "mrs %0, CNTV_CVAL_EL0" :
"=&r" ( value ) : :
"memory"
11002static inline void _AArch64_Write_cntv_cval_el0( uint64_t value )
11005 "msr CNTV_CVAL_EL0, %0" : :
"r" ( value ) :
"memory"
11011#define AARCH64_CNTV_TVAL_EL0_TIMERVALUE( _val ) ( ( _val ) << 0 )
11012#define AARCH64_CNTV_TVAL_EL0_TIMERVALUE_SHIFT 0
11013#define AARCH64_CNTV_TVAL_EL0_TIMERVALUE_MASK 0xffffffffU
11014#define AARCH64_CNTV_TVAL_EL0_TIMERVALUE_GET( _reg ) \
11015 ( ( ( _reg ) >> 0 ) & 0xffffffffU )
11017static inline uint64_t _AArch64_Read_cntv_tval_el0(
void )
11022 "mrs %0, CNTV_TVAL_EL0" :
"=&r" ( value ) : :
"memory"
11028static inline void _AArch64_Write_cntv_tval_el0( uint64_t value )
11031 "msr CNTV_TVAL_EL0, %0" : :
"r" ( value ) :
"memory"
11037static inline uint64_t _AArch64_Read_cntvctss_el0(
void )
11042 "mrs %0, CNTVCTSS_EL0" :
"=&r" ( value ) : :
"memory"
11050static inline uint64_t _AArch64_Read_cntvct_el0(
void )
11055 "mrs %0, CNTVCT_EL0" :
"=&r" ( value ) : :
"memory"