This header file provides the API to read and write the AArch64 system registers.
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#define | AARCH64_CCSIDR2_EL1_NUMSETS(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_CCSIDR2_EL1_NUMSETS_SHIFT 0 |
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#define | AARCH64_CCSIDR2_EL1_NUMSETS_MASK 0xffffffU |
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#define | AARCH64_CCSIDR2_EL1_NUMSETS_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffffU ) |
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#define | AARCH64_CCSIDR_EL1_LINESIZE(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_CCSIDR_EL1_LINESIZE_SHIFT 0 |
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#define | AARCH64_CCSIDR_EL1_LINESIZE_MASK 0x7U |
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#define | AARCH64_CCSIDR_EL1_LINESIZE_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x7U ) |
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#define | AARCH64_CCSIDR_EL1_ASSOCIATIVITY_0(_val) ( ( _val ) << 3 ) |
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#define | AARCH64_CCSIDR_EL1_ASSOCIATIVITY_SHIFT_0 3 |
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#define | AARCH64_CCSIDR_EL1_ASSOCIATIVITY_MASK_0 0x1ff8U |
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#define | AARCH64_CCSIDR_EL1_ASSOCIATIVITY_GET_0(_reg) ( ( ( _reg ) >> 3 ) & 0x3ffU ) |
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#define | AARCH64_CCSIDR_EL1_ASSOCIATIVITY_1(_val) ( ( _val ) << 3 ) |
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#define | AARCH64_CCSIDR_EL1_ASSOCIATIVITY_SHIFT_1 3 |
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#define | AARCH64_CCSIDR_EL1_ASSOCIATIVITY_MASK_1 0xfffff8U |
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#define | AARCH64_CCSIDR_EL1_ASSOCIATIVITY_GET_1(_reg) ( ( ( _reg ) >> 3 ) & 0x1fffffU ) |
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#define | AARCH64_CCSIDR_EL1_NUMSETS_0(_val) ( ( _val ) << 13 ) |
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#define | AARCH64_CCSIDR_EL1_NUMSETS_SHIFT_0 13 |
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#define | AARCH64_CCSIDR_EL1_NUMSETS_MASK_0 0xfffe000U |
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#define | AARCH64_CCSIDR_EL1_NUMSETS_GET_0(_reg) ( ( ( _reg ) >> 13 ) & 0x7fffU ) |
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#define | AARCH64_CCSIDR_EL1_NUMSETS_1(_val) ( ( _val ) << 32 ) |
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#define | AARCH64_CCSIDR_EL1_NUMSETS_SHIFT_1 32 |
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#define | AARCH64_CCSIDR_EL1_NUMSETS_MASK_1 0xffffff00000000ULL |
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#define | AARCH64_CCSIDR_EL1_NUMSETS_GET_1(_reg) ( ( ( _reg ) >> 32 ) & 0xffffffULL ) |
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#define | AARCH64_CLIDR_EL1_CTYPE1(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_CLIDR_EL1_CTYPE1_SHIFT 0 |
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#define | AARCH64_CLIDR_EL1_CTYPE1_MASK ( 0x7U << 0 ) |
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#define | AARCH64_CLIDR_EL1_CTYPE1_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x7U ) |
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#define | AARCH64_CLIDR_EL1_CTYPE2(_val) ( ( _val ) << 3 ) |
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#define | AARCH64_CLIDR_EL1_CTYPE2_SHIFT 3 |
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#define | AARCH64_CLIDR_EL1_CTYPE2_MASK ( 0x7U << 3 ) |
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#define | AARCH64_CLIDR_EL1_CTYPE2_GET(_reg) ( ( ( _reg ) >> 3 ) & 0x7U ) |
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#define | AARCH64_CLIDR_EL1_CTYPE3(_val) ( ( _val ) << 6 ) |
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#define | AARCH64_CLIDR_EL1_CTYPE3_SHIFT 6 |
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#define | AARCH64_CLIDR_EL1_CTYPE3_MASK ( 0x7U << 6 ) |
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#define | AARCH64_CLIDR_EL1_CTYPE3_GET(_reg) ( ( ( _reg ) >> 6 ) & 0x7U ) |
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#define | AARCH64_CLIDR_EL1_CTYPE4(_val) ( ( _val ) << 9 ) |
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#define | AARCH64_CLIDR_EL1_CTYPE4_SHIFT 9 |
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#define | AARCH64_CLIDR_EL1_CTYPE4_MASK ( 0x7U << 9 ) |
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#define | AARCH64_CLIDR_EL1_CTYPE4_GET(_reg) ( ( ( _reg ) >> 9 ) & 0x7U ) |
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#define | AARCH64_CLIDR_EL1_CTYPE5(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_CLIDR_EL1_CTYPE5_SHIFT 12 |
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#define | AARCH64_CLIDR_EL1_CTYPE5_MASK ( 0x7U << 12 ) |
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#define | AARCH64_CLIDR_EL1_CTYPE5_GET(_reg) ( ( ( _reg ) >> 12 ) & 0x7U ) |
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#define | AARCH64_CLIDR_EL1_CTYPE6(_val) ( ( _val ) << 15 ) |
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#define | AARCH64_CLIDR_EL1_CTYPE6_SHIFT 15 |
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#define | AARCH64_CLIDR_EL1_CTYPE6_MASK ( 0x7U << 15 ) |
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#define | AARCH64_CLIDR_EL1_CTYPE6_GET(_reg) ( ( ( _reg ) >> 15 ) & 0x7U ) |
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#define | AARCH64_CLIDR_EL1_CTYPE7(_val) ( ( _val ) << 18 ) |
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#define | AARCH64_CLIDR_EL1_CTYPE7_SHIFT 18 |
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#define | AARCH64_CLIDR_EL1_CTYPE7_MASK ( 0x7U << 18 ) |
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#define | AARCH64_CLIDR_EL1_CTYPE7_GET(_reg) ( ( ( _reg ) >> 18 ) & 0x7U ) |
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#define | AARCH64_CLIDR_EL1_LOUIS(_val) ( ( _val ) << 21 ) |
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#define | AARCH64_CLIDR_EL1_LOUIS_SHIFT 21 |
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#define | AARCH64_CLIDR_EL1_LOUIS_MASK 0xe00000U |
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#define | AARCH64_CLIDR_EL1_LOUIS_GET(_reg) ( ( ( _reg ) >> 21 ) & 0x7U ) |
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#define | AARCH64_CLIDR_EL1_LOC(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_CLIDR_EL1_LOC_SHIFT 24 |
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#define | AARCH64_CLIDR_EL1_LOC_MASK 0x7000000U |
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#define | AARCH64_CLIDR_EL1_LOC_GET(_reg) ( ( ( _reg ) >> 24 ) & 0x7U ) |
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#define | AARCH64_CLIDR_EL1_LOUU(_val) ( ( _val ) << 27 ) |
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#define | AARCH64_CLIDR_EL1_LOUU_SHIFT 27 |
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#define | AARCH64_CLIDR_EL1_LOUU_MASK 0x38000000U |
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#define | AARCH64_CLIDR_EL1_LOUU_GET(_reg) ( ( ( _reg ) >> 27 ) & 0x7U ) |
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#define | AARCH64_CLIDR_EL1_ICB(_val) ( ( _val ) << 30 ) |
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#define | AARCH64_CLIDR_EL1_ICB_SHIFT 30 |
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#define | AARCH64_CLIDR_EL1_ICB_MASK 0x1c0000000ULL |
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#define | AARCH64_CLIDR_EL1_ICB_GET(_reg) ( ( ( _reg ) >> 30 ) & 0x7ULL ) |
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#define | AARCH64_CONTEXTIDR_EL1_PROCID(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_CONTEXTIDR_EL1_PROCID_SHIFT 0 |
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#define | AARCH64_CONTEXTIDR_EL1_PROCID_MASK 0xffffffffU |
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#define | AARCH64_CONTEXTIDR_EL1_PROCID_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffffffU ) |
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#define | AARCH64_CONTEXTIDR_EL2_PROCID(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_CONTEXTIDR_EL2_PROCID_SHIFT 0 |
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#define | AARCH64_CONTEXTIDR_EL2_PROCID_MASK 0xffffffffU |
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#define | AARCH64_CONTEXTIDR_EL2_PROCID_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffffffU ) |
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#define | AARCH64_CPACR_EL1_ZEN(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_CPACR_EL1_ZEN_SHIFT 16 |
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#define | AARCH64_CPACR_EL1_ZEN_MASK 0x30000U |
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#define | AARCH64_CPACR_EL1_ZEN_GET(_reg) ( ( ( _reg ) >> 16 ) & 0x3U ) |
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#define | AARCH64_CPACR_EL1_FPEN(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_CPACR_EL1_FPEN_SHIFT 20 |
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#define | AARCH64_CPACR_EL1_FPEN_MASK 0x300000U |
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#define | AARCH64_CPACR_EL1_FPEN_GET(_reg) ( ( ( _reg ) >> 20 ) & 0x3U ) |
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#define | AARCH64_CPACR_EL1_TTA 0x10000000U |
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#define | AARCH64_CPTR_EL2_TZ 0x100U |
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#define | AARCH64_CPTR_EL2_TFP 0x400U |
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#define | AARCH64_CPTR_EL2_ZEN(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_CPTR_EL2_ZEN_SHIFT 16 |
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#define | AARCH64_CPTR_EL2_ZEN_MASK 0x30000U |
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#define | AARCH64_CPTR_EL2_ZEN_GET(_reg) ( ( ( _reg ) >> 16 ) & 0x3U ) |
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#define | AARCH64_CPTR_EL2_TTA_0 0x100000U |
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#define | AARCH64_CPTR_EL2_FPEN(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_CPTR_EL2_FPEN_SHIFT 20 |
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#define | AARCH64_CPTR_EL2_FPEN_MASK 0x300000U |
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#define | AARCH64_CPTR_EL2_FPEN_GET(_reg) ( ( ( _reg ) >> 20 ) & 0x3U ) |
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#define | AARCH64_CPTR_EL2_TTA_1 0x10000000U |
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#define | AARCH64_CPTR_EL2_TAM 0x40000000U |
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#define | AARCH64_CPTR_EL2_TCPAC 0x80000000U |
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#define | AARCH64_CPTR_EL3_EZ 0x100U |
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#define | AARCH64_CPTR_EL3_TFP 0x400U |
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#define | AARCH64_CPTR_EL3_TTA 0x100000U |
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#define | AARCH64_CPTR_EL3_TAM 0x40000000U |
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#define | AARCH64_CPTR_EL3_TCPAC 0x80000000U |
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#define | AARCH64_CSSELR_EL1_IND 0x1U |
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#define | AARCH64_CSSELR_EL1_LEVEL(_val) ( ( _val ) << 1 ) |
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#define | AARCH64_CSSELR_EL1_LEVEL_SHIFT 1 |
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#define | AARCH64_CSSELR_EL1_LEVEL_MASK 0xeU |
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#define | AARCH64_CSSELR_EL1_LEVEL_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x7U ) |
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#define | AARCH64_CSSELR_EL1_TND 0x10U |
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#define | AARCH64_CTR_EL0_IMINLINE(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_CTR_EL0_IMINLINE_SHIFT 0 |
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#define | AARCH64_CTR_EL0_IMINLINE_MASK 0xfU |
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#define | AARCH64_CTR_EL0_IMINLINE_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_CTR_EL0_L1IP(_val) ( ( _val ) << 14 ) |
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#define | AARCH64_CTR_EL0_L1IP_SHIFT 14 |
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#define | AARCH64_CTR_EL0_L1IP_MASK 0xc000U |
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#define | AARCH64_CTR_EL0_L1IP_GET(_reg) ( ( ( _reg ) >> 14 ) & 0x3U ) |
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#define | AARCH64_CTR_EL0_DMINLINE(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_CTR_EL0_DMINLINE_SHIFT 16 |
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#define | AARCH64_CTR_EL0_DMINLINE_MASK 0xf0000U |
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#define | AARCH64_CTR_EL0_DMINLINE_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_CTR_EL0_ERG(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_CTR_EL0_ERG_SHIFT 20 |
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#define | AARCH64_CTR_EL0_ERG_MASK 0xf00000U |
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#define | AARCH64_CTR_EL0_ERG_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_CTR_EL0_CWG(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_CTR_EL0_CWG_SHIFT 24 |
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#define | AARCH64_CTR_EL0_CWG_MASK 0xf000000U |
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#define | AARCH64_CTR_EL0_CWG_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU ) |
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#define | AARCH64_CTR_EL0_IDC 0x10000000U |
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#define | AARCH64_CTR_EL0_DIC 0x20000000U |
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#define | AARCH64_CTR_EL0_TMINLINE(_val) ( ( _val ) << 32 ) |
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#define | AARCH64_CTR_EL0_TMINLINE_SHIFT 32 |
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#define | AARCH64_CTR_EL0_TMINLINE_MASK 0x3f00000000ULL |
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#define | AARCH64_CTR_EL0_TMINLINE_GET(_reg) ( ( ( _reg ) >> 32 ) & 0x3fULL ) |
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#define | AARCH64_DCZID_EL0_BS(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_DCZID_EL0_BS_SHIFT 0 |
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#define | AARCH64_DCZID_EL0_BS_MASK 0xfU |
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#define | AARCH64_DCZID_EL0_BS_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_DCZID_EL0_DZP 0x10U |
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#define | AARCH64_ESR_EL1_DIRECTION 0x1U |
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#define | AARCH64_ESR_EL1_ERETA 0x1U |
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#define | AARCH64_ESR_EL1_IOF 0x1U |
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#define | AARCH64_ESR_EL1_TI 0x1U |
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#define | AARCH64_ESR_EL1_BTYPE(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ESR_EL1_BTYPE_SHIFT 0 |
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#define | AARCH64_ESR_EL1_BTYPE_MASK 0x3U |
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#define | AARCH64_ESR_EL1_BTYPE_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3U ) |
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#define | AARCH64_ESR_EL1_DFSC(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ESR_EL1_DFSC_SHIFT 0 |
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#define | AARCH64_ESR_EL1_DFSC_MASK 0x3fU |
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#define | AARCH64_ESR_EL1_DFSC_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3fU ) |
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#define | AARCH64_ESR_EL1_IFSC(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ESR_EL1_IFSC_SHIFT 0 |
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#define | AARCH64_ESR_EL1_IFSC_MASK 0x3fU |
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#define | AARCH64_ESR_EL1_IFSC_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3fU ) |
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#define | AARCH64_ESR_EL1_COMMENT(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ESR_EL1_COMMENT_SHIFT 0 |
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#define | AARCH64_ESR_EL1_COMMENT_MASK 0xffffU |
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#define | AARCH64_ESR_EL1_COMMENT_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffU ) |
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#define | AARCH64_ESR_EL1_IMM16(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ESR_EL1_IMM16_SHIFT 0 |
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#define | AARCH64_ESR_EL1_IMM16_MASK 0xffffU |
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#define | AARCH64_ESR_EL1_IMM16_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffU ) |
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#define | AARCH64_ESR_EL1_ISS(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ESR_EL1_ISS_SHIFT 0 |
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#define | AARCH64_ESR_EL1_ISS_MASK 0x1ffffffU |
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#define | AARCH64_ESR_EL1_ISS_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x1ffffffU ) |
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#define | AARCH64_ESR_EL1_DZF 0x2U |
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#define | AARCH64_ESR_EL1_ERET 0x2U |
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#define | AARCH64_ESR_EL1_AM(_val) ( ( _val ) << 1 ) |
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#define | AARCH64_ESR_EL1_AM_SHIFT 1 |
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#define | AARCH64_ESR_EL1_AM_MASK 0xeU |
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#define | AARCH64_ESR_EL1_AM_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x7U ) |
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#define | AARCH64_ESR_EL1_CRM(_val) ( ( _val ) << 1 ) |
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#define | AARCH64_ESR_EL1_CRM_SHIFT 1 |
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#define | AARCH64_ESR_EL1_CRM_MASK 0x1eU |
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#define | AARCH64_ESR_EL1_CRM_GET(_reg) ( ( ( _reg ) >> 1 ) & 0xfU ) |
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#define | AARCH64_ESR_EL1_OFF 0x4U |
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#define | AARCH64_ESR_EL1_UFF 0x8U |
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#define | AARCH64_ESR_EL1_IXF 0x10U |
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#define | AARCH64_ESR_EL1_OFFSET 0x10U |
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#define | AARCH64_ESR_EL1_RN(_val) ( ( _val ) << 5 ) |
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#define | AARCH64_ESR_EL1_RN_SHIFT 5 |
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#define | AARCH64_ESR_EL1_RN_MASK 0x3e0U |
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#define | AARCH64_ESR_EL1_RN_GET(_reg) ( ( ( _reg ) >> 5 ) & 0x1fU ) |
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#define | AARCH64_ESR_EL1_RT(_val) ( ( _val ) << 5 ) |
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#define | AARCH64_ESR_EL1_RT_SHIFT 5 |
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#define | AARCH64_ESR_EL1_RT_MASK 0x3e0U |
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#define | AARCH64_ESR_EL1_RT_GET(_reg) ( ( ( _reg ) >> 5 ) & 0x1fU ) |
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#define | AARCH64_ESR_EL1_EX 0x40U |
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#define | AARCH64_ESR_EL1_WNR 0x40U |
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#define | AARCH64_ESR_EL1_IDF 0x80U |
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#define | AARCH64_ESR_EL1_S1PTW 0x80U |
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#define | AARCH64_ESR_EL1_CM 0x100U |
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#define | AARCH64_ESR_EL1_VECITR(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ESR_EL1_VECITR_SHIFT 8 |
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#define | AARCH64_ESR_EL1_VECITR_MASK 0x700U |
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#define | AARCH64_ESR_EL1_VECITR_GET(_reg) ( ( ( _reg ) >> 8 ) & 0x7U ) |
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#define | AARCH64_ESR_EL1_EA 0x200U |
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#define | AARCH64_ESR_EL1_FNV 0x400U |
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#define | AARCH64_ESR_EL1_AET(_val) ( ( _val ) << 10 ) |
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#define | AARCH64_ESR_EL1_AET_SHIFT 10 |
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#define | AARCH64_ESR_EL1_AET_MASK 0x1c00U |
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#define | AARCH64_ESR_EL1_AET_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x7U ) |
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#define | AARCH64_ESR_EL1_CRN(_val) ( ( _val ) << 10 ) |
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#define | AARCH64_ESR_EL1_CRN_SHIFT 10 |
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#define | AARCH64_ESR_EL1_CRN_MASK 0x3c00U |
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#define | AARCH64_ESR_EL1_CRN_GET(_reg) ( ( ( _reg ) >> 10 ) & 0xfU ) |
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#define | AARCH64_ESR_EL1_RT2(_val) ( ( _val ) << 10 ) |
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#define | AARCH64_ESR_EL1_RT2_SHIFT 10 |
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#define | AARCH64_ESR_EL1_RT2_MASK 0x7c00U |
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#define | AARCH64_ESR_EL1_RT2_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x1fU ) |
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#define | AARCH64_ESR_EL1_SET(_val) ( ( _val ) << 11 ) |
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#define | AARCH64_ESR_EL1_SET_SHIFT 11 |
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#define | AARCH64_ESR_EL1_SET_MASK 0x1800U |
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#define | AARCH64_ESR_EL1_SET_GET(_reg) ( ( ( _reg ) >> 11 ) & 0x3U ) |
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#define | AARCH64_ESR_EL1_IMM8(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ESR_EL1_IMM8_SHIFT 12 |
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#define | AARCH64_ESR_EL1_IMM8_MASK 0xff000U |
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#define | AARCH64_ESR_EL1_IMM8_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xffU ) |
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#define | AARCH64_ESR_EL1_IESB 0x2000U |
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#define | AARCH64_ESR_EL1_VNCR 0x2000U |
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#define | AARCH64_ESR_EL1_AR 0x4000U |
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#define | AARCH64_ESR_EL1_OP1(_val) ( ( _val ) << 14 ) |
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#define | AARCH64_ESR_EL1_OP1_SHIFT 14 |
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#define | AARCH64_ESR_EL1_OP1_MASK 0x1c000U |
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#define | AARCH64_ESR_EL1_OP1_GET(_reg) ( ( ( _reg ) >> 14 ) & 0x7U ) |
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#define | AARCH64_ESR_EL1_OPC1_0(_val) ( ( _val ) << 14 ) |
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#define | AARCH64_ESR_EL1_OPC1_SHIFT_0 14 |
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#define | AARCH64_ESR_EL1_OPC1_MASK_0 0x1c000U |
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#define | AARCH64_ESR_EL1_OPC1_GET_0(_reg) ( ( ( _reg ) >> 14 ) & 0x7U ) |
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#define | AARCH64_ESR_EL1_SF 0x8000U |
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#define | AARCH64_ESR_EL1_OPC1_1(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ESR_EL1_OPC1_SHIFT_1 16 |
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#define | AARCH64_ESR_EL1_OPC1_MASK_1 0xf0000U |
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#define | AARCH64_ESR_EL1_OPC1_GET_1(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_ESR_EL1_SRT(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ESR_EL1_SRT_SHIFT 16 |
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#define | AARCH64_ESR_EL1_SRT_MASK 0x1f0000U |
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#define | AARCH64_ESR_EL1_SRT_GET(_reg) ( ( ( _reg ) >> 16 ) & 0x1fU ) |
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#define | AARCH64_ESR_EL1_OP2(_val) ( ( _val ) << 17 ) |
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#define | AARCH64_ESR_EL1_OP2_SHIFT 17 |
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#define | AARCH64_ESR_EL1_OP2_MASK 0xe0000U |
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#define | AARCH64_ESR_EL1_OP2_GET(_reg) ( ( ( _reg ) >> 17 ) & 0x7U ) |
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#define | AARCH64_ESR_EL1_OPC2(_val) ( ( _val ) << 17 ) |
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#define | AARCH64_ESR_EL1_OPC2_SHIFT 17 |
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#define | AARCH64_ESR_EL1_OPC2_MASK 0xe0000U |
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#define | AARCH64_ESR_EL1_OPC2_GET(_reg) ( ( ( _reg ) >> 17 ) & 0x7U ) |
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#define | AARCH64_ESR_EL1_CCKNOWNPASS 0x80000U |
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#define | AARCH64_ESR_EL1_OP0(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ESR_EL1_OP0_SHIFT 20 |
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#define | AARCH64_ESR_EL1_OP0_MASK 0x300000U |
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#define | AARCH64_ESR_EL1_OP0_GET(_reg) ( ( ( _reg ) >> 20 ) & 0x3U ) |
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#define | AARCH64_ESR_EL1_COND(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ESR_EL1_COND_SHIFT 20 |
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#define | AARCH64_ESR_EL1_COND_MASK 0xf00000U |
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#define | AARCH64_ESR_EL1_COND_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_ESR_EL1_SSE 0x200000U |
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#define | AARCH64_ESR_EL1_SAS(_val) ( ( _val ) << 22 ) |
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#define | AARCH64_ESR_EL1_SAS_SHIFT 22 |
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#define | AARCH64_ESR_EL1_SAS_MASK 0xc00000U |
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#define | AARCH64_ESR_EL1_SAS_GET(_reg) ( ( ( _reg ) >> 22 ) & 0x3U ) |
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#define | AARCH64_ESR_EL1_TFV 0x800000U |
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#define | AARCH64_ESR_EL1_CV 0x1000000U |
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#define | AARCH64_ESR_EL1_IDS 0x1000000U |
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#define | AARCH64_ESR_EL1_ISV 0x1000000U |
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#define | AARCH64_ESR_EL1_IL 0x2000000U |
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#define | AARCH64_ESR_EL1_EC(_val) ( ( _val ) << 26 ) |
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#define | AARCH64_ESR_EL1_EC_SHIFT 26 |
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#define | AARCH64_ESR_EL1_EC_MASK 0xfc000000U |
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#define | AARCH64_ESR_EL1_EC_GET(_reg) ( ( ( _reg ) >> 26 ) & 0x3fU ) |
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#define | AARCH64_ESR_EL2_DIRECTION 0x1U |
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#define | AARCH64_ESR_EL2_ERETA 0x1U |
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#define | AARCH64_ESR_EL2_IOF 0x1U |
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#define | AARCH64_ESR_EL2_TI 0x1U |
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#define | AARCH64_ESR_EL2_BTYPE(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ESR_EL2_BTYPE_SHIFT 0 |
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#define | AARCH64_ESR_EL2_BTYPE_MASK 0x3U |
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#define | AARCH64_ESR_EL2_BTYPE_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3U ) |
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#define | AARCH64_ESR_EL2_DFSC(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ESR_EL2_DFSC_SHIFT 0 |
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#define | AARCH64_ESR_EL2_DFSC_MASK 0x3fU |
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#define | AARCH64_ESR_EL2_DFSC_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3fU ) |
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#define | AARCH64_ESR_EL2_IFSC(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ESR_EL2_IFSC_SHIFT 0 |
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#define | AARCH64_ESR_EL2_IFSC_MASK 0x3fU |
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#define | AARCH64_ESR_EL2_IFSC_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3fU ) |
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#define | AARCH64_ESR_EL2_COMMENT(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ESR_EL2_COMMENT_SHIFT 0 |
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#define | AARCH64_ESR_EL2_COMMENT_MASK 0xffffU |
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#define | AARCH64_ESR_EL2_COMMENT_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffU ) |
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#define | AARCH64_ESR_EL2_IMM16(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ESR_EL2_IMM16_SHIFT 0 |
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#define | AARCH64_ESR_EL2_IMM16_MASK 0xffffU |
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#define | AARCH64_ESR_EL2_IMM16_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffU ) |
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#define | AARCH64_ESR_EL2_ISS(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ESR_EL2_ISS_SHIFT 0 |
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#define | AARCH64_ESR_EL2_ISS_MASK 0x1ffffffU |
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#define | AARCH64_ESR_EL2_ISS_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x1ffffffU ) |
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#define | AARCH64_ESR_EL2_DZF 0x2U |
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#define | AARCH64_ESR_EL2_ERET 0x2U |
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#define | AARCH64_ESR_EL2_AM(_val) ( ( _val ) << 1 ) |
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#define | AARCH64_ESR_EL2_AM_SHIFT 1 |
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#define | AARCH64_ESR_EL2_AM_MASK 0xeU |
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#define | AARCH64_ESR_EL2_AM_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x7U ) |
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#define | AARCH64_ESR_EL2_CRM(_val) ( ( _val ) << 1 ) |
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#define | AARCH64_ESR_EL2_CRM_SHIFT 1 |
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#define | AARCH64_ESR_EL2_CRM_MASK 0x1eU |
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#define | AARCH64_ESR_EL2_CRM_GET(_reg) ( ( ( _reg ) >> 1 ) & 0xfU ) |
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#define | AARCH64_ESR_EL2_OFF 0x4U |
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#define | AARCH64_ESR_EL2_UFF 0x8U |
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#define | AARCH64_ESR_EL2_IXF 0x10U |
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#define | AARCH64_ESR_EL2_OFFSET 0x10U |
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#define | AARCH64_ESR_EL2_RN(_val) ( ( _val ) << 5 ) |
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#define | AARCH64_ESR_EL2_RN_SHIFT 5 |
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#define | AARCH64_ESR_EL2_RN_MASK 0x3e0U |
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#define | AARCH64_ESR_EL2_RN_GET(_reg) ( ( ( _reg ) >> 5 ) & 0x1fU ) |
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#define | AARCH64_ESR_EL2_RT(_val) ( ( _val ) << 5 ) |
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#define | AARCH64_ESR_EL2_RT_SHIFT 5 |
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#define | AARCH64_ESR_EL2_RT_MASK 0x3e0U |
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#define | AARCH64_ESR_EL2_RT_GET(_reg) ( ( ( _reg ) >> 5 ) & 0x1fU ) |
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#define | AARCH64_ESR_EL2_EX 0x40U |
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#define | AARCH64_ESR_EL2_WNR 0x40U |
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#define | AARCH64_ESR_EL2_IDF 0x80U |
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#define | AARCH64_ESR_EL2_S1PTW 0x80U |
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#define | AARCH64_ESR_EL2_CM 0x100U |
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#define | AARCH64_ESR_EL2_VECITR(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ESR_EL2_VECITR_SHIFT 8 |
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#define | AARCH64_ESR_EL2_VECITR_MASK 0x700U |
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#define | AARCH64_ESR_EL2_VECITR_GET(_reg) ( ( ( _reg ) >> 8 ) & 0x7U ) |
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#define | AARCH64_ESR_EL2_EA 0x200U |
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#define | AARCH64_ESR_EL2_FNV 0x400U |
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#define | AARCH64_ESR_EL2_AET(_val) ( ( _val ) << 10 ) |
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#define | AARCH64_ESR_EL2_AET_SHIFT 10 |
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#define | AARCH64_ESR_EL2_AET_MASK 0x1c00U |
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#define | AARCH64_ESR_EL2_AET_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x7U ) |
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#define | AARCH64_ESR_EL2_CRN(_val) ( ( _val ) << 10 ) |
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#define | AARCH64_ESR_EL2_CRN_SHIFT 10 |
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#define | AARCH64_ESR_EL2_CRN_MASK 0x3c00U |
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#define | AARCH64_ESR_EL2_CRN_GET(_reg) ( ( ( _reg ) >> 10 ) & 0xfU ) |
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#define | AARCH64_ESR_EL2_RT2(_val) ( ( _val ) << 10 ) |
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#define | AARCH64_ESR_EL2_RT2_SHIFT 10 |
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#define | AARCH64_ESR_EL2_RT2_MASK 0x7c00U |
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#define | AARCH64_ESR_EL2_RT2_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x1fU ) |
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#define | AARCH64_ESR_EL2_SET(_val) ( ( _val ) << 11 ) |
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#define | AARCH64_ESR_EL2_SET_SHIFT 11 |
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#define | AARCH64_ESR_EL2_SET_MASK 0x1800U |
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#define | AARCH64_ESR_EL2_SET_GET(_reg) ( ( ( _reg ) >> 11 ) & 0x3U ) |
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#define | AARCH64_ESR_EL2_IMM8(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ESR_EL2_IMM8_SHIFT 12 |
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#define | AARCH64_ESR_EL2_IMM8_MASK 0xff000U |
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#define | AARCH64_ESR_EL2_IMM8_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xffU ) |
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#define | AARCH64_ESR_EL2_IESB 0x2000U |
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#define | AARCH64_ESR_EL2_VNCR 0x2000U |
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#define | AARCH64_ESR_EL2_AR 0x4000U |
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#define | AARCH64_ESR_EL2_OP1(_val) ( ( _val ) << 14 ) |
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#define | AARCH64_ESR_EL2_OP1_SHIFT 14 |
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#define | AARCH64_ESR_EL2_OP1_MASK 0x1c000U |
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#define | AARCH64_ESR_EL2_OP1_GET(_reg) ( ( ( _reg ) >> 14 ) & 0x7U ) |
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#define | AARCH64_ESR_EL2_OPC1_0(_val) ( ( _val ) << 14 ) |
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#define | AARCH64_ESR_EL2_OPC1_SHIFT_0 14 |
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#define | AARCH64_ESR_EL2_OPC1_MASK_0 0x1c000U |
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#define | AARCH64_ESR_EL2_OPC1_GET_0(_reg) ( ( ( _reg ) >> 14 ) & 0x7U ) |
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#define | AARCH64_ESR_EL2_SF 0x8000U |
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#define | AARCH64_ESR_EL2_OPC1_1(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ESR_EL2_OPC1_SHIFT_1 16 |
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#define | AARCH64_ESR_EL2_OPC1_MASK_1 0xf0000U |
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#define | AARCH64_ESR_EL2_OPC1_GET_1(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_ESR_EL2_SRT(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ESR_EL2_SRT_SHIFT 16 |
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#define | AARCH64_ESR_EL2_SRT_MASK 0x1f0000U |
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#define | AARCH64_ESR_EL2_SRT_GET(_reg) ( ( ( _reg ) >> 16 ) & 0x1fU ) |
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#define | AARCH64_ESR_EL2_OP2(_val) ( ( _val ) << 17 ) |
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#define | AARCH64_ESR_EL2_OP2_SHIFT 17 |
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#define | AARCH64_ESR_EL2_OP2_MASK 0xe0000U |
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#define | AARCH64_ESR_EL2_OP2_GET(_reg) ( ( ( _reg ) >> 17 ) & 0x7U ) |
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#define | AARCH64_ESR_EL2_OPC2(_val) ( ( _val ) << 17 ) |
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#define | AARCH64_ESR_EL2_OPC2_SHIFT 17 |
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#define | AARCH64_ESR_EL2_OPC2_MASK 0xe0000U |
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#define | AARCH64_ESR_EL2_OPC2_GET(_reg) ( ( ( _reg ) >> 17 ) & 0x7U ) |
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#define | AARCH64_ESR_EL2_CCKNOWNPASS 0x80000U |
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#define | AARCH64_ESR_EL2_OP0(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ESR_EL2_OP0_SHIFT 20 |
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#define | AARCH64_ESR_EL2_OP0_MASK 0x300000U |
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#define | AARCH64_ESR_EL2_OP0_GET(_reg) ( ( ( _reg ) >> 20 ) & 0x3U ) |
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#define | AARCH64_ESR_EL2_COND(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ESR_EL2_COND_SHIFT 20 |
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#define | AARCH64_ESR_EL2_COND_MASK 0xf00000U |
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#define | AARCH64_ESR_EL2_COND_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_ESR_EL2_SSE 0x200000U |
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#define | AARCH64_ESR_EL2_SAS(_val) ( ( _val ) << 22 ) |
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#define | AARCH64_ESR_EL2_SAS_SHIFT 22 |
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#define | AARCH64_ESR_EL2_SAS_MASK 0xc00000U |
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#define | AARCH64_ESR_EL2_SAS_GET(_reg) ( ( ( _reg ) >> 22 ) & 0x3U ) |
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#define | AARCH64_ESR_EL2_TFV 0x800000U |
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#define | AARCH64_ESR_EL2_CV 0x1000000U |
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#define | AARCH64_ESR_EL2_IDS 0x1000000U |
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#define | AARCH64_ESR_EL2_ISV 0x1000000U |
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#define | AARCH64_ESR_EL2_IL 0x2000000U |
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#define | AARCH64_ESR_EL2_EC(_val) ( ( _val ) << 26 ) |
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#define | AARCH64_ESR_EL2_EC_SHIFT 26 |
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#define | AARCH64_ESR_EL2_EC_MASK 0xfc000000U |
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#define | AARCH64_ESR_EL2_EC_GET(_reg) ( ( ( _reg ) >> 26 ) & 0x3fU ) |
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#define | AARCH64_ESR_EL3_DIRECTION 0x1U |
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#define | AARCH64_ESR_EL3_ERETA 0x1U |
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#define | AARCH64_ESR_EL3_IOF 0x1U |
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#define | AARCH64_ESR_EL3_TI 0x1U |
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#define | AARCH64_ESR_EL3_BTYPE(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ESR_EL3_BTYPE_SHIFT 0 |
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#define | AARCH64_ESR_EL3_BTYPE_MASK 0x3U |
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#define | AARCH64_ESR_EL3_BTYPE_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3U ) |
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#define | AARCH64_ESR_EL3_DFSC(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ESR_EL3_DFSC_SHIFT 0 |
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#define | AARCH64_ESR_EL3_DFSC_MASK 0x3fU |
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#define | AARCH64_ESR_EL3_DFSC_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3fU ) |
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#define | AARCH64_ESR_EL3_IFSC(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ESR_EL3_IFSC_SHIFT 0 |
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#define | AARCH64_ESR_EL3_IFSC_MASK 0x3fU |
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#define | AARCH64_ESR_EL3_IFSC_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3fU ) |
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#define | AARCH64_ESR_EL3_COMMENT(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ESR_EL3_COMMENT_SHIFT 0 |
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#define | AARCH64_ESR_EL3_COMMENT_MASK 0xffffU |
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#define | AARCH64_ESR_EL3_COMMENT_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffU ) |
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#define | AARCH64_ESR_EL3_IMM16(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ESR_EL3_IMM16_SHIFT 0 |
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#define | AARCH64_ESR_EL3_IMM16_MASK 0xffffU |
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#define | AARCH64_ESR_EL3_IMM16_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffU ) |
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#define | AARCH64_ESR_EL3_ISS(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ESR_EL3_ISS_SHIFT 0 |
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#define | AARCH64_ESR_EL3_ISS_MASK 0x1ffffffU |
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#define | AARCH64_ESR_EL3_ISS_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x1ffffffU ) |
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#define | AARCH64_ESR_EL3_DZF 0x2U |
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#define | AARCH64_ESR_EL3_ERET 0x2U |
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#define | AARCH64_ESR_EL3_AM(_val) ( ( _val ) << 1 ) |
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#define | AARCH64_ESR_EL3_AM_SHIFT 1 |
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#define | AARCH64_ESR_EL3_AM_MASK 0xeU |
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#define | AARCH64_ESR_EL3_AM_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x7U ) |
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#define | AARCH64_ESR_EL3_CRM(_val) ( ( _val ) << 1 ) |
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#define | AARCH64_ESR_EL3_CRM_SHIFT 1 |
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#define | AARCH64_ESR_EL3_CRM_MASK 0x1eU |
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#define | AARCH64_ESR_EL3_CRM_GET(_reg) ( ( ( _reg ) >> 1 ) & 0xfU ) |
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#define | AARCH64_ESR_EL3_OFF 0x4U |
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#define | AARCH64_ESR_EL3_UFF 0x8U |
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#define | AARCH64_ESR_EL3_IXF 0x10U |
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#define | AARCH64_ESR_EL3_OFFSET 0x10U |
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#define | AARCH64_ESR_EL3_RN(_val) ( ( _val ) << 5 ) |
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#define | AARCH64_ESR_EL3_RN_SHIFT 5 |
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#define | AARCH64_ESR_EL3_RN_MASK 0x3e0U |
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#define | AARCH64_ESR_EL3_RN_GET(_reg) ( ( ( _reg ) >> 5 ) & 0x1fU ) |
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#define | AARCH64_ESR_EL3_RT(_val) ( ( _val ) << 5 ) |
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#define | AARCH64_ESR_EL3_RT_SHIFT 5 |
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#define | AARCH64_ESR_EL3_RT_MASK 0x3e0U |
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#define | AARCH64_ESR_EL3_RT_GET(_reg) ( ( ( _reg ) >> 5 ) & 0x1fU ) |
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#define | AARCH64_ESR_EL3_EX 0x40U |
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#define | AARCH64_ESR_EL3_WNR 0x40U |
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#define | AARCH64_ESR_EL3_IDF 0x80U |
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#define | AARCH64_ESR_EL3_S1PTW 0x80U |
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#define | AARCH64_ESR_EL3_CM 0x100U |
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#define | AARCH64_ESR_EL3_VECITR(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ESR_EL3_VECITR_SHIFT 8 |
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#define | AARCH64_ESR_EL3_VECITR_MASK 0x700U |
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#define | AARCH64_ESR_EL3_VECITR_GET(_reg) ( ( ( _reg ) >> 8 ) & 0x7U ) |
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#define | AARCH64_ESR_EL3_EA 0x200U |
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#define | AARCH64_ESR_EL3_FNV 0x400U |
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#define | AARCH64_ESR_EL3_AET(_val) ( ( _val ) << 10 ) |
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#define | AARCH64_ESR_EL3_AET_SHIFT 10 |
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#define | AARCH64_ESR_EL3_AET_MASK 0x1c00U |
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#define | AARCH64_ESR_EL3_AET_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x7U ) |
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#define | AARCH64_ESR_EL3_CRN(_val) ( ( _val ) << 10 ) |
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#define | AARCH64_ESR_EL3_CRN_SHIFT 10 |
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#define | AARCH64_ESR_EL3_CRN_MASK 0x3c00U |
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#define | AARCH64_ESR_EL3_CRN_GET(_reg) ( ( ( _reg ) >> 10 ) & 0xfU ) |
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#define | AARCH64_ESR_EL3_RT2(_val) ( ( _val ) << 10 ) |
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#define | AARCH64_ESR_EL3_RT2_SHIFT 10 |
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#define | AARCH64_ESR_EL3_RT2_MASK 0x7c00U |
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#define | AARCH64_ESR_EL3_RT2_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x1fU ) |
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#define | AARCH64_ESR_EL3_SET(_val) ( ( _val ) << 11 ) |
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#define | AARCH64_ESR_EL3_SET_SHIFT 11 |
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#define | AARCH64_ESR_EL3_SET_MASK 0x1800U |
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#define | AARCH64_ESR_EL3_SET_GET(_reg) ( ( ( _reg ) >> 11 ) & 0x3U ) |
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#define | AARCH64_ESR_EL3_IMM8(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ESR_EL3_IMM8_SHIFT 12 |
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#define | AARCH64_ESR_EL3_IMM8_MASK 0xff000U |
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#define | AARCH64_ESR_EL3_IMM8_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xffU ) |
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#define | AARCH64_ESR_EL3_IESB 0x2000U |
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#define | AARCH64_ESR_EL3_VNCR 0x2000U |
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#define | AARCH64_ESR_EL3_AR 0x4000U |
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#define | AARCH64_ESR_EL3_OP1(_val) ( ( _val ) << 14 ) |
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#define | AARCH64_ESR_EL3_OP1_SHIFT 14 |
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#define | AARCH64_ESR_EL3_OP1_MASK 0x1c000U |
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#define | AARCH64_ESR_EL3_OP1_GET(_reg) ( ( ( _reg ) >> 14 ) & 0x7U ) |
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#define | AARCH64_ESR_EL3_OPC1_0(_val) ( ( _val ) << 14 ) |
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#define | AARCH64_ESR_EL3_OPC1_SHIFT_0 14 |
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#define | AARCH64_ESR_EL3_OPC1_MASK_0 0x1c000U |
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#define | AARCH64_ESR_EL3_OPC1_GET_0(_reg) ( ( ( _reg ) >> 14 ) & 0x7U ) |
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#define | AARCH64_ESR_EL3_SF 0x8000U |
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#define | AARCH64_ESR_EL3_OPC1_1(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ESR_EL3_OPC1_SHIFT_1 16 |
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#define | AARCH64_ESR_EL3_OPC1_MASK_1 0xf0000U |
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#define | AARCH64_ESR_EL3_OPC1_GET_1(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_ESR_EL3_SRT(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ESR_EL3_SRT_SHIFT 16 |
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#define | AARCH64_ESR_EL3_SRT_MASK 0x1f0000U |
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#define | AARCH64_ESR_EL3_SRT_GET(_reg) ( ( ( _reg ) >> 16 ) & 0x1fU ) |
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#define | AARCH64_ESR_EL3_OP2(_val) ( ( _val ) << 17 ) |
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#define | AARCH64_ESR_EL3_OP2_SHIFT 17 |
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#define | AARCH64_ESR_EL3_OP2_MASK 0xe0000U |
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#define | AARCH64_ESR_EL3_OP2_GET(_reg) ( ( ( _reg ) >> 17 ) & 0x7U ) |
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#define | AARCH64_ESR_EL3_OPC2(_val) ( ( _val ) << 17 ) |
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#define | AARCH64_ESR_EL3_OPC2_SHIFT 17 |
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#define | AARCH64_ESR_EL3_OPC2_MASK 0xe0000U |
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#define | AARCH64_ESR_EL3_OPC2_GET(_reg) ( ( ( _reg ) >> 17 ) & 0x7U ) |
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#define | AARCH64_ESR_EL3_CCKNOWNPASS 0x80000U |
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#define | AARCH64_ESR_EL3_OP0(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ESR_EL3_OP0_SHIFT 20 |
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#define | AARCH64_ESR_EL3_OP0_MASK 0x300000U |
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#define | AARCH64_ESR_EL3_OP0_GET(_reg) ( ( ( _reg ) >> 20 ) & 0x3U ) |
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#define | AARCH64_ESR_EL3_COND(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ESR_EL3_COND_SHIFT 20 |
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#define | AARCH64_ESR_EL3_COND_MASK 0xf00000U |
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#define | AARCH64_ESR_EL3_COND_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_ESR_EL3_SSE 0x200000U |
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#define | AARCH64_ESR_EL3_SAS(_val) ( ( _val ) << 22 ) |
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#define | AARCH64_ESR_EL3_SAS_SHIFT 22 |
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#define | AARCH64_ESR_EL3_SAS_MASK 0xc00000U |
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#define | AARCH64_ESR_EL3_SAS_GET(_reg) ( ( ( _reg ) >> 22 ) & 0x3U ) |
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#define | AARCH64_ESR_EL3_TFV 0x800000U |
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#define | AARCH64_ESR_EL3_CV 0x1000000U |
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#define | AARCH64_ESR_EL3_IDS 0x1000000U |
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#define | AARCH64_ESR_EL3_ISV 0x1000000U |
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#define | AARCH64_ESR_EL3_IL 0x2000000U |
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#define | AARCH64_ESR_EL3_EC(_val) ( ( _val ) << 26 ) |
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#define | AARCH64_ESR_EL3_EC_SHIFT 26 |
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#define | AARCH64_ESR_EL3_EC_MASK 0xfc000000U |
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#define | AARCH64_ESR_EL3_EC_GET(_reg) ( ( ( _reg ) >> 26 ) & 0x3fU ) |
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#define | AARCH64_FPEXC32_EL2_IOF 0x1U |
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#define | AARCH64_FPEXC32_EL2_DZF 0x2U |
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#define | AARCH64_FPEXC32_EL2_OFF 0x4U |
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#define | AARCH64_FPEXC32_EL2_UFF 0x8U |
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#define | AARCH64_FPEXC32_EL2_IXF 0x10U |
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#define | AARCH64_FPEXC32_EL2_IDF 0x80U |
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#define | AARCH64_FPEXC32_EL2_VECITR(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_FPEXC32_EL2_VECITR_SHIFT 8 |
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#define | AARCH64_FPEXC32_EL2_VECITR_MASK 0x700U |
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#define | AARCH64_FPEXC32_EL2_VECITR_GET(_reg) ( ( ( _reg ) >> 8 ) & 0x7U ) |
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#define | AARCH64_FPEXC32_EL2_TFV 0x4000000U |
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#define | AARCH64_FPEXC32_EL2_VV 0x8000000U |
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#define | AARCH64_FPEXC32_EL2_FP2V 0x10000000U |
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#define | AARCH64_FPEXC32_EL2_DEX 0x20000000U |
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#define | AARCH64_FPEXC32_EL2_EN 0x40000000U |
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#define | AARCH64_FPEXC32_EL2_EX 0x80000000U |
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#define | AARCH64_GCR_EL1_EXCLUDE(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_GCR_EL1_EXCLUDE_SHIFT 0 |
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#define | AARCH64_GCR_EL1_EXCLUDE_MASK 0xffffU |
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#define | AARCH64_GCR_EL1_EXCLUDE_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffU ) |
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#define | AARCH64_GCR_EL1_RRND 0x10000U |
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#define | AARCH64_GMID_EL1_BS(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_GMID_EL1_BS_SHIFT 0 |
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#define | AARCH64_GMID_EL1_BS_MASK 0xfU |
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#define | AARCH64_GMID_EL1_BS_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_HAFGRTR_EL2_AMCNTEN0 0x1U |
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#define | AARCH64_HAFGRTR_EL2_AMCNTEN1 0x20000U |
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#define | AARCH64_HAFGRTR_EL2_AMEVCNTR10_EL0 0x40000U |
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#define | AARCH64_HAFGRTR_EL2_AMEVTYPER10_EL0 0x80000U |
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#define | AARCH64_HAFGRTR_EL2_AMEVCNTR11_EL0 0x100000U |
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#define | AARCH64_HAFGRTR_EL2_AMEVTYPER11_EL0 0x200000U |
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#define | AARCH64_HAFGRTR_EL2_AMEVCNTR12_EL0 0x400000U |
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#define | AARCH64_HAFGRTR_EL2_AMEVTYPER12_EL0 0x800000U |
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#define | AARCH64_HAFGRTR_EL2_AMEVCNTR13_EL0 0x1000000U |
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#define | AARCH64_HAFGRTR_EL2_AMEVTYPER13_EL0 0x2000000U |
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#define | AARCH64_HAFGRTR_EL2_AMEVCNTR14_EL0 0x4000000U |
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#define | AARCH64_HAFGRTR_EL2_AMEVTYPER14_EL0 0x8000000U |
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#define | AARCH64_HAFGRTR_EL2_AMEVCNTR15_EL0 0x10000000U |
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#define | AARCH64_HAFGRTR_EL2_AMEVTYPER15_EL0 0x20000000U |
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#define | AARCH64_HAFGRTR_EL2_AMEVCNTR16_EL0 0x40000000U |
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#define | AARCH64_HAFGRTR_EL2_AMEVTYPER16_EL0 0x80000000U |
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#define | AARCH64_HAFGRTR_EL2_AMEVCNTR17_EL0 0x100000000ULL |
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#define | AARCH64_HAFGRTR_EL2_AMEVTYPER17_EL0 0x200000000ULL |
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#define | AARCH64_HAFGRTR_EL2_AMEVCNTR18_EL0 0x400000000ULL |
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#define | AARCH64_HAFGRTR_EL2_AMEVTYPER18_EL0 0x800000000ULL |
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#define | AARCH64_HAFGRTR_EL2_AMEVCNTR19_EL0 0x1000000000ULL |
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#define | AARCH64_HAFGRTR_EL2_AMEVTYPER19_EL0 0x2000000000ULL |
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#define | AARCH64_HAFGRTR_EL2_AMEVCNTR110_EL0 0x4000000000ULL |
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#define | AARCH64_HAFGRTR_EL2_AMEVTYPER110_EL0 0x8000000000ULL |
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#define | AARCH64_HAFGRTR_EL2_AMEVCNTR111_EL0 0x10000000000ULL |
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#define | AARCH64_HAFGRTR_EL2_AMEVTYPER111_EL0 0x20000000000ULL |
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#define | AARCH64_HAFGRTR_EL2_AMEVCNTR112_EL0 0x40000000000ULL |
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#define | AARCH64_HAFGRTR_EL2_AMEVTYPER112_EL0 0x80000000000ULL |
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#define | AARCH64_HAFGRTR_EL2_AMEVCNTR113_EL0 0x100000000000ULL |
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#define | AARCH64_HAFGRTR_EL2_AMEVTYPER113_EL0 0x200000000000ULL |
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#define | AARCH64_HAFGRTR_EL2_AMEVCNTR114_EL0 0x400000000000ULL |
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#define | AARCH64_HAFGRTR_EL2_AMEVTYPER114_EL0 0x800000000000ULL |
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#define | AARCH64_HAFGRTR_EL2_AMEVCNTR115_EL0 0x1000000000000ULL |
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#define | AARCH64_HAFGRTR_EL2_AMEVTYPER115_EL0 0x2000000000000ULL |
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#define | AARCH64_HCR_EL2_VM 0x1U |
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#define | AARCH64_HCR_EL2_SWIO 0x2U |
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#define | AARCH64_HCR_EL2_PTW 0x4U |
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#define | AARCH64_HCR_EL2_FMO 0x8U |
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#define | AARCH64_HCR_EL2_IMO 0x10U |
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#define | AARCH64_HCR_EL2_AMO 0x20U |
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#define | AARCH64_HCR_EL2_VF 0x40U |
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#define | AARCH64_HCR_EL2_VI 0x80U |
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#define | AARCH64_HCR_EL2_VSE 0x100U |
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#define | AARCH64_HCR_EL2_FB 0x200U |
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#define | AARCH64_HCR_EL2_BSU(_val) ( ( _val ) << 10 ) |
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#define | AARCH64_HCR_EL2_BSU_SHIFT 10 |
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#define | AARCH64_HCR_EL2_BSU_MASK 0xc00U |
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#define | AARCH64_HCR_EL2_BSU_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x3U ) |
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#define | AARCH64_HCR_EL2_DC 0x1000U |
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#define | AARCH64_HCR_EL2_TWI 0x2000U |
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#define | AARCH64_HCR_EL2_TWE 0x4000U |
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#define | AARCH64_HCR_EL2_TID0 0x8000U |
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#define | AARCH64_HCR_EL2_TID1 0x10000U |
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#define | AARCH64_HCR_EL2_TID2 0x20000U |
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#define | AARCH64_HCR_EL2_TID3 0x40000U |
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#define | AARCH64_HCR_EL2_TSC 0x80000U |
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#define | AARCH64_HCR_EL2_TIDCP 0x100000U |
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#define | AARCH64_HCR_EL2_TACR 0x200000U |
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#define | AARCH64_HCR_EL2_TSW 0x400000U |
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#define | AARCH64_HCR_EL2_TPCP 0x800000U |
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#define | AARCH64_HCR_EL2_TPU 0x1000000U |
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#define | AARCH64_HCR_EL2_TTLB 0x2000000U |
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#define | AARCH64_HCR_EL2_TVM 0x4000000U |
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#define | AARCH64_HCR_EL2_TGE 0x8000000U |
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#define | AARCH64_HCR_EL2_TDZ 0x10000000U |
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#define | AARCH64_HCR_EL2_HCD 0x20000000U |
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#define | AARCH64_HCR_EL2_TRVM 0x40000000U |
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#define | AARCH64_HCR_EL2_RW 0x80000000U |
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#define | AARCH64_HCR_EL2_CD 0x100000000ULL |
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#define | AARCH64_HCR_EL2_ID 0x200000000ULL |
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#define | AARCH64_HCR_EL2_E2H 0x400000000ULL |
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#define | AARCH64_HCR_EL2_TLOR 0x800000000ULL |
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#define | AARCH64_HCR_EL2_TERR 0x1000000000ULL |
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#define | AARCH64_HCR_EL2_TEA 0x2000000000ULL |
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#define | AARCH64_HCR_EL2_MIOCNCE 0x4000000000ULL |
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#define | AARCH64_HCR_EL2_APK 0x10000000000ULL |
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#define | AARCH64_HCR_EL2_API 0x20000000000ULL |
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#define | AARCH64_HCR_EL2_NV 0x40000000000ULL |
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#define | AARCH64_HCR_EL2_NV1 0x80000000000ULL |
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#define | AARCH64_HCR_EL2_AT 0x100000000000ULL |
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#define | AARCH64_HCR_EL2_NV2 0x200000000000ULL |
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#define | AARCH64_HCR_EL2_FWB 0x400000000000ULL |
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#define | AARCH64_HCR_EL2_FIEN 0x800000000000ULL |
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#define | AARCH64_HCR_EL2_TID4 0x2000000000000ULL |
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#define | AARCH64_HCR_EL2_TICAB 0x4000000000000ULL |
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#define | AARCH64_HCR_EL2_AMVOFFEN 0x8000000000000ULL |
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#define | AARCH64_HCR_EL2_TOCU 0x10000000000000ULL |
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#define | AARCH64_HCR_EL2_ENSCXT 0x20000000000000ULL |
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#define | AARCH64_HCR_EL2_TTLBIS 0x40000000000000ULL |
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#define | AARCH64_HCR_EL2_TTLBOS 0x80000000000000ULL |
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#define | AARCH64_HCR_EL2_ATA 0x100000000000000ULL |
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#define | AARCH64_HCR_EL2_DCT 0x200000000000000ULL |
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#define | AARCH64_HCR_EL2_TID5 0x400000000000000ULL |
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#define | AARCH64_HCR_EL2_TWEDEN 0x800000000000000ULL |
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#define | AARCH64_HCR_EL2_TWEDEL(_val) ( ( _val ) << 60 ) |
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#define | AARCH64_HCR_EL2_TWEDEL_SHIFT 60 |
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#define | AARCH64_HCR_EL2_TWEDEL_MASK 0xf000000000000000ULL |
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#define | AARCH64_HCR_EL2_TWEDEL_GET(_reg) ( ( ( _reg ) >> 60 ) & 0xfULL ) |
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#define | AARCH64_HDFGRTR_EL2_DBGBCRN_EL1 0x1U |
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#define | AARCH64_HDFGRTR_EL2_DBGBVRN_EL1 0x2U |
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#define | AARCH64_HDFGRTR_EL2_DBGWCRN_EL1 0x4U |
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#define | AARCH64_HDFGRTR_EL2_DBGWVRN_EL1 0x8U |
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#define | AARCH64_HDFGRTR_EL2_MDSCR_EL1 0x10U |
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#define | AARCH64_HDFGRTR_EL2_DBGCLAIM 0x20U |
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#define | AARCH64_HDFGRTR_EL2_DBGAUTHSTATUS_EL1 0x40U |
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#define | AARCH64_HDFGRTR_EL2_DBGPRCR_EL1 0x80U |
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#define | AARCH64_HDFGRTR_EL2_OSLSR_EL1 0x200U |
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#define | AARCH64_HDFGRTR_EL2_OSECCR_EL1 0x400U |
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#define | AARCH64_HDFGRTR_EL2_OSDLR_EL1 0x800U |
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#define | AARCH64_HDFGRTR_EL2_PMEVCNTRN_EL0 0x1000U |
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#define | AARCH64_HDFGRTR_EL2_PMEVTYPERN_EL0 0x2000U |
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#define | AARCH64_HDFGRTR_EL2_PMCCFILTR_EL0 0x4000U |
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#define | AARCH64_HDFGRTR_EL2_PMCCNTR_EL0 0x8000U |
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#define | AARCH64_HDFGRTR_EL2_PMCNTEN 0x10000U |
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#define | AARCH64_HDFGRTR_EL2_PMINTEN 0x20000U |
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#define | AARCH64_HDFGRTR_EL2_PMOVS 0x40000U |
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#define | AARCH64_HDFGRTR_EL2_PMSELR_EL0 0x80000U |
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#define | AARCH64_HDFGRTR_EL2_PMMIR_EL1 0x400000U |
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#define | AARCH64_HDFGRTR_EL2_PMBLIMITR_EL1 0x800000U |
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#define | AARCH64_HDFGRTR_EL2_PMBPTR_EL1 0x1000000U |
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#define | AARCH64_HDFGRTR_EL2_PMBSR_EL1 0x2000000U |
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#define | AARCH64_HDFGRTR_EL2_PMSCR_EL1 0x4000000U |
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#define | AARCH64_HDFGRTR_EL2_PMSEVFR_EL1 0x8000000U |
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#define | AARCH64_HDFGRTR_EL2_PMSFCR_EL1 0x10000000U |
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#define | AARCH64_HDFGRTR_EL2_PMSICR_EL1 0x20000000U |
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#define | AARCH64_HDFGRTR_EL2_PMSIDR_EL1 0x40000000U |
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#define | AARCH64_HDFGRTR_EL2_PMSIRR_EL1 0x80000000U |
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#define | AARCH64_HDFGRTR_EL2_PMSLATFR_EL1 0x100000000ULL |
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#define | AARCH64_HDFGRTR_EL2_TRC 0x200000000ULL |
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#define | AARCH64_HDFGRTR_EL2_TRCAUTHSTATUS 0x400000000ULL |
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#define | AARCH64_HDFGRTR_EL2_TRCAUXCTLR 0x800000000ULL |
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#define | AARCH64_HDFGRTR_EL2_TRCCLAIM 0x1000000000ULL |
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#define | AARCH64_HDFGRTR_EL2_TRCCNTVRN 0x2000000000ULL |
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#define | AARCH64_HDFGRTR_EL2_TRCID 0x10000000000ULL |
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#define | AARCH64_HDFGRTR_EL2_TRCIMSPECN 0x20000000000ULL |
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#define | AARCH64_HDFGRTR_EL2_TRCOSLSR 0x80000000000ULL |
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#define | AARCH64_HDFGRTR_EL2_TRCPRGCTLR 0x100000000000ULL |
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#define | AARCH64_HDFGRTR_EL2_TRCSEQSTR 0x200000000000ULL |
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#define | AARCH64_HDFGRTR_EL2_TRCSSCSRN 0x400000000000ULL |
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#define | AARCH64_HDFGRTR_EL2_TRCSTATR 0x800000000000ULL |
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#define | AARCH64_HDFGRTR_EL2_TRCVICTLR 0x1000000000000ULL |
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#define | AARCH64_HDFGRTR_EL2_PMUSERENR_EL0 0x200000000000000ULL |
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#define | AARCH64_HDFGRTR_EL2_PMCEIDN_EL0 0x400000000000000ULL |
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#define | AARCH64_HDFGWTR_EL2_DBGBCRN_EL1 0x1U |
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#define | AARCH64_HDFGWTR_EL2_DBGBVRN_EL1 0x2U |
| |
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#define | AARCH64_HDFGWTR_EL2_DBGWCRN_EL1 0x4U |
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#define | AARCH64_HDFGWTR_EL2_DBGWVRN_EL1 0x8U |
| |
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#define | AARCH64_HDFGWTR_EL2_MDSCR_EL1 0x10U |
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#define | AARCH64_HDFGWTR_EL2_DBGCLAIM 0x20U |
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#define | AARCH64_HDFGWTR_EL2_DBGPRCR_EL1 0x80U |
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#define | AARCH64_HDFGWTR_EL2_OSLAR_EL1 0x100U |
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#define | AARCH64_HDFGWTR_EL2_OSECCR_EL1 0x400U |
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#define | AARCH64_HDFGWTR_EL2_OSDLR_EL1 0x800U |
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#define | AARCH64_HDFGWTR_EL2_PMEVCNTRN_EL0 0x1000U |
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#define | AARCH64_HDFGWTR_EL2_PMEVTYPERN_EL0 0x2000U |
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#define | AARCH64_HDFGWTR_EL2_PMCCFILTR_EL0 0x4000U |
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#define | AARCH64_HDFGWTR_EL2_PMCCNTR_EL0 0x8000U |
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#define | AARCH64_HDFGWTR_EL2_PMCNTEN 0x10000U |
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#define | AARCH64_HDFGWTR_EL2_PMINTEN 0x20000U |
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#define | AARCH64_HDFGWTR_EL2_PMOVS 0x40000U |
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#define | AARCH64_HDFGWTR_EL2_PMSELR_EL0 0x80000U |
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#define | AARCH64_HDFGWTR_EL2_PMSWINC_EL0 0x100000U |
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#define | AARCH64_HDFGWTR_EL2_PMCR_EL0 0x200000U |
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#define | AARCH64_HDFGWTR_EL2_PMBLIMITR_EL1 0x800000U |
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#define | AARCH64_HDFGWTR_EL2_PMBPTR_EL1 0x1000000U |
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#define | AARCH64_HDFGWTR_EL2_PMBSR_EL1 0x2000000U |
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#define | AARCH64_HDFGWTR_EL2_PMSCR_EL1 0x4000000U |
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#define | AARCH64_HDFGWTR_EL2_PMSEVFR_EL1 0x8000000U |
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#define | AARCH64_HDFGWTR_EL2_PMSFCR_EL1 0x10000000U |
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#define | AARCH64_HDFGWTR_EL2_PMSICR_EL1 0x20000000U |
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#define | AARCH64_HDFGWTR_EL2_PMSIRR_EL1 0x80000000U |
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#define | AARCH64_HDFGWTR_EL2_PMSLATFR_EL1 0x100000000ULL |
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#define | AARCH64_HDFGWTR_EL2_TRC 0x200000000ULL |
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#define | AARCH64_HDFGWTR_EL2_TRCAUXCTLR 0x800000000ULL |
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#define | AARCH64_HDFGWTR_EL2_TRCCLAIM 0x1000000000ULL |
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#define | AARCH64_HDFGWTR_EL2_TRCCNTVRN 0x2000000000ULL |
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#define | AARCH64_HDFGWTR_EL2_TRCIMSPECN 0x20000000000ULL |
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#define | AARCH64_HDFGWTR_EL2_TRCOSLAR 0x40000000000ULL |
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#define | AARCH64_HDFGWTR_EL2_TRCPRGCTLR 0x100000000000ULL |
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#define | AARCH64_HDFGWTR_EL2_TRCSEQSTR 0x200000000000ULL |
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#define | AARCH64_HDFGWTR_EL2_TRCSSCSRN 0x400000000000ULL |
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#define | AARCH64_HDFGWTR_EL2_TRCVICTLR 0x1000000000000ULL |
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#define | AARCH64_HDFGWTR_EL2_TRFCR_EL1 0x2000000000000ULL |
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#define | AARCH64_HDFGWTR_EL2_PMUSERENR_EL0 0x200000000000000ULL |
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#define | AARCH64_HFGITR_EL2_ICIALLUIS 0x1U |
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#define | AARCH64_HFGITR_EL2_ICIALLU 0x2U |
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#define | AARCH64_HFGITR_EL2_ICIVAU 0x4U |
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#define | AARCH64_HFGITR_EL2_DCIVAC 0x8U |
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#define | AARCH64_HFGITR_EL2_DCISW 0x10U |
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#define | AARCH64_HFGITR_EL2_DCCSW 0x20U |
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#define | AARCH64_HFGITR_EL2_DCCISW 0x40U |
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#define | AARCH64_HFGITR_EL2_DCCVAU 0x80U |
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#define | AARCH64_HFGITR_EL2_DCCVAP 0x100U |
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#define | AARCH64_HFGITR_EL2_DCCVADP 0x200U |
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#define | AARCH64_HFGITR_EL2_DCCIVAC 0x400U |
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#define | AARCH64_HFGITR_EL2_DCZVA 0x800U |
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#define | AARCH64_HFGITR_EL2_ATS1E1R 0x1000U |
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#define | AARCH64_HFGITR_EL2_ATS1E1W 0x2000U |
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#define | AARCH64_HFGITR_EL2_ATS1E0R 0x4000U |
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#define | AARCH64_HFGITR_EL2_ATS1E0W 0x8000U |
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#define | AARCH64_HFGITR_EL2_ATS1E1RP 0x10000U |
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#define | AARCH64_HFGITR_EL2_ATS1E1WP 0x20000U |
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#define | AARCH64_HFGITR_EL2_TLBIVMALLE1OS 0x40000U |
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#define | AARCH64_HFGITR_EL2_TLBIVAE1OS 0x80000U |
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#define | AARCH64_HFGITR_EL2_TLBIASIDE1OS 0x100000U |
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#define | AARCH64_HFGITR_EL2_TLBIVAAE1OS 0x200000U |
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#define | AARCH64_HFGITR_EL2_TLBIVALE1OS 0x400000U |
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#define | AARCH64_HFGITR_EL2_TLBIVAALE1OS 0x800000U |
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#define | AARCH64_HFGITR_EL2_TLBIRVAE1OS 0x1000000U |
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#define | AARCH64_HFGITR_EL2_TLBIRVAAE1OS 0x2000000U |
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#define | AARCH64_HFGITR_EL2_TLBIRVALE1OS 0x4000000U |
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#define | AARCH64_HFGITR_EL2_TLBIRVAALE1OS 0x8000000U |
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#define | AARCH64_HFGITR_EL2_TLBIVMALLE1IS 0x10000000U |
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#define | AARCH64_HFGITR_EL2_TLBIVAE1IS 0x20000000U |
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#define | AARCH64_HFGITR_EL2_TLBIASIDE1IS 0x40000000U |
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#define | AARCH64_HFGITR_EL2_TLBIVAAE1IS 0x80000000U |
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#define | AARCH64_HFGITR_EL2_TLBIVALE1IS 0x100000000ULL |
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#define | AARCH64_HFGITR_EL2_TLBIVAALE1IS 0x200000000ULL |
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#define | AARCH64_HFGITR_EL2_TLBIRVAE1IS 0x400000000ULL |
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#define | AARCH64_HFGITR_EL2_TLBIRVAAE1IS 0x800000000ULL |
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#define | AARCH64_HFGITR_EL2_TLBIRVALE1IS 0x1000000000ULL |
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#define | AARCH64_HFGITR_EL2_TLBIRVAALE1IS 0x2000000000ULL |
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#define | AARCH64_HFGITR_EL2_TLBIRVAE1 0x4000000000ULL |
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#define | AARCH64_HFGITR_EL2_TLBIRVAAE1 0x8000000000ULL |
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#define | AARCH64_HFGITR_EL2_TLBIRVALE1 0x10000000000ULL |
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#define | AARCH64_HFGITR_EL2_TLBIRVAALE1 0x20000000000ULL |
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#define | AARCH64_HFGITR_EL2_TLBIVMALLE1 0x40000000000ULL |
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#define | AARCH64_HFGITR_EL2_TLBIVAE1 0x80000000000ULL |
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#define | AARCH64_HFGITR_EL2_TLBIASIDE1 0x100000000000ULL |
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#define | AARCH64_HFGITR_EL2_TLBIVAAE1 0x200000000000ULL |
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#define | AARCH64_HFGITR_EL2_TLBIVALE1 0x400000000000ULL |
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#define | AARCH64_HFGITR_EL2_TLBIVAALE1 0x800000000000ULL |
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#define | AARCH64_HFGITR_EL2_CFPRCTX 0x1000000000000ULL |
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#define | AARCH64_HFGITR_EL2_DVPRCTX 0x2000000000000ULL |
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#define | AARCH64_HFGITR_EL2_CPPRCTX 0x4000000000000ULL |
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#define | AARCH64_HFGITR_EL2_ERET 0x8000000000000ULL |
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#define | AARCH64_HFGITR_EL2_SVC_EL0 0x10000000000000ULL |
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#define | AARCH64_HFGITR_EL2_SVC_EL1 0x20000000000000ULL |
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#define | AARCH64_HFGITR_EL2_DCCVAC 0x40000000000000ULL |
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#define | AARCH64_HFGRTR_EL2_AFSR0_EL1 0x1U |
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#define | AARCH64_HFGRTR_EL2_AFSR1_EL1 0x2U |
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#define | AARCH64_HFGRTR_EL2_AIDR_EL1 0x4U |
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#define | AARCH64_HFGRTR_EL2_AMAIR_EL1 0x8U |
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#define | AARCH64_HFGRTR_EL2_APDAKEY 0x10U |
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#define | AARCH64_HFGRTR_EL2_APDBKEY 0x20U |
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#define | AARCH64_HFGRTR_EL2_APGAKEY 0x40U |
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#define | AARCH64_HFGRTR_EL2_APIAKEY 0x80U |
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#define | AARCH64_HFGRTR_EL2_APIBKEY 0x100U |
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#define | AARCH64_HFGRTR_EL2_CCSIDR_EL1 0x200U |
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#define | AARCH64_HFGRTR_EL2_CLIDR_EL1 0x400U |
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#define | AARCH64_HFGRTR_EL2_CONTEXTIDR_EL1 0x800U |
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#define | AARCH64_HFGRTR_EL2_CPACR_EL1 0x1000U |
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#define | AARCH64_HFGRTR_EL2_CSSELR_EL1 0x2000U |
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#define | AARCH64_HFGRTR_EL2_CTR_EL0 0x4000U |
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#define | AARCH64_HFGRTR_EL2_DCZID_EL0 0x8000U |
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#define | AARCH64_HFGRTR_EL2_ESR_EL1 0x10000U |
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#define | AARCH64_HFGRTR_EL2_FAR_EL1 0x20000U |
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#define | AARCH64_HFGRTR_EL2_ISR_EL1 0x40000U |
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#define | AARCH64_HFGRTR_EL2_LORC_EL1 0x80000U |
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#define | AARCH64_HFGRTR_EL2_LOREA_EL1 0x100000U |
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#define | AARCH64_HFGRTR_EL2_LORID_EL1 0x200000U |
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#define | AARCH64_HFGRTR_EL2_LORN_EL1 0x400000U |
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#define | AARCH64_HFGRTR_EL2_LORSA_EL1 0x800000U |
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#define | AARCH64_HFGRTR_EL2_MAIR_EL1 0x1000000U |
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#define | AARCH64_HFGRTR_EL2_MIDR_EL1 0x2000000U |
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#define | AARCH64_HFGRTR_EL2_MPIDR_EL1 0x4000000U |
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#define | AARCH64_HFGRTR_EL2_PAR_EL1 0x8000000U |
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#define | AARCH64_HFGRTR_EL2_REVIDR_EL1 0x10000000U |
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#define | AARCH64_HFGRTR_EL2_SCTLR_EL1 0x20000000U |
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#define | AARCH64_HFGRTR_EL2_SCXTNUM_EL1 0x40000000U |
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#define | AARCH64_HFGRTR_EL2_SCXTNUM_EL0 0x80000000U |
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#define | AARCH64_HFGRTR_EL2_TCR_EL1 0x100000000ULL |
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#define | AARCH64_HFGRTR_EL2_TPIDR_EL1 0x200000000ULL |
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#define | AARCH64_HFGRTR_EL2_TPIDRRO_EL0 0x400000000ULL |
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#define | AARCH64_HFGRTR_EL2_TPIDR_EL0 0x800000000ULL |
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#define | AARCH64_HFGRTR_EL2_TTBR0_EL1 0x1000000000ULL |
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#define | AARCH64_HFGRTR_EL2_TTBR1_EL1 0x2000000000ULL |
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#define | AARCH64_HFGRTR_EL2_VBAR_EL1 0x4000000000ULL |
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#define | AARCH64_HFGRTR_EL2_ICC_IGRPENN_EL1 0x8000000000ULL |
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#define | AARCH64_HFGRTR_EL2_ERRIDR_EL1 0x10000000000ULL |
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#define | AARCH64_HFGRTR_EL2_ERRSELR_EL1 0x20000000000ULL |
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#define | AARCH64_HFGRTR_EL2_ERXFR_EL1 0x40000000000ULL |
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#define | AARCH64_HFGRTR_EL2_ERXCTLR_EL1 0x80000000000ULL |
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#define | AARCH64_HFGRTR_EL2_ERXSTATUS_EL1 0x100000000000ULL |
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#define | AARCH64_HFGRTR_EL2_ERXMISCN_EL1 0x200000000000ULL |
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#define | AARCH64_HFGRTR_EL2_ERXPFGF_EL1 0x400000000000ULL |
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#define | AARCH64_HFGRTR_EL2_ERXPFGCTL_EL1 0x800000000000ULL |
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#define | AARCH64_HFGRTR_EL2_ERXPFGCDN_EL1 0x1000000000000ULL |
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#define | AARCH64_HFGRTR_EL2_ERXADDR_EL1 0x2000000000000ULL |
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#define | AARCH64_HFGWTR_EL2_AFSR0_EL1 0x1U |
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#define | AARCH64_HFGWTR_EL2_AFSR1_EL1 0x2U |
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#define | AARCH64_HFGWTR_EL2_AMAIR_EL1 0x8U |
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#define | AARCH64_HFGWTR_EL2_APDAKEY 0x10U |
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#define | AARCH64_HFGWTR_EL2_APDBKEY 0x20U |
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#define | AARCH64_HFGWTR_EL2_APGAKEY 0x40U |
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#define | AARCH64_HFGWTR_EL2_APIAKEY 0x80U |
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#define | AARCH64_HFGWTR_EL2_APIBKEY 0x100U |
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#define | AARCH64_HFGWTR_EL2_CONTEXTIDR_EL1 0x800U |
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#define | AARCH64_HFGWTR_EL2_CPACR_EL1 0x1000U |
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#define | AARCH64_HFGWTR_EL2_CSSELR_EL1 0x2000U |
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#define | AARCH64_HFGWTR_EL2_ESR_EL1 0x10000U |
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#define | AARCH64_HFGWTR_EL2_FAR_EL1 0x20000U |
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#define | AARCH64_HFGWTR_EL2_LORC_EL1 0x80000U |
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#define | AARCH64_HFGWTR_EL2_LOREA_EL1 0x100000U |
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#define | AARCH64_HFGWTR_EL2_LORN_EL1 0x400000U |
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#define | AARCH64_HFGWTR_EL2_LORSA_EL1 0x800000U |
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#define | AARCH64_HFGWTR_EL2_MAIR_EL1 0x1000000U |
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#define | AARCH64_HFGWTR_EL2_PAR_EL1 0x8000000U |
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#define | AARCH64_HFGWTR_EL2_SCTLR_EL1 0x20000000U |
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#define | AARCH64_HFGWTR_EL2_SCXTNUM_EL1 0x40000000U |
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#define | AARCH64_HFGWTR_EL2_SCXTNUM_EL0 0x80000000U |
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#define | AARCH64_HFGWTR_EL2_TCR_EL1 0x100000000ULL |
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#define | AARCH64_HFGWTR_EL2_TPIDR_EL1 0x200000000ULL |
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#define | AARCH64_HFGWTR_EL2_TPIDRRO_EL0 0x400000000ULL |
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#define | AARCH64_HFGWTR_EL2_TPIDR_EL0 0x800000000ULL |
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#define | AARCH64_HFGWTR_EL2_TTBR0_EL1 0x1000000000ULL |
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#define | AARCH64_HFGWTR_EL2_TTBR1_EL1 0x2000000000ULL |
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#define | AARCH64_HFGWTR_EL2_VBAR_EL1 0x4000000000ULL |
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#define | AARCH64_HFGWTR_EL2_ICC_IGRPENN_EL1 0x8000000000ULL |
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#define | AARCH64_HFGWTR_EL2_ERRSELR_EL1 0x20000000000ULL |
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#define | AARCH64_HFGWTR_EL2_ERXCTLR_EL1 0x80000000000ULL |
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#define | AARCH64_HFGWTR_EL2_ERXSTATUS_EL1 0x100000000000ULL |
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#define | AARCH64_HFGWTR_EL2_ERXMISCN_EL1 0x200000000000ULL |
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#define | AARCH64_HFGWTR_EL2_ERXPFGCTL_EL1 0x800000000000ULL |
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#define | AARCH64_HFGWTR_EL2_ERXPFGCDN_EL1 0x1000000000000ULL |
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#define | AARCH64_HFGWTR_EL2_ERXADDR_EL1 0x2000000000000ULL |
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#define | AARCH64_HPFAR_EL2_FIPA_47_12(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_HPFAR_EL2_FIPA_47_12_SHIFT 4 |
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#define | AARCH64_HPFAR_EL2_FIPA_47_12_MASK 0xfffffffff0ULL |
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#define | AARCH64_HPFAR_EL2_FIPA_47_12_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfffffffffULL ) |
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#define | AARCH64_HPFAR_EL2_FIPA_51_48(_val) ( ( _val ) << 40 ) |
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#define | AARCH64_HPFAR_EL2_FIPA_51_48_SHIFT 40 |
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#define | AARCH64_HPFAR_EL2_FIPA_51_48_MASK 0xf0000000000ULL |
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#define | AARCH64_HPFAR_EL2_FIPA_51_48_GET(_reg) ( ( ( _reg ) >> 40 ) & 0xfULL ) |
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#define | AARCH64_HPFAR_EL2_NS 0x8000000000000000ULL |
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#define | AARCH64_ID_AA64DFR0_EL1_DEBUGVER(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ID_AA64DFR0_EL1_DEBUGVER_SHIFT 0 |
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#define | AARCH64_ID_AA64DFR0_EL1_DEBUGVER_MASK 0xfU |
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#define | AARCH64_ID_AA64DFR0_EL1_DEBUGVER_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_ID_AA64DFR0_EL1_TRACEVER(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_ID_AA64DFR0_EL1_TRACEVER_SHIFT 4 |
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#define | AARCH64_ID_AA64DFR0_EL1_TRACEVER_MASK 0xf0U |
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#define | AARCH64_ID_AA64DFR0_EL1_TRACEVER_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_ID_AA64DFR0_EL1_PMUVER(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ID_AA64DFR0_EL1_PMUVER_SHIFT 8 |
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#define | AARCH64_ID_AA64DFR0_EL1_PMUVER_MASK 0xf00U |
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#define | AARCH64_ID_AA64DFR0_EL1_PMUVER_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_ID_AA64DFR0_EL1_BRPS(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ID_AA64DFR0_EL1_BRPS_SHIFT 12 |
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#define | AARCH64_ID_AA64DFR0_EL1_BRPS_MASK 0xf000U |
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#define | AARCH64_ID_AA64DFR0_EL1_BRPS_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_ID_AA64DFR0_EL1_WRPS(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ID_AA64DFR0_EL1_WRPS_SHIFT 20 |
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#define | AARCH64_ID_AA64DFR0_EL1_WRPS_MASK 0xf00000U |
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#define | AARCH64_ID_AA64DFR0_EL1_WRPS_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_ID_AA64DFR0_EL1_CTX_CMPS(_val) ( ( _val ) << 28 ) |
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#define | AARCH64_ID_AA64DFR0_EL1_CTX_CMPS_SHIFT 28 |
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#define | AARCH64_ID_AA64DFR0_EL1_CTX_CMPS_MASK 0xf0000000U |
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#define | AARCH64_ID_AA64DFR0_EL1_CTX_CMPS_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU ) |
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#define | AARCH64_ID_AA64DFR0_EL1_PMSVER(_val) ( ( _val ) << 32 ) |
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#define | AARCH64_ID_AA64DFR0_EL1_PMSVER_SHIFT 32 |
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#define | AARCH64_ID_AA64DFR0_EL1_PMSVER_MASK 0xf00000000ULL |
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#define | AARCH64_ID_AA64DFR0_EL1_PMSVER_GET(_reg) ( ( ( _reg ) >> 32 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64DFR0_EL1_DOUBLELOCK(_val) ( ( _val ) << 36 ) |
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#define | AARCH64_ID_AA64DFR0_EL1_DOUBLELOCK_SHIFT 36 |
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#define | AARCH64_ID_AA64DFR0_EL1_DOUBLELOCK_MASK 0xf000000000ULL |
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#define | AARCH64_ID_AA64DFR0_EL1_DOUBLELOCK_GET(_reg) ( ( ( _reg ) >> 36 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64DFR0_EL1_TRACEFILT(_val) ( ( _val ) << 40 ) |
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#define | AARCH64_ID_AA64DFR0_EL1_TRACEFILT_SHIFT 40 |
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#define | AARCH64_ID_AA64DFR0_EL1_TRACEFILT_MASK 0xf0000000000ULL |
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#define | AARCH64_ID_AA64DFR0_EL1_TRACEFILT_GET(_reg) ( ( ( _reg ) >> 40 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64DFR0_EL1_MTPMU(_val) ( ( _val ) << 48 ) |
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#define | AARCH64_ID_AA64DFR0_EL1_MTPMU_SHIFT 48 |
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#define | AARCH64_ID_AA64DFR0_EL1_MTPMU_MASK 0xf000000000000ULL |
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#define | AARCH64_ID_AA64DFR0_EL1_MTPMU_GET(_reg) ( ( ( _reg ) >> 48 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_AES(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_AES_SHIFT 4 |
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#define | AARCH64_ID_AA64ISAR0_EL1_AES_MASK 0xf0U |
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#define | AARCH64_ID_AA64ISAR0_EL1_AES_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_SHA1(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_SHA1_SHIFT 8 |
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#define | AARCH64_ID_AA64ISAR0_EL1_SHA1_MASK 0xf00U |
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#define | AARCH64_ID_AA64ISAR0_EL1_SHA1_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_SHA2(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_SHA2_SHIFT 12 |
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#define | AARCH64_ID_AA64ISAR0_EL1_SHA2_MASK 0xf000U |
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#define | AARCH64_ID_AA64ISAR0_EL1_SHA2_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_CRC32(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_CRC32_SHIFT 16 |
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#define | AARCH64_ID_AA64ISAR0_EL1_CRC32_MASK 0xf0000U |
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#define | AARCH64_ID_AA64ISAR0_EL1_CRC32_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_ATOMIC(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_ATOMIC_SHIFT 20 |
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#define | AARCH64_ID_AA64ISAR0_EL1_ATOMIC_MASK 0xf00000U |
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#define | AARCH64_ID_AA64ISAR0_EL1_ATOMIC_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_RDM(_val) ( ( _val ) << 28 ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_RDM_SHIFT 28 |
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#define | AARCH64_ID_AA64ISAR0_EL1_RDM_MASK 0xf0000000U |
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#define | AARCH64_ID_AA64ISAR0_EL1_RDM_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_SHA3(_val) ( ( _val ) << 32 ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_SHA3_SHIFT 32 |
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#define | AARCH64_ID_AA64ISAR0_EL1_SHA3_MASK 0xf00000000ULL |
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#define | AARCH64_ID_AA64ISAR0_EL1_SHA3_GET(_reg) ( ( ( _reg ) >> 32 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_SM3(_val) ( ( _val ) << 36 ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_SM3_SHIFT 36 |
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#define | AARCH64_ID_AA64ISAR0_EL1_SM3_MASK 0xf000000000ULL |
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#define | AARCH64_ID_AA64ISAR0_EL1_SM3_GET(_reg) ( ( ( _reg ) >> 36 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_SM4(_val) ( ( _val ) << 40 ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_SM4_SHIFT 40 |
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#define | AARCH64_ID_AA64ISAR0_EL1_SM4_MASK 0xf0000000000ULL |
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#define | AARCH64_ID_AA64ISAR0_EL1_SM4_GET(_reg) ( ( ( _reg ) >> 40 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_DP(_val) ( ( _val ) << 44 ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_DP_SHIFT 44 |
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#define | AARCH64_ID_AA64ISAR0_EL1_DP_MASK 0xf00000000000ULL |
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#define | AARCH64_ID_AA64ISAR0_EL1_DP_GET(_reg) ( ( ( _reg ) >> 44 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_FHM(_val) ( ( _val ) << 48 ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_FHM_SHIFT 48 |
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#define | AARCH64_ID_AA64ISAR0_EL1_FHM_MASK 0xf000000000000ULL |
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#define | AARCH64_ID_AA64ISAR0_EL1_FHM_GET(_reg) ( ( ( _reg ) >> 48 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_TS(_val) ( ( _val ) << 52 ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_TS_SHIFT 52 |
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#define | AARCH64_ID_AA64ISAR0_EL1_TS_MASK 0xf0000000000000ULL |
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#define | AARCH64_ID_AA64ISAR0_EL1_TS_GET(_reg) ( ( ( _reg ) >> 52 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_TLB(_val) ( ( _val ) << 56 ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_TLB_SHIFT 56 |
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#define | AARCH64_ID_AA64ISAR0_EL1_TLB_MASK 0xf00000000000000ULL |
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#define | AARCH64_ID_AA64ISAR0_EL1_TLB_GET(_reg) ( ( ( _reg ) >> 56 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_RNDR(_val) ( ( _val ) << 60 ) |
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#define | AARCH64_ID_AA64ISAR0_EL1_RNDR_SHIFT 60 |
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#define | AARCH64_ID_AA64ISAR0_EL1_RNDR_MASK 0xf000000000000000ULL |
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#define | AARCH64_ID_AA64ISAR0_EL1_RNDR_GET(_reg) ( ( ( _reg ) >> 60 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_DPB(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_DPB_SHIFT 0 |
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#define | AARCH64_ID_AA64ISAR1_EL1_DPB_MASK 0xfU |
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#define | AARCH64_ID_AA64ISAR1_EL1_DPB_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_APA(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_APA_SHIFT 4 |
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#define | AARCH64_ID_AA64ISAR1_EL1_APA_MASK 0xf0U |
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#define | AARCH64_ID_AA64ISAR1_EL1_APA_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_API(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_API_SHIFT 8 |
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#define | AARCH64_ID_AA64ISAR1_EL1_API_MASK 0xf00U |
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#define | AARCH64_ID_AA64ISAR1_EL1_API_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_JSCVT(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_JSCVT_SHIFT 12 |
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#define | AARCH64_ID_AA64ISAR1_EL1_JSCVT_MASK 0xf000U |
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#define | AARCH64_ID_AA64ISAR1_EL1_JSCVT_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_FCMA(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_FCMA_SHIFT 16 |
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#define | AARCH64_ID_AA64ISAR1_EL1_FCMA_MASK 0xf0000U |
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#define | AARCH64_ID_AA64ISAR1_EL1_FCMA_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_LRCPC(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_LRCPC_SHIFT 20 |
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#define | AARCH64_ID_AA64ISAR1_EL1_LRCPC_MASK 0xf00000U |
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#define | AARCH64_ID_AA64ISAR1_EL1_LRCPC_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_GPA(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_GPA_SHIFT 24 |
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#define | AARCH64_ID_AA64ISAR1_EL1_GPA_MASK 0xf000000U |
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#define | AARCH64_ID_AA64ISAR1_EL1_GPA_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_GPI(_val) ( ( _val ) << 28 ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_GPI_SHIFT 28 |
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#define | AARCH64_ID_AA64ISAR1_EL1_GPI_MASK 0xf0000000U |
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#define | AARCH64_ID_AA64ISAR1_EL1_GPI_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_FRINTTS(_val) ( ( _val ) << 32 ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32 |
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#define | AARCH64_ID_AA64ISAR1_EL1_FRINTTS_MASK 0xf00000000ULL |
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#define | AARCH64_ID_AA64ISAR1_EL1_FRINTTS_GET(_reg) ( ( ( _reg ) >> 32 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_SB(_val) ( ( _val ) << 36 ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_SB_SHIFT 36 |
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#define | AARCH64_ID_AA64ISAR1_EL1_SB_MASK 0xf000000000ULL |
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#define | AARCH64_ID_AA64ISAR1_EL1_SB_GET(_reg) ( ( ( _reg ) >> 36 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_SPECRES(_val) ( ( _val ) << 40 ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_SPECRES_SHIFT 40 |
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#define | AARCH64_ID_AA64ISAR1_EL1_SPECRES_MASK 0xf0000000000ULL |
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#define | AARCH64_ID_AA64ISAR1_EL1_SPECRES_GET(_reg) ( ( ( _reg ) >> 40 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_BF16(_val) ( ( _val ) << 44 ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_BF16_SHIFT 44 |
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#define | AARCH64_ID_AA64ISAR1_EL1_BF16_MASK 0xf00000000000ULL |
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#define | AARCH64_ID_AA64ISAR1_EL1_BF16_GET(_reg) ( ( ( _reg ) >> 44 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_DGH(_val) ( ( _val ) << 48 ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_DGH_SHIFT 48 |
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#define | AARCH64_ID_AA64ISAR1_EL1_DGH_MASK 0xf000000000000ULL |
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#define | AARCH64_ID_AA64ISAR1_EL1_DGH_GET(_reg) ( ( ( _reg ) >> 48 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_I8MM(_val) ( ( _val ) << 52 ) |
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#define | AARCH64_ID_AA64ISAR1_EL1_I8MM_SHIFT 52 |
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#define | AARCH64_ID_AA64ISAR1_EL1_I8MM_MASK 0xf0000000000000ULL |
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#define | AARCH64_ID_AA64ISAR1_EL1_I8MM_GET(_reg) ( ( ( _reg ) >> 52 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_PARANGE(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_PARANGE_SHIFT 0 |
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#define | AARCH64_ID_AA64MMFR0_EL1_PARANGE_MASK 0xfU |
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#define | AARCH64_ID_AA64MMFR0_EL1_PARANGE_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_ASIDBITS(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_ASIDBITS_SHIFT 4 |
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#define | AARCH64_ID_AA64MMFR0_EL1_ASIDBITS_MASK 0xf0U |
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#define | AARCH64_ID_AA64MMFR0_EL1_ASIDBITS_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_BIGEND(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_BIGEND_SHIFT 8 |
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#define | AARCH64_ID_AA64MMFR0_EL1_BIGEND_MASK 0xf00U |
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#define | AARCH64_ID_AA64MMFR0_EL1_BIGEND_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_SNSMEM(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_SNSMEM_SHIFT 12 |
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#define | AARCH64_ID_AA64MMFR0_EL1_SNSMEM_MASK 0xf000U |
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#define | AARCH64_ID_AA64MMFR0_EL1_SNSMEM_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_BIGENDEL0(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT 16 |
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#define | AARCH64_ID_AA64MMFR0_EL1_BIGENDEL0_MASK 0xf0000U |
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#define | AARCH64_ID_AA64MMFR0_EL1_BIGENDEL0_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_TGRAN16(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_TGRAN16_SHIFT 20 |
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#define | AARCH64_ID_AA64MMFR0_EL1_TGRAN16_MASK 0xf00000U |
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#define | AARCH64_ID_AA64MMFR0_EL1_TGRAN16_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_TGRAN64(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_TGRAN64_SHIFT 24 |
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#define | AARCH64_ID_AA64MMFR0_EL1_TGRAN64_MASK 0xf000000U |
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#define | AARCH64_ID_AA64MMFR0_EL1_TGRAN64_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_TGRAN4(_val) ( ( _val ) << 28 ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_TGRAN4_SHIFT 28 |
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#define | AARCH64_ID_AA64MMFR0_EL1_TGRAN4_MASK 0xf0000000U |
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#define | AARCH64_ID_AA64MMFR0_EL1_TGRAN4_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_TGRAN16_2(_val) ( ( _val ) << 32 ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT 32 |
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#define | AARCH64_ID_AA64MMFR0_EL1_TGRAN16_2_MASK 0xf00000000ULL |
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#define | AARCH64_ID_AA64MMFR0_EL1_TGRAN16_2_GET(_reg) ( ( ( _reg ) >> 32 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_TGRAN64_2(_val) ( ( _val ) << 36 ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT 36 |
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#define | AARCH64_ID_AA64MMFR0_EL1_TGRAN64_2_MASK 0xf000000000ULL |
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#define | AARCH64_ID_AA64MMFR0_EL1_TGRAN64_2_GET(_reg) ( ( ( _reg ) >> 36 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_TGRAN4_2(_val) ( ( _val ) << 40 ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT 40 |
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#define | AARCH64_ID_AA64MMFR0_EL1_TGRAN4_2_MASK 0xf0000000000ULL |
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#define | AARCH64_ID_AA64MMFR0_EL1_TGRAN4_2_GET(_reg) ( ( ( _reg ) >> 40 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_EXS(_val) ( ( _val ) << 44 ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_EXS_SHIFT 44 |
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#define | AARCH64_ID_AA64MMFR0_EL1_EXS_MASK 0xf00000000000ULL |
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#define | AARCH64_ID_AA64MMFR0_EL1_EXS_GET(_reg) ( ( ( _reg ) >> 44 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_FGT(_val) ( ( _val ) << 56 ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_FGT_SHIFT 56 |
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#define | AARCH64_ID_AA64MMFR0_EL1_FGT_MASK 0xf00000000000000ULL |
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#define | AARCH64_ID_AA64MMFR0_EL1_FGT_GET(_reg) ( ( ( _reg ) >> 56 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_ECV(_val) ( ( _val ) << 60 ) |
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#define | AARCH64_ID_AA64MMFR0_EL1_ECV_SHIFT 60 |
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#define | AARCH64_ID_AA64MMFR0_EL1_ECV_MASK 0xf000000000000000ULL |
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#define | AARCH64_ID_AA64MMFR0_EL1_ECV_GET(_reg) ( ( ( _reg ) >> 60 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64MMFR1_EL1_HAFDBS(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ID_AA64MMFR1_EL1_HAFDBS_SHIFT 0 |
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#define | AARCH64_ID_AA64MMFR1_EL1_HAFDBS_MASK 0xfU |
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#define | AARCH64_ID_AA64MMFR1_EL1_HAFDBS_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_ID_AA64MMFR1_EL1_VMIDBITS(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_ID_AA64MMFR1_EL1_VMIDBITS_SHIFT 4 |
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#define | AARCH64_ID_AA64MMFR1_EL1_VMIDBITS_MASK 0xf0U |
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#define | AARCH64_ID_AA64MMFR1_EL1_VMIDBITS_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_ID_AA64MMFR1_EL1_VH(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ID_AA64MMFR1_EL1_VH_SHIFT 8 |
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#define | AARCH64_ID_AA64MMFR1_EL1_VH_MASK 0xf00U |
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#define | AARCH64_ID_AA64MMFR1_EL1_VH_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_ID_AA64MMFR1_EL1_HPDS(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ID_AA64MMFR1_EL1_HPDS_SHIFT 12 |
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#define | AARCH64_ID_AA64MMFR1_EL1_HPDS_MASK 0xf000U |
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#define | AARCH64_ID_AA64MMFR1_EL1_HPDS_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_ID_AA64MMFR1_EL1_LO(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ID_AA64MMFR1_EL1_LO_SHIFT 16 |
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#define | AARCH64_ID_AA64MMFR1_EL1_LO_MASK 0xf0000U |
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#define | AARCH64_ID_AA64MMFR1_EL1_LO_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_ID_AA64MMFR1_EL1_PAN(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ID_AA64MMFR1_EL1_PAN_SHIFT 20 |
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#define | AARCH64_ID_AA64MMFR1_EL1_PAN_MASK 0xf00000U |
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#define | AARCH64_ID_AA64MMFR1_EL1_PAN_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_ID_AA64MMFR1_EL1_SPECSEI(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_ID_AA64MMFR1_EL1_SPECSEI_SHIFT 24 |
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#define | AARCH64_ID_AA64MMFR1_EL1_SPECSEI_MASK 0xf000000U |
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#define | AARCH64_ID_AA64MMFR1_EL1_SPECSEI_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU ) |
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#define | AARCH64_ID_AA64MMFR1_EL1_XNX(_val) ( ( _val ) << 28 ) |
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#define | AARCH64_ID_AA64MMFR1_EL1_XNX_SHIFT 28 |
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#define | AARCH64_ID_AA64MMFR1_EL1_XNX_MASK 0xf0000000U |
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#define | AARCH64_ID_AA64MMFR1_EL1_XNX_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU ) |
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#define | AARCH64_ID_AA64MMFR1_EL1_TWED(_val) ( ( _val ) << 32 ) |
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#define | AARCH64_ID_AA64MMFR1_EL1_TWED_SHIFT 32 |
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#define | AARCH64_ID_AA64MMFR1_EL1_TWED_MASK 0xf00000000ULL |
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#define | AARCH64_ID_AA64MMFR1_EL1_TWED_GET(_reg) ( ( ( _reg ) >> 32 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64MMFR1_EL1_ETS(_val) ( ( _val ) << 36 ) |
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#define | AARCH64_ID_AA64MMFR1_EL1_ETS_SHIFT 36 |
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#define | AARCH64_ID_AA64MMFR1_EL1_ETS_MASK 0xf000000000ULL |
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#define | AARCH64_ID_AA64MMFR1_EL1_ETS_GET(_reg) ( ( ( _reg ) >> 36 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_CNP(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_CNP_SHIFT 0 |
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#define | AARCH64_ID_AA64MMFR2_EL1_CNP_MASK 0xfU |
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#define | AARCH64_ID_AA64MMFR2_EL1_CNP_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_UAO(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_UAO_SHIFT 4 |
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#define | AARCH64_ID_AA64MMFR2_EL1_UAO_MASK 0xf0U |
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#define | AARCH64_ID_AA64MMFR2_EL1_UAO_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_LSM(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_LSM_SHIFT 8 |
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#define | AARCH64_ID_AA64MMFR2_EL1_LSM_MASK 0xf00U |
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#define | AARCH64_ID_AA64MMFR2_EL1_LSM_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_IESB(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_IESB_SHIFT 12 |
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#define | AARCH64_ID_AA64MMFR2_EL1_IESB_MASK 0xf000U |
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#define | AARCH64_ID_AA64MMFR2_EL1_IESB_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_VARANGE(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_VARANGE_SHIFT 16 |
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#define | AARCH64_ID_AA64MMFR2_EL1_VARANGE_MASK 0xf0000U |
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#define | AARCH64_ID_AA64MMFR2_EL1_VARANGE_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_CCIDX(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_CCIDX_SHIFT 20 |
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#define | AARCH64_ID_AA64MMFR2_EL1_CCIDX_MASK 0xf00000U |
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#define | AARCH64_ID_AA64MMFR2_EL1_CCIDX_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_NV(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_NV_SHIFT 24 |
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#define | AARCH64_ID_AA64MMFR2_EL1_NV_MASK 0xf000000U |
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#define | AARCH64_ID_AA64MMFR2_EL1_NV_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_ST(_val) ( ( _val ) << 28 ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_ST_SHIFT 28 |
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#define | AARCH64_ID_AA64MMFR2_EL1_ST_MASK 0xf0000000U |
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#define | AARCH64_ID_AA64MMFR2_EL1_ST_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_AT(_val) ( ( _val ) << 32 ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_AT_SHIFT 32 |
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#define | AARCH64_ID_AA64MMFR2_EL1_AT_MASK 0xf00000000ULL |
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#define | AARCH64_ID_AA64MMFR2_EL1_AT_GET(_reg) ( ( ( _reg ) >> 32 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_IDS(_val) ( ( _val ) << 36 ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_IDS_SHIFT 36 |
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#define | AARCH64_ID_AA64MMFR2_EL1_IDS_MASK 0xf000000000ULL |
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#define | AARCH64_ID_AA64MMFR2_EL1_IDS_GET(_reg) ( ( ( _reg ) >> 36 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_FWB(_val) ( ( _val ) << 40 ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_FWB_SHIFT 40 |
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#define | AARCH64_ID_AA64MMFR2_EL1_FWB_MASK 0xf0000000000ULL |
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#define | AARCH64_ID_AA64MMFR2_EL1_FWB_GET(_reg) ( ( ( _reg ) >> 40 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_TTL(_val) ( ( _val ) << 48 ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_TTL_SHIFT 48 |
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#define | AARCH64_ID_AA64MMFR2_EL1_TTL_MASK 0xf000000000000ULL |
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#define | AARCH64_ID_AA64MMFR2_EL1_TTL_GET(_reg) ( ( ( _reg ) >> 48 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_BBM(_val) ( ( _val ) << 52 ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_BBM_SHIFT 52 |
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#define | AARCH64_ID_AA64MMFR2_EL1_BBM_MASK 0xf0000000000000ULL |
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#define | AARCH64_ID_AA64MMFR2_EL1_BBM_GET(_reg) ( ( ( _reg ) >> 52 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_EVT(_val) ( ( _val ) << 56 ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_EVT_SHIFT 56 |
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#define | AARCH64_ID_AA64MMFR2_EL1_EVT_MASK 0xf00000000000000ULL |
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#define | AARCH64_ID_AA64MMFR2_EL1_EVT_GET(_reg) ( ( ( _reg ) >> 56 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_E0PD(_val) ( ( _val ) << 60 ) |
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#define | AARCH64_ID_AA64MMFR2_EL1_E0PD_SHIFT 60 |
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#define | AARCH64_ID_AA64MMFR2_EL1_E0PD_MASK 0xf000000000000000ULL |
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#define | AARCH64_ID_AA64MMFR2_EL1_E0PD_GET(_reg) ( ( ( _reg ) >> 60 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64PFR0_EL1_EL0(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ID_AA64PFR0_EL1_EL0_SHIFT 0 |
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#define | AARCH64_ID_AA64PFR0_EL1_EL0_MASK 0xfU |
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#define | AARCH64_ID_AA64PFR0_EL1_EL0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_ID_AA64PFR0_EL1_EL1(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_ID_AA64PFR0_EL1_EL1_SHIFT 4 |
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#define | AARCH64_ID_AA64PFR0_EL1_EL1_MASK 0xf0U |
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#define | AARCH64_ID_AA64PFR0_EL1_EL1_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_ID_AA64PFR0_EL1_EL2(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ID_AA64PFR0_EL1_EL2_SHIFT 8 |
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#define | AARCH64_ID_AA64PFR0_EL1_EL2_MASK 0xf00U |
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#define | AARCH64_ID_AA64PFR0_EL1_EL2_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_ID_AA64PFR0_EL1_EL3(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ID_AA64PFR0_EL1_EL3_SHIFT 12 |
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#define | AARCH64_ID_AA64PFR0_EL1_EL3_MASK 0xf000U |
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#define | AARCH64_ID_AA64PFR0_EL1_EL3_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_ID_AA64PFR0_EL1_FP(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ID_AA64PFR0_EL1_FP_SHIFT 16 |
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#define | AARCH64_ID_AA64PFR0_EL1_FP_MASK 0xf0000U |
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#define | AARCH64_ID_AA64PFR0_EL1_FP_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_ID_AA64PFR0_EL1_ADVSIMD(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ID_AA64PFR0_EL1_ADVSIMD_SHIFT 20 |
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#define | AARCH64_ID_AA64PFR0_EL1_ADVSIMD_MASK 0xf00000U |
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#define | AARCH64_ID_AA64PFR0_EL1_ADVSIMD_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_ID_AA64PFR0_EL1_GIC(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_ID_AA64PFR0_EL1_GIC_SHIFT 24 |
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#define | AARCH64_ID_AA64PFR0_EL1_GIC_MASK 0xf000000U |
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#define | AARCH64_ID_AA64PFR0_EL1_GIC_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU ) |
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#define | AARCH64_ID_AA64PFR0_EL1_RAS(_val) ( ( _val ) << 28 ) |
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#define | AARCH64_ID_AA64PFR0_EL1_RAS_SHIFT 28 |
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#define | AARCH64_ID_AA64PFR0_EL1_RAS_MASK 0xf0000000U |
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#define | AARCH64_ID_AA64PFR0_EL1_RAS_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU ) |
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#define | AARCH64_ID_AA64PFR0_EL1_SVE(_val) ( ( _val ) << 32 ) |
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#define | AARCH64_ID_AA64PFR0_EL1_SVE_SHIFT 32 |
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#define | AARCH64_ID_AA64PFR0_EL1_SVE_MASK 0xf00000000ULL |
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#define | AARCH64_ID_AA64PFR0_EL1_SVE_GET(_reg) ( ( ( _reg ) >> 32 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64PFR0_EL1_SEL2(_val) ( ( _val ) << 36 ) |
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#define | AARCH64_ID_AA64PFR0_EL1_SEL2_SHIFT 36 |
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#define | AARCH64_ID_AA64PFR0_EL1_SEL2_MASK 0xf000000000ULL |
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#define | AARCH64_ID_AA64PFR0_EL1_SEL2_GET(_reg) ( ( ( _reg ) >> 36 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64PFR0_EL1_MPAM(_val) ( ( _val ) << 40 ) |
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#define | AARCH64_ID_AA64PFR0_EL1_MPAM_SHIFT 40 |
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#define | AARCH64_ID_AA64PFR0_EL1_MPAM_MASK 0xf0000000000ULL |
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#define | AARCH64_ID_AA64PFR0_EL1_MPAM_GET(_reg) ( ( ( _reg ) >> 40 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64PFR0_EL1_AMU(_val) ( ( _val ) << 44 ) |
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#define | AARCH64_ID_AA64PFR0_EL1_AMU_SHIFT 44 |
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#define | AARCH64_ID_AA64PFR0_EL1_AMU_MASK 0xf00000000000ULL |
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#define | AARCH64_ID_AA64PFR0_EL1_AMU_GET(_reg) ( ( ( _reg ) >> 44 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64PFR0_EL1_DIT(_val) ( ( _val ) << 48 ) |
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#define | AARCH64_ID_AA64PFR0_EL1_DIT_SHIFT 48 |
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#define | AARCH64_ID_AA64PFR0_EL1_DIT_MASK 0xf000000000000ULL |
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#define | AARCH64_ID_AA64PFR0_EL1_DIT_GET(_reg) ( ( ( _reg ) >> 48 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64PFR0_EL1_CSV2(_val) ( ( _val ) << 56 ) |
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#define | AARCH64_ID_AA64PFR0_EL1_CSV2_SHIFT 56 |
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#define | AARCH64_ID_AA64PFR0_EL1_CSV2_MASK 0xf00000000000000ULL |
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#define | AARCH64_ID_AA64PFR0_EL1_CSV2_GET(_reg) ( ( ( _reg ) >> 56 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64PFR0_EL1_CSV3(_val) ( ( _val ) << 60 ) |
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#define | AARCH64_ID_AA64PFR0_EL1_CSV3_SHIFT 60 |
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#define | AARCH64_ID_AA64PFR0_EL1_CSV3_MASK 0xf000000000000000ULL |
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#define | AARCH64_ID_AA64PFR0_EL1_CSV3_GET(_reg) ( ( ( _reg ) >> 60 ) & 0xfULL ) |
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#define | AARCH64_ID_AA64PFR1_EL1_BT(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ID_AA64PFR1_EL1_BT_SHIFT 0 |
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#define | AARCH64_ID_AA64PFR1_EL1_BT_MASK 0xfU |
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#define | AARCH64_ID_AA64PFR1_EL1_BT_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_ID_AA64PFR1_EL1_SSBS(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_ID_AA64PFR1_EL1_SSBS_SHIFT 4 |
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#define | AARCH64_ID_AA64PFR1_EL1_SSBS_MASK 0xf0U |
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#define | AARCH64_ID_AA64PFR1_EL1_SSBS_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_ID_AA64PFR1_EL1_MTE(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ID_AA64PFR1_EL1_MTE_SHIFT 8 |
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#define | AARCH64_ID_AA64PFR1_EL1_MTE_MASK 0xf00U |
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#define | AARCH64_ID_AA64PFR1_EL1_MTE_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_ID_AA64PFR1_EL1_RAS_FRAC(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ID_AA64PFR1_EL1_RAS_FRAC_SHIFT 12 |
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#define | AARCH64_ID_AA64PFR1_EL1_RAS_FRAC_MASK 0xf000U |
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#define | AARCH64_ID_AA64PFR1_EL1_RAS_FRAC_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_ID_AA64PFR1_EL1_MPAM_FRAC(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ID_AA64PFR1_EL1_MPAM_FRAC_SHIFT 16 |
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#define | AARCH64_ID_AA64PFR1_EL1_MPAM_FRAC_MASK 0xf0000U |
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#define | AARCH64_ID_AA64PFR1_EL1_MPAM_FRAC_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_ID_DFR0_EL1_COPDBG(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ID_DFR0_EL1_COPDBG_SHIFT 0 |
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#define | AARCH64_ID_DFR0_EL1_COPDBG_MASK 0xfU |
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#define | AARCH64_ID_DFR0_EL1_COPDBG_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_ID_DFR0_EL1_COPSDBG(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_ID_DFR0_EL1_COPSDBG_SHIFT 4 |
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#define | AARCH64_ID_DFR0_EL1_COPSDBG_MASK 0xf0U |
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#define | AARCH64_ID_DFR0_EL1_COPSDBG_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_ID_DFR0_EL1_MMAPDBG(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ID_DFR0_EL1_MMAPDBG_SHIFT 8 |
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#define | AARCH64_ID_DFR0_EL1_MMAPDBG_MASK 0xf00U |
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#define | AARCH64_ID_DFR0_EL1_MMAPDBG_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_ID_DFR0_EL1_COPTRC(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ID_DFR0_EL1_COPTRC_SHIFT 12 |
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#define | AARCH64_ID_DFR0_EL1_COPTRC_MASK 0xf000U |
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#define | AARCH64_ID_DFR0_EL1_COPTRC_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_ID_DFR0_EL1_MMAPTRC(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ID_DFR0_EL1_MMAPTRC_SHIFT 16 |
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#define | AARCH64_ID_DFR0_EL1_MMAPTRC_MASK 0xf0000U |
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#define | AARCH64_ID_DFR0_EL1_MMAPTRC_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_ID_DFR0_EL1_MPROFDBG(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ID_DFR0_EL1_MPROFDBG_SHIFT 20 |
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#define | AARCH64_ID_DFR0_EL1_MPROFDBG_MASK 0xf00000U |
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#define | AARCH64_ID_DFR0_EL1_MPROFDBG_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_ID_DFR0_EL1_PERFMON(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_ID_DFR0_EL1_PERFMON_SHIFT 24 |
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#define | AARCH64_ID_DFR0_EL1_PERFMON_MASK 0xf000000U |
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#define | AARCH64_ID_DFR0_EL1_PERFMON_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU ) |
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#define | AARCH64_ID_DFR0_EL1_TRACEFILT(_val) ( ( _val ) << 28 ) |
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#define | AARCH64_ID_DFR0_EL1_TRACEFILT_SHIFT 28 |
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#define | AARCH64_ID_DFR0_EL1_TRACEFILT_MASK 0xf0000000U |
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#define | AARCH64_ID_DFR0_EL1_TRACEFILT_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU ) |
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#define | AARCH64_ID_DFR1_EL1_MTPMU(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ID_DFR1_EL1_MTPMU_SHIFT 0 |
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#define | AARCH64_ID_DFR1_EL1_MTPMU_MASK 0xfU |
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#define | AARCH64_ID_DFR1_EL1_MTPMU_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR0_EL1_SWAP(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ID_ISAR0_EL1_SWAP_SHIFT 0 |
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#define | AARCH64_ID_ISAR0_EL1_SWAP_MASK 0xfU |
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#define | AARCH64_ID_ISAR0_EL1_SWAP_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR0_EL1_BITCOUNT(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_ID_ISAR0_EL1_BITCOUNT_SHIFT 4 |
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#define | AARCH64_ID_ISAR0_EL1_BITCOUNT_MASK 0xf0U |
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#define | AARCH64_ID_ISAR0_EL1_BITCOUNT_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR0_EL1_BITFIELD(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ID_ISAR0_EL1_BITFIELD_SHIFT 8 |
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#define | AARCH64_ID_ISAR0_EL1_BITFIELD_MASK 0xf00U |
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#define | AARCH64_ID_ISAR0_EL1_BITFIELD_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR0_EL1_CMPBRANCH(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ID_ISAR0_EL1_CMPBRANCH_SHIFT 12 |
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#define | AARCH64_ID_ISAR0_EL1_CMPBRANCH_MASK 0xf000U |
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#define | AARCH64_ID_ISAR0_EL1_CMPBRANCH_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR0_EL1_COPROC(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ID_ISAR0_EL1_COPROC_SHIFT 16 |
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#define | AARCH64_ID_ISAR0_EL1_COPROC_MASK 0xf0000U |
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#define | AARCH64_ID_ISAR0_EL1_COPROC_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR0_EL1_DEBUG(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ID_ISAR0_EL1_DEBUG_SHIFT 20 |
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#define | AARCH64_ID_ISAR0_EL1_DEBUG_MASK 0xf00000U |
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#define | AARCH64_ID_ISAR0_EL1_DEBUG_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR0_EL1_DIVIDE(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_ID_ISAR0_EL1_DIVIDE_SHIFT 24 |
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#define | AARCH64_ID_ISAR0_EL1_DIVIDE_MASK 0xf000000U |
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#define | AARCH64_ID_ISAR0_EL1_DIVIDE_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR1_EL1_ENDIAN(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ID_ISAR1_EL1_ENDIAN_SHIFT 0 |
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#define | AARCH64_ID_ISAR1_EL1_ENDIAN_MASK 0xfU |
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#define | AARCH64_ID_ISAR1_EL1_ENDIAN_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR1_EL1_EXCEPT(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_ID_ISAR1_EL1_EXCEPT_SHIFT 4 |
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#define | AARCH64_ID_ISAR1_EL1_EXCEPT_MASK 0xf0U |
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#define | AARCH64_ID_ISAR1_EL1_EXCEPT_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR1_EL1_EXCEPT_AR(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ID_ISAR1_EL1_EXCEPT_AR_SHIFT 8 |
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#define | AARCH64_ID_ISAR1_EL1_EXCEPT_AR_MASK 0xf00U |
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#define | AARCH64_ID_ISAR1_EL1_EXCEPT_AR_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR1_EL1_EXTEND(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ID_ISAR1_EL1_EXTEND_SHIFT 12 |
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#define | AARCH64_ID_ISAR1_EL1_EXTEND_MASK 0xf000U |
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#define | AARCH64_ID_ISAR1_EL1_EXTEND_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR1_EL1_IFTHEN(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ID_ISAR1_EL1_IFTHEN_SHIFT 16 |
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#define | AARCH64_ID_ISAR1_EL1_IFTHEN_MASK 0xf0000U |
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#define | AARCH64_ID_ISAR1_EL1_IFTHEN_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR1_EL1_IMMEDIATE(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ID_ISAR1_EL1_IMMEDIATE_SHIFT 20 |
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#define | AARCH64_ID_ISAR1_EL1_IMMEDIATE_MASK 0xf00000U |
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#define | AARCH64_ID_ISAR1_EL1_IMMEDIATE_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR1_EL1_INTERWORK(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_ID_ISAR1_EL1_INTERWORK_SHIFT 24 |
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#define | AARCH64_ID_ISAR1_EL1_INTERWORK_MASK 0xf000000U |
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#define | AARCH64_ID_ISAR1_EL1_INTERWORK_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR1_EL1_JAZELLE(_val) ( ( _val ) << 28 ) |
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#define | AARCH64_ID_ISAR1_EL1_JAZELLE_SHIFT 28 |
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#define | AARCH64_ID_ISAR1_EL1_JAZELLE_MASK 0xf0000000U |
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#define | AARCH64_ID_ISAR1_EL1_JAZELLE_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR2_EL1_LOADSTORE(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ID_ISAR2_EL1_LOADSTORE_SHIFT 0 |
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#define | AARCH64_ID_ISAR2_EL1_LOADSTORE_MASK 0xfU |
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#define | AARCH64_ID_ISAR2_EL1_LOADSTORE_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR2_EL1_MEMHINT(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_ID_ISAR2_EL1_MEMHINT_SHIFT 4 |
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#define | AARCH64_ID_ISAR2_EL1_MEMHINT_MASK 0xf0U |
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#define | AARCH64_ID_ISAR2_EL1_MEMHINT_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR2_EL1_MULTIACCESSINT(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ID_ISAR2_EL1_MULTIACCESSINT_SHIFT 8 |
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#define | AARCH64_ID_ISAR2_EL1_MULTIACCESSINT_MASK 0xf00U |
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#define | AARCH64_ID_ISAR2_EL1_MULTIACCESSINT_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR2_EL1_MULT(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ID_ISAR2_EL1_MULT_SHIFT 12 |
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#define | AARCH64_ID_ISAR2_EL1_MULT_MASK 0xf000U |
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#define | AARCH64_ID_ISAR2_EL1_MULT_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR2_EL1_MULTS(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ID_ISAR2_EL1_MULTS_SHIFT 16 |
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#define | AARCH64_ID_ISAR2_EL1_MULTS_MASK 0xf0000U |
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#define | AARCH64_ID_ISAR2_EL1_MULTS_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR2_EL1_MULTU(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ID_ISAR2_EL1_MULTU_SHIFT 20 |
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#define | AARCH64_ID_ISAR2_EL1_MULTU_MASK 0xf00000U |
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#define | AARCH64_ID_ISAR2_EL1_MULTU_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR2_EL1_PSR_AR(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_ID_ISAR2_EL1_PSR_AR_SHIFT 24 |
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#define | AARCH64_ID_ISAR2_EL1_PSR_AR_MASK 0xf000000U |
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#define | AARCH64_ID_ISAR2_EL1_PSR_AR_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR2_EL1_REVERSAL(_val) ( ( _val ) << 28 ) |
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#define | AARCH64_ID_ISAR2_EL1_REVERSAL_SHIFT 28 |
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#define | AARCH64_ID_ISAR2_EL1_REVERSAL_MASK 0xf0000000U |
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#define | AARCH64_ID_ISAR2_EL1_REVERSAL_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR3_EL1_SATURATE(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ID_ISAR3_EL1_SATURATE_SHIFT 0 |
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#define | AARCH64_ID_ISAR3_EL1_SATURATE_MASK 0xfU |
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#define | AARCH64_ID_ISAR3_EL1_SATURATE_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR3_EL1_SIMD(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_ID_ISAR3_EL1_SIMD_SHIFT 4 |
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#define | AARCH64_ID_ISAR3_EL1_SIMD_MASK 0xf0U |
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#define | AARCH64_ID_ISAR3_EL1_SIMD_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR3_EL1_SVC(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ID_ISAR3_EL1_SVC_SHIFT 8 |
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#define | AARCH64_ID_ISAR3_EL1_SVC_MASK 0xf00U |
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#define | AARCH64_ID_ISAR3_EL1_SVC_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR3_EL1_SYNCHPRIM(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ID_ISAR3_EL1_SYNCHPRIM_SHIFT 12 |
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#define | AARCH64_ID_ISAR3_EL1_SYNCHPRIM_MASK 0xf000U |
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#define | AARCH64_ID_ISAR3_EL1_SYNCHPRIM_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR3_EL1_TABBRANCH(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ID_ISAR3_EL1_TABBRANCH_SHIFT 16 |
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#define | AARCH64_ID_ISAR3_EL1_TABBRANCH_MASK 0xf0000U |
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#define | AARCH64_ID_ISAR3_EL1_TABBRANCH_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR3_EL1_T32COPY(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ID_ISAR3_EL1_T32COPY_SHIFT 20 |
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#define | AARCH64_ID_ISAR3_EL1_T32COPY_MASK 0xf00000U |
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#define | AARCH64_ID_ISAR3_EL1_T32COPY_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR3_EL1_TRUENOP(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_ID_ISAR3_EL1_TRUENOP_SHIFT 24 |
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#define | AARCH64_ID_ISAR3_EL1_TRUENOP_MASK 0xf000000U |
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#define | AARCH64_ID_ISAR3_EL1_TRUENOP_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR3_EL1_T32EE(_val) ( ( _val ) << 28 ) |
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#define | AARCH64_ID_ISAR3_EL1_T32EE_SHIFT 28 |
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#define | AARCH64_ID_ISAR3_EL1_T32EE_MASK 0xf0000000U |
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#define | AARCH64_ID_ISAR3_EL1_T32EE_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR4_EL1_UNPRIV(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ID_ISAR4_EL1_UNPRIV_SHIFT 0 |
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#define | AARCH64_ID_ISAR4_EL1_UNPRIV_MASK 0xfU |
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#define | AARCH64_ID_ISAR4_EL1_UNPRIV_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR4_EL1_WITHSHIFTS(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_ID_ISAR4_EL1_WITHSHIFTS_SHIFT 4 |
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#define | AARCH64_ID_ISAR4_EL1_WITHSHIFTS_MASK 0xf0U |
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#define | AARCH64_ID_ISAR4_EL1_WITHSHIFTS_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR4_EL1_WRITEBACK(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ID_ISAR4_EL1_WRITEBACK_SHIFT 8 |
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#define | AARCH64_ID_ISAR4_EL1_WRITEBACK_MASK 0xf00U |
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#define | AARCH64_ID_ISAR4_EL1_WRITEBACK_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR4_EL1_SMC(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ID_ISAR4_EL1_SMC_SHIFT 12 |
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#define | AARCH64_ID_ISAR4_EL1_SMC_MASK 0xf000U |
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#define | AARCH64_ID_ISAR4_EL1_SMC_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR4_EL1_BARRIER(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ID_ISAR4_EL1_BARRIER_SHIFT 16 |
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#define | AARCH64_ID_ISAR4_EL1_BARRIER_MASK 0xf0000U |
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#define | AARCH64_ID_ISAR4_EL1_BARRIER_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR4_EL1_SYNCHPRIM_FRAC(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ID_ISAR4_EL1_SYNCHPRIM_FRAC_SHIFT 20 |
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#define | AARCH64_ID_ISAR4_EL1_SYNCHPRIM_FRAC_MASK 0xf00000U |
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#define | AARCH64_ID_ISAR4_EL1_SYNCHPRIM_FRAC_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR4_EL1_PSR_M(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_ID_ISAR4_EL1_PSR_M_SHIFT 24 |
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#define | AARCH64_ID_ISAR4_EL1_PSR_M_MASK 0xf000000U |
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#define | AARCH64_ID_ISAR4_EL1_PSR_M_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR4_EL1_SWP_FRAC(_val) ( ( _val ) << 28 ) |
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#define | AARCH64_ID_ISAR4_EL1_SWP_FRAC_SHIFT 28 |
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#define | AARCH64_ID_ISAR4_EL1_SWP_FRAC_MASK 0xf0000000U |
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#define | AARCH64_ID_ISAR4_EL1_SWP_FRAC_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR5_EL1_SEVL(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ID_ISAR5_EL1_SEVL_SHIFT 0 |
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#define | AARCH64_ID_ISAR5_EL1_SEVL_MASK 0xfU |
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#define | AARCH64_ID_ISAR5_EL1_SEVL_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR5_EL1_AES(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_ID_ISAR5_EL1_AES_SHIFT 4 |
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#define | AARCH64_ID_ISAR5_EL1_AES_MASK 0xf0U |
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#define | AARCH64_ID_ISAR5_EL1_AES_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR5_EL1_SHA1(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ID_ISAR5_EL1_SHA1_SHIFT 8 |
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#define | AARCH64_ID_ISAR5_EL1_SHA1_MASK 0xf00U |
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#define | AARCH64_ID_ISAR5_EL1_SHA1_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR5_EL1_SHA2(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ID_ISAR5_EL1_SHA2_SHIFT 12 |
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#define | AARCH64_ID_ISAR5_EL1_SHA2_MASK 0xf000U |
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#define | AARCH64_ID_ISAR5_EL1_SHA2_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR5_EL1_CRC32(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ID_ISAR5_EL1_CRC32_SHIFT 16 |
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#define | AARCH64_ID_ISAR5_EL1_CRC32_MASK 0xf0000U |
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#define | AARCH64_ID_ISAR5_EL1_CRC32_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR5_EL1_RDM(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_ID_ISAR5_EL1_RDM_SHIFT 24 |
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#define | AARCH64_ID_ISAR5_EL1_RDM_MASK 0xf000000U |
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#define | AARCH64_ID_ISAR5_EL1_RDM_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR5_EL1_VCMA(_val) ( ( _val ) << 28 ) |
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#define | AARCH64_ID_ISAR5_EL1_VCMA_SHIFT 28 |
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#define | AARCH64_ID_ISAR5_EL1_VCMA_MASK 0xf0000000U |
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#define | AARCH64_ID_ISAR5_EL1_VCMA_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR6_EL1_JSCVT(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ID_ISAR6_EL1_JSCVT_SHIFT 0 |
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#define | AARCH64_ID_ISAR6_EL1_JSCVT_MASK 0xfU |
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#define | AARCH64_ID_ISAR6_EL1_JSCVT_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR6_EL1_DP(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_ID_ISAR6_EL1_DP_SHIFT 4 |
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#define | AARCH64_ID_ISAR6_EL1_DP_MASK 0xf0U |
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#define | AARCH64_ID_ISAR6_EL1_DP_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR6_EL1_FHM(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ID_ISAR6_EL1_FHM_SHIFT 8 |
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#define | AARCH64_ID_ISAR6_EL1_FHM_MASK 0xf00U |
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#define | AARCH64_ID_ISAR6_EL1_FHM_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR6_EL1_SB(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ID_ISAR6_EL1_SB_SHIFT 12 |
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#define | AARCH64_ID_ISAR6_EL1_SB_MASK 0xf000U |
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#define | AARCH64_ID_ISAR6_EL1_SB_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR6_EL1_SPECRES(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ID_ISAR6_EL1_SPECRES_SHIFT 16 |
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#define | AARCH64_ID_ISAR6_EL1_SPECRES_MASK 0xf0000U |
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#define | AARCH64_ID_ISAR6_EL1_SPECRES_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR6_EL1_BF16(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ID_ISAR6_EL1_BF16_SHIFT 20 |
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#define | AARCH64_ID_ISAR6_EL1_BF16_MASK 0xf00000U |
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#define | AARCH64_ID_ISAR6_EL1_BF16_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_ID_ISAR6_EL1_I8MM(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_ID_ISAR6_EL1_I8MM_SHIFT 24 |
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#define | AARCH64_ID_ISAR6_EL1_I8MM_MASK 0xf000000U |
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#define | AARCH64_ID_ISAR6_EL1_I8MM_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR0_EL1_VMSA(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ID_MMFR0_EL1_VMSA_SHIFT 0 |
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#define | AARCH64_ID_MMFR0_EL1_VMSA_MASK 0xfU |
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#define | AARCH64_ID_MMFR0_EL1_VMSA_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR0_EL1_PMSA(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_ID_MMFR0_EL1_PMSA_SHIFT 4 |
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#define | AARCH64_ID_MMFR0_EL1_PMSA_MASK 0xf0U |
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#define | AARCH64_ID_MMFR0_EL1_PMSA_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR0_EL1_OUTERSHR(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ID_MMFR0_EL1_OUTERSHR_SHIFT 8 |
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#define | AARCH64_ID_MMFR0_EL1_OUTERSHR_MASK 0xf00U |
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#define | AARCH64_ID_MMFR0_EL1_OUTERSHR_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR0_EL1_SHARELVL(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ID_MMFR0_EL1_SHARELVL_SHIFT 12 |
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#define | AARCH64_ID_MMFR0_EL1_SHARELVL_MASK 0xf000U |
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#define | AARCH64_ID_MMFR0_EL1_SHARELVL_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR0_EL1_TCM(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ID_MMFR0_EL1_TCM_SHIFT 16 |
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#define | AARCH64_ID_MMFR0_EL1_TCM_MASK 0xf0000U |
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#define | AARCH64_ID_MMFR0_EL1_TCM_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR0_EL1_AUXREG(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ID_MMFR0_EL1_AUXREG_SHIFT 20 |
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#define | AARCH64_ID_MMFR0_EL1_AUXREG_MASK 0xf00000U |
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#define | AARCH64_ID_MMFR0_EL1_AUXREG_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR0_EL1_FCSE(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_ID_MMFR0_EL1_FCSE_SHIFT 24 |
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#define | AARCH64_ID_MMFR0_EL1_FCSE_MASK 0xf000000U |
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#define | AARCH64_ID_MMFR0_EL1_FCSE_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR0_EL1_INNERSHR(_val) ( ( _val ) << 28 ) |
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#define | AARCH64_ID_MMFR0_EL1_INNERSHR_SHIFT 28 |
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#define | AARCH64_ID_MMFR0_EL1_INNERSHR_MASK 0xf0000000U |
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#define | AARCH64_ID_MMFR0_EL1_INNERSHR_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR1_EL1_L1HVDVA(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ID_MMFR1_EL1_L1HVDVA_SHIFT 0 |
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#define | AARCH64_ID_MMFR1_EL1_L1HVDVA_MASK 0xfU |
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#define | AARCH64_ID_MMFR1_EL1_L1HVDVA_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR1_EL1_L1UNIVA(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_ID_MMFR1_EL1_L1UNIVA_SHIFT 4 |
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#define | AARCH64_ID_MMFR1_EL1_L1UNIVA_MASK 0xf0U |
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#define | AARCH64_ID_MMFR1_EL1_L1UNIVA_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR1_EL1_L1HVDSW(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ID_MMFR1_EL1_L1HVDSW_SHIFT 8 |
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#define | AARCH64_ID_MMFR1_EL1_L1HVDSW_MASK 0xf00U |
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#define | AARCH64_ID_MMFR1_EL1_L1HVDSW_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR1_EL1_L1UNISW(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ID_MMFR1_EL1_L1UNISW_SHIFT 12 |
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#define | AARCH64_ID_MMFR1_EL1_L1UNISW_MASK 0xf000U |
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#define | AARCH64_ID_MMFR1_EL1_L1UNISW_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR1_EL1_L1HVD(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ID_MMFR1_EL1_L1HVD_SHIFT 16 |
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#define | AARCH64_ID_MMFR1_EL1_L1HVD_MASK 0xf0000U |
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#define | AARCH64_ID_MMFR1_EL1_L1HVD_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR1_EL1_L1UNI(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ID_MMFR1_EL1_L1UNI_SHIFT 20 |
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#define | AARCH64_ID_MMFR1_EL1_L1UNI_MASK 0xf00000U |
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#define | AARCH64_ID_MMFR1_EL1_L1UNI_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR1_EL1_L1TSTCLN(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_ID_MMFR1_EL1_L1TSTCLN_SHIFT 24 |
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#define | AARCH64_ID_MMFR1_EL1_L1TSTCLN_MASK 0xf000000U |
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#define | AARCH64_ID_MMFR1_EL1_L1TSTCLN_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR1_EL1_BPRED(_val) ( ( _val ) << 28 ) |
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#define | AARCH64_ID_MMFR1_EL1_BPRED_SHIFT 28 |
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#define | AARCH64_ID_MMFR1_EL1_BPRED_MASK 0xf0000000U |
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#define | AARCH64_ID_MMFR1_EL1_BPRED_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR2_EL1_L1HVDFG(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ID_MMFR2_EL1_L1HVDFG_SHIFT 0 |
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#define | AARCH64_ID_MMFR2_EL1_L1HVDFG_MASK 0xfU |
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#define | AARCH64_ID_MMFR2_EL1_L1HVDFG_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR2_EL1_L1HVDBG(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_ID_MMFR2_EL1_L1HVDBG_SHIFT 4 |
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#define | AARCH64_ID_MMFR2_EL1_L1HVDBG_MASK 0xf0U |
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#define | AARCH64_ID_MMFR2_EL1_L1HVDBG_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR2_EL1_L1HVDRNG(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ID_MMFR2_EL1_L1HVDRNG_SHIFT 8 |
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#define | AARCH64_ID_MMFR2_EL1_L1HVDRNG_MASK 0xf00U |
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#define | AARCH64_ID_MMFR2_EL1_L1HVDRNG_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR2_EL1_HVDTLB(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ID_MMFR2_EL1_HVDTLB_SHIFT 12 |
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#define | AARCH64_ID_MMFR2_EL1_HVDTLB_MASK 0xf000U |
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#define | AARCH64_ID_MMFR2_EL1_HVDTLB_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR2_EL1_UNITLB(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ID_MMFR2_EL1_UNITLB_SHIFT 16 |
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#define | AARCH64_ID_MMFR2_EL1_UNITLB_MASK 0xf0000U |
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#define | AARCH64_ID_MMFR2_EL1_UNITLB_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR2_EL1_MEMBARR(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ID_MMFR2_EL1_MEMBARR_SHIFT 20 |
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#define | AARCH64_ID_MMFR2_EL1_MEMBARR_MASK 0xf00000U |
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#define | AARCH64_ID_MMFR2_EL1_MEMBARR_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR2_EL1_WFISTALL(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_ID_MMFR2_EL1_WFISTALL_SHIFT 24 |
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#define | AARCH64_ID_MMFR2_EL1_WFISTALL_MASK 0xf000000U |
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#define | AARCH64_ID_MMFR2_EL1_WFISTALL_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR2_EL1_HWACCFLG(_val) ( ( _val ) << 28 ) |
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#define | AARCH64_ID_MMFR2_EL1_HWACCFLG_SHIFT 28 |
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#define | AARCH64_ID_MMFR2_EL1_HWACCFLG_MASK 0xf0000000U |
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#define | AARCH64_ID_MMFR2_EL1_HWACCFLG_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR3_EL1_CMAINTVA(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ID_MMFR3_EL1_CMAINTVA_SHIFT 0 |
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#define | AARCH64_ID_MMFR3_EL1_CMAINTVA_MASK 0xfU |
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#define | AARCH64_ID_MMFR3_EL1_CMAINTVA_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR3_EL1_CMAINTSW(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_ID_MMFR3_EL1_CMAINTSW_SHIFT 4 |
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#define | AARCH64_ID_MMFR3_EL1_CMAINTSW_MASK 0xf0U |
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#define | AARCH64_ID_MMFR3_EL1_CMAINTSW_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR3_EL1_BPMAINT(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ID_MMFR3_EL1_BPMAINT_SHIFT 8 |
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#define | AARCH64_ID_MMFR3_EL1_BPMAINT_MASK 0xf00U |
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#define | AARCH64_ID_MMFR3_EL1_BPMAINT_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR3_EL1_MAINTBCST(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ID_MMFR3_EL1_MAINTBCST_SHIFT 12 |
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#define | AARCH64_ID_MMFR3_EL1_MAINTBCST_MASK 0xf000U |
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#define | AARCH64_ID_MMFR3_EL1_MAINTBCST_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR3_EL1_PAN(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ID_MMFR3_EL1_PAN_SHIFT 16 |
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#define | AARCH64_ID_MMFR3_EL1_PAN_MASK 0xf0000U |
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#define | AARCH64_ID_MMFR3_EL1_PAN_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR3_EL1_COHWALK(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ID_MMFR3_EL1_COHWALK_SHIFT 20 |
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#define | AARCH64_ID_MMFR3_EL1_COHWALK_MASK 0xf00000U |
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#define | AARCH64_ID_MMFR3_EL1_COHWALK_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR3_EL1_CMEMSZ(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_ID_MMFR3_EL1_CMEMSZ_SHIFT 24 |
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#define | AARCH64_ID_MMFR3_EL1_CMEMSZ_MASK 0xf000000U |
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#define | AARCH64_ID_MMFR3_EL1_CMEMSZ_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR3_EL1_SUPERSEC(_val) ( ( _val ) << 28 ) |
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#define | AARCH64_ID_MMFR3_EL1_SUPERSEC_SHIFT 28 |
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#define | AARCH64_ID_MMFR3_EL1_SUPERSEC_MASK 0xf0000000U |
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#define | AARCH64_ID_MMFR3_EL1_SUPERSEC_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR4_EL1_SPECSEI(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ID_MMFR4_EL1_SPECSEI_SHIFT 0 |
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#define | AARCH64_ID_MMFR4_EL1_SPECSEI_MASK 0xfU |
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#define | AARCH64_ID_MMFR4_EL1_SPECSEI_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR4_EL1_AC2(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_ID_MMFR4_EL1_AC2_SHIFT 4 |
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#define | AARCH64_ID_MMFR4_EL1_AC2_MASK 0xf0U |
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#define | AARCH64_ID_MMFR4_EL1_AC2_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR4_EL1_XNX(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ID_MMFR4_EL1_XNX_SHIFT 8 |
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#define | AARCH64_ID_MMFR4_EL1_XNX_MASK 0xf00U |
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#define | AARCH64_ID_MMFR4_EL1_XNX_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR4_EL1_CNP(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ID_MMFR4_EL1_CNP_SHIFT 12 |
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#define | AARCH64_ID_MMFR4_EL1_CNP_MASK 0xf000U |
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#define | AARCH64_ID_MMFR4_EL1_CNP_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR4_EL1_HPDS(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ID_MMFR4_EL1_HPDS_SHIFT 16 |
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#define | AARCH64_ID_MMFR4_EL1_HPDS_MASK 0xf0000U |
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#define | AARCH64_ID_MMFR4_EL1_HPDS_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR4_EL1_LSM(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ID_MMFR4_EL1_LSM_SHIFT 20 |
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#define | AARCH64_ID_MMFR4_EL1_LSM_MASK 0xf00000U |
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#define | AARCH64_ID_MMFR4_EL1_LSM_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR4_EL1_CCIDX(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_ID_MMFR4_EL1_CCIDX_SHIFT 24 |
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#define | AARCH64_ID_MMFR4_EL1_CCIDX_MASK 0xf000000U |
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#define | AARCH64_ID_MMFR4_EL1_CCIDX_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR4_EL1_EVT(_val) ( ( _val ) << 28 ) |
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#define | AARCH64_ID_MMFR4_EL1_EVT_SHIFT 28 |
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#define | AARCH64_ID_MMFR4_EL1_EVT_MASK 0xf0000000U |
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#define | AARCH64_ID_MMFR4_EL1_EVT_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU ) |
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#define | AARCH64_ID_MMFR5_EL1_ETS(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ID_MMFR5_EL1_ETS_SHIFT 0 |
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#define | AARCH64_ID_MMFR5_EL1_ETS_MASK 0xfU |
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#define | AARCH64_ID_MMFR5_EL1_ETS_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_ID_PFR0_EL1_STATE0(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ID_PFR0_EL1_STATE0_SHIFT 0 |
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#define | AARCH64_ID_PFR0_EL1_STATE0_MASK 0xfU |
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#define | AARCH64_ID_PFR0_EL1_STATE0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_ID_PFR0_EL1_STATE1(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_ID_PFR0_EL1_STATE1_SHIFT 4 |
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#define | AARCH64_ID_PFR0_EL1_STATE1_MASK 0xf0U |
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#define | AARCH64_ID_PFR0_EL1_STATE1_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_ID_PFR0_EL1_STATE2(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ID_PFR0_EL1_STATE2_SHIFT 8 |
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#define | AARCH64_ID_PFR0_EL1_STATE2_MASK 0xf00U |
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#define | AARCH64_ID_PFR0_EL1_STATE2_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_ID_PFR0_EL1_STATE3(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ID_PFR0_EL1_STATE3_SHIFT 12 |
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#define | AARCH64_ID_PFR0_EL1_STATE3_MASK 0xf000U |
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#define | AARCH64_ID_PFR0_EL1_STATE3_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_ID_PFR0_EL1_CSV2(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ID_PFR0_EL1_CSV2_SHIFT 16 |
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#define | AARCH64_ID_PFR0_EL1_CSV2_MASK 0xf0000U |
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#define | AARCH64_ID_PFR0_EL1_CSV2_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_ID_PFR0_EL1_AMU(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ID_PFR0_EL1_AMU_SHIFT 20 |
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#define | AARCH64_ID_PFR0_EL1_AMU_MASK 0xf00000U |
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#define | AARCH64_ID_PFR0_EL1_AMU_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_ID_PFR0_EL1_DIT(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_ID_PFR0_EL1_DIT_SHIFT 24 |
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#define | AARCH64_ID_PFR0_EL1_DIT_MASK 0xf000000U |
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#define | AARCH64_ID_PFR0_EL1_DIT_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU ) |
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#define | AARCH64_ID_PFR0_EL1_RAS(_val) ( ( _val ) << 28 ) |
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#define | AARCH64_ID_PFR0_EL1_RAS_SHIFT 28 |
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#define | AARCH64_ID_PFR0_EL1_RAS_MASK 0xf0000000U |
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#define | AARCH64_ID_PFR0_EL1_RAS_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU ) |
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#define | AARCH64_ID_PFR1_EL1_PROGMOD(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ID_PFR1_EL1_PROGMOD_SHIFT 0 |
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#define | AARCH64_ID_PFR1_EL1_PROGMOD_MASK 0xfU |
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#define | AARCH64_ID_PFR1_EL1_PROGMOD_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_ID_PFR1_EL1_SECURITY(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_ID_PFR1_EL1_SECURITY_SHIFT 4 |
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#define | AARCH64_ID_PFR1_EL1_SECURITY_MASK 0xf0U |
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#define | AARCH64_ID_PFR1_EL1_SECURITY_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_ID_PFR1_EL1_MPROGMOD(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ID_PFR1_EL1_MPROGMOD_SHIFT 8 |
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#define | AARCH64_ID_PFR1_EL1_MPROGMOD_MASK 0xf00U |
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#define | AARCH64_ID_PFR1_EL1_MPROGMOD_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_ID_PFR1_EL1_VIRTUALIZATION(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_ID_PFR1_EL1_VIRTUALIZATION_SHIFT 12 |
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#define | AARCH64_ID_PFR1_EL1_VIRTUALIZATION_MASK 0xf000U |
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#define | AARCH64_ID_PFR1_EL1_VIRTUALIZATION_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_ID_PFR1_EL1_GENTIMER(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_ID_PFR1_EL1_GENTIMER_SHIFT 16 |
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#define | AARCH64_ID_PFR1_EL1_GENTIMER_MASK 0xf0000U |
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#define | AARCH64_ID_PFR1_EL1_GENTIMER_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_ID_PFR1_EL1_SEC_FRAC(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_ID_PFR1_EL1_SEC_FRAC_SHIFT 20 |
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#define | AARCH64_ID_PFR1_EL1_SEC_FRAC_MASK 0xf00000U |
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#define | AARCH64_ID_PFR1_EL1_SEC_FRAC_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_ID_PFR1_EL1_VIRT_FRAC(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_ID_PFR1_EL1_VIRT_FRAC_SHIFT 24 |
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#define | AARCH64_ID_PFR1_EL1_VIRT_FRAC_MASK 0xf000000U |
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#define | AARCH64_ID_PFR1_EL1_VIRT_FRAC_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU ) |
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#define | AARCH64_ID_PFR1_EL1_GIC(_val) ( ( _val ) << 28 ) |
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#define | AARCH64_ID_PFR1_EL1_GIC_SHIFT 28 |
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#define | AARCH64_ID_PFR1_EL1_GIC_MASK 0xf0000000U |
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#define | AARCH64_ID_PFR1_EL1_GIC_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU ) |
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#define | AARCH64_ID_PFR2_EL1_CSV3(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ID_PFR2_EL1_CSV3_SHIFT 0 |
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#define | AARCH64_ID_PFR2_EL1_CSV3_MASK 0xfU |
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#define | AARCH64_ID_PFR2_EL1_CSV3_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_ID_PFR2_EL1_SSBS(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_ID_PFR2_EL1_SSBS_SHIFT 4 |
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#define | AARCH64_ID_PFR2_EL1_SSBS_MASK 0xf0U |
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#define | AARCH64_ID_PFR2_EL1_SSBS_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_ID_PFR2_EL1_RAS_FRAC(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_ID_PFR2_EL1_RAS_FRAC_SHIFT 8 |
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#define | AARCH64_ID_PFR2_EL1_RAS_FRAC_MASK 0xf00U |
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#define | AARCH64_ID_PFR2_EL1_RAS_FRAC_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_IFSR32_EL2_FS_3_0(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_IFSR32_EL2_FS_3_0_SHIFT 0 |
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#define | AARCH64_IFSR32_EL2_FS_3_0_MASK 0xfU |
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#define | AARCH64_IFSR32_EL2_FS_3_0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_IFSR32_EL2_STATUS(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_IFSR32_EL2_STATUS_SHIFT 0 |
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#define | AARCH64_IFSR32_EL2_STATUS_MASK 0x3fU |
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#define | AARCH64_IFSR32_EL2_STATUS_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3fU ) |
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#define | AARCH64_IFSR32_EL2_LPAE 0x200U |
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#define | AARCH64_IFSR32_EL2_FS_4 0x400U |
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#define | AARCH64_IFSR32_EL2_EXT 0x1000U |
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#define | AARCH64_IFSR32_EL2_FNV 0x10000U |
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#define | AARCH64_ISR_EL1_F 0x40U |
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#define | AARCH64_ISR_EL1_I 0x80U |
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#define | AARCH64_ISR_EL1_A 0x100U |
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#define | AARCH64_LORC_EL1_EN 0x1U |
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#define | AARCH64_LORC_EL1_DS(_val) ( ( _val ) << 2 ) |
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#define | AARCH64_LORC_EL1_DS_SHIFT 2 |
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#define | AARCH64_LORC_EL1_DS_MASK 0x3fcU |
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#define | AARCH64_LORC_EL1_DS_GET(_reg) ( ( ( _reg ) >> 2 ) & 0xffU ) |
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#define | AARCH64_LOREA_EL1_EA_47_16(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_LOREA_EL1_EA_47_16_SHIFT 16 |
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#define | AARCH64_LOREA_EL1_EA_47_16_MASK 0xffffffff0000ULL |
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#define | AARCH64_LOREA_EL1_EA_47_16_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xffffffffULL ) |
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#define | AARCH64_LOREA_EL1_EA_51_48(_val) ( ( _val ) << 48 ) |
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#define | AARCH64_LOREA_EL1_EA_51_48_SHIFT 48 |
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#define | AARCH64_LOREA_EL1_EA_51_48_MASK 0xf000000000000ULL |
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#define | AARCH64_LOREA_EL1_EA_51_48_GET(_reg) ( ( ( _reg ) >> 48 ) & 0xfULL ) |
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#define | AARCH64_LORID_EL1_LR(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_LORID_EL1_LR_SHIFT 0 |
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#define | AARCH64_LORID_EL1_LR_MASK 0xffU |
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#define | AARCH64_LORID_EL1_LR_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU ) |
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#define | AARCH64_LORID_EL1_LD(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_LORID_EL1_LD_SHIFT 16 |
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#define | AARCH64_LORID_EL1_LD_MASK 0xff0000U |
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#define | AARCH64_LORID_EL1_LD_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xffU ) |
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#define | AARCH64_LORN_EL1_NUM(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_LORN_EL1_NUM_SHIFT 0 |
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#define | AARCH64_LORN_EL1_NUM_MASK 0xffU |
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#define | AARCH64_LORN_EL1_NUM_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU ) |
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#define | AARCH64_LORSA_EL1_VALID 0x1U |
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#define | AARCH64_LORSA_EL1_SA_47_16(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_LORSA_EL1_SA_47_16_SHIFT 16 |
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#define | AARCH64_LORSA_EL1_SA_47_16_MASK 0xffffffff0000ULL |
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#define | AARCH64_LORSA_EL1_SA_47_16_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xffffffffULL ) |
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#define | AARCH64_LORSA_EL1_SA_51_48(_val) ( ( _val ) << 48 ) |
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#define | AARCH64_LORSA_EL1_SA_51_48_SHIFT 48 |
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#define | AARCH64_LORSA_EL1_SA_51_48_MASK 0xf000000000000ULL |
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#define | AARCH64_LORSA_EL1_SA_51_48_GET(_reg) ( ( ( _reg ) >> 48 ) & 0xfULL ) |
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#define | AARCH64_MAIR_EL1_ATTR0(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_MAIR_EL1_ATTR1(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_MAIR_EL1_ATTR2(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_MAIR_EL1_ATTR3(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_MAIR_EL1_ATTR4(_val) ( ( _val ) << 32 ) |
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#define | AARCH64_MAIR_EL1_ATTR5(_val) ( ( _val ) << 40 ) |
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#define | AARCH64_MAIR_EL1_ATTR6(_val) ( ( _val ) << 48 ) |
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#define | AARCH64_MAIR_EL1_ATTR7(_val) ( ( _val ) << 56 ) |
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#define | AARCH64_MIDR_EL1_REVISION(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_MIDR_EL1_REVISION_SHIFT 0 |
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#define | AARCH64_MIDR_EL1_REVISION_MASK 0xfU |
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#define | AARCH64_MIDR_EL1_REVISION_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_MIDR_EL1_PARTNUM(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_MIDR_EL1_PARTNUM_SHIFT 4 |
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#define | AARCH64_MIDR_EL1_PARTNUM_MASK 0xfff0U |
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#define | AARCH64_MIDR_EL1_PARTNUM_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfffU ) |
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#define | AARCH64_MIDR_EL1_ARCHITECTURE(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_MIDR_EL1_ARCHITECTURE_SHIFT 16 |
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#define | AARCH64_MIDR_EL1_ARCHITECTURE_MASK 0xf0000U |
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#define | AARCH64_MIDR_EL1_ARCHITECTURE_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_MIDR_EL1_VARIANT(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_MIDR_EL1_VARIANT_SHIFT 20 |
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#define | AARCH64_MIDR_EL1_VARIANT_MASK 0xf00000U |
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#define | AARCH64_MIDR_EL1_VARIANT_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_MIDR_EL1_IMPLEMENTER(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_MIDR_EL1_IMPLEMENTER_SHIFT 24 |
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#define | AARCH64_MIDR_EL1_IMPLEMENTER_MASK 0xff000000U |
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#define | AARCH64_MIDR_EL1_IMPLEMENTER_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xffU ) |
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#define | AARCH64_MPIDR_EL1_AFF0(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_MPIDR_EL1_AFF0_SHIFT 0 |
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#define | AARCH64_MPIDR_EL1_AFF0_MASK 0xffU |
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#define | AARCH64_MPIDR_EL1_AFF0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU ) |
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#define | AARCH64_MPIDR_EL1_AFF1(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_MPIDR_EL1_AFF1_SHIFT 8 |
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#define | AARCH64_MPIDR_EL1_AFF1_MASK 0xff00U |
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#define | AARCH64_MPIDR_EL1_AFF1_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xffU ) |
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#define | AARCH64_MPIDR_EL1_AFF2(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_MPIDR_EL1_AFF2_SHIFT 16 |
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#define | AARCH64_MPIDR_EL1_AFF2_MASK 0xff0000U |
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#define | AARCH64_MPIDR_EL1_AFF2_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xffU ) |
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#define | AARCH64_MPIDR_EL1_MT 0x1000000U |
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#define | AARCH64_MPIDR_EL1_U 0x40000000U |
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#define | AARCH64_MPIDR_EL1_AFF3(_val) ( ( _val ) << 32 ) |
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#define | AARCH64_MPIDR_EL1_AFF3_SHIFT 32 |
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#define | AARCH64_MPIDR_EL1_AFF3_MASK 0xff00000000ULL |
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#define | AARCH64_MPIDR_EL1_AFF3_GET(_reg) ( ( ( _reg ) >> 32 ) & 0xffULL ) |
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#define | AARCH64_MVFR0_EL1_SIMDREG(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_MVFR0_EL1_SIMDREG_SHIFT 0 |
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#define | AARCH64_MVFR0_EL1_SIMDREG_MASK 0xfU |
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#define | AARCH64_MVFR0_EL1_SIMDREG_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_MVFR0_EL1_FPSP(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_MVFR0_EL1_FPSP_SHIFT 4 |
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#define | AARCH64_MVFR0_EL1_FPSP_MASK 0xf0U |
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#define | AARCH64_MVFR0_EL1_FPSP_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_MVFR0_EL1_FPDP(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_MVFR0_EL1_FPDP_SHIFT 8 |
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#define | AARCH64_MVFR0_EL1_FPDP_MASK 0xf00U |
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#define | AARCH64_MVFR0_EL1_FPDP_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_MVFR0_EL1_FPTRAP(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_MVFR0_EL1_FPTRAP_SHIFT 12 |
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#define | AARCH64_MVFR0_EL1_FPTRAP_MASK 0xf000U |
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#define | AARCH64_MVFR0_EL1_FPTRAP_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_MVFR0_EL1_FPDIVIDE(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_MVFR0_EL1_FPDIVIDE_SHIFT 16 |
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#define | AARCH64_MVFR0_EL1_FPDIVIDE_MASK 0xf0000U |
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#define | AARCH64_MVFR0_EL1_FPDIVIDE_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_MVFR0_EL1_FPSQRT(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_MVFR0_EL1_FPSQRT_SHIFT 20 |
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#define | AARCH64_MVFR0_EL1_FPSQRT_MASK 0xf00000U |
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#define | AARCH64_MVFR0_EL1_FPSQRT_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_MVFR0_EL1_FPSHVEC(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_MVFR0_EL1_FPSHVEC_SHIFT 24 |
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#define | AARCH64_MVFR0_EL1_FPSHVEC_MASK 0xf000000U |
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#define | AARCH64_MVFR0_EL1_FPSHVEC_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU ) |
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#define | AARCH64_MVFR0_EL1_FPROUND(_val) ( ( _val ) << 28 ) |
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#define | AARCH64_MVFR0_EL1_FPROUND_SHIFT 28 |
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#define | AARCH64_MVFR0_EL1_FPROUND_MASK 0xf0000000U |
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#define | AARCH64_MVFR0_EL1_FPROUND_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU ) |
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#define | AARCH64_MVFR1_EL1_FPFTZ(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_MVFR1_EL1_FPFTZ_SHIFT 0 |
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#define | AARCH64_MVFR1_EL1_FPFTZ_MASK 0xfU |
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#define | AARCH64_MVFR1_EL1_FPFTZ_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_MVFR1_EL1_FPDNAN(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_MVFR1_EL1_FPDNAN_SHIFT 4 |
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#define | AARCH64_MVFR1_EL1_FPDNAN_MASK 0xf0U |
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#define | AARCH64_MVFR1_EL1_FPDNAN_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_MVFR1_EL1_SIMDLS(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_MVFR1_EL1_SIMDLS_SHIFT 8 |
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#define | AARCH64_MVFR1_EL1_SIMDLS_MASK 0xf00U |
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#define | AARCH64_MVFR1_EL1_SIMDLS_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_MVFR1_EL1_SIMDINT(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_MVFR1_EL1_SIMDINT_SHIFT 12 |
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#define | AARCH64_MVFR1_EL1_SIMDINT_MASK 0xf000U |
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#define | AARCH64_MVFR1_EL1_SIMDINT_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_MVFR1_EL1_SIMDSP(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_MVFR1_EL1_SIMDSP_SHIFT 16 |
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#define | AARCH64_MVFR1_EL1_SIMDSP_MASK 0xf0000U |
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#define | AARCH64_MVFR1_EL1_SIMDSP_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_MVFR1_EL1_SIMDHP(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_MVFR1_EL1_SIMDHP_SHIFT 20 |
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#define | AARCH64_MVFR1_EL1_SIMDHP_MASK 0xf00000U |
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#define | AARCH64_MVFR1_EL1_SIMDHP_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_MVFR1_EL1_FPHP(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_MVFR1_EL1_FPHP_SHIFT 24 |
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#define | AARCH64_MVFR1_EL1_FPHP_MASK 0xf000000U |
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#define | AARCH64_MVFR1_EL1_FPHP_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU ) |
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#define | AARCH64_MVFR1_EL1_SIMDFMAC(_val) ( ( _val ) << 28 ) |
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#define | AARCH64_MVFR1_EL1_SIMDFMAC_SHIFT 28 |
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#define | AARCH64_MVFR1_EL1_SIMDFMAC_MASK 0xf0000000U |
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#define | AARCH64_MVFR1_EL1_SIMDFMAC_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU ) |
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#define | AARCH64_MVFR2_EL1_SIMDMISC(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_MVFR2_EL1_SIMDMISC_SHIFT 0 |
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#define | AARCH64_MVFR2_EL1_SIMDMISC_MASK 0xfU |
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#define | AARCH64_MVFR2_EL1_SIMDMISC_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_MVFR2_EL1_FPMISC(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_MVFR2_EL1_FPMISC_SHIFT 4 |
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#define | AARCH64_MVFR2_EL1_FPMISC_MASK 0xf0U |
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#define | AARCH64_MVFR2_EL1_FPMISC_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_PAR_EL1_F 0x1U |
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#define | AARCH64_PAR_EL1_FST(_val) ( ( _val ) << 1 ) |
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#define | AARCH64_PAR_EL1_FST_SHIFT 1 |
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#define | AARCH64_PAR_EL1_FST_MASK 0x7eU |
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#define | AARCH64_PAR_EL1_FST_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x3fU ) |
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#define | AARCH64_PAR_EL1_SH(_val) ( ( _val ) << 7 ) |
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#define | AARCH64_PAR_EL1_SH_SHIFT 7 |
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#define | AARCH64_PAR_EL1_SH_MASK 0x180U |
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#define | AARCH64_PAR_EL1_SH_GET(_reg) ( ( ( _reg ) >> 7 ) & 0x3U ) |
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#define | AARCH64_PAR_EL1_PTW 0x100U |
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#define | AARCH64_PAR_EL1_NS 0x200U |
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#define | AARCH64_PAR_EL1_S 0x200U |
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#define | AARCH64_PAR_EL1_PA_47_12(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_PAR_EL1_PA_47_12_SHIFT 12 |
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#define | AARCH64_PAR_EL1_PA_47_12_MASK 0xfffffffff000ULL |
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#define | AARCH64_PAR_EL1_PA_47_12_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfffffffffULL ) |
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#define | AARCH64_PAR_EL1_PA_51_48(_val) ( ( _val ) << 48 ) |
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#define | AARCH64_PAR_EL1_PA_51_48_SHIFT 48 |
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#define | AARCH64_PAR_EL1_PA_51_48_MASK 0xf000000000000ULL |
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#define | AARCH64_PAR_EL1_PA_51_48_GET(_reg) ( ( ( _reg ) >> 48 ) & 0xfULL ) |
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#define | AARCH64_PAR_EL1_ATTR(_val) ( ( _val ) << 56 ) |
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#define | AARCH64_PAR_EL1_ATTR_SHIFT 56 |
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#define | AARCH64_PAR_EL1_ATTR_MASK 0xff00000000000000ULL |
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#define | AARCH64_PAR_EL1_ATTR_GET(_reg) ( ( ( _reg ) >> 56 ) & 0xffULL ) |
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#define | AARCH64_RGSR_EL1_TAG(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_RGSR_EL1_TAG_SHIFT 0 |
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#define | AARCH64_RGSR_EL1_TAG_MASK 0xfU |
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#define | AARCH64_RGSR_EL1_TAG_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_RGSR_EL1_SEED(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_RGSR_EL1_SEED_SHIFT 8 |
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#define | AARCH64_RGSR_EL1_SEED_MASK 0xffff00U |
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#define | AARCH64_RGSR_EL1_SEED_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xffffU ) |
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#define | AARCH64_RMR_EL1_AA64 0x1U |
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#define | AARCH64_RMR_EL1_RR 0x2U |
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#define | AARCH64_RMR_EL2_AA64 0x1U |
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#define | AARCH64_RMR_EL2_RR 0x2U |
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#define | AARCH64_RMR_EL3_AA64 0x1U |
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#define | AARCH64_RMR_EL3_RR 0x2U |
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#define | AARCH64_SCR_EL3_NS 0x1U |
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#define | AARCH64_SCR_EL3_IRQ 0x2U |
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#define | AARCH64_SCR_EL3_FIQ 0x4U |
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#define | AARCH64_SCR_EL3_EA 0x8U |
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#define | AARCH64_SCR_EL3_SMD 0x80U |
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#define | AARCH64_SCR_EL3_HCE 0x100U |
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#define | AARCH64_SCR_EL3_SIF 0x200U |
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#define | AARCH64_SCR_EL3_RW 0x400U |
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#define | AARCH64_SCR_EL3_ST 0x800U |
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#define | AARCH64_SCR_EL3_TWI 0x1000U |
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#define | AARCH64_SCR_EL3_TWE 0x2000U |
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#define | AARCH64_SCR_EL3_TLOR 0x4000U |
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#define | AARCH64_SCR_EL3_TERR 0x8000U |
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#define | AARCH64_SCR_EL3_APK 0x10000U |
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#define | AARCH64_SCR_EL3_API 0x20000U |
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#define | AARCH64_SCR_EL3_EEL2 0x40000U |
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#define | AARCH64_SCR_EL3_EASE 0x80000U |
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#define | AARCH64_SCR_EL3_NMEA 0x100000U |
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#define | AARCH64_SCR_EL3_FIEN 0x200000U |
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#define | AARCH64_SCR_EL3_ENSCXT 0x2000000U |
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#define | AARCH64_SCR_EL3_ATA 0x4000000U |
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#define | AARCH64_SCR_EL3_FGTEN 0x8000000U |
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#define | AARCH64_SCR_EL3_ECVEN 0x10000000U |
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#define | AARCH64_SCR_EL3_TWEDEN 0x20000000U |
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#define | AARCH64_SCR_EL3_TWEDEL(_val) ( ( _val ) << 30 ) |
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#define | AARCH64_SCR_EL3_TWEDEL_SHIFT 30 |
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#define | AARCH64_SCR_EL3_TWEDEL_MASK 0x3c0000000ULL |
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#define | AARCH64_SCR_EL3_TWEDEL_GET(_reg) ( ( ( _reg ) >> 30 ) & 0xfULL ) |
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#define | AARCH64_SCR_EL3_AMVOFFEN 0x800000000ULL |
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#define | AARCH64_SCTLR_EL1_M 0x1U |
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#define | AARCH64_SCTLR_EL1_A 0x2U |
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#define | AARCH64_SCTLR_EL1_C 0x4U |
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#define | AARCH64_SCTLR_EL1_SA 0x8U |
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#define | AARCH64_SCTLR_EL1_SA0 0x10U |
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#define | AARCH64_SCTLR_EL1_CP15BEN 0x20U |
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#define | AARCH64_SCTLR_EL1_NAA 0x40U |
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#define | AARCH64_SCTLR_EL1_ITD 0x80U |
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#define | AARCH64_SCTLR_EL1_SED 0x100U |
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#define | AARCH64_SCTLR_EL1_UMA 0x200U |
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#define | AARCH64_SCTLR_EL1_ENRCTX 0x400U |
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#define | AARCH64_SCTLR_EL1_EOS 0x800U |
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#define | AARCH64_SCTLR_EL1_I 0x1000U |
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#define | AARCH64_SCTLR_EL1_ENDB 0x2000U |
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#define | AARCH64_SCTLR_EL1_DZE 0x4000U |
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#define | AARCH64_SCTLR_EL1_UCT 0x8000U |
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#define | AARCH64_SCTLR_EL1_NTWI 0x10000U |
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#define | AARCH64_SCTLR_EL1_NTWE 0x40000U |
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#define | AARCH64_SCTLR_EL1_WXN 0x80000U |
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#define | AARCH64_SCTLR_EL1_TSCXT 0x100000U |
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#define | AARCH64_SCTLR_EL1_IESB 0x200000U |
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#define | AARCH64_SCTLR_EL1_EIS 0x400000U |
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#define | AARCH64_SCTLR_EL1_SPAN 0x800000U |
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#define | AARCH64_SCTLR_EL1_E0E 0x1000000U |
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#define | AARCH64_SCTLR_EL1_EE 0x2000000U |
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#define | AARCH64_SCTLR_EL1_UCI 0x4000000U |
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#define | AARCH64_SCTLR_EL1_ENDA 0x8000000U |
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#define | AARCH64_SCTLR_EL1_NTLSMD 0x10000000U |
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#define | AARCH64_SCTLR_EL1_LSMAOE 0x20000000U |
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#define | AARCH64_SCTLR_EL1_ENIB 0x40000000U |
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#define | AARCH64_SCTLR_EL1_ENIA 0x80000000U |
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#define | AARCH64_SCTLR_EL1_BT0 0x800000000ULL |
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#define | AARCH64_SCTLR_EL1_BT1 0x1000000000ULL |
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#define | AARCH64_SCTLR_EL1_ITFSB 0x2000000000ULL |
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#define | AARCH64_SCTLR_EL1_TCF0(_val) ( ( _val ) << 38 ) |
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#define | AARCH64_SCTLR_EL1_TCF0_SHIFT 38 |
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#define | AARCH64_SCTLR_EL1_TCF0_MASK 0xc000000000ULL |
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#define | AARCH64_SCTLR_EL1_TCF0_GET(_reg) ( ( ( _reg ) >> 38 ) & 0x3ULL ) |
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#define | AARCH64_SCTLR_EL1_TCF(_val) ( ( _val ) << 40 ) |
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#define | AARCH64_SCTLR_EL1_TCF_SHIFT 40 |
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#define | AARCH64_SCTLR_EL1_TCF_MASK 0x30000000000ULL |
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#define | AARCH64_SCTLR_EL1_TCF_GET(_reg) ( ( ( _reg ) >> 40 ) & 0x3ULL ) |
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#define | AARCH64_SCTLR_EL1_ATA0 0x40000000000ULL |
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#define | AARCH64_SCTLR_EL1_ATA 0x80000000000ULL |
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#define | AARCH64_SCTLR_EL1_DSSBS 0x100000000000ULL |
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#define | AARCH64_SCTLR_EL1_TWEDEN 0x200000000000ULL |
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#define | AARCH64_SCTLR_EL1_TWEDEL(_val) ( ( _val ) << 46 ) |
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#define | AARCH64_SCTLR_EL1_TWEDEL_SHIFT 46 |
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#define | AARCH64_SCTLR_EL1_TWEDEL_MASK 0x3c00000000000ULL |
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#define | AARCH64_SCTLR_EL1_TWEDEL_GET(_reg) ( ( ( _reg ) >> 46 ) & 0xfULL ) |
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#define | AARCH64_SCTLR_EL2_M 0x1U |
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#define | AARCH64_SCTLR_EL2_A 0x2U |
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#define | AARCH64_SCTLR_EL2_C 0x4U |
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#define | AARCH64_SCTLR_EL2_SA 0x8U |
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#define | AARCH64_SCTLR_EL2_SA0 0x10U |
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#define | AARCH64_SCTLR_EL2_CP15BEN 0x20U |
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#define | AARCH64_SCTLR_EL2_NAA 0x40U |
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#define | AARCH64_SCTLR_EL2_ITD 0x80U |
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#define | AARCH64_SCTLR_EL2_SED 0x100U |
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#define | AARCH64_SCTLR_EL2_ENRCTX 0x400U |
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#define | AARCH64_SCTLR_EL2_EOS 0x800U |
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#define | AARCH64_SCTLR_EL2_I 0x1000U |
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#define | AARCH64_SCTLR_EL2_ENDB 0x2000U |
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#define | AARCH64_SCTLR_EL2_DZE 0x4000U |
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#define | AARCH64_SCTLR_EL2_UCT 0x8000U |
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#define | AARCH64_SCTLR_EL2_NTWI 0x10000U |
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#define | AARCH64_SCTLR_EL2_NTWE 0x40000U |
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#define | AARCH64_SCTLR_EL2_WXN 0x80000U |
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#define | AARCH64_SCTLR_EL2_TSCXT 0x100000U |
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#define | AARCH64_SCTLR_EL2_IESB 0x200000U |
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#define | AARCH64_SCTLR_EL2_EIS 0x400000U |
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#define | AARCH64_SCTLR_EL2_SPAN 0x800000U |
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#define | AARCH64_SCTLR_EL2_E0E 0x1000000U |
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#define | AARCH64_SCTLR_EL2_EE 0x2000000U |
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#define | AARCH64_SCTLR_EL2_UCI 0x4000000U |
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#define | AARCH64_SCTLR_EL2_ENDA 0x8000000U |
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#define | AARCH64_SCTLR_EL2_NTLSMD 0x10000000U |
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#define | AARCH64_SCTLR_EL2_LSMAOE 0x20000000U |
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#define | AARCH64_SCTLR_EL2_ENIB 0x40000000U |
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#define | AARCH64_SCTLR_EL2_ENIA 0x80000000U |
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#define | AARCH64_SCTLR_EL2_BT0 0x800000000ULL |
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#define | AARCH64_SCTLR_EL2_BT 0x1000000000ULL |
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#define | AARCH64_SCTLR_EL2_BT1 0x1000000000ULL |
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#define | AARCH64_SCTLR_EL2_ITFSB 0x2000000000ULL |
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#define | AARCH64_SCTLR_EL2_TCF0(_val) ( ( _val ) << 38 ) |
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#define | AARCH64_SCTLR_EL2_TCF0_SHIFT 38 |
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#define | AARCH64_SCTLR_EL2_TCF0_MASK 0xc000000000ULL |
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#define | AARCH64_SCTLR_EL2_TCF0_GET(_reg) ( ( ( _reg ) >> 38 ) & 0x3ULL ) |
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#define | AARCH64_SCTLR_EL2_TCF(_val) ( ( _val ) << 40 ) |
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#define | AARCH64_SCTLR_EL2_TCF_SHIFT 40 |
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#define | AARCH64_SCTLR_EL2_TCF_MASK 0x30000000000ULL |
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#define | AARCH64_SCTLR_EL2_TCF_GET(_reg) ( ( ( _reg ) >> 40 ) & 0x3ULL ) |
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#define | AARCH64_SCTLR_EL2_ATA0 0x40000000000ULL |
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#define | AARCH64_SCTLR_EL2_ATA 0x80000000000ULL |
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#define | AARCH64_SCTLR_EL2_DSSBS 0x100000000000ULL |
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#define | AARCH64_SCTLR_EL2_TWEDEN 0x200000000000ULL |
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#define | AARCH64_SCTLR_EL2_TWEDEL(_val) ( ( _val ) << 46 ) |
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#define | AARCH64_SCTLR_EL2_TWEDEL_SHIFT 46 |
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#define | AARCH64_SCTLR_EL2_TWEDEL_MASK 0x3c00000000000ULL |
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#define | AARCH64_SCTLR_EL2_TWEDEL_GET(_reg) ( ( ( _reg ) >> 46 ) & 0xfULL ) |
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#define | AARCH64_SCTLR_EL3_M 0x1U |
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#define | AARCH64_SCTLR_EL3_A 0x2U |
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#define | AARCH64_SCTLR_EL3_C 0x4U |
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#define | AARCH64_SCTLR_EL3_SA 0x8U |
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#define | AARCH64_SCTLR_EL3_NAA 0x40U |
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#define | AARCH64_SCTLR_EL3_EOS 0x800U |
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#define | AARCH64_SCTLR_EL3_I 0x1000U |
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#define | AARCH64_SCTLR_EL3_ENDB 0x2000U |
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#define | AARCH64_SCTLR_EL3_WXN 0x80000U |
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#define | AARCH64_SCTLR_EL3_IESB 0x200000U |
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#define | AARCH64_SCTLR_EL3_EIS 0x400000U |
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#define | AARCH64_SCTLR_EL3_EE 0x2000000U |
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#define | AARCH64_SCTLR_EL3_ENDA 0x8000000U |
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#define | AARCH64_SCTLR_EL3_ENIB 0x40000000U |
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#define | AARCH64_SCTLR_EL3_ENIA 0x80000000U |
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#define | AARCH64_SCTLR_EL3_BT 0x1000000000ULL |
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#define | AARCH64_SCTLR_EL3_ITFSB 0x2000000000ULL |
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#define | AARCH64_SCTLR_EL3_TCF(_val) ( ( _val ) << 40 ) |
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#define | AARCH64_SCTLR_EL3_TCF_SHIFT 40 |
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#define | AARCH64_SCTLR_EL3_TCF_MASK 0x30000000000ULL |
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#define | AARCH64_SCTLR_EL3_TCF_GET(_reg) ( ( ( _reg ) >> 40 ) & 0x3ULL ) |
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#define | AARCH64_SCTLR_EL3_ATA 0x80000000000ULL |
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#define | AARCH64_SCTLR_EL3_DSSBS 0x100000000000ULL |
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#define | AARCH64_TCR_EL1_T0SZ(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_TCR_EL1_T0SZ_SHIFT 0 |
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#define | AARCH64_TCR_EL1_T0SZ_MASK 0x3fU |
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#define | AARCH64_TCR_EL1_T0SZ_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3fU ) |
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#define | AARCH64_TCR_EL1_EPD0 0x80U |
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#define | AARCH64_TCR_EL1_IRGN0(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_TCR_EL1_IRGN0_SHIFT 8 |
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#define | AARCH64_TCR_EL1_IRGN0_MASK 0x300U |
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#define | AARCH64_TCR_EL1_IRGN0_GET(_reg) ( ( ( _reg ) >> 8 ) & 0x3U ) |
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#define | AARCH64_TCR_EL1_ORGN0(_val) ( ( _val ) << 10 ) |
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#define | AARCH64_TCR_EL1_ORGN0_SHIFT 10 |
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#define | AARCH64_TCR_EL1_ORGN0_MASK 0xc00U |
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#define | AARCH64_TCR_EL1_ORGN0_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x3U ) |
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#define | AARCH64_TCR_EL1_SH0(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_TCR_EL1_SH0_SHIFT 12 |
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#define | AARCH64_TCR_EL1_SH0_MASK 0x3000U |
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#define | AARCH64_TCR_EL1_SH0_GET(_reg) ( ( ( _reg ) >> 12 ) & 0x3U ) |
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#define | AARCH64_TCR_EL1_TG0(_val) ( ( _val ) << 14 ) |
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#define | AARCH64_TCR_EL1_TG0_SHIFT 14 |
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#define | AARCH64_TCR_EL1_TG0_MASK 0xc000U |
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#define | AARCH64_TCR_EL1_TG0_GET(_reg) ( ( ( _reg ) >> 14 ) & 0x3U ) |
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#define | AARCH64_TCR_EL1_T1SZ(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_TCR_EL1_T1SZ_SHIFT 16 |
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#define | AARCH64_TCR_EL1_T1SZ_MASK 0x3f0000U |
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#define | AARCH64_TCR_EL1_T1SZ_GET(_reg) ( ( ( _reg ) >> 16 ) & 0x3fU ) |
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#define | AARCH64_TCR_EL1_A1 0x400000U |
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#define | AARCH64_TCR_EL1_EPD1 0x800000U |
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#define | AARCH64_TCR_EL1_IRGN1(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_TCR_EL1_IRGN1_SHIFT 24 |
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#define | AARCH64_TCR_EL1_IRGN1_MASK 0x3000000U |
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#define | AARCH64_TCR_EL1_IRGN1_GET(_reg) ( ( ( _reg ) >> 24 ) & 0x3U ) |
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#define | AARCH64_TCR_EL1_ORGN1(_val) ( ( _val ) << 26 ) |
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#define | AARCH64_TCR_EL1_ORGN1_SHIFT 26 |
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#define | AARCH64_TCR_EL1_ORGN1_MASK 0xc000000U |
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#define | AARCH64_TCR_EL1_ORGN1_GET(_reg) ( ( ( _reg ) >> 26 ) & 0x3U ) |
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#define | AARCH64_TCR_EL1_SH1(_val) ( ( _val ) << 28 ) |
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#define | AARCH64_TCR_EL1_SH1_SHIFT 28 |
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#define | AARCH64_TCR_EL1_SH1_MASK 0x30000000U |
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#define | AARCH64_TCR_EL1_SH1_GET(_reg) ( ( ( _reg ) >> 28 ) & 0x3U ) |
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#define | AARCH64_TCR_EL1_TG1(_val) ( ( _val ) << 30 ) |
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#define | AARCH64_TCR_EL1_TG1_SHIFT 30 |
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#define | AARCH64_TCR_EL1_TG1_MASK 0xc0000000U |
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#define | AARCH64_TCR_EL1_TG1_GET(_reg) ( ( ( _reg ) >> 30 ) & 0x3U ) |
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#define | AARCH64_TCR_EL1_IPS(_val) ( ( _val ) << 32 ) |
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#define | AARCH64_TCR_EL1_IPS_SHIFT 32 |
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#define | AARCH64_TCR_EL1_IPS_MASK 0x700000000ULL |
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#define | AARCH64_TCR_EL1_IPS_GET(_reg) ( ( ( _reg ) >> 32 ) & 0x7ULL ) |
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#define | AARCH64_TCR_EL1_AS 0x1000000000ULL |
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#define | AARCH64_TCR_EL1_TBI0 0x2000000000ULL |
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#define | AARCH64_TCR_EL1_TBI1 0x4000000000ULL |
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#define | AARCH64_TCR_EL1_HA 0x8000000000ULL |
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#define | AARCH64_TCR_EL1_HD 0x10000000000ULL |
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#define | AARCH64_TCR_EL1_HPD0 0x20000000000ULL |
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#define | AARCH64_TCR_EL1_HPD1 0x40000000000ULL |
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#define | AARCH64_TCR_EL1_HWU059 0x80000000000ULL |
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#define | AARCH64_TCR_EL1_HWU060 0x100000000000ULL |
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#define | AARCH64_TCR_EL1_HWU061 0x200000000000ULL |
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#define | AARCH64_TCR_EL1_HWU062 0x400000000000ULL |
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#define | AARCH64_TCR_EL1_HWU159 0x800000000000ULL |
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#define | AARCH64_TCR_EL1_HWU160 0x1000000000000ULL |
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#define | AARCH64_TCR_EL1_HWU161 0x2000000000000ULL |
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#define | AARCH64_TCR_EL1_HWU162 0x4000000000000ULL |
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#define | AARCH64_TCR_EL1_TBID0 0x8000000000000ULL |
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#define | AARCH64_TCR_EL1_TBID1 0x10000000000000ULL |
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#define | AARCH64_TCR_EL1_NFD0 0x20000000000000ULL |
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#define | AARCH64_TCR_EL1_NFD1 0x40000000000000ULL |
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#define | AARCH64_TCR_EL1_E0PD0 0x80000000000000ULL |
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#define | AARCH64_TCR_EL1_E0PD1 0x100000000000000ULL |
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#define | AARCH64_TCR_EL1_TCMA0 0x200000000000000ULL |
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#define | AARCH64_TCR_EL1_TCMA1 0x400000000000000ULL |
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#define | AARCH64_TCR_EL2_T0SZ(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_TCR_EL2_T0SZ_SHIFT 0 |
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#define | AARCH64_TCR_EL2_T0SZ_MASK 0x3fU |
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#define | AARCH64_TCR_EL2_T0SZ_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3fU ) |
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#define | AARCH64_TCR_EL2_EPD0 0x80U |
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#define | AARCH64_TCR_EL2_IRGN0(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_TCR_EL2_IRGN0_SHIFT 8 |
| |
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#define | AARCH64_TCR_EL2_IRGN0_MASK 0x300U |
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#define | AARCH64_TCR_EL2_IRGN0_GET(_reg) ( ( ( _reg ) >> 8 ) & 0x3U ) |
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#define | AARCH64_TCR_EL2_ORGN0(_val) ( ( _val ) << 10 ) |
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#define | AARCH64_TCR_EL2_ORGN0_SHIFT 10 |
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#define | AARCH64_TCR_EL2_ORGN0_MASK 0xc00U |
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#define | AARCH64_TCR_EL2_ORGN0_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x3U ) |
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#define | AARCH64_TCR_EL2_SH0(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_TCR_EL2_SH0_SHIFT 12 |
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#define | AARCH64_TCR_EL2_SH0_MASK 0x3000U |
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#define | AARCH64_TCR_EL2_SH0_GET(_reg) ( ( ( _reg ) >> 12 ) & 0x3U ) |
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#define | AARCH64_TCR_EL2_TG0(_val) ( ( _val ) << 14 ) |
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#define | AARCH64_TCR_EL2_TG0_SHIFT 14 |
| |
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#define | AARCH64_TCR_EL2_TG0_MASK 0xc000U |
| |
|
#define | AARCH64_TCR_EL2_TG0_GET(_reg) ( ( ( _reg ) >> 14 ) & 0x3U ) |
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#define | AARCH64_TCR_EL2_PS(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_TCR_EL2_PS_SHIFT 16 |
| |
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#define | AARCH64_TCR_EL2_PS_MASK 0x70000U |
| |
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#define | AARCH64_TCR_EL2_PS_GET(_reg) ( ( ( _reg ) >> 16 ) & 0x7U ) |
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#define | AARCH64_TCR_EL2_T1SZ(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_TCR_EL2_T1SZ_SHIFT 16 |
| |
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#define | AARCH64_TCR_EL2_T1SZ_MASK 0x3f0000U |
| |
|
#define | AARCH64_TCR_EL2_T1SZ_GET(_reg) ( ( ( _reg ) >> 16 ) & 0x3fU ) |
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#define | AARCH64_TCR_EL2_TBI 0x100000U |
| |
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#define | AARCH64_TCR_EL2_HA_0 0x200000U |
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#define | AARCH64_TCR_EL2_A1 0x400000U |
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#define | AARCH64_TCR_EL2_HD_0 0x400000U |
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#define | AARCH64_TCR_EL2_EPD1 0x800000U |
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#define | AARCH64_TCR_EL2_HPD 0x1000000U |
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#define | AARCH64_TCR_EL2_IRGN1(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_TCR_EL2_IRGN1_SHIFT 24 |
| |
|
#define | AARCH64_TCR_EL2_IRGN1_MASK 0x3000000U |
| |
|
#define | AARCH64_TCR_EL2_IRGN1_GET(_reg) ( ( ( _reg ) >> 24 ) & 0x3U ) |
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#define | AARCH64_TCR_EL2_HWU59 0x2000000U |
| |
|
#define | AARCH64_TCR_EL2_HWU60 0x4000000U |
| |
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#define | AARCH64_TCR_EL2_ORGN1(_val) ( ( _val ) << 26 ) |
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#define | AARCH64_TCR_EL2_ORGN1_SHIFT 26 |
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#define | AARCH64_TCR_EL2_ORGN1_MASK 0xc000000U |
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#define | AARCH64_TCR_EL2_ORGN1_GET(_reg) ( ( ( _reg ) >> 26 ) & 0x3U ) |
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#define | AARCH64_TCR_EL2_HWU61 0x8000000U |
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#define | AARCH64_TCR_EL2_HWU62 0x10000000U |
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#define | AARCH64_TCR_EL2_SH1(_val) ( ( _val ) << 28 ) |
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#define | AARCH64_TCR_EL2_SH1_SHIFT 28 |
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#define | AARCH64_TCR_EL2_SH1_MASK 0x30000000U |
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#define | AARCH64_TCR_EL2_SH1_GET(_reg) ( ( ( _reg ) >> 28 ) & 0x3U ) |
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#define | AARCH64_TCR_EL2_TBID 0x20000000U |
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#define | AARCH64_TCR_EL2_TCMA 0x40000000U |
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#define | AARCH64_TCR_EL2_TG1(_val) ( ( _val ) << 30 ) |
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#define | AARCH64_TCR_EL2_TG1_SHIFT 30 |
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#define | AARCH64_TCR_EL2_TG1_MASK 0xc0000000U |
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#define | AARCH64_TCR_EL2_TG1_GET(_reg) ( ( ( _reg ) >> 30 ) & 0x3U ) |
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#define | AARCH64_TCR_EL2_IPS(_val) ( ( _val ) << 32 ) |
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#define | AARCH64_TCR_EL2_IPS_SHIFT 32 |
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#define | AARCH64_TCR_EL2_IPS_MASK 0x700000000ULL |
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#define | AARCH64_TCR_EL2_IPS_GET(_reg) ( ( ( _reg ) >> 32 ) & 0x7ULL ) |
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#define | AARCH64_TCR_EL2_AS 0x1000000000ULL |
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#define | AARCH64_TCR_EL2_TBI0 0x2000000000ULL |
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#define | AARCH64_TCR_EL2_TBI1 0x4000000000ULL |
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#define | AARCH64_TCR_EL2_HA_1 0x8000000000ULL |
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#define | AARCH64_TCR_EL2_HD_1 0x10000000000ULL |
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#define | AARCH64_TCR_EL2_HPD0 0x20000000000ULL |
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#define | AARCH64_TCR_EL2_HPD1 0x40000000000ULL |
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#define | AARCH64_TCR_EL2_HWU059 0x80000000000ULL |
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#define | AARCH64_TCR_EL2_HWU060 0x100000000000ULL |
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#define | AARCH64_TCR_EL2_HWU061 0x200000000000ULL |
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#define | AARCH64_TCR_EL2_HWU062 0x400000000000ULL |
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#define | AARCH64_TCR_EL2_HWU159 0x800000000000ULL |
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#define | AARCH64_TCR_EL2_HWU160 0x1000000000000ULL |
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#define | AARCH64_TCR_EL2_HWU161 0x2000000000000ULL |
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#define | AARCH64_TCR_EL2_HWU162 0x4000000000000ULL |
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#define | AARCH64_TCR_EL2_TBID0 0x8000000000000ULL |
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#define | AARCH64_TCR_EL2_TBID1 0x10000000000000ULL |
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#define | AARCH64_TCR_EL2_NFD0 0x20000000000000ULL |
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#define | AARCH64_TCR_EL2_NFD1 0x40000000000000ULL |
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#define | AARCH64_TCR_EL2_E0PD0 0x80000000000000ULL |
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#define | AARCH64_TCR_EL2_E0PD1 0x100000000000000ULL |
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#define | AARCH64_TCR_EL2_TCMA0 0x200000000000000ULL |
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#define | AARCH64_TCR_EL2_TCMA1 0x400000000000000ULL |
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#define | AARCH64_TCR_EL3_T0SZ(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_TCR_EL3_T0SZ_SHIFT 0 |
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#define | AARCH64_TCR_EL3_T0SZ_MASK 0x3fU |
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#define | AARCH64_TCR_EL3_T0SZ_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3fU ) |
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#define | AARCH64_TCR_EL3_IRGN0(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_TCR_EL3_IRGN0_SHIFT 8 |
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#define | AARCH64_TCR_EL3_IRGN0_MASK 0x300U |
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#define | AARCH64_TCR_EL3_IRGN0_GET(_reg) ( ( ( _reg ) >> 8 ) & 0x3U ) |
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#define | AARCH64_TCR_EL3_ORGN0(_val) ( ( _val ) << 10 ) |
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#define | AARCH64_TCR_EL3_ORGN0_SHIFT 10 |
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#define | AARCH64_TCR_EL3_ORGN0_MASK 0xc00U |
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#define | AARCH64_TCR_EL3_ORGN0_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x3U ) |
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#define | AARCH64_TCR_EL3_SH0(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_TCR_EL3_SH0_SHIFT 12 |
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#define | AARCH64_TCR_EL3_SH0_MASK 0x3000U |
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#define | AARCH64_TCR_EL3_SH0_GET(_reg) ( ( ( _reg ) >> 12 ) & 0x3U ) |
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#define | AARCH64_TCR_EL3_TG0(_val) ( ( _val ) << 14 ) |
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#define | AARCH64_TCR_EL3_TG0_SHIFT 14 |
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#define | AARCH64_TCR_EL3_TG0_MASK 0xc000U |
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#define | AARCH64_TCR_EL3_TG0_GET(_reg) ( ( ( _reg ) >> 14 ) & 0x3U ) |
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#define | AARCH64_TCR_EL3_PS(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_TCR_EL3_PS_SHIFT 16 |
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#define | AARCH64_TCR_EL3_PS_MASK 0x70000U |
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#define | AARCH64_TCR_EL3_PS_GET(_reg) ( ( ( _reg ) >> 16 ) & 0x7U ) |
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#define | AARCH64_TCR_EL3_TBI 0x100000U |
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#define | AARCH64_TCR_EL3_HA 0x200000U |
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#define | AARCH64_TCR_EL3_HD 0x400000U |
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#define | AARCH64_TCR_EL3_HPD 0x1000000U |
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#define | AARCH64_TCR_EL3_HWU59 0x2000000U |
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#define | AARCH64_TCR_EL3_HWU60 0x4000000U |
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#define | AARCH64_TCR_EL3_HWU61 0x8000000U |
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#define | AARCH64_TCR_EL3_HWU62 0x10000000U |
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#define | AARCH64_TCR_EL3_TBID 0x20000000U |
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#define | AARCH64_TCR_EL3_TCMA 0x40000000U |
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#define | AARCH64_TFSRE0_EL1_TF0 0x1U |
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#define | AARCH64_TFSRE0_EL1_TF1 0x2U |
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#define | AARCH64_TFSR_EL1_TF0 0x1U |
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#define | AARCH64_TFSR_EL1_TF1 0x2U |
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#define | AARCH64_TFSR_EL2_TF0 0x1U |
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#define | AARCH64_TFSR_EL2_TF1 0x2U |
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#define | AARCH64_TFSR_EL3_TF0 0x1U |
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#define | AARCH64_TTBR0_EL1_CNP 0x1U |
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#define | AARCH64_TTBR0_EL1_BADDR(_val) ( ( _val ) << 1 ) |
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#define | AARCH64_TTBR0_EL1_BADDR_SHIFT 1 |
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#define | AARCH64_TTBR0_EL1_BADDR_MASK 0xfffffffffffeULL |
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#define | AARCH64_TTBR0_EL1_BADDR_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x7fffffffffffULL ) |
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#define | AARCH64_TTBR0_EL1_ASID(_val) ( ( _val ) << 48 ) |
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#define | AARCH64_TTBR0_EL1_ASID_SHIFT 48 |
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#define | AARCH64_TTBR0_EL1_ASID_MASK 0xffff000000000000ULL |
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#define | AARCH64_TTBR0_EL1_ASID_GET(_reg) ( ( ( _reg ) >> 48 ) & 0xffffULL ) |
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#define | AARCH64_TTBR0_EL2_CNP 0x1U |
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#define | AARCH64_TTBR0_EL2_BADDR(_val) ( ( _val ) << 1 ) |
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#define | AARCH64_TTBR0_EL2_BADDR_SHIFT 1 |
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#define | AARCH64_TTBR0_EL2_BADDR_MASK 0xfffffffffffeULL |
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#define | AARCH64_TTBR0_EL2_BADDR_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x7fffffffffffULL ) |
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#define | AARCH64_TTBR0_EL2_ASID(_val) ( ( _val ) << 48 ) |
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#define | AARCH64_TTBR0_EL2_ASID_SHIFT 48 |
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#define | AARCH64_TTBR0_EL2_ASID_MASK 0xffff000000000000ULL |
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#define | AARCH64_TTBR0_EL2_ASID_GET(_reg) ( ( ( _reg ) >> 48 ) & 0xffffULL ) |
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#define | AARCH64_TTBR0_EL3_CNP 0x1U |
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#define | AARCH64_TTBR0_EL3_BADDR(_val) ( ( _val ) << 1 ) |
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#define | AARCH64_TTBR0_EL3_BADDR_SHIFT 1 |
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#define | AARCH64_TTBR0_EL3_BADDR_MASK 0xfffffffffffeULL |
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#define | AARCH64_TTBR0_EL3_BADDR_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x7fffffffffffULL ) |
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#define | AARCH64_TTBR1_EL1_CNP 0x1U |
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#define | AARCH64_TTBR1_EL1_BADDR(_val) ( ( _val ) << 1 ) |
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#define | AARCH64_TTBR1_EL1_BADDR_SHIFT 1 |
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#define | AARCH64_TTBR1_EL1_BADDR_MASK 0xfffffffffffeULL |
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#define | AARCH64_TTBR1_EL1_BADDR_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x7fffffffffffULL ) |
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#define | AARCH64_TTBR1_EL1_ASID(_val) ( ( _val ) << 48 ) |
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#define | AARCH64_TTBR1_EL1_ASID_SHIFT 48 |
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#define | AARCH64_TTBR1_EL1_ASID_MASK 0xffff000000000000ULL |
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#define | AARCH64_TTBR1_EL1_ASID_GET(_reg) ( ( ( _reg ) >> 48 ) & 0xffffULL ) |
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#define | AARCH64_TTBR1_EL2_CNP 0x1U |
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#define | AARCH64_TTBR1_EL2_BADDR(_val) ( ( _val ) << 1 ) |
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#define | AARCH64_TTBR1_EL2_BADDR_SHIFT 1 |
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#define | AARCH64_TTBR1_EL2_BADDR_MASK 0xfffffffffffeULL |
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#define | AARCH64_TTBR1_EL2_BADDR_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x7fffffffffffULL ) |
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#define | AARCH64_TTBR1_EL2_ASID(_val) ( ( _val ) << 48 ) |
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#define | AARCH64_TTBR1_EL2_ASID_SHIFT 48 |
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#define | AARCH64_TTBR1_EL2_ASID_MASK 0xffff000000000000ULL |
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#define | AARCH64_TTBR1_EL2_ASID_GET(_reg) ( ( ( _reg ) >> 48 ) & 0xffffULL ) |
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#define | AARCH64_VMPIDR_EL2_AFF0(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_VMPIDR_EL2_AFF0_SHIFT 0 |
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#define | AARCH64_VMPIDR_EL2_AFF0_MASK 0xffU |
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#define | AARCH64_VMPIDR_EL2_AFF0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU ) |
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#define | AARCH64_VMPIDR_EL2_AFF1(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_VMPIDR_EL2_AFF1_SHIFT 8 |
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#define | AARCH64_VMPIDR_EL2_AFF1_MASK 0xff00U |
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#define | AARCH64_VMPIDR_EL2_AFF1_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xffU ) |
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#define | AARCH64_VMPIDR_EL2_AFF2(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_VMPIDR_EL2_AFF2_SHIFT 16 |
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#define | AARCH64_VMPIDR_EL2_AFF2_MASK 0xff0000U |
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#define | AARCH64_VMPIDR_EL2_AFF2_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xffU ) |
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#define | AARCH64_VMPIDR_EL2_MT 0x1000000U |
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#define | AARCH64_VMPIDR_EL2_U 0x40000000U |
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#define | AARCH64_VMPIDR_EL2_AFF3(_val) ( ( _val ) << 32 ) |
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#define | AARCH64_VMPIDR_EL2_AFF3_SHIFT 32 |
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#define | AARCH64_VMPIDR_EL2_AFF3_MASK 0xff00000000ULL |
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#define | AARCH64_VMPIDR_EL2_AFF3_GET(_reg) ( ( ( _reg ) >> 32 ) & 0xffULL ) |
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#define | AARCH64_VNCR_EL2_BADDR(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_VNCR_EL2_BADDR_SHIFT 12 |
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#define | AARCH64_VNCR_EL2_BADDR_MASK 0x1ffffffffff000ULL |
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#define | AARCH64_VNCR_EL2_BADDR_GET(_reg) ( ( ( _reg ) >> 12 ) & 0x1ffffffffffULL ) |
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#define | AARCH64_VNCR_EL2_RESS(_val) ( ( _val ) << 53 ) |
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#define | AARCH64_VNCR_EL2_RESS_SHIFT 53 |
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#define | AARCH64_VNCR_EL2_RESS_MASK 0xffe0000000000000ULL |
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#define | AARCH64_VNCR_EL2_RESS_GET(_reg) ( ( ( _reg ) >> 53 ) & 0x7ffULL ) |
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#define | AARCH64_VPIDR_EL2_REVISION(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_VPIDR_EL2_REVISION_SHIFT 0 |
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#define | AARCH64_VPIDR_EL2_REVISION_MASK 0xfU |
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#define | AARCH64_VPIDR_EL2_REVISION_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_VPIDR_EL2_PARTNUM(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_VPIDR_EL2_PARTNUM_SHIFT 4 |
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#define | AARCH64_VPIDR_EL2_PARTNUM_MASK 0xfff0U |
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#define | AARCH64_VPIDR_EL2_PARTNUM_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfffU ) |
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#define | AARCH64_VPIDR_EL2_ARCHITECTURE(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_VPIDR_EL2_ARCHITECTURE_SHIFT 16 |
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#define | AARCH64_VPIDR_EL2_ARCHITECTURE_MASK 0xf0000U |
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#define | AARCH64_VPIDR_EL2_ARCHITECTURE_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_VPIDR_EL2_VARIANT(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_VPIDR_EL2_VARIANT_SHIFT 20 |
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#define | AARCH64_VPIDR_EL2_VARIANT_MASK 0xf00000U |
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#define | AARCH64_VPIDR_EL2_VARIANT_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_VPIDR_EL2_IMPLEMENTER(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_VPIDR_EL2_IMPLEMENTER_SHIFT 24 |
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#define | AARCH64_VPIDR_EL2_IMPLEMENTER_MASK 0xff000000U |
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#define | AARCH64_VPIDR_EL2_IMPLEMENTER_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xffU ) |
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#define | AARCH64_VSTCR_EL2_T0SZ(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_VSTCR_EL2_T0SZ_SHIFT 0 |
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#define | AARCH64_VSTCR_EL2_T0SZ_MASK 0x3fU |
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#define | AARCH64_VSTCR_EL2_T0SZ_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3fU ) |
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#define | AARCH64_VSTCR_EL2_SL0(_val) ( ( _val ) << 6 ) |
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#define | AARCH64_VSTCR_EL2_SL0_SHIFT 6 |
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#define | AARCH64_VSTCR_EL2_SL0_MASK 0xc0U |
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#define | AARCH64_VSTCR_EL2_SL0_GET(_reg) ( ( ( _reg ) >> 6 ) & 0x3U ) |
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#define | AARCH64_VSTCR_EL2_TG0(_val) ( ( _val ) << 14 ) |
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#define | AARCH64_VSTCR_EL2_TG0_SHIFT 14 |
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#define | AARCH64_VSTCR_EL2_TG0_MASK 0xc000U |
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#define | AARCH64_VSTCR_EL2_TG0_GET(_reg) ( ( ( _reg ) >> 14 ) & 0x3U ) |
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#define | AARCH64_VSTCR_EL2_SW 0x20000000U |
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#define | AARCH64_VSTCR_EL2_SA 0x40000000U |
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#define | AARCH64_VSTTBR_EL2_CNP 0x1U |
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#define | AARCH64_VSTTBR_EL2_BADDR(_val) ( ( _val ) << 1 ) |
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#define | AARCH64_VSTTBR_EL2_BADDR_SHIFT 1 |
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#define | AARCH64_VSTTBR_EL2_BADDR_MASK 0xfffffffffffeULL |
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#define | AARCH64_VSTTBR_EL2_BADDR_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x7fffffffffffULL ) |
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#define | AARCH64_VTCR_EL2_T0SZ(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_VTCR_EL2_T0SZ_SHIFT 0 |
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#define | AARCH64_VTCR_EL2_T0SZ_MASK 0x3fU |
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#define | AARCH64_VTCR_EL2_T0SZ_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3fU ) |
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#define | AARCH64_VTCR_EL2_SL0(_val) ( ( _val ) << 6 ) |
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#define | AARCH64_VTCR_EL2_SL0_SHIFT 6 |
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#define | AARCH64_VTCR_EL2_SL0_MASK 0xc0U |
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#define | AARCH64_VTCR_EL2_SL0_GET(_reg) ( ( ( _reg ) >> 6 ) & 0x3U ) |
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#define | AARCH64_VTCR_EL2_IRGN0(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_VTCR_EL2_IRGN0_SHIFT 8 |
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#define | AARCH64_VTCR_EL2_IRGN0_MASK 0x300U |
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#define | AARCH64_VTCR_EL2_IRGN0_GET(_reg) ( ( ( _reg ) >> 8 ) & 0x3U ) |
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#define | AARCH64_VTCR_EL2_ORGN0(_val) ( ( _val ) << 10 ) |
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#define | AARCH64_VTCR_EL2_ORGN0_SHIFT 10 |
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#define | AARCH64_VTCR_EL2_ORGN0_MASK 0xc00U |
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#define | AARCH64_VTCR_EL2_ORGN0_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x3U ) |
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#define | AARCH64_VTCR_EL2_SH0(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_VTCR_EL2_SH0_SHIFT 12 |
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#define | AARCH64_VTCR_EL2_SH0_MASK 0x3000U |
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#define | AARCH64_VTCR_EL2_SH0_GET(_reg) ( ( ( _reg ) >> 12 ) & 0x3U ) |
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#define | AARCH64_VTCR_EL2_TG0(_val) ( ( _val ) << 14 ) |
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#define | AARCH64_VTCR_EL2_TG0_SHIFT 14 |
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#define | AARCH64_VTCR_EL2_TG0_MASK 0xc000U |
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#define | AARCH64_VTCR_EL2_TG0_GET(_reg) ( ( ( _reg ) >> 14 ) & 0x3U ) |
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#define | AARCH64_VTCR_EL2_PS(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_VTCR_EL2_PS_SHIFT 16 |
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#define | AARCH64_VTCR_EL2_PS_MASK 0x70000U |
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#define | AARCH64_VTCR_EL2_PS_GET(_reg) ( ( ( _reg ) >> 16 ) & 0x7U ) |
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#define | AARCH64_VTCR_EL2_VS 0x80000U |
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#define | AARCH64_VTCR_EL2_HA 0x200000U |
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#define | AARCH64_VTCR_EL2_HD 0x400000U |
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#define | AARCH64_VTCR_EL2_HWU59 0x2000000U |
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#define | AARCH64_VTCR_EL2_HWU60 0x4000000U |
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#define | AARCH64_VTCR_EL2_HWU61 0x8000000U |
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#define | AARCH64_VTCR_EL2_HWU62 0x10000000U |
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#define | AARCH64_VTCR_EL2_NSW 0x20000000U |
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#define | AARCH64_VTCR_EL2_NSA 0x40000000U |
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#define | AARCH64_VTTBR_EL2_CNP 0x1U |
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#define | AARCH64_VTTBR_EL2_BADDR(_val) ( ( _val ) << 1 ) |
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#define | AARCH64_VTTBR_EL2_BADDR_SHIFT 1 |
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#define | AARCH64_VTTBR_EL2_BADDR_MASK 0xfffffffffffeULL |
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#define | AARCH64_VTTBR_EL2_BADDR_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x7fffffffffffULL ) |
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#define | AARCH64_VTTBR_EL2_VMID_7_0(_val) ( ( _val ) << 48 ) |
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#define | AARCH64_VTTBR_EL2_VMID_7_0_SHIFT 48 |
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#define | AARCH64_VTTBR_EL2_VMID_7_0_MASK 0xff000000000000ULL |
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#define | AARCH64_VTTBR_EL2_VMID_7_0_GET(_reg) ( ( ( _reg ) >> 48 ) & 0xffULL ) |
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#define | AARCH64_VTTBR_EL2_VMID_15_8(_val) ( ( _val ) << 56 ) |
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#define | AARCH64_VTTBR_EL2_VMID_15_8_SHIFT 56 |
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#define | AARCH64_VTTBR_EL2_VMID_15_8_MASK 0xff00000000000000ULL |
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#define | AARCH64_VTTBR_EL2_VMID_15_8_GET(_reg) ( ( ( _reg ) >> 56 ) & 0xffULL ) |
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#define | AARCH64_DBGAUTHSTATUS_EL1_NSID(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_DBGAUTHSTATUS_EL1_NSID_SHIFT 0 |
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#define | AARCH64_DBGAUTHSTATUS_EL1_NSID_MASK 0x3U |
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#define | AARCH64_DBGAUTHSTATUS_EL1_NSID_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3U ) |
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#define | AARCH64_DBGAUTHSTATUS_EL1_NSNID(_val) ( ( _val ) << 2 ) |
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#define | AARCH64_DBGAUTHSTATUS_EL1_NSNID_SHIFT 2 |
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#define | AARCH64_DBGAUTHSTATUS_EL1_NSNID_MASK 0xcU |
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#define | AARCH64_DBGAUTHSTATUS_EL1_NSNID_GET(_reg) ( ( ( _reg ) >> 2 ) & 0x3U ) |
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#define | AARCH64_DBGAUTHSTATUS_EL1_SID(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_DBGAUTHSTATUS_EL1_SID_SHIFT 4 |
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#define | AARCH64_DBGAUTHSTATUS_EL1_SID_MASK 0x30U |
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#define | AARCH64_DBGAUTHSTATUS_EL1_SID_GET(_reg) ( ( ( _reg ) >> 4 ) & 0x3U ) |
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#define | AARCH64_DBGAUTHSTATUS_EL1_SNID(_val) ( ( _val ) << 6 ) |
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#define | AARCH64_DBGAUTHSTATUS_EL1_SNID_SHIFT 6 |
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#define | AARCH64_DBGAUTHSTATUS_EL1_SNID_MASK 0xc0U |
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#define | AARCH64_DBGAUTHSTATUS_EL1_SNID_GET(_reg) ( ( ( _reg ) >> 6 ) & 0x3U ) |
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#define | AARCH64_DBGBCR_N_EL1_E 0x1U |
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#define | AARCH64_DBGBCR_N_EL1_PMC(_val) ( ( _val ) << 1 ) |
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#define | AARCH64_DBGBCR_N_EL1_PMC_SHIFT 1 |
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#define | AARCH64_DBGBCR_N_EL1_PMC_MASK 0x6U |
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#define | AARCH64_DBGBCR_N_EL1_PMC_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x3U ) |
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#define | AARCH64_DBGBCR_N_EL1_BAS(_val) ( ( _val ) << 5 ) |
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#define | AARCH64_DBGBCR_N_EL1_BAS_SHIFT 5 |
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#define | AARCH64_DBGBCR_N_EL1_BAS_MASK 0x1e0U |
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#define | AARCH64_DBGBCR_N_EL1_BAS_GET(_reg) ( ( ( _reg ) >> 5 ) & 0xfU ) |
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#define | AARCH64_DBGBCR_N_EL1_HMC 0x2000U |
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#define | AARCH64_DBGBCR_N_EL1_SSC(_val) ( ( _val ) << 14 ) |
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#define | AARCH64_DBGBCR_N_EL1_SSC_SHIFT 14 |
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#define | AARCH64_DBGBCR_N_EL1_SSC_MASK 0xc000U |
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#define | AARCH64_DBGBCR_N_EL1_SSC_GET(_reg) ( ( ( _reg ) >> 14 ) & 0x3U ) |
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#define | AARCH64_DBGBCR_N_EL1_LBN(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_DBGBCR_N_EL1_LBN_SHIFT 16 |
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#define | AARCH64_DBGBCR_N_EL1_LBN_MASK 0xf0000U |
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#define | AARCH64_DBGBCR_N_EL1_LBN_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_DBGBCR_N_EL1_BT(_val) ( ( _val ) << 20 ) |
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#define | AARCH64_DBGBCR_N_EL1_BT_SHIFT 20 |
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#define | AARCH64_DBGBCR_N_EL1_BT_MASK 0xf00000U |
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#define | AARCH64_DBGBCR_N_EL1_BT_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU ) |
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#define | AARCH64_DBGBVR_N_EL1_CONTEXTID(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_DBGBVR_N_EL1_CONTEXTID_SHIFT 0 |
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#define | AARCH64_DBGBVR_N_EL1_CONTEXTID_MASK 0xffffffffU |
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#define | AARCH64_DBGBVR_N_EL1_CONTEXTID_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffffffU ) |
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#define | AARCH64_DBGBVR_N_EL1_VA_48_2(_val) ( ( _val ) << 2 ) |
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#define | AARCH64_DBGBVR_N_EL1_VA_48_2_SHIFT 2 |
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#define | AARCH64_DBGBVR_N_EL1_VA_48_2_MASK 0x1fffffffffffcULL |
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#define | AARCH64_DBGBVR_N_EL1_VA_48_2_GET(_reg) ( ( ( _reg ) >> 2 ) & 0x7fffffffffffULL ) |
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#define | AARCH64_DBGBVR_N_EL1_VMID_7_0(_val) ( ( _val ) << 32 ) |
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#define | AARCH64_DBGBVR_N_EL1_VMID_7_0_SHIFT 32 |
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#define | AARCH64_DBGBVR_N_EL1_VMID_7_0_MASK 0xff00000000ULL |
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#define | AARCH64_DBGBVR_N_EL1_VMID_7_0_GET(_reg) ( ( ( _reg ) >> 32 ) & 0xffULL ) |
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#define | AARCH64_DBGBVR_N_EL1_CONTEXTID2(_val) ( ( _val ) << 32 ) |
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#define | AARCH64_DBGBVR_N_EL1_CONTEXTID2_SHIFT 32 |
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#define | AARCH64_DBGBVR_N_EL1_CONTEXTID2_MASK 0xffffffff00000000ULL |
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#define | AARCH64_DBGBVR_N_EL1_CONTEXTID2_GET(_reg) ( ( ( _reg ) >> 32 ) & 0xffffffffULL ) |
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#define | AARCH64_DBGBVR_N_EL1_VMID_15_8(_val) ( ( _val ) << 40 ) |
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#define | AARCH64_DBGBVR_N_EL1_VMID_15_8_SHIFT 40 |
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#define | AARCH64_DBGBVR_N_EL1_VMID_15_8_MASK 0xff0000000000ULL |
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#define | AARCH64_DBGBVR_N_EL1_VMID_15_8_GET(_reg) ( ( ( _reg ) >> 40 ) & 0xffULL ) |
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#define | AARCH64_DBGBVR_N_EL1_VA_52_49(_val) ( ( _val ) << 49 ) |
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#define | AARCH64_DBGBVR_N_EL1_VA_52_49_SHIFT 49 |
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#define | AARCH64_DBGBVR_N_EL1_VA_52_49_MASK 0x1e000000000000ULL |
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#define | AARCH64_DBGBVR_N_EL1_VA_52_49_GET(_reg) ( ( ( _reg ) >> 49 ) & 0xfULL ) |
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#define | AARCH64_DBGBVR_N_EL1_RESS_14_4(_val) ( ( _val ) << 53 ) |
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#define | AARCH64_DBGBVR_N_EL1_RESS_14_4_SHIFT 53 |
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#define | AARCH64_DBGBVR_N_EL1_RESS_14_4_MASK 0xffe0000000000000ULL |
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#define | AARCH64_DBGBVR_N_EL1_RESS_14_4_GET(_reg) ( ( ( _reg ) >> 53 ) & 0x7ffULL ) |
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#define | AARCH64_DBGCLAIMCLR_EL1_CLAIM(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_DBGCLAIMCLR_EL1_CLAIM_SHIFT 0 |
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#define | AARCH64_DBGCLAIMCLR_EL1_CLAIM_MASK 0xffU |
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#define | AARCH64_DBGCLAIMCLR_EL1_CLAIM_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU ) |
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#define | AARCH64_DBGCLAIMSET_EL1_CLAIM(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_DBGCLAIMSET_EL1_CLAIM_SHIFT 0 |
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#define | AARCH64_DBGCLAIMSET_EL1_CLAIM_MASK 0xffU |
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#define | AARCH64_DBGCLAIMSET_EL1_CLAIM_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU ) |
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#define | AARCH64_DBGDTR_EL0_LOWWORD(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_DBGDTR_EL0_LOWWORD_SHIFT 0 |
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#define | AARCH64_DBGDTR_EL0_LOWWORD_MASK 0xffffffffU |
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#define | AARCH64_DBGDTR_EL0_LOWWORD_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffffffU ) |
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#define | AARCH64_DBGDTR_EL0_HIGHWORD(_val) ( ( _val ) << 32 ) |
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#define | AARCH64_DBGDTR_EL0_HIGHWORD_SHIFT 32 |
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#define | AARCH64_DBGDTR_EL0_HIGHWORD_MASK 0xffffffff00000000ULL |
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#define | AARCH64_DBGDTR_EL0_HIGHWORD_GET(_reg) ( ( ( _reg ) >> 32 ) & 0xffffffffULL ) |
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#define | AARCH64_DBGPRCR_EL1_CORENPDRQ 0x1U |
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#define | AARCH64_DBGVCR32_EL2_SU 0x2U |
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#define | AARCH64_DBGVCR32_EL2_U 0x2U |
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#define | AARCH64_DBGVCR32_EL2_S 0x4U |
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#define | AARCH64_DBGVCR32_EL2_SS 0x4U |
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#define | AARCH64_DBGVCR32_EL2_P 0x8U |
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#define | AARCH64_DBGVCR32_EL2_SP 0x8U |
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#define | AARCH64_DBGVCR32_EL2_D 0x10U |
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#define | AARCH64_DBGVCR32_EL2_SD 0x10U |
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#define | AARCH64_DBGVCR32_EL2_I 0x40U |
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#define | AARCH64_DBGVCR32_EL2_SI 0x40U |
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#define | AARCH64_DBGVCR32_EL2_F 0x80U |
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#define | AARCH64_DBGVCR32_EL2_SF 0x80U |
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#define | AARCH64_DBGVCR32_EL2_NSU 0x2000000U |
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#define | AARCH64_DBGVCR32_EL2_NSS 0x4000000U |
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#define | AARCH64_DBGVCR32_EL2_NSP 0x8000000U |
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#define | AARCH64_DBGVCR32_EL2_NSD 0x10000000U |
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#define | AARCH64_DBGVCR32_EL2_NSI 0x40000000U |
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#define | AARCH64_DBGVCR32_EL2_NSF 0x80000000U |
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#define | AARCH64_DBGWCR_N_EL1_E 0x1U |
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#define | AARCH64_DBGWCR_N_EL1_PAC(_val) ( ( _val ) << 1 ) |
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#define | AARCH64_DBGWCR_N_EL1_PAC_SHIFT 1 |
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#define | AARCH64_DBGWCR_N_EL1_PAC_MASK 0x6U |
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#define | AARCH64_DBGWCR_N_EL1_PAC_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x3U ) |
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#define | AARCH64_DBGWCR_N_EL1_LSC(_val) ( ( _val ) << 3 ) |
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#define | AARCH64_DBGWCR_N_EL1_LSC_SHIFT 3 |
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#define | AARCH64_DBGWCR_N_EL1_LSC_MASK 0x18U |
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#define | AARCH64_DBGWCR_N_EL1_LSC_GET(_reg) ( ( ( _reg ) >> 3 ) & 0x3U ) |
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#define | AARCH64_DBGWCR_N_EL1_BAS(_val) ( ( _val ) << 5 ) |
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#define | AARCH64_DBGWCR_N_EL1_BAS_SHIFT 5 |
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#define | AARCH64_DBGWCR_N_EL1_BAS_MASK 0x1fe0U |
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#define | AARCH64_DBGWCR_N_EL1_BAS_GET(_reg) ( ( ( _reg ) >> 5 ) & 0xffU ) |
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#define | AARCH64_DBGWCR_N_EL1_HMC 0x2000U |
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#define | AARCH64_DBGWCR_N_EL1_SSC(_val) ( ( _val ) << 14 ) |
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#define | AARCH64_DBGWCR_N_EL1_SSC_SHIFT 14 |
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#define | AARCH64_DBGWCR_N_EL1_SSC_MASK 0xc000U |
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#define | AARCH64_DBGWCR_N_EL1_SSC_GET(_reg) ( ( ( _reg ) >> 14 ) & 0x3U ) |
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#define | AARCH64_DBGWCR_N_EL1_LBN(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_DBGWCR_N_EL1_LBN_SHIFT 16 |
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#define | AARCH64_DBGWCR_N_EL1_LBN_MASK 0xf0000U |
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#define | AARCH64_DBGWCR_N_EL1_LBN_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_DBGWCR_N_EL1_WT 0x100000U |
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#define | AARCH64_DBGWCR_N_EL1_MASK(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_DBGWCR_N_EL1_MASK_SHIFT 24 |
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#define | AARCH64_DBGWCR_N_EL1_MASK_MASK 0x1f000000U |
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#define | AARCH64_DBGWCR_N_EL1_MASK_GET(_reg) ( ( ( _reg ) >> 24 ) & 0x1fU ) |
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#define | AARCH64_DBGWVR_N_EL1_VA_48_2(_val) ( ( _val ) << 2 ) |
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#define | AARCH64_DBGWVR_N_EL1_VA_48_2_SHIFT 2 |
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#define | AARCH64_DBGWVR_N_EL1_VA_48_2_MASK 0x1fffffffffffcULL |
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#define | AARCH64_DBGWVR_N_EL1_VA_48_2_GET(_reg) ( ( ( _reg ) >> 2 ) & 0x7fffffffffffULL ) |
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#define | AARCH64_DBGWVR_N_EL1_VA_52_49(_val) ( ( _val ) << 49 ) |
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#define | AARCH64_DBGWVR_N_EL1_VA_52_49_SHIFT 49 |
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#define | AARCH64_DBGWVR_N_EL1_VA_52_49_MASK 0x1e000000000000ULL |
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#define | AARCH64_DBGWVR_N_EL1_VA_52_49_GET(_reg) ( ( ( _reg ) >> 49 ) & 0xfULL ) |
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#define | AARCH64_DBGWVR_N_EL1_RESS_14_4(_val) ( ( _val ) << 53 ) |
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#define | AARCH64_DBGWVR_N_EL1_RESS_14_4_SHIFT 53 |
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#define | AARCH64_DBGWVR_N_EL1_RESS_14_4_MASK 0xffe0000000000000ULL |
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#define | AARCH64_DBGWVR_N_EL1_RESS_14_4_GET(_reg) ( ( ( _reg ) >> 53 ) & 0x7ffULL ) |
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#define | AARCH64_DSPSR_EL0_M_3_0(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_DSPSR_EL0_M_3_0_SHIFT 0 |
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#define | AARCH64_DSPSR_EL0_M_3_0_MASK 0xfU |
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#define | AARCH64_DSPSR_EL0_M_3_0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_DSPSR_EL0_M_4 0x10U |
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#define | AARCH64_DSPSR_EL0_T 0x20U |
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#define | AARCH64_DSPSR_EL0_F 0x40U |
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#define | AARCH64_DSPSR_EL0_I 0x80U |
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#define | AARCH64_DSPSR_EL0_A 0x100U |
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#define | AARCH64_DSPSR_EL0_D 0x200U |
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#define | AARCH64_DSPSR_EL0_E 0x200U |
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#define | AARCH64_DSPSR_EL0_BTYPE(_val) ( ( _val ) << 10 ) |
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#define | AARCH64_DSPSR_EL0_BTYPE_SHIFT 10 |
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#define | AARCH64_DSPSR_EL0_BTYPE_MASK 0xc00U |
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#define | AARCH64_DSPSR_EL0_BTYPE_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x3U ) |
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#define | AARCH64_DSPSR_EL0_IT_7_2(_val) ( ( _val ) << 10 ) |
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#define | AARCH64_DSPSR_EL0_IT_7_2_SHIFT 10 |
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#define | AARCH64_DSPSR_EL0_IT_7_2_MASK 0xfc00U |
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#define | AARCH64_DSPSR_EL0_IT_7_2_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x3fU ) |
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#define | AARCH64_DSPSR_EL0_SSBS_0 0x1000U |
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#define | AARCH64_DSPSR_EL0_GE(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_DSPSR_EL0_GE_SHIFT 16 |
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#define | AARCH64_DSPSR_EL0_GE_MASK 0xf0000U |
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#define | AARCH64_DSPSR_EL0_GE_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_DSPSR_EL0_IL 0x100000U |
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#define | AARCH64_DSPSR_EL0_SS 0x200000U |
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#define | AARCH64_DSPSR_EL0_PAN 0x400000U |
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#define | AARCH64_DSPSR_EL0_SSBS_1 0x800000U |
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#define | AARCH64_DSPSR_EL0_UAO 0x800000U |
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#define | AARCH64_DSPSR_EL0_DIT 0x1000000U |
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#define | AARCH64_DSPSR_EL0_TCO 0x2000000U |
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#define | AARCH64_DSPSR_EL0_IT_1_0(_val) ( ( _val ) << 25 ) |
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#define | AARCH64_DSPSR_EL0_IT_1_0_SHIFT 25 |
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#define | AARCH64_DSPSR_EL0_IT_1_0_MASK 0x6000000U |
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#define | AARCH64_DSPSR_EL0_IT_1_0_GET(_reg) ( ( ( _reg ) >> 25 ) & 0x3U ) |
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#define | AARCH64_DSPSR_EL0_Q 0x8000000U |
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#define | AARCH64_DSPSR_EL0_V 0x10000000U |
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#define | AARCH64_DSPSR_EL0_C 0x20000000U |
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#define | AARCH64_DSPSR_EL0_Z 0x40000000U |
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#define | AARCH64_DSPSR_EL0_N 0x80000000U |
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#define | AARCH64_MDCCINT_EL1_TX 0x20000000U |
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#define | AARCH64_MDCCINT_EL1_RX 0x40000000U |
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#define | AARCH64_MDCCSR_EL0_TXFULL 0x20000000U |
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#define | AARCH64_MDCCSR_EL0_RXFULL 0x40000000U |
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#define | AARCH64_MDCR_EL2_HPMN(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_MDCR_EL2_HPMN_SHIFT 0 |
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#define | AARCH64_MDCR_EL2_HPMN_MASK 0x1fU |
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#define | AARCH64_MDCR_EL2_HPMN_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x1fU ) |
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#define | AARCH64_MDCR_EL2_TPMCR 0x20U |
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#define | AARCH64_MDCR_EL2_TPM 0x40U |
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#define | AARCH64_MDCR_EL2_HPME 0x80U |
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#define | AARCH64_MDCR_EL2_TDE 0x100U |
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#define | AARCH64_MDCR_EL2_TDA 0x200U |
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#define | AARCH64_MDCR_EL2_TDOSA 0x400U |
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#define | AARCH64_MDCR_EL2_TDRA 0x800U |
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#define | AARCH64_MDCR_EL2_E2PB(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_MDCR_EL2_E2PB_SHIFT 12 |
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#define | AARCH64_MDCR_EL2_E2PB_MASK 0x3000U |
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#define | AARCH64_MDCR_EL2_E2PB_GET(_reg) ( ( ( _reg ) >> 12 ) & 0x3U ) |
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#define | AARCH64_MDCR_EL2_TPMS 0x4000U |
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#define | AARCH64_MDCR_EL2_HPMD 0x20000U |
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#define | AARCH64_MDCR_EL2_TTRF 0x80000U |
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#define | AARCH64_MDCR_EL2_HCCD 0x800000U |
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#define | AARCH64_MDCR_EL2_HLP 0x4000000U |
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#define | AARCH64_MDCR_EL2_TDCC 0x8000000U |
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#define | AARCH64_MDCR_EL2_MTPME 0x10000000U |
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#define | AARCH64_MDCR_EL3_TPM 0x40U |
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#define | AARCH64_MDCR_EL3_TDA 0x200U |
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#define | AARCH64_MDCR_EL3_TDOSA 0x400U |
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#define | AARCH64_MDCR_EL3_NSPB(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_MDCR_EL3_NSPB_SHIFT 12 |
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#define | AARCH64_MDCR_EL3_NSPB_MASK 0x3000U |
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#define | AARCH64_MDCR_EL3_NSPB_GET(_reg) ( ( ( _reg ) >> 12 ) & 0x3U ) |
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#define | AARCH64_MDCR_EL3_SPD32(_val) ( ( _val ) << 14 ) |
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#define | AARCH64_MDCR_EL3_SPD32_SHIFT 14 |
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#define | AARCH64_MDCR_EL3_SPD32_MASK 0xc000U |
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#define | AARCH64_MDCR_EL3_SPD32_GET(_reg) ( ( ( _reg ) >> 14 ) & 0x3U ) |
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#define | AARCH64_MDCR_EL3_SDD 0x10000U |
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#define | AARCH64_MDCR_EL3_SPME 0x20000U |
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#define | AARCH64_MDCR_EL3_STE 0x40000U |
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#define | AARCH64_MDCR_EL3_TTRF 0x80000U |
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#define | AARCH64_MDCR_EL3_EDAD 0x100000U |
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#define | AARCH64_MDCR_EL3_EPMAD 0x200000U |
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#define | AARCH64_MDCR_EL3_SCCD 0x800000U |
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#define | AARCH64_MDCR_EL3_TDCC 0x8000000U |
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#define | AARCH64_MDCR_EL3_MTPME 0x10000000U |
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#define | AARCH64_MDRAR_EL1_VALID(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_MDRAR_EL1_VALID_SHIFT 0 |
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#define | AARCH64_MDRAR_EL1_VALID_MASK 0x3U |
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#define | AARCH64_MDRAR_EL1_VALID_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3U ) |
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#define | AARCH64_MDRAR_EL1_ROMADDR_47_12(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_MDRAR_EL1_ROMADDR_47_12_SHIFT 12 |
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#define | AARCH64_MDRAR_EL1_ROMADDR_47_12_MASK 0xfffffffff000ULL |
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#define | AARCH64_MDRAR_EL1_ROMADDR_47_12_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfffffffffULL ) |
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#define | AARCH64_MDRAR_EL1_ROMADDR_51_48(_val) ( ( _val ) << 48 ) |
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#define | AARCH64_MDRAR_EL1_ROMADDR_51_48_SHIFT 48 |
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#define | AARCH64_MDRAR_EL1_ROMADDR_51_48_MASK 0xf000000000000ULL |
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#define | AARCH64_MDRAR_EL1_ROMADDR_51_48_GET(_reg) ( ( ( _reg ) >> 48 ) & 0xfULL ) |
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#define | AARCH64_MDSCR_EL1_SS 0x1U |
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#define | AARCH64_MDSCR_EL1_ERR 0x40U |
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#define | AARCH64_MDSCR_EL1_TDCC 0x1000U |
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#define | AARCH64_MDSCR_EL1_KDE 0x2000U |
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#define | AARCH64_MDSCR_EL1_HDE 0x4000U |
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#define | AARCH64_MDSCR_EL1_MDE 0x8000U |
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#define | AARCH64_MDSCR_EL1_SC2 0x80000U |
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#define | AARCH64_MDSCR_EL1_TDA 0x200000U |
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#define | AARCH64_MDSCR_EL1_INTDIS(_val) ( ( _val ) << 22 ) |
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#define | AARCH64_MDSCR_EL1_INTDIS_SHIFT 22 |
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#define | AARCH64_MDSCR_EL1_INTDIS_MASK 0xc00000U |
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#define | AARCH64_MDSCR_EL1_INTDIS_GET(_reg) ( ( ( _reg ) >> 22 ) & 0x3U ) |
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#define | AARCH64_MDSCR_EL1_TXU 0x4000000U |
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#define | AARCH64_MDSCR_EL1_RXO 0x8000000U |
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#define | AARCH64_MDSCR_EL1_TXFULL 0x20000000U |
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#define | AARCH64_MDSCR_EL1_RXFULL 0x40000000U |
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#define | AARCH64_MDSCR_EL1_TFO 0x80000000U |
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#define | AARCH64_OSDLR_EL1_DLK 0x1U |
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#define | AARCH64_OSECCR_EL1_EDECCR(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_OSECCR_EL1_EDECCR_SHIFT 0 |
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#define | AARCH64_OSECCR_EL1_EDECCR_MASK 0xffffffffU |
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#define | AARCH64_OSECCR_EL1_EDECCR_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffffffU ) |
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#define | AARCH64_OSLAR_EL1_OSLK 0x1U |
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#define | AARCH64_OSLSR_EL1_OSLM_0 0x1U |
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#define | AARCH64_OSLSR_EL1_OSLK 0x2U |
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#define | AARCH64_OSLSR_EL1_NTT 0x4U |
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#define | AARCH64_OSLSR_EL1_OSLM_1 0x8U |
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#define | AARCH64_SDER32_EL2_SUIDEN 0x1U |
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#define | AARCH64_SDER32_EL2_SUNIDEN 0x2U |
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#define | AARCH64_SDER32_EL3_SUIDEN 0x1U |
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#define | AARCH64_SDER32_EL3_SUNIDEN 0x2U |
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#define | AARCH64_TRFCR_EL1_E0TRE 0x1U |
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#define | AARCH64_TRFCR_EL1_E1TRE 0x2U |
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#define | AARCH64_TRFCR_EL1_TS(_val) ( ( _val ) << 5 ) |
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#define | AARCH64_TRFCR_EL1_TS_SHIFT 5 |
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#define | AARCH64_TRFCR_EL1_TS_MASK 0x60U |
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#define | AARCH64_TRFCR_EL1_TS_GET(_reg) ( ( ( _reg ) >> 5 ) & 0x3U ) |
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#define | AARCH64_TRFCR_EL2_E0HTRE 0x1U |
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#define | AARCH64_TRFCR_EL2_E2TRE 0x2U |
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#define | AARCH64_TRFCR_EL2_CX 0x8U |
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#define | AARCH64_TRFCR_EL2_TS(_val) ( ( _val ) << 5 ) |
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#define | AARCH64_TRFCR_EL2_TS_SHIFT 5 |
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#define | AARCH64_TRFCR_EL2_TS_MASK 0x60U |
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#define | AARCH64_TRFCR_EL2_TS_GET(_reg) ( ( ( _reg ) >> 5 ) & 0x3U ) |
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#define | AARCH64_PMCCFILTR_EL0_SH 0x1000000U |
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#define | AARCH64_PMCCFILTR_EL0_M 0x4000000U |
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#define | AARCH64_PMCCFILTR_EL0_NSH 0x8000000U |
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#define | AARCH64_PMCCFILTR_EL0_NSU 0x10000000U |
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#define | AARCH64_PMCCFILTR_EL0_NSK 0x20000000U |
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#define | AARCH64_PMCCFILTR_EL0_U 0x40000000U |
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#define | AARCH64_PMCCFILTR_EL0_P 0x80000000U |
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#define | AARCH64_PMCNTENCLR_EL0_C 0x80000000U |
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#define | AARCH64_PMCNTENSET_EL0_C 0x80000000U |
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#define | AARCH64_PMCR_EL0_E 0x1U |
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#define | AARCH64_PMCR_EL0_P 0x2U |
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#define | AARCH64_PMCR_EL0_C 0x4U |
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#define | AARCH64_PMCR_EL0_D 0x8U |
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#define | AARCH64_PMCR_EL0_X 0x10U |
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#define | AARCH64_PMCR_EL0_DP 0x20U |
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#define | AARCH64_PMCR_EL0_LC 0x40U |
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#define | AARCH64_PMCR_EL0_LP 0x80U |
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#define | AARCH64_PMCR_EL0_N(_val) ( ( _val ) << 11 ) |
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#define | AARCH64_PMCR_EL0_N_SHIFT 11 |
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#define | AARCH64_PMCR_EL0_N_MASK 0xf800U |
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#define | AARCH64_PMCR_EL0_N_GET(_reg) ( ( ( _reg ) >> 11 ) & 0x1fU ) |
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#define | AARCH64_PMCR_EL0_IDCODE(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_PMCR_EL0_IDCODE_SHIFT 16 |
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#define | AARCH64_PMCR_EL0_IDCODE_MASK 0xff0000U |
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#define | AARCH64_PMCR_EL0_IDCODE_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xffU ) |
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#define | AARCH64_PMCR_EL0_IMP(_val) ( ( _val ) << 24 ) |
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#define | AARCH64_PMCR_EL0_IMP_SHIFT 24 |
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#define | AARCH64_PMCR_EL0_IMP_MASK 0xff000000U |
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#define | AARCH64_PMCR_EL0_IMP_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xffU ) |
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#define | AARCH64_PMEVTYPER_N_EL0_EVTCOUNT_9_0(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_PMEVTYPER_N_EL0_EVTCOUNT_9_0_SHIFT 0 |
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#define | AARCH64_PMEVTYPER_N_EL0_EVTCOUNT_9_0_MASK 0x3ffU |
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#define | AARCH64_PMEVTYPER_N_EL0_EVTCOUNT_9_0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3ffU ) |
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#define | AARCH64_PMEVTYPER_N_EL0_EVTCOUNT_15_10(_val) ( ( _val ) << 10 ) |
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#define | AARCH64_PMEVTYPER_N_EL0_EVTCOUNT_15_10_SHIFT 10 |
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#define | AARCH64_PMEVTYPER_N_EL0_EVTCOUNT_15_10_MASK 0xfc00U |
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#define | AARCH64_PMEVTYPER_N_EL0_EVTCOUNT_15_10_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x3fU ) |
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#define | AARCH64_PMEVTYPER_N_EL0_SH 0x1000000U |
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#define | AARCH64_PMEVTYPER_N_EL0_MT 0x2000000U |
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#define | AARCH64_PMEVTYPER_N_EL0_M 0x4000000U |
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#define | AARCH64_PMEVTYPER_N_EL0_NSH 0x8000000U |
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#define | AARCH64_PMEVTYPER_N_EL0_NSU 0x10000000U |
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#define | AARCH64_PMEVTYPER_N_EL0_NSK 0x20000000U |
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#define | AARCH64_PMEVTYPER_N_EL0_U 0x40000000U |
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#define | AARCH64_PMEVTYPER_N_EL0_P 0x80000000U |
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#define | AARCH64_PMINTENCLR_EL1_C 0x80000000U |
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#define | AARCH64_PMINTENSET_EL1_C 0x80000000U |
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#define | AARCH64_PMMIR_EL1_SLOTS(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_PMMIR_EL1_SLOTS_SHIFT 0 |
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#define | AARCH64_PMMIR_EL1_SLOTS_MASK 0xffU |
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#define | AARCH64_PMMIR_EL1_SLOTS_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU ) |
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#define | AARCH64_PMOVSCLR_EL0_C 0x80000000U |
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#define | AARCH64_PMOVSSET_EL0_C 0x80000000U |
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#define | AARCH64_PMSELR_EL0_SEL(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_PMSELR_EL0_SEL_SHIFT 0 |
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#define | AARCH64_PMSELR_EL0_SEL_MASK 0x1fU |
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#define | AARCH64_PMSELR_EL0_SEL_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x1fU ) |
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#define | AARCH64_PMUSERENR_EL0_EN 0x1U |
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#define | AARCH64_PMUSERENR_EL0_SW 0x2U |
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#define | AARCH64_PMUSERENR_EL0_CR 0x4U |
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#define | AARCH64_PMUSERENR_EL0_ER 0x8U |
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#define | AARCH64_PMXEVCNTR_EL0_PMEVCNTR_N(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_PMXEVCNTR_EL0_PMEVCNTR_N_SHIFT 0 |
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#define | AARCH64_PMXEVCNTR_EL0_PMEVCNTR_N_MASK 0xffffffffU |
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#define | AARCH64_PMXEVCNTR_EL0_PMEVCNTR_N_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffffffU ) |
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#define | AARCH64_AMCFGR_EL0_N(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_AMCFGR_EL0_N_SHIFT 0 |
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#define | AARCH64_AMCFGR_EL0_N_MASK 0xffU |
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#define | AARCH64_AMCFGR_EL0_N_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU ) |
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#define | AARCH64_AMCFGR_EL0_SIZE(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_AMCFGR_EL0_SIZE_SHIFT 8 |
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#define | AARCH64_AMCFGR_EL0_SIZE_MASK 0x3f00U |
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#define | AARCH64_AMCFGR_EL0_SIZE_GET(_reg) ( ( ( _reg ) >> 8 ) & 0x3fU ) |
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#define | AARCH64_AMCFGR_EL0_HDBG 0x1000000U |
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#define | AARCH64_AMCFGR_EL0_NCG(_val) ( ( _val ) << 28 ) |
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#define | AARCH64_AMCFGR_EL0_NCG_SHIFT 28 |
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#define | AARCH64_AMCFGR_EL0_NCG_MASK 0xf0000000U |
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#define | AARCH64_AMCFGR_EL0_NCG_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU ) |
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#define | AARCH64_AMCGCR_EL0_CG0NC(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_AMCGCR_EL0_CG0NC_SHIFT 0 |
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#define | AARCH64_AMCGCR_EL0_CG0NC_MASK 0xffU |
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#define | AARCH64_AMCGCR_EL0_CG0NC_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU ) |
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#define | AARCH64_AMCGCR_EL0_CG1NC(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_AMCGCR_EL0_CG1NC_SHIFT 8 |
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#define | AARCH64_AMCGCR_EL0_CG1NC_MASK 0xff00U |
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#define | AARCH64_AMCGCR_EL0_CG1NC_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xffU ) |
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#define | AARCH64_AMCR_EL0_HDBG 0x400U |
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#define | AARCH64_AMCR_EL0_CG1RZ 0x20000U |
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#define | AARCH64_AMEVTYPER0_N_EL0_EVTCOUNT(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_AMEVTYPER0_N_EL0_EVTCOUNT_SHIFT 0 |
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#define | AARCH64_AMEVTYPER0_N_EL0_EVTCOUNT_MASK 0xffffU |
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#define | AARCH64_AMEVTYPER0_N_EL0_EVTCOUNT_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffU ) |
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#define | AARCH64_AMEVTYPER1_N_EL0_EVTCOUNT(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_AMEVTYPER1_N_EL0_EVTCOUNT_SHIFT 0 |
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#define | AARCH64_AMEVTYPER1_N_EL0_EVTCOUNT_MASK 0xffffU |
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#define | AARCH64_AMEVTYPER1_N_EL0_EVTCOUNT_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffU ) |
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#define | AARCH64_AMUSERENR_EL0_EN 0x1U |
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#define | AARCH64_PMBIDR_EL1_ALIGN(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_PMBIDR_EL1_ALIGN_SHIFT 0 |
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#define | AARCH64_PMBIDR_EL1_ALIGN_MASK 0xfU |
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#define | AARCH64_PMBIDR_EL1_ALIGN_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_PMBIDR_EL1_P 0x10U |
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#define | AARCH64_PMBIDR_EL1_F 0x20U |
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#define | AARCH64_PMBLIMITR_EL1_E 0x1U |
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#define | AARCH64_PMBLIMITR_EL1_FM(_val) ( ( _val ) << 1 ) |
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#define | AARCH64_PMBLIMITR_EL1_FM_SHIFT 1 |
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#define | AARCH64_PMBLIMITR_EL1_FM_MASK 0x6U |
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#define | AARCH64_PMBLIMITR_EL1_FM_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x3U ) |
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#define | AARCH64_PMBLIMITR_EL1_LIMIT(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_PMBLIMITR_EL1_LIMIT_SHIFT 12 |
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#define | AARCH64_PMBLIMITR_EL1_LIMIT_MASK 0xfffffffffffff000ULL |
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#define | AARCH64_PMBLIMITR_EL1_LIMIT_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfffffffffffffULL ) |
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#define | AARCH64_PMBSR_EL1_BSC(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_PMBSR_EL1_BSC_SHIFT 0 |
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#define | AARCH64_PMBSR_EL1_BSC_MASK 0x3fU |
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#define | AARCH64_PMBSR_EL1_BSC_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3fU ) |
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#define | AARCH64_PMBSR_EL1_FSC(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_PMBSR_EL1_FSC_SHIFT 0 |
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#define | AARCH64_PMBSR_EL1_FSC_MASK 0x3fU |
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#define | AARCH64_PMBSR_EL1_FSC_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3fU ) |
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#define | AARCH64_PMBSR_EL1_MSS(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_PMBSR_EL1_MSS_SHIFT 0 |
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#define | AARCH64_PMBSR_EL1_MSS_MASK 0xffffU |
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#define | AARCH64_PMBSR_EL1_MSS_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffU ) |
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#define | AARCH64_PMBSR_EL1_COLL 0x10000U |
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#define | AARCH64_PMBSR_EL1_S 0x20000U |
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#define | AARCH64_PMBSR_EL1_EA 0x40000U |
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#define | AARCH64_PMBSR_EL1_DL 0x80000U |
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#define | AARCH64_PMBSR_EL1_EC(_val) ( ( _val ) << 26 ) |
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#define | AARCH64_PMBSR_EL1_EC_SHIFT 26 |
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#define | AARCH64_PMBSR_EL1_EC_MASK 0xfc000000U |
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#define | AARCH64_PMBSR_EL1_EC_GET(_reg) ( ( ( _reg ) >> 26 ) & 0x3fU ) |
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#define | AARCH64_PMSCR_EL1_E0SPE 0x1U |
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#define | AARCH64_PMSCR_EL1_E1SPE 0x2U |
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#define | AARCH64_PMSCR_EL1_CX 0x8U |
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#define | AARCH64_PMSCR_EL1_PA 0x10U |
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#define | AARCH64_PMSCR_EL1_TS 0x20U |
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#define | AARCH64_PMSCR_EL1_PCT(_val) ( ( _val ) << 6 ) |
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#define | AARCH64_PMSCR_EL1_PCT_SHIFT 6 |
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#define | AARCH64_PMSCR_EL1_PCT_MASK 0xc0U |
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#define | AARCH64_PMSCR_EL1_PCT_GET(_reg) ( ( ( _reg ) >> 6 ) & 0x3U ) |
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#define | AARCH64_PMSCR_EL2_E0HSPE 0x1U |
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#define | AARCH64_PMSCR_EL2_E2SPE 0x2U |
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#define | AARCH64_PMSCR_EL2_CX 0x8U |
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#define | AARCH64_PMSCR_EL2_PA 0x10U |
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#define | AARCH64_PMSCR_EL2_TS 0x20U |
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#define | AARCH64_PMSCR_EL2_PCT(_val) ( ( _val ) << 6 ) |
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#define | AARCH64_PMSCR_EL2_PCT_SHIFT 6 |
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#define | AARCH64_PMSCR_EL2_PCT_MASK 0xc0U |
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#define | AARCH64_PMSCR_EL2_PCT_GET(_reg) ( ( ( _reg ) >> 6 ) & 0x3U ) |
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#define | AARCH64_PMSEVFR_EL1_E_1 0x2U |
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#define | AARCH64_PMSEVFR_EL1_E_3 0x8U |
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#define | AARCH64_PMSEVFR_EL1_E_5 0x20U |
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#define | AARCH64_PMSEVFR_EL1_E_7 0x80U |
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#define | AARCH64_PMSEVFR_EL1_E_11 0x800U |
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#define | AARCH64_PMSEVFR_EL1_E_12 0x1000U |
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#define | AARCH64_PMSEVFR_EL1_E_13 0x2000U |
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#define | AARCH64_PMSEVFR_EL1_E_14 0x4000U |
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#define | AARCH64_PMSEVFR_EL1_E_15 0x8000U |
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#define | AARCH64_PMSEVFR_EL1_E_17 0x20000U |
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#define | AARCH64_PMSEVFR_EL1_E_18 0x40000U |
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#define | AARCH64_PMSEVFR_EL1_E_24 0x1000000U |
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#define | AARCH64_PMSEVFR_EL1_E_25 0x2000000U |
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#define | AARCH64_PMSEVFR_EL1_E_26 0x4000000U |
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#define | AARCH64_PMSEVFR_EL1_E_27 0x8000000U |
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#define | AARCH64_PMSEVFR_EL1_E_28 0x10000000U |
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#define | AARCH64_PMSEVFR_EL1_E_29 0x20000000U |
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#define | AARCH64_PMSEVFR_EL1_E_30 0x40000000U |
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#define | AARCH64_PMSEVFR_EL1_E_31 0x80000000U |
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#define | AARCH64_PMSEVFR_EL1_E_48 0x1000000000000ULL |
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#define | AARCH64_PMSEVFR_EL1_E_49 0x2000000000000ULL |
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#define | AARCH64_PMSEVFR_EL1_E_50 0x4000000000000ULL |
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#define | AARCH64_PMSEVFR_EL1_E_51 0x8000000000000ULL |
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#define | AARCH64_PMSEVFR_EL1_E_52 0x10000000000000ULL |
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#define | AARCH64_PMSEVFR_EL1_E_53 0x20000000000000ULL |
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#define | AARCH64_PMSEVFR_EL1_E_54 0x40000000000000ULL |
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#define | AARCH64_PMSEVFR_EL1_E_55 0x80000000000000ULL |
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#define | AARCH64_PMSEVFR_EL1_E_56 0x100000000000000ULL |
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#define | AARCH64_PMSEVFR_EL1_E_57 0x200000000000000ULL |
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#define | AARCH64_PMSEVFR_EL1_E_58 0x400000000000000ULL |
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#define | AARCH64_PMSEVFR_EL1_E_59 0x800000000000000ULL |
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#define | AARCH64_PMSEVFR_EL1_E_60 0x1000000000000000ULL |
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#define | AARCH64_PMSEVFR_EL1_E_61 0x2000000000000000ULL |
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#define | AARCH64_PMSEVFR_EL1_E_62 0x4000000000000000ULL |
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#define | AARCH64_PMSEVFR_EL1_E_63 0x8000000000000000ULL |
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#define | AARCH64_PMSFCR_EL1_FE 0x1U |
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#define | AARCH64_PMSFCR_EL1_FT 0x2U |
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#define | AARCH64_PMSFCR_EL1_FL 0x4U |
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#define | AARCH64_PMSFCR_EL1_B 0x10000U |
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#define | AARCH64_PMSFCR_EL1_LD 0x20000U |
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#define | AARCH64_PMSFCR_EL1_ST 0x40000U |
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#define | AARCH64_PMSICR_EL1_COUNT(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_PMSICR_EL1_COUNT_SHIFT 0 |
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#define | AARCH64_PMSICR_EL1_COUNT_MASK 0xffffffffU |
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#define | AARCH64_PMSICR_EL1_COUNT_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffffffU ) |
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#define | AARCH64_PMSICR_EL1_ECOUNT(_val) ( ( _val ) << 56 ) |
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#define | AARCH64_PMSICR_EL1_ECOUNT_SHIFT 56 |
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#define | AARCH64_PMSICR_EL1_ECOUNT_MASK 0xff00000000000000ULL |
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#define | AARCH64_PMSICR_EL1_ECOUNT_GET(_reg) ( ( ( _reg ) >> 56 ) & 0xffULL ) |
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#define | AARCH64_PMSIDR_EL1_FE 0x1U |
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#define | AARCH64_PMSIDR_EL1_FT 0x2U |
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#define | AARCH64_PMSIDR_EL1_FL 0x4U |
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#define | AARCH64_PMSIDR_EL1_ARCHINST 0x8U |
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#define | AARCH64_PMSIDR_EL1_LDS 0x10U |
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#define | AARCH64_PMSIDR_EL1_ERND 0x20U |
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#define | AARCH64_PMSIDR_EL1_INTERVAL(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_PMSIDR_EL1_INTERVAL_SHIFT 8 |
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#define | AARCH64_PMSIDR_EL1_INTERVAL_MASK 0xf00U |
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#define | AARCH64_PMSIDR_EL1_INTERVAL_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU ) |
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#define | AARCH64_PMSIDR_EL1_MAXSIZE(_val) ( ( _val ) << 12 ) |
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#define | AARCH64_PMSIDR_EL1_MAXSIZE_SHIFT 12 |
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#define | AARCH64_PMSIDR_EL1_MAXSIZE_MASK 0xf000U |
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#define | AARCH64_PMSIDR_EL1_MAXSIZE_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU ) |
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#define | AARCH64_PMSIDR_EL1_COUNTSIZE(_val) ( ( _val ) << 16 ) |
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#define | AARCH64_PMSIDR_EL1_COUNTSIZE_SHIFT 16 |
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#define | AARCH64_PMSIDR_EL1_COUNTSIZE_MASK 0xf0000U |
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#define | AARCH64_PMSIDR_EL1_COUNTSIZE_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU ) |
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#define | AARCH64_PMSIRR_EL1_RND 0x1U |
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#define | AARCH64_PMSIRR_EL1_INTERVAL(_val) ( ( _val ) << 8 ) |
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#define | AARCH64_PMSIRR_EL1_INTERVAL_SHIFT 8 |
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#define | AARCH64_PMSIRR_EL1_INTERVAL_MASK 0xffffff00U |
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#define | AARCH64_PMSIRR_EL1_INTERVAL_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xffffffU ) |
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#define | AARCH64_PMSLATFR_EL1_MINLAT(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_PMSLATFR_EL1_MINLAT_SHIFT 0 |
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#define | AARCH64_PMSLATFR_EL1_MINLAT_MASK 0xfffU |
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#define | AARCH64_PMSLATFR_EL1_MINLAT_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfffU ) |
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#define | AARCH64_DISR_EL1_DFSC(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_DISR_EL1_DFSC_SHIFT 0 |
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#define | AARCH64_DISR_EL1_DFSC_MASK 0x3fU |
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#define | AARCH64_DISR_EL1_DFSC_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3fU ) |
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#define | AARCH64_DISR_EL1_ISS(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_DISR_EL1_ISS_SHIFT 0 |
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#define | AARCH64_DISR_EL1_ISS_MASK 0xffffffU |
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#define | AARCH64_DISR_EL1_ISS_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffffU ) |
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#define | AARCH64_DISR_EL1_EA 0x200U |
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#define | AARCH64_DISR_EL1_AET(_val) ( ( _val ) << 10 ) |
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#define | AARCH64_DISR_EL1_AET_SHIFT 10 |
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#define | AARCH64_DISR_EL1_AET_MASK 0x1c00U |
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#define | AARCH64_DISR_EL1_AET_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x7U ) |
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#define | AARCH64_DISR_EL1_IDS 0x1000000U |
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#define | AARCH64_DISR_EL1_A 0x80000000U |
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#define | AARCH64_ERRIDR_EL1_NUM(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ERRIDR_EL1_NUM_SHIFT 0 |
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#define | AARCH64_ERRIDR_EL1_NUM_MASK 0xffffU |
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#define | AARCH64_ERRIDR_EL1_NUM_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffU ) |
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#define | AARCH64_ERRSELR_EL1_SEL(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_ERRSELR_EL1_SEL_SHIFT 0 |
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#define | AARCH64_ERRSELR_EL1_SEL_MASK 0xffffU |
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#define | AARCH64_ERRSELR_EL1_SEL_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffU ) |
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#define | AARCH64_VDISR_EL2_FS_3_0(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_VDISR_EL2_FS_3_0_SHIFT 0 |
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#define | AARCH64_VDISR_EL2_FS_3_0_MASK 0xfU |
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#define | AARCH64_VDISR_EL2_FS_3_0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU ) |
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#define | AARCH64_VDISR_EL2_STATUS(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_VDISR_EL2_STATUS_SHIFT 0 |
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#define | AARCH64_VDISR_EL2_STATUS_MASK 0x3fU |
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#define | AARCH64_VDISR_EL2_STATUS_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3fU ) |
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#define | AARCH64_VDISR_EL2_ISS(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_VDISR_EL2_ISS_SHIFT 0 |
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#define | AARCH64_VDISR_EL2_ISS_MASK 0xffffffU |
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#define | AARCH64_VDISR_EL2_ISS_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffffU ) |
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#define | AARCH64_VDISR_EL2_LPAE 0x200U |
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#define | AARCH64_VDISR_EL2_FS_4 0x400U |
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#define | AARCH64_VDISR_EL2_EXT 0x1000U |
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#define | AARCH64_VDISR_EL2_AET(_val) ( ( _val ) << 14 ) |
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#define | AARCH64_VDISR_EL2_AET_SHIFT 14 |
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#define | AARCH64_VDISR_EL2_AET_MASK 0xc000U |
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#define | AARCH64_VDISR_EL2_AET_GET(_reg) ( ( ( _reg ) >> 14 ) & 0x3U ) |
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#define | AARCH64_VDISR_EL2_IDS 0x1000000U |
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#define | AARCH64_VDISR_EL2_A 0x80000000U |
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#define | AARCH64_VSESR_EL2_ISS(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_VSESR_EL2_ISS_SHIFT 0 |
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#define | AARCH64_VSESR_EL2_ISS_MASK 0xffffffU |
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#define | AARCH64_VSESR_EL2_ISS_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffffU ) |
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#define | AARCH64_VSESR_EL2_EXT 0x1000U |
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#define | AARCH64_VSESR_EL2_AET(_val) ( ( _val ) << 14 ) |
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#define | AARCH64_VSESR_EL2_AET_SHIFT 14 |
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#define | AARCH64_VSESR_EL2_AET_MASK 0xc000U |
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#define | AARCH64_VSESR_EL2_AET_GET(_reg) ( ( ( _reg ) >> 14 ) & 0x3U ) |
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#define | AARCH64_VSESR_EL2_IDS 0x1000000U |
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#define | AARCH64_CNTHCTL_EL2_EL0PCTEN 0x1U |
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#define | AARCH64_CNTHCTL_EL2_EL1PCTEN_0 0x1U |
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#define | AARCH64_CNTHCTL_EL2_EL0VCTEN 0x2U |
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#define | AARCH64_CNTHCTL_EL2_EL1PCEN 0x2U |
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#define | AARCH64_CNTHCTL_EL2_EVNTEN 0x4U |
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#define | AARCH64_CNTHCTL_EL2_EVNTDIR 0x8U |
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#define | AARCH64_CNTHCTL_EL2_EVNTI(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_CNTHCTL_EL2_EVNTI_SHIFT 4 |
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#define | AARCH64_CNTHCTL_EL2_EVNTI_MASK 0xf0U |
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#define | AARCH64_CNTHCTL_EL2_EVNTI_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_CNTHCTL_EL2_EL0VTEN 0x100U |
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#define | AARCH64_CNTHCTL_EL2_EL0PTEN 0x200U |
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#define | AARCH64_CNTHCTL_EL2_EL1PCTEN_1 0x400U |
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#define | AARCH64_CNTHCTL_EL2_EL1PTEN 0x800U |
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#define | AARCH64_CNTHCTL_EL2_ECV 0x1000U |
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#define | AARCH64_CNTHCTL_EL2_EL1TVT 0x2000U |
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#define | AARCH64_CNTHCTL_EL2_EL1TVCT 0x4000U |
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#define | AARCH64_CNTHCTL_EL2_EL1NVPCT 0x8000U |
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#define | AARCH64_CNTHCTL_EL2_EL1NVVCT 0x10000U |
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#define | AARCH64_CNTHCTL_EL2_EVNTIS 0x20000U |
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#define | AARCH64_CNTHP_CTL_EL2_ENABLE 0x1U |
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#define | AARCH64_CNTHP_CTL_EL2_IMASK 0x2U |
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#define | AARCH64_CNTHP_CTL_EL2_ISTATUS 0x4U |
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#define | AARCH64_CNTHP_TVAL_EL2_TIMERVALUE(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_CNTHP_TVAL_EL2_TIMERVALUE_SHIFT 0 |
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#define | AARCH64_CNTHP_TVAL_EL2_TIMERVALUE_MASK 0xffffffffU |
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#define | AARCH64_CNTHP_TVAL_EL2_TIMERVALUE_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffffffU ) |
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#define | AARCH64_CNTHPS_CTL_EL2_ENABLE 0x1U |
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#define | AARCH64_CNTHPS_CTL_EL2_IMASK 0x2U |
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#define | AARCH64_CNTHPS_CTL_EL2_ISTATUS 0x4U |
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#define | AARCH64_CNTHPS_TVAL_EL2_TIMERVALUE(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_CNTHPS_TVAL_EL2_TIMERVALUE_SHIFT 0 |
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#define | AARCH64_CNTHPS_TVAL_EL2_TIMERVALUE_MASK 0xffffffffU |
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#define | AARCH64_CNTHPS_TVAL_EL2_TIMERVALUE_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffffffU ) |
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#define | AARCH64_CNTHV_CTL_EL2_ENABLE 0x1U |
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#define | AARCH64_CNTHV_CTL_EL2_IMASK 0x2U |
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#define | AARCH64_CNTHV_CTL_EL2_ISTATUS 0x4U |
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#define | AARCH64_CNTHV_TVAL_EL2_TIMERVALUE(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_CNTHV_TVAL_EL2_TIMERVALUE_SHIFT 0 |
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#define | AARCH64_CNTHV_TVAL_EL2_TIMERVALUE_MASK 0xffffffffU |
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#define | AARCH64_CNTHV_TVAL_EL2_TIMERVALUE_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffffffU ) |
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#define | AARCH64_CNTHVS_CTL_EL2_ENABLE 0x1U |
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#define | AARCH64_CNTHVS_CTL_EL2_IMASK 0x2U |
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#define | AARCH64_CNTHVS_CTL_EL2_ISTATUS 0x4U |
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#define | AARCH64_CNTHVS_TVAL_EL2_TIMERVALUE(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_CNTHVS_TVAL_EL2_TIMERVALUE_SHIFT 0 |
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#define | AARCH64_CNTHVS_TVAL_EL2_TIMERVALUE_MASK 0xffffffffU |
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#define | AARCH64_CNTHVS_TVAL_EL2_TIMERVALUE_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffffffU ) |
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#define | AARCH64_CNTKCTL_EL1_EL0PCTEN 0x1U |
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#define | AARCH64_CNTKCTL_EL1_EL0VCTEN 0x2U |
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#define | AARCH64_CNTKCTL_EL1_EVNTEN 0x4U |
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#define | AARCH64_CNTKCTL_EL1_EVNTDIR 0x8U |
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#define | AARCH64_CNTKCTL_EL1_EVNTI(_val) ( ( _val ) << 4 ) |
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#define | AARCH64_CNTKCTL_EL1_EVNTI_SHIFT 4 |
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#define | AARCH64_CNTKCTL_EL1_EVNTI_MASK 0xf0U |
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#define | AARCH64_CNTKCTL_EL1_EVNTI_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU ) |
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#define | AARCH64_CNTKCTL_EL1_EL0VTEN 0x100U |
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#define | AARCH64_CNTKCTL_EL1_EL0PTEN 0x200U |
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#define | AARCH64_CNTKCTL_EL1_EVNTIS 0x20000U |
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#define | AARCH64_CNTP_CTL_EL0_ENABLE 0x1U |
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#define | AARCH64_CNTP_CTL_EL0_IMASK 0x2U |
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#define | AARCH64_CNTP_CTL_EL0_ISTATUS 0x4U |
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#define | AARCH64_CNTP_TVAL_EL0_TIMERVALUE(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_CNTP_TVAL_EL0_TIMERVALUE_SHIFT 0 |
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#define | AARCH64_CNTP_TVAL_EL0_TIMERVALUE_MASK 0xffffffffU |
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#define | AARCH64_CNTP_TVAL_EL0_TIMERVALUE_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffffffU ) |
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#define | AARCH64_CNTPS_CTL_EL1_ENABLE 0x1U |
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#define | AARCH64_CNTPS_CTL_EL1_IMASK 0x2U |
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#define | AARCH64_CNTPS_CTL_EL1_ISTATUS 0x4U |
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#define | AARCH64_CNTPS_TVAL_EL1_TIMERVALUE(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_CNTPS_TVAL_EL1_TIMERVALUE_SHIFT 0 |
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#define | AARCH64_CNTPS_TVAL_EL1_TIMERVALUE_MASK 0xffffffffU |
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#define | AARCH64_CNTPS_TVAL_EL1_TIMERVALUE_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffffffU ) |
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#define | AARCH64_CNTV_CTL_EL0_ENABLE 0x1U |
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#define | AARCH64_CNTV_CTL_EL0_IMASK 0x2U |
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#define | AARCH64_CNTV_CTL_EL0_ISTATUS 0x4U |
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#define | AARCH64_CNTV_TVAL_EL0_TIMERVALUE(_val) ( ( _val ) << 0 ) |
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#define | AARCH64_CNTV_TVAL_EL0_TIMERVALUE_SHIFT 0 |
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#define | AARCH64_CNTV_TVAL_EL0_TIMERVALUE_MASK 0xffffffffU |
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#define | AARCH64_CNTV_TVAL_EL0_TIMERVALUE_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffffffU ) |
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1.9.6