xqspipsu.h

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/******************************************************************************
* Copyright (C) 2014 - 2022 Xilinx, Inc.  All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
 
 
/*****************************************************************************/
#ifndef XQSPIPSU_H_     
#define XQSPIPSU_H_     
#ifdef __cplusplus
extern "C" {
#endif
 
/***************************** Include Files *********************************/
 
#include "xstatus.h"
#include "xqspipsu_hw.h"
#include "xil_cache.h"
#include "xil_mem.h"
#if defined  (XCLOCKING)
#include "xil_clocking.h"
#endif
 
/**************************** Type Definitions *******************************/
typedef void (*XQspiPsu_StatusHandler) (const void *CallBackRef, u32 StatusEvent,
                    u32 ByteCount);
 
typedef struct {
    u8 *TxBfrPtr;   
    u8 *RxBfrPtr;   
    u32 ByteCount;  
    u32 BusWidth;   
    u32 Flags;  
    u8 PollData;    
    u32 PollTimeout;
    u8 PollStatusCmd; 
    u8 PollBusMask;   
    u64 RxAddr64bit;  
    u8 Xfer64bit;     
} XQspiPsu_Msg;
 
typedef struct {
    u16 DeviceId;       
    UINTPTR BaseAddress;    
    u32 InputClockHz;   
    u8  ConnectionMode; 
    u8  BusWidth;       
    u8 IsCacheCoherent; 
#if defined  (XCLOCKING)
    u32 RefClk;     
#endif
} XQspiPsu_Config;
 
typedef struct {
    XQspiPsu_Config Config;  
    u32 IsReady;         
    u8 *SendBufferPtr;   
    u8 *RecvBufferPtr;   
    u64 RecvBuffer;      
    u8 *GenFifoBufferPtr;    
    s32 TxBytes;     
    s32 RxBytes;     
    s32 GenFifoEntries;  
#ifdef __rtems__
    volatile
#endif
    u32 IsBusy;      
    u32 ReadMode;        
    u32 GenFifoCS;      
    u32 GenFifoBus;     
    s32 NumMsg;     
    s32 MsgCnt;     
    s32 IsUnaligned;    
    u8 IsManualstart;   
    XQspiPsu_Msg *Msg;  
    XQspiPsu_StatusHandler StatusHandler;   
    void *StatusRef;    
} XQspiPsu;
 
/***************** Macros (Inline Functions) Definitions *********************/
 
#define BYTES256_PER_PAGE   256U        
#define BYTES512_PER_PAGE   512U        
#define BYTES1024_PER_PAGE  1024U       
#define PAGES16_PER_SECTOR  16U     
#define PAGES128_PER_SECTOR 128U        
#define PAGES256_PER_SECTOR 256U        
#define PAGES512_PER_SECTOR 512U        
#define PAGES1024_PER_SECTOR    1024U       
#define NUM_OF_SECTORS2     2U      
#define NUM_OF_SECTORS4     4U      
#define NUM_OF_SECTORS8     8U      
#define NUM_OF_SECTORS16    16U     
#define NUM_OF_SECTORS32    32U     
#define NUM_OF_SECTORS64    64U     
#define NUM_OF_SECTORS128   128U        
#define NUM_OF_SECTORS256   256U        
#define NUM_OF_SECTORS512   512U        
#define NUM_OF_SECTORS1024  1024U       
#define NUM_OF_SECTORS2048  2048U       
#define NUM_OF_SECTORS4096  4096U       
#define NUM_OF_SECTORS8192  8192U       
#define SECTOR_SIZE_64K     0X10000U    
#define SECTOR_SIZE_128K    0X20000U    
#define SECTOR_SIZE_256K    0X40000U    
#define SECTOR_SIZE_512K    0X80000U    
#define XQSPIPSU_READMODE_DMA   0x0U    
#define XQSPIPSU_READMODE_IO    0x1U    
#define XQSPIPSU_SELECT_FLASH_CS_LOWER  0x1U    
#define XQSPIPSU_SELECT_FLASH_CS_UPPER  0x2U    
#define XQSPIPSU_SELECT_FLASH_CS_BOTH   0x3U    
#define XQSPIPSU_SELECT_FLASH_BUS_LOWER 0x1U    
#define XQSPIPSU_SELECT_FLASH_BUS_UPPER 0x2U    
#define XQSPIPSU_SELECT_FLASH_BUS_BOTH  0x3U    
#define XQSPIPSU_SELECT_MODE_SPI    0x1U    
#define XQSPIPSU_SELECT_MODE_DUALSPI    0x2U    
#define XQSPIPSU_SELECT_MODE_QUADSPI    0x4U    
#define XQSPIPSU_GENFIFO_CS_SETUP   0x05U   
#define XQSPIPSU_GENFIFO_CS_HOLD    0x04U   
#define XQSPIPSU_CLK_ACTIVE_LOW_OPTION  0x2U    
#define XQSPIPSU_CLK_PHASE_1_OPTION 0x4U    
#define XQSPIPSU_MANUAL_START_OPTION    0x8U    
#if !defined (versal)
#define XQSPIPSU_LQSPI_MODE_OPTION  0x20U   
#define XQSPIPSU_LQSPI_LESS_THEN_SIXTEENMB  1U 
#endif
 
#define XQSPIPSU_GENFIFO_EXP_START  0x100U 
#define XQSPIPSU_DMA_BYTES_MAX      0x10000000U 
#define XQSPIPSU_CLK_PRESCALE_2     0x00U   
#define XQSPIPSU_CLK_PRESCALE_4     0x01U   
#define XQSPIPSU_CLK_PRESCALE_8     0x02U   
#define XQSPIPSU_CLK_PRESCALE_16    0x03U   
#define XQSPIPSU_CLK_PRESCALE_32    0x04U   
#define XQSPIPSU_CLK_PRESCALE_64    0x05U   
#define XQSPIPSU_CLK_PRESCALE_128   0x06U   
#define XQSPIPSU_CLK_PRESCALE_256   0x07U   
#define XQSPIPSU_CR_PRESC_MAXIMUM   7U  
#define XQSPIPSU_CONNECTION_MODE_SINGLE     0U 
#define XQSPIPSU_CONNECTION_MODE_STACKED    1U 
#define XQSPIPSU_CONNECTION_MODE_PARALLEL   2U 
/*QSPI Frequencies*/
#define XQSPIPSU_FREQ_37_5MHZ 37500000U 
#define XQSPIPSU_FREQ_40MHZ 40000000U   
#define XQSPIPSU_FREQ_100MHZ 100000000U 
#define XQSPIPSU_FREQ_150MHZ 150000000U 
/* Add more flags as required */
#define XQSPIPSU_MSG_FLAG_STRIPE    0x1U 
#define XQSPIPSU_MSG_FLAG_RX        0x2U 
#define XQSPIPSU_MSG_FLAG_TX        0x4U 
#define XQSPIPSU_MSG_FLAG_POLL      0x8U 
#define XQSPIPSU_RXADDR_OVER_32BIT  0x100000000U 
#define XQSPIPSU_SET_WP     1 
#define XQspiPsu_Select(InstancePtr, Mask)  \
    XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + \
            XQSPIPSU_SEL_OFFSET, (Mask))
 
#define XQspiPsu_Enable(InstancePtr)    \
    XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + \
            XQSPIPSU_EN_OFFSET, XQSPIPSU_EN_MASK)
 
#define XQspiPsu_Disable(InstancePtr)   \
    XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + \
            XQSPIPSU_EN_OFFSET, 0x0U)
 
#if !defined (versal)
#define XQspiPsu_GetLqspiConfigReg(InstancePtr) \
    XQspiPsu_In32((XQSPIPS_BASEADDR) + \
            XQSPIPSU_LQSPI_CR_OFFSET)
#endif
 
/*****************************************************************************/
static inline void XQspiPsu_ManualStartEnable(XQspiPsu *InstancePtr)
{
    Xil_AssertVoid(InstancePtr != NULL);
    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
#ifdef DEBUG
    xil_printf("\nXQspiPsu_ManualStartEnable\r\n");
#endif
 
    if (InstancePtr->IsManualstart == (u8)TRUE) {
#ifdef DEBUG
        xil_printf("\nManual Start\r\n");
#endif
        XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
        XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET) |
            XQSPIPSU_CFG_START_GEN_FIFO_MASK);
    }
}
/*****************************************************************************/
static inline void XQspiPsu_GenFifoEntryCSAssert(const XQspiPsu *InstancePtr)
{
    u32 GenFifoEntry;
 
    Xil_AssertVoid(InstancePtr != NULL);
    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
#ifdef DEBUG
    xil_printf("\nXQspiPsu_GenFifoEntryCSAssert\r\n");
#endif
 
    GenFifoEntry = 0x0U;
    GenFifoEntry |= (XQSPIPSU_GENFIFO_MODE_SPI | InstancePtr->GenFifoCS |
                     InstancePtr->GenFifoBus | XQSPIPSU_GENFIFO_CS_SETUP);
#ifdef DEBUG
    xil_printf("\nFifoEntry=%08x\r\n", GenFifoEntry);
#endif
    XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
        XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
}
 
/*****************************************************************************/
static inline void XQspiPsu_GenFifoEntryCSDeAssert(const XQspiPsu *InstancePtr)
{
    u32 GenFifoEntry;
 
    Xil_AssertVoid(InstancePtr != NULL);
    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
#ifdef DEBUG
    xil_printf("\nXQspiPsu_GenFifoEntryCSDeAssert\r\n");
#endif
 
    GenFifoEntry = 0x0U;
    GenFifoEntry |= (XQSPIPSU_GENFIFO_MODE_SPI | InstancePtr->GenFifoBus |
                    XQSPIPSU_GENFIFO_CS_HOLD);
#ifdef DEBUG
    xil_printf("\nFifoEntry=%08x\r\n", GenFifoEntry);
#endif
    XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
        XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
}
 
/*****************************************************************************/
static inline void StubStatusHandler(const void *CallBackRef, u32 StatusEvent,
                u32 ByteCount)
{
    (const void) CallBackRef;
    (void) StatusEvent;
    (void) ByteCount;
 
    Xil_AssertVoidAlways();
}
/************************** Function Prototypes ******************************/
 
/* Initialization and reset */
XQspiPsu_Config *XQspiPsu_LookupConfig(u16 DeviceId);
s32 XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr,
               const XQspiPsu_Config *ConfigPtr,
               UINTPTR EffectiveAddr);
void XQspiPsu_Reset(XQspiPsu *InstancePtr);
void XQspiPsu_Abort(XQspiPsu *InstancePtr);
 
/* Transfer functions and handlers */
s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
                u32 NumMsg);
s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
                u32 NumMsg);
s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr);
void XQspiPsu_SetStatusHandler(XQspiPsu *InstancePtr, void *CallBackRef,
                XQspiPsu_StatusHandler FuncPointer);
 
/* Non blocking Transfer functions */
s32 XQspiPsu_StartDmaTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
                u32 NumMsg);
s32 XQspiPsu_CheckDmaDone(XQspiPsu *InstancePtr);
 
/* Configuration functions */
s32 XQspiPsu_SetClkPrescaler(const XQspiPsu *InstancePtr, u8 Prescaler);
void XQspiPsu_SelectFlash(XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus);
s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options);
s32 XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options);
u32 XQspiPsu_GetOptions(const XQspiPsu *InstancePtr);
s32 XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode);
void XQspiPsu_SetWP(const XQspiPsu *InstancePtr, u8 Value);
void XQspiPsu_WriteProtectToggle(const XQspiPsu *InstancePtr, u32 Toggle);
void XQspiPsu_Idle(const XQspiPsu *InstancePtr);
 
/************************** Variable Prototypes ******************************/
 
#ifndef __rtems__
extern XQspiPsu_Config XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES];
#endif /* __rtems__ */
 
#ifdef __cplusplus
}
#endif
 
 
#endif /* XQSPIPSU_H_ */