RTEMS 6.1-rc1
Data Fields
Matrix Struct Reference

Matrix hardware registers. More...

#include <component_matrix.h>

Data Fields

__IO uint32_t MATRIX_MCFG0
 (Matrix Offset: 0x0000) Master Configuration Register 0
 
__IO uint32_t MATRIX_MCFG1
 (Matrix Offset: 0x0004) Master Configuration Register 1
 
__IO uint32_t MATRIX_MCFG2
 (Matrix Offset: 0x0008) Master Configuration Register 2
 
__IO uint32_t MATRIX_MCFG3
 (Matrix Offset: 0x000C) Master Configuration Register 3
 
__IO uint32_t MATRIX_MCFG4
 (Matrix Offset: 0x0010) Master Configuration Register 4
 
__IO uint32_t MATRIX_MCFG5
 (Matrix Offset: 0x0014) Master Configuration Register 5
 
__IO uint32_t MATRIX_MCFG6
 (Matrix Offset: 0x0018) Master Configuration Register 6
 
__I uint32_t Reserved1 [1]
 
__IO uint32_t MATRIX_MCFG8
 (Matrix Offset: 0x0020) Master Configuration Register 8
 
__IO uint32_t MATRIX_MCFG9
 (Matrix Offset: 0x0024) Master Configuration Register 9
 
__IO uint32_t MATRIX_MCFG10
 (Matrix Offset: 0x0028) Master Configuration Register 10
 
__IO uint32_t MATRIX_MCFG11
 (Matrix Offset: 0x002C) Master Configuration Register 11
 
__I uint32_t Reserved2 [4]
 
__IO uint32_t MATRIX_SCFG [9]
 (Matrix Offset: 0x0040) Slave Configuration Register
 
__I uint32_t Reserved3 [7]
 
MatrixPr MATRIX_PR [MATRIXPR_NUMBER]
 (Matrix Offset: 0x0080) 0 .. 8
 
__I uint32_t Reserved4 [14]
 
__IO uint32_t MATRIX_MRCR
 (Matrix Offset: 0x0100) Master Remap Control Register
 
__I uint32_t Reserved5 [3]
 
__IO uint32_t CCFG_CAN0
 (Matrix Offset: 0x0110) CAN0 Configuration Register
 
__IO uint32_t CCFG_SYSIO
 (Matrix Offset: 0x0114) System I/O and CAN1 Configuration Register More...
 
__I uint32_t Reserved6 [3]
 
__IO uint32_t CCFG_SMCNFCS
 (Matrix Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register
 
__I uint32_t Reserved7 [47]
 
__IO uint32_t MATRIX_WPMR
 (Matrix Offset: 0x01E4) Write Protection Mode Register
 
__I uint32_t MATRIX_WPSR
 (Matrix Offset: 0x01E8) Write Protection Status Register
 
__IO uint32_t MATRIX_PRAS0
 (Matrix Offset: 0x0080) Priority Register A for Slave 0
 
__IO uint32_t MATRIX_PRBS0
 (Matrix Offset: 0x0084) Priority Register B for Slave 0
 
__IO uint32_t MATRIX_PRAS1
 (Matrix Offset: 0x0088) Priority Register A for Slave 1
 
__IO uint32_t MATRIX_PRBS1
 (Matrix Offset: 0x008C) Priority Register B for Slave 1
 
__IO uint32_t MATRIX_PRAS2
 (Matrix Offset: 0x0090) Priority Register A for Slave 2
 
__IO uint32_t MATRIX_PRBS2
 (Matrix Offset: 0x0094) Priority Register B for Slave 2
 
__IO uint32_t MATRIX_PRAS3
 (Matrix Offset: 0x0098) Priority Register A for Slave 3
 
__IO uint32_t MATRIX_PRBS3
 (Matrix Offset: 0x009C) Priority Register B for Slave 3
 
__IO uint32_t MATRIX_PRAS4
 (Matrix Offset: 0x00A0) Priority Register A for Slave 4
 
__IO uint32_t MATRIX_PRBS4
 (Matrix Offset: 0x00A4) Priority Register B for Slave 4
 
__IO uint32_t MATRIX_PRAS5
 (Matrix Offset: 0x00A8) Priority Register A for Slave 5
 
__IO uint32_t MATRIX_PRBS5
 (Matrix Offset: 0x00AC) Priority Register B for Slave 5
 
__IO uint32_t MATRIX_PRAS6
 (Matrix Offset: 0x00B0) Priority Register A for Slave 6
 
__IO uint32_t MATRIX_PRBS6
 (Matrix Offset: 0x00B4) Priority Register B for Slave 6
 
__IO uint32_t MATRIX_PRAS7
 (Matrix Offset: 0x00B8) Priority Register A for Slave 7
 
__IO uint32_t MATRIX_PRBS7
 (Matrix Offset: 0x00BC) Priority Register B for Slave 7
 
__IO uint32_t MATRIX_PRAS8
 (Matrix Offset: 0x00C0) Priority Register A for Slave 8
 
__IO uint32_t MATRIX_PRBS8
 (Matrix Offset: 0x00C4) Priority Register B for Slave 8
 
__IO uint32_t MATRIX_MCFG [12]
 (Matrix Offset: 0x0000) Master Configuration Register
 
__I uint32_t MATRIX_VERSION
 (Matrix Offset: 0x01FC) Version Register
 

Detailed Description

Matrix hardware registers.

Field Documentation

◆ CCFG_SYSIO

__IO uint32_t Matrix::CCFG_SYSIO

(Matrix Offset: 0x0114) System I/O and CAN1 Configuration Register

(Matrix Offset: 0x0114) System I/O Configuration Register

The documentation for this struct was generated from the following files:
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