RTEMS 6.1-rc1
grspw2-regs.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2021, 2023 embedded brains GmbH & Co. KG
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36/*
37 * This file is part of the RTEMS quality process and was automatically
38 * generated. If you find something that needs to be fixed or
39 * worded better please post a report or patch to an RTEMS mailing list
40 * or raise a bug report:
41 *
42 * https://www.rtems.org/bugs.html
43 *
44 * For information on updating and regenerating please refer to the How-To
45 * section in the Software Requirements Engineering chapter of the
46 * RTEMS Software Engineering manual. The manual is provided as a part of
47 * a release. For development sources please refer to the online
48 * documentation at:
49 *
50 * https://docs.rtems.org
51 */
52
53/* Generated from spec:/dev/grlib/if/grspw2-header */
54
55#ifndef _GRLIB_GRSPW2_REGS_H
56#define _GRLIB_GRSPW2_REGS_H
57
58#include <stdint.h>
59
60#ifdef __cplusplus
61extern "C" {
62#endif
63
64/* Generated from spec:/dev/grlib/if/grspw2-dma */
65
84#define GRSPW2_DMACTRL_INTNUM_SHIFT 26
85#define GRSPW2_DMACTRL_INTNUM_MASK 0xfc000000U
86#define GRSPW2_DMACTRL_INTNUM_GET( _reg ) \
87 ( ( ( _reg ) & GRSPW2_DMACTRL_INTNUM_MASK ) >> \
88 GRSPW2_DMACTRL_INTNUM_SHIFT )
89#define GRSPW2_DMACTRL_INTNUM_SET( _reg, _val ) \
90 ( ( ( _reg ) & ~GRSPW2_DMACTRL_INTNUM_MASK ) | \
91 ( ( ( _val ) << GRSPW2_DMACTRL_INTNUM_SHIFT ) & \
92 GRSPW2_DMACTRL_INTNUM_MASK ) )
93#define GRSPW2_DMACTRL_INTNUM( _val ) \
94 ( ( ( _val ) << GRSPW2_DMACTRL_INTNUM_SHIFT ) & \
95 GRSPW2_DMACTRL_INTNUM_MASK )
96
97#define GRSPW2_DMACTRL_RES_SHIFT 24
98#define GRSPW2_DMACTRL_RES_MASK 0x3000000U
99#define GRSPW2_DMACTRL_RES_GET( _reg ) \
100 ( ( ( _reg ) & GRSPW2_DMACTRL_RES_MASK ) >> \
101 GRSPW2_DMACTRL_RES_SHIFT )
102#define GRSPW2_DMACTRL_RES_SET( _reg, _val ) \
103 ( ( ( _reg ) & ~GRSPW2_DMACTRL_RES_MASK ) | \
104 ( ( ( _val ) << GRSPW2_DMACTRL_RES_SHIFT ) & \
105 GRSPW2_DMACTRL_RES_MASK ) )
106#define GRSPW2_DMACTRL_RES( _val ) \
107 ( ( ( _val ) << GRSPW2_DMACTRL_RES_SHIFT ) & \
108 GRSPW2_DMACTRL_RES_MASK )
109
110#define GRSPW2_DMACTRL_EP 0x800000U
111
112#define GRSPW2_DMACTRL_TR 0x400000U
113
114#define GRSPW2_DMACTRL_IE 0x200000U
115
116#define GRSPW2_DMACTRL_IT 0x100000U
117
118#define GRSPW2_DMACTRL_RP 0x80000U
119
120#define GRSPW2_DMACTRL_TP 0x40000U
121
122#define GRSPW2_DMACTRL_TL 0x20000U
123
124#define GRSPW2_DMACTRL_LE 0x10000U
125
126#define GRSPW2_DMACTRL_SP 0x8000U
127
128#define GRSPW2_DMACTRL_SA 0x4000U
129
130#define GRSPW2_DMACTRL_EN 0x2000U
131
132#define GRSPW2_DMACTRL_NS 0x1000U
133
134#define GRSPW2_DMACTRL_RD 0x800U
135
136#define GRSPW2_DMACTRL_RX 0x400U
137
138#define GRSPW2_DMACTRL_AT 0x200U
139
140#define GRSPW2_DMACTRL_RA 0x100U
141
142#define GRSPW2_DMACTRL_TA 0x80U
143
144#define GRSPW2_DMACTRL_PR 0x40U
145
146#define GRSPW2_DMACTRL_PS 0x20U
147
148#define GRSPW2_DMACTRL_AI 0x10U
149
150#define GRSPW2_DMACTRL_RI 0x8U
151
152#define GRSPW2_DMACTRL_TI 0x4U
153
154#define GRSPW2_DMACTRL_RE 0x2U
155
156#define GRSPW2_DMACTRL_TE 0x1U
157
168#define GRSPW2_DMAMAXLEN_RXMAXLEN_SHIFT 2
169#define GRSPW2_DMAMAXLEN_RXMAXLEN_MASK 0x1fffffcU
170#define GRSPW2_DMAMAXLEN_RXMAXLEN_GET( _reg ) \
171 ( ( ( _reg ) & GRSPW2_DMAMAXLEN_RXMAXLEN_MASK ) >> \
172 GRSPW2_DMAMAXLEN_RXMAXLEN_SHIFT )
173#define GRSPW2_DMAMAXLEN_RXMAXLEN_SET( _reg, _val ) \
174 ( ( ( _reg ) & ~GRSPW2_DMAMAXLEN_RXMAXLEN_MASK ) | \
175 ( ( ( _val ) << GRSPW2_DMAMAXLEN_RXMAXLEN_SHIFT ) & \
176 GRSPW2_DMAMAXLEN_RXMAXLEN_MASK ) )
177#define GRSPW2_DMAMAXLEN_RXMAXLEN( _val ) \
178 ( ( ( _val ) << GRSPW2_DMAMAXLEN_RXMAXLEN_SHIFT ) & \
179 GRSPW2_DMAMAXLEN_RXMAXLEN_MASK )
180
181#define GRSPW2_DMAMAXLEN_RES_SHIFT 0
182#define GRSPW2_DMAMAXLEN_RES_MASK 0x3U
183#define GRSPW2_DMAMAXLEN_RES_GET( _reg ) \
184 ( ( ( _reg ) & GRSPW2_DMAMAXLEN_RES_MASK ) >> \
185 GRSPW2_DMAMAXLEN_RES_SHIFT )
186#define GRSPW2_DMAMAXLEN_RES_SET( _reg, _val ) \
187 ( ( ( _reg ) & ~GRSPW2_DMAMAXLEN_RES_MASK ) | \
188 ( ( ( _val ) << GRSPW2_DMAMAXLEN_RES_SHIFT ) & \
189 GRSPW2_DMAMAXLEN_RES_MASK ) )
190#define GRSPW2_DMAMAXLEN_RES( _val ) \
191 ( ( ( _val ) << GRSPW2_DMAMAXLEN_RES_SHIFT ) & \
192 GRSPW2_DMAMAXLEN_RES_MASK )
193
205#define GRSPW2_DMATXDESC_DESCBASEADDR_SHIFT 0
206#define GRSPW2_DMATXDESC_DESCBASEADDR_MASK 0xffffffffU
207#define GRSPW2_DMATXDESC_DESCBASEADDR_GET( _reg ) \
208 ( ( ( _reg ) & GRSPW2_DMATXDESC_DESCBASEADDR_MASK ) >> \
209 GRSPW2_DMATXDESC_DESCBASEADDR_SHIFT )
210#define GRSPW2_DMATXDESC_DESCBASEADDR_SET( _reg, _val ) \
211 ( ( ( _reg ) & ~GRSPW2_DMATXDESC_DESCBASEADDR_MASK ) | \
212 ( ( ( _val ) << GRSPW2_DMATXDESC_DESCBASEADDR_SHIFT ) & \
213 GRSPW2_DMATXDESC_DESCBASEADDR_MASK ) )
214#define GRSPW2_DMATXDESC_DESCBASEADDR( _val ) \
215 ( ( ( _val ) << GRSPW2_DMATXDESC_DESCBASEADDR_SHIFT ) & \
216 GRSPW2_DMATXDESC_DESCBASEADDR_MASK )
217
218#define GRSPW2_DMATXDESC_DESCSEL_SHIFT 4
219#define GRSPW2_DMATXDESC_DESCSEL_MASK 0xfffffff0U
220#define GRSPW2_DMATXDESC_DESCSEL_GET( _reg ) \
221 ( ( ( _reg ) & GRSPW2_DMATXDESC_DESCSEL_MASK ) >> \
222 GRSPW2_DMATXDESC_DESCSEL_SHIFT )
223#define GRSPW2_DMATXDESC_DESCSEL_SET( _reg, _val ) \
224 ( ( ( _reg ) & ~GRSPW2_DMATXDESC_DESCSEL_MASK ) | \
225 ( ( ( _val ) << GRSPW2_DMATXDESC_DESCSEL_SHIFT ) & \
226 GRSPW2_DMATXDESC_DESCSEL_MASK ) )
227#define GRSPW2_DMATXDESC_DESCSEL( _val ) \
228 ( ( ( _val ) << GRSPW2_DMATXDESC_DESCSEL_SHIFT ) & \
229 GRSPW2_DMATXDESC_DESCSEL_MASK )
230
242#define GRSPW2_DMARXDESC_DESCBASEADDR_SHIFT 10
243#define GRSPW2_DMARXDESC_DESCBASEADDR_MASK 0xfffffc00U
244#define GRSPW2_DMARXDESC_DESCBASEADDR_GET( _reg ) \
245 ( ( ( _reg ) & GRSPW2_DMARXDESC_DESCBASEADDR_MASK ) >> \
246 GRSPW2_DMARXDESC_DESCBASEADDR_SHIFT )
247#define GRSPW2_DMARXDESC_DESCBASEADDR_SET( _reg, _val ) \
248 ( ( ( _reg ) & ~GRSPW2_DMARXDESC_DESCBASEADDR_MASK ) | \
249 ( ( ( _val ) << GRSPW2_DMARXDESC_DESCBASEADDR_SHIFT ) & \
250 GRSPW2_DMARXDESC_DESCBASEADDR_MASK ) )
251#define GRSPW2_DMARXDESC_DESCBASEADDR( _val ) \
252 ( ( ( _val ) << GRSPW2_DMARXDESC_DESCBASEADDR_SHIFT ) & \
253 GRSPW2_DMARXDESC_DESCBASEADDR_MASK )
254
255#define GRSPW2_DMARXDESC_DESCSEL_SHIFT 3
256#define GRSPW2_DMARXDESC_DESCSEL_MASK 0x3f8U
257#define GRSPW2_DMARXDESC_DESCSEL_GET( _reg ) \
258 ( ( ( _reg ) & GRSPW2_DMARXDESC_DESCSEL_MASK ) >> \
259 GRSPW2_DMARXDESC_DESCSEL_SHIFT )
260#define GRSPW2_DMARXDESC_DESCSEL_SET( _reg, _val ) \
261 ( ( ( _reg ) & ~GRSPW2_DMARXDESC_DESCSEL_MASK ) | \
262 ( ( ( _val ) << GRSPW2_DMARXDESC_DESCSEL_SHIFT ) & \
263 GRSPW2_DMARXDESC_DESCSEL_MASK ) )
264#define GRSPW2_DMARXDESC_DESCSEL( _val ) \
265 ( ( ( _val ) << GRSPW2_DMARXDESC_DESCSEL_SHIFT ) & \
266 GRSPW2_DMARXDESC_DESCSEL_MASK )
267
278#define GRSPW2_DMAADDR_MASK_SHIFT 8
279#define GRSPW2_DMAADDR_MASK_MASK 0xff00U
280#define GRSPW2_DMAADDR_MASK_GET( _reg ) \
281 ( ( ( _reg ) & GRSPW2_DMAADDR_MASK_MASK ) >> \
282 GRSPW2_DMAADDR_MASK_SHIFT )
283#define GRSPW2_DMAADDR_MASK_SET( _reg, _val ) \
284 ( ( ( _reg ) & ~GRSPW2_DMAADDR_MASK_MASK ) | \
285 ( ( ( _val ) << GRSPW2_DMAADDR_MASK_SHIFT ) & \
286 GRSPW2_DMAADDR_MASK_MASK ) )
287#define GRSPW2_DMAADDR_MASK( _val ) \
288 ( ( ( _val ) << GRSPW2_DMAADDR_MASK_SHIFT ) & \
289 GRSPW2_DMAADDR_MASK_MASK )
290
291#define GRSPW2_DMAADDR_ADDR_SHIFT 0
292#define GRSPW2_DMAADDR_ADDR_MASK 0xffU
293#define GRSPW2_DMAADDR_ADDR_GET( _reg ) \
294 ( ( ( _reg ) & GRSPW2_DMAADDR_ADDR_MASK ) >> \
295 GRSPW2_DMAADDR_ADDR_SHIFT )
296#define GRSPW2_DMAADDR_ADDR_SET( _reg, _val ) \
297 ( ( ( _reg ) & ~GRSPW2_DMAADDR_ADDR_MASK ) | \
298 ( ( ( _val ) << GRSPW2_DMAADDR_ADDR_SHIFT ) & \
299 GRSPW2_DMAADDR_ADDR_MASK ) )
300#define GRSPW2_DMAADDR_ADDR( _val ) \
301 ( ( ( _val ) << GRSPW2_DMAADDR_ADDR_SHIFT ) & \
302 GRSPW2_DMAADDR_ADDR_MASK )
303
309typedef struct grspw2_dma {
313 uint32_t dmactrl;
314
318 uint32_t dmamaxlen;
319
323 uint32_t dmatxdesc;
324
328 uint32_t dmarxdesc;
329
333 uint32_t dmaaddr;
334
335 uint32_t reserved_14_20[ 3 ];
336} grspw2_dma;
337
340/* Generated from spec:/dev/grlib/if/grspw2 */
341
360#define GRSPW2_CTRL_RA 0x80000000U
361
362#define GRSPW2_CTRL_RX 0x40000000U
363
364#define GRSPW2_CTRL_RC 0x20000000U
365
366#define GRSPW2_CTRL_NCH_SHIFT 27
367#define GRSPW2_CTRL_NCH_MASK 0x18000000U
368#define GRSPW2_CTRL_NCH_GET( _reg ) \
369 ( ( ( _reg ) & GRSPW2_CTRL_NCH_MASK ) >> \
370 GRSPW2_CTRL_NCH_SHIFT )
371#define GRSPW2_CTRL_NCH_SET( _reg, _val ) \
372 ( ( ( _reg ) & ~GRSPW2_CTRL_NCH_MASK ) | \
373 ( ( ( _val ) << GRSPW2_CTRL_NCH_SHIFT ) & \
374 GRSPW2_CTRL_NCH_MASK ) )
375#define GRSPW2_CTRL_NCH( _val ) \
376 ( ( ( _val ) << GRSPW2_CTRL_NCH_SHIFT ) & \
377 GRSPW2_CTRL_NCH_MASK )
378
379#define GRSPW2_CTRL_PO 0x4000000U
380
381#define GRSPW2_CTRL_CC 0x2000000U
382
383#define GRSPW2_CTRL_ID 0x1000000U
384
385#define GRSPW2_CTRL_R 0x800000U
386
387#define GRSPW2_CTRL_LE 0x400000U
388
389#define GRSPW2_CTRL_PS 0x200000U
390
391#define GRSPW2_CTRL_NP 0x100000U
392
393#define GRSPW2_CTRL_PNPA_SHIFT 18
394#define GRSPW2_CTRL_PNPA_MASK 0xc0000U
395#define GRSPW2_CTRL_PNPA_GET( _reg ) \
396 ( ( ( _reg ) & GRSPW2_CTRL_PNPA_MASK ) >> \
397 GRSPW2_CTRL_PNPA_SHIFT )
398#define GRSPW2_CTRL_PNPA_SET( _reg, _val ) \
399 ( ( ( _reg ) & ~GRSPW2_CTRL_PNPA_MASK ) | \
400 ( ( ( _val ) << GRSPW2_CTRL_PNPA_SHIFT ) & \
401 GRSPW2_CTRL_PNPA_MASK ) )
402#define GRSPW2_CTRL_PNPA( _val ) \
403 ( ( ( _val ) << GRSPW2_CTRL_PNPA_SHIFT ) & \
404 GRSPW2_CTRL_PNPA_MASK )
405
406#define GRSPW2_CTRL_RD 0x20000U
407
408#define GRSPW2_CTRL_RE 0x10000U
409
410#define GRSPW2_CTRL_PE 0x8000U
411
412#define GRSPW2_CTRL_R 0x4000U
413
414#define GRSPW2_CTRL_TL 0x2000U
415
416#define GRSPW2_CTRL_TF 0x1000U
417
418#define GRSPW2_CTRL_TR 0x800U
419
420#define GRSPW2_CTRL_TT 0x400U
421
422#define GRSPW2_CTRL_LI 0x200U
423
424#define GRSPW2_CTRL_TQ 0x100U
425
426#define GRSPW2_CTRL_R 0x80U
427
428#define GRSPW2_CTRL_RS 0x40U
429
430#define GRSPW2_CTRL_PM 0x20U
431
432#define GRSPW2_CTRL_TI 0x10U
433
434#define GRSPW2_CTRL_IE 0x8U
435
436#define GRSPW2_CTRL_AS 0x4U
437
438#define GRSPW2_CTRL_LS 0x2U
439
440#define GRSPW2_CTRL_LD 0x1U
441
452#define GRSPW2_STS_NRXD_SHIFT 26
453#define GRSPW2_STS_NRXD_MASK 0xc000000U
454#define GRSPW2_STS_NRXD_GET( _reg ) \
455 ( ( ( _reg ) & GRSPW2_STS_NRXD_MASK ) >> \
456 GRSPW2_STS_NRXD_SHIFT )
457#define GRSPW2_STS_NRXD_SET( _reg, _val ) \
458 ( ( ( _reg ) & ~GRSPW2_STS_NRXD_MASK ) | \
459 ( ( ( _val ) << GRSPW2_STS_NRXD_SHIFT ) & \
460 GRSPW2_STS_NRXD_MASK ) )
461#define GRSPW2_STS_NRXD( _val ) \
462 ( ( ( _val ) << GRSPW2_STS_NRXD_SHIFT ) & \
463 GRSPW2_STS_NRXD_MASK )
464
465#define GRSPW2_STS_NTXD 0x2000000U
466
467#define GRSPW2_STS_LS_SHIFT 21
468#define GRSPW2_STS_LS_MASK 0xe00000U
469#define GRSPW2_STS_LS_GET( _reg ) \
470 ( ( ( _reg ) & GRSPW2_STS_LS_MASK ) >> \
471 GRSPW2_STS_LS_SHIFT )
472#define GRSPW2_STS_LS_SET( _reg, _val ) \
473 ( ( ( _reg ) & ~GRSPW2_STS_LS_MASK ) | \
474 ( ( ( _val ) << GRSPW2_STS_LS_SHIFT ) & \
475 GRSPW2_STS_LS_MASK ) )
476#define GRSPW2_STS_LS( _val ) \
477 ( ( ( _val ) << GRSPW2_STS_LS_SHIFT ) & \
478 GRSPW2_STS_LS_MASK )
479
480#define GRSPW2_STS_AP 0x200U
481
482#define GRSPW2_STS_EE 0x100U
483
484#define GRSPW2_STS_IA 0x80U
485
486#define GRSPW2_STS_RES_SHIFT 5
487#define GRSPW2_STS_RES_MASK 0x60U
488#define GRSPW2_STS_RES_GET( _reg ) \
489 ( ( ( _reg ) & GRSPW2_STS_RES_MASK ) >> \
490 GRSPW2_STS_RES_SHIFT )
491#define GRSPW2_STS_RES_SET( _reg, _val ) \
492 ( ( ( _reg ) & ~GRSPW2_STS_RES_MASK ) | \
493 ( ( ( _val ) << GRSPW2_STS_RES_SHIFT ) & \
494 GRSPW2_STS_RES_MASK ) )
495#define GRSPW2_STS_RES( _val ) \
496 ( ( ( _val ) << GRSPW2_STS_RES_SHIFT ) & \
497 GRSPW2_STS_RES_MASK )
498
499#define GRSPW2_STS_PE 0x10U
500
501#define GRSPW2_STS_DE 0x8U
502
503#define GRSPW2_STS_ER 0x4U
504
505#define GRSPW2_STS_CE 0x2U
506
507#define GRSPW2_STS_TO 0x1U
508
519#define GRSPW2_DEFADDR_DEFMASK_SHIFT 8
520#define GRSPW2_DEFADDR_DEFMASK_MASK 0xff00U
521#define GRSPW2_DEFADDR_DEFMASK_GET( _reg ) \
522 ( ( ( _reg ) & GRSPW2_DEFADDR_DEFMASK_MASK ) >> \
523 GRSPW2_DEFADDR_DEFMASK_SHIFT )
524#define GRSPW2_DEFADDR_DEFMASK_SET( _reg, _val ) \
525 ( ( ( _reg ) & ~GRSPW2_DEFADDR_DEFMASK_MASK ) | \
526 ( ( ( _val ) << GRSPW2_DEFADDR_DEFMASK_SHIFT ) & \
527 GRSPW2_DEFADDR_DEFMASK_MASK ) )
528#define GRSPW2_DEFADDR_DEFMASK( _val ) \
529 ( ( ( _val ) << GRSPW2_DEFADDR_DEFMASK_SHIFT ) & \
530 GRSPW2_DEFADDR_DEFMASK_MASK )
531
532#define GRSPW2_DEFADDR_DEFADDR_SHIFT 0
533#define GRSPW2_DEFADDR_DEFADDR_MASK 0xffU
534#define GRSPW2_DEFADDR_DEFADDR_GET( _reg ) \
535 ( ( ( _reg ) & GRSPW2_DEFADDR_DEFADDR_MASK ) >> \
536 GRSPW2_DEFADDR_DEFADDR_SHIFT )
537#define GRSPW2_DEFADDR_DEFADDR_SET( _reg, _val ) \
538 ( ( ( _reg ) & ~GRSPW2_DEFADDR_DEFADDR_MASK ) | \
539 ( ( ( _val ) << GRSPW2_DEFADDR_DEFADDR_SHIFT ) & \
540 GRSPW2_DEFADDR_DEFADDR_MASK ) )
541#define GRSPW2_DEFADDR_DEFADDR( _val ) \
542 ( ( ( _val ) << GRSPW2_DEFADDR_DEFADDR_SHIFT ) & \
543 GRSPW2_DEFADDR_DEFADDR_MASK )
544
555#define GRSPW2_CLKDIV_CLKDIVSTART_SHIFT 8
556#define GRSPW2_CLKDIV_CLKDIVSTART_MASK 0xff00U
557#define GRSPW2_CLKDIV_CLKDIVSTART_GET( _reg ) \
558 ( ( ( _reg ) & GRSPW2_CLKDIV_CLKDIVSTART_MASK ) >> \
559 GRSPW2_CLKDIV_CLKDIVSTART_SHIFT )
560#define GRSPW2_CLKDIV_CLKDIVSTART_SET( _reg, _val ) \
561 ( ( ( _reg ) & ~GRSPW2_CLKDIV_CLKDIVSTART_MASK ) | \
562 ( ( ( _val ) << GRSPW2_CLKDIV_CLKDIVSTART_SHIFT ) & \
563 GRSPW2_CLKDIV_CLKDIVSTART_MASK ) )
564#define GRSPW2_CLKDIV_CLKDIVSTART( _val ) \
565 ( ( ( _val ) << GRSPW2_CLKDIV_CLKDIVSTART_SHIFT ) & \
566 GRSPW2_CLKDIV_CLKDIVSTART_MASK )
567
568#define GRSPW2_CLKDIV_CLKDIVRUN_SHIFT 0
569#define GRSPW2_CLKDIV_CLKDIVRUN_MASK 0xffU
570#define GRSPW2_CLKDIV_CLKDIVRUN_GET( _reg ) \
571 ( ( ( _reg ) & GRSPW2_CLKDIV_CLKDIVRUN_MASK ) >> \
572 GRSPW2_CLKDIV_CLKDIVRUN_SHIFT )
573#define GRSPW2_CLKDIV_CLKDIVRUN_SET( _reg, _val ) \
574 ( ( ( _reg ) & ~GRSPW2_CLKDIV_CLKDIVRUN_MASK ) | \
575 ( ( ( _val ) << GRSPW2_CLKDIV_CLKDIVRUN_SHIFT ) & \
576 GRSPW2_CLKDIV_CLKDIVRUN_MASK ) )
577#define GRSPW2_CLKDIV_CLKDIVRUN( _val ) \
578 ( ( ( _val ) << GRSPW2_CLKDIV_CLKDIVRUN_SHIFT ) & \
579 GRSPW2_CLKDIV_CLKDIVRUN_MASK )
580
591#define GRSPW2_DKEY_DESTKEY_SHIFT 0
592#define GRSPW2_DKEY_DESTKEY_MASK 0xffU
593#define GRSPW2_DKEY_DESTKEY_GET( _reg ) \
594 ( ( ( _reg ) & GRSPW2_DKEY_DESTKEY_MASK ) >> \
595 GRSPW2_DKEY_DESTKEY_SHIFT )
596#define GRSPW2_DKEY_DESTKEY_SET( _reg, _val ) \
597 ( ( ( _reg ) & ~GRSPW2_DKEY_DESTKEY_MASK ) | \
598 ( ( ( _val ) << GRSPW2_DKEY_DESTKEY_SHIFT ) & \
599 GRSPW2_DKEY_DESTKEY_MASK ) )
600#define GRSPW2_DKEY_DESTKEY( _val ) \
601 ( ( ( _val ) << GRSPW2_DKEY_DESTKEY_SHIFT ) & \
602 GRSPW2_DKEY_DESTKEY_MASK )
603
614#define GRSPW2_TC_TCTRL_SHIFT 6
615#define GRSPW2_TC_TCTRL_MASK 0xc0U
616#define GRSPW2_TC_TCTRL_GET( _reg ) \
617 ( ( ( _reg ) & GRSPW2_TC_TCTRL_MASK ) >> \
618 GRSPW2_TC_TCTRL_SHIFT )
619#define GRSPW2_TC_TCTRL_SET( _reg, _val ) \
620 ( ( ( _reg ) & ~GRSPW2_TC_TCTRL_MASK ) | \
621 ( ( ( _val ) << GRSPW2_TC_TCTRL_SHIFT ) & \
622 GRSPW2_TC_TCTRL_MASK ) )
623#define GRSPW2_TC_TCTRL( _val ) \
624 ( ( ( _val ) << GRSPW2_TC_TCTRL_SHIFT ) & \
625 GRSPW2_TC_TCTRL_MASK )
626
627#define GRSPW2_TC_TIMECNT_SHIFT 0
628#define GRSPW2_TC_TIMECNT_MASK 0x3fU
629#define GRSPW2_TC_TIMECNT_GET( _reg ) \
630 ( ( ( _reg ) & GRSPW2_TC_TIMECNT_MASK ) >> \
631 GRSPW2_TC_TIMECNT_SHIFT )
632#define GRSPW2_TC_TIMECNT_SET( _reg, _val ) \
633 ( ( ( _reg ) & ~GRSPW2_TC_TIMECNT_MASK ) | \
634 ( ( ( _val ) << GRSPW2_TC_TIMECNT_SHIFT ) & \
635 GRSPW2_TC_TIMECNT_MASK ) )
636#define GRSPW2_TC_TIMECNT( _val ) \
637 ( ( ( _val ) << GRSPW2_TC_TIMECNT_SHIFT ) & \
638 GRSPW2_TC_TIMECNT_MASK )
639
650#define GRSPW2_INTCTRL_INTNUM_SHIFT 26
651#define GRSPW2_INTCTRL_INTNUM_MASK 0xfc000000U
652#define GRSPW2_INTCTRL_INTNUM_GET( _reg ) \
653 ( ( ( _reg ) & GRSPW2_INTCTRL_INTNUM_MASK ) >> \
654 GRSPW2_INTCTRL_INTNUM_SHIFT )
655#define GRSPW2_INTCTRL_INTNUM_SET( _reg, _val ) \
656 ( ( ( _reg ) & ~GRSPW2_INTCTRL_INTNUM_MASK ) | \
657 ( ( ( _val ) << GRSPW2_INTCTRL_INTNUM_SHIFT ) & \
658 GRSPW2_INTCTRL_INTNUM_MASK ) )
659#define GRSPW2_INTCTRL_INTNUM( _val ) \
660 ( ( ( _val ) << GRSPW2_INTCTRL_INTNUM_SHIFT ) & \
661 GRSPW2_INTCTRL_INTNUM_MASK )
662
663#define GRSPW2_INTCTRL_RS 0x2000000U
664
665#define GRSPW2_INTCTRL_EE 0x1000000U
666
667#define GRSPW2_INTCTRL_IA 0x800000U
668
669#define GRSPW2_INTCTRL_RES 0x2U
670
671#define GRSPW2_INTCTRL_TQ_SHIFT 21
672#define GRSPW2_INTCTRL_TQ_MASK 0x600000U
673#define GRSPW2_INTCTRL_TQ_GET( _reg ) \
674 ( ( ( _reg ) & GRSPW2_INTCTRL_TQ_MASK ) >> \
675 GRSPW2_INTCTRL_TQ_SHIFT )
676#define GRSPW2_INTCTRL_TQ_SET( _reg, _val ) \
677 ( ( ( _reg ) & ~GRSPW2_INTCTRL_TQ_MASK ) | \
678 ( ( ( _val ) << GRSPW2_INTCTRL_TQ_SHIFT ) & \
679 GRSPW2_INTCTRL_TQ_MASK ) )
680#define GRSPW2_INTCTRL_TQ( _val ) \
681 ( ( ( _val ) << GRSPW2_INTCTRL_TQ_SHIFT ) & \
682 GRSPW2_INTCTRL_TQ_MASK )
683
684#define GRSPW2_INTCTRL_AQ 0x100000U
685
686#define GRSPW2_INTCTRL_IQ 0x80000U
687
688#define GRSPW2_INTCTRL_RES 0x40000U
689
690#define GRSPW2_INTCTRL_AA_SHIFT 16
691#define GRSPW2_INTCTRL_AA_MASK 0x30000U
692#define GRSPW2_INTCTRL_AA_GET( _reg ) \
693 ( ( ( _reg ) & GRSPW2_INTCTRL_AA_MASK ) >> \
694 GRSPW2_INTCTRL_AA_SHIFT )
695#define GRSPW2_INTCTRL_AA_SET( _reg, _val ) \
696 ( ( ( _reg ) & ~GRSPW2_INTCTRL_AA_MASK ) | \
697 ( ( ( _val ) << GRSPW2_INTCTRL_AA_SHIFT ) & \
698 GRSPW2_INTCTRL_AA_MASK ) )
699#define GRSPW2_INTCTRL_AA( _val ) \
700 ( ( ( _val ) << GRSPW2_INTCTRL_AA_SHIFT ) & \
701 GRSPW2_INTCTRL_AA_MASK )
702
703#define GRSPW2_INTCTRL_AT 0x8000U
704
705#define GRSPW2_INTCTRL_IT 0x4000U
706
707#define GRSPW2_INTCTRL_RES 0x2000U
708
709#define GRSPW2_INTCTRL_ID_SHIFT 8
710#define GRSPW2_INTCTRL_ID_MASK 0x1f00U
711#define GRSPW2_INTCTRL_ID_GET( _reg ) \
712 ( ( ( _reg ) & GRSPW2_INTCTRL_ID_MASK ) >> \
713 GRSPW2_INTCTRL_ID_SHIFT )
714#define GRSPW2_INTCTRL_ID_SET( _reg, _val ) \
715 ( ( ( _reg ) & ~GRSPW2_INTCTRL_ID_MASK ) | \
716 ( ( ( _val ) << GRSPW2_INTCTRL_ID_SHIFT ) & \
717 GRSPW2_INTCTRL_ID_MASK ) )
718#define GRSPW2_INTCTRL_ID( _val ) \
719 ( ( ( _val ) << GRSPW2_INTCTRL_ID_SHIFT ) & \
720 GRSPW2_INTCTRL_ID_MASK )
721
722#define GRSPW2_INTCTRL_II 0x80U
723
724#define GRSPW2_INTCTRL_TXINT 0x40U
725
736#define GRSPW2_INTRX_RXIRQ_SHIFT 0
737#define GRSPW2_INTRX_RXIRQ_MASK 0xffffffffU
738#define GRSPW2_INTRX_RXIRQ_GET( _reg ) \
739 ( ( ( _reg ) & GRSPW2_INTRX_RXIRQ_MASK ) >> \
740 GRSPW2_INTRX_RXIRQ_SHIFT )
741#define GRSPW2_INTRX_RXIRQ_SET( _reg, _val ) \
742 ( ( ( _reg ) & ~GRSPW2_INTRX_RXIRQ_MASK ) | \
743 ( ( ( _val ) << GRSPW2_INTRX_RXIRQ_SHIFT ) & \
744 GRSPW2_INTRX_RXIRQ_MASK ) )
745#define GRSPW2_INTRX_RXIRQ( _val ) \
746 ( ( ( _val ) << GRSPW2_INTRX_RXIRQ_SHIFT ) & \
747 GRSPW2_INTRX_RXIRQ_MASK )
748
759#define GRSPW2_INTTO_INTTO_SHIFT 0
760#define GRSPW2_INTTO_INTTO_MASK 0xffffffffU
761#define GRSPW2_INTTO_INTTO_GET( _reg ) \
762 ( ( ( _reg ) & GRSPW2_INTTO_INTTO_MASK ) >> \
763 GRSPW2_INTTO_INTTO_SHIFT )
764#define GRSPW2_INTTO_INTTO_SET( _reg, _val ) \
765 ( ( ( _reg ) & ~GRSPW2_INTTO_INTTO_MASK ) | \
766 ( ( ( _val ) << GRSPW2_INTTO_INTTO_SHIFT ) & \
767 GRSPW2_INTTO_INTTO_MASK ) )
768#define GRSPW2_INTTO_INTTO( _val ) \
769 ( ( ( _val ) << GRSPW2_INTTO_INTTO_SHIFT ) & \
770 GRSPW2_INTTO_INTTO_MASK )
771
782#define GRSPW2_INTTOEXT_INTTOEXT_SHIFT 0
783#define GRSPW2_INTTOEXT_INTTOEXT_MASK 0xffffffffU
784#define GRSPW2_INTTOEXT_INTTOEXT_GET( _reg ) \
785 ( ( ( _reg ) & GRSPW2_INTTOEXT_INTTOEXT_MASK ) >> \
786 GRSPW2_INTTOEXT_INTTOEXT_SHIFT )
787#define GRSPW2_INTTOEXT_INTTOEXT_SET( _reg, _val ) \
788 ( ( ( _reg ) & ~GRSPW2_INTTOEXT_INTTOEXT_MASK ) | \
789 ( ( ( _val ) << GRSPW2_INTTOEXT_INTTOEXT_SHIFT ) & \
790 GRSPW2_INTTOEXT_INTTOEXT_MASK ) )
791#define GRSPW2_INTTOEXT_INTTOEXT( _val ) \
792 ( ( ( _val ) << GRSPW2_INTTOEXT_INTTOEXT_SHIFT ) & \
793 GRSPW2_INTTOEXT_INTTOEXT_MASK )
794
805#define GRSPW2_TICKMASK_MASK_SHIFT 0
806#define GRSPW2_TICKMASK_MASK_MASK 0xffffffffU
807#define GRSPW2_TICKMASK_MASK_GET( _reg ) \
808 ( ( ( _reg ) & GRSPW2_TICKMASK_MASK_MASK ) >> \
809 GRSPW2_TICKMASK_MASK_SHIFT )
810#define GRSPW2_TICKMASK_MASK_SET( _reg, _val ) \
811 ( ( ( _reg ) & ~GRSPW2_TICKMASK_MASK_MASK ) | \
812 ( ( ( _val ) << GRSPW2_TICKMASK_MASK_SHIFT ) & \
813 GRSPW2_TICKMASK_MASK_MASK ) )
814#define GRSPW2_TICKMASK_MASK( _val ) \
815 ( ( ( _val ) << GRSPW2_TICKMASK_MASK_SHIFT ) & \
816 GRSPW2_TICKMASK_MASK_MASK )
817
829#define GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_SHIFT 0
830#define GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_MASK 0xffffffffU
831#define GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_GET( _reg ) \
832 ( ( ( _reg ) & GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_MASK ) >> \
833 GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_SHIFT )
834#define GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_SET( _reg, _val ) \
835 ( ( ( _reg ) & ~GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_MASK ) | \
836 ( ( ( _val ) << GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_SHIFT ) & \
837 GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_MASK ) )
838#define GRSPW2_AUTOACK_TICKMASKEXT_AAMASK( _val ) \
839 ( ( ( _val ) << GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_SHIFT ) & \
840 GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_MASK )
841
853#define GRSPW2_INTCFG_INTNUM3_SHIFT 26
854#define GRSPW2_INTCFG_INTNUM3_MASK 0xfc000000U
855#define GRSPW2_INTCFG_INTNUM3_GET( _reg ) \
856 ( ( ( _reg ) & GRSPW2_INTCFG_INTNUM3_MASK ) >> \
857 GRSPW2_INTCFG_INTNUM3_SHIFT )
858#define GRSPW2_INTCFG_INTNUM3_SET( _reg, _val ) \
859 ( ( ( _reg ) & ~GRSPW2_INTCFG_INTNUM3_MASK ) | \
860 ( ( ( _val ) << GRSPW2_INTCFG_INTNUM3_SHIFT ) & \
861 GRSPW2_INTCFG_INTNUM3_MASK ) )
862#define GRSPW2_INTCFG_INTNUM3( _val ) \
863 ( ( ( _val ) << GRSPW2_INTCFG_INTNUM3_SHIFT ) & \
864 GRSPW2_INTCFG_INTNUM3_MASK )
865
866#define GRSPW2_INTCFG_INTNUM2_SHIFT 20
867#define GRSPW2_INTCFG_INTNUM2_MASK 0x3f00000U
868#define GRSPW2_INTCFG_INTNUM2_GET( _reg ) \
869 ( ( ( _reg ) & GRSPW2_INTCFG_INTNUM2_MASK ) >> \
870 GRSPW2_INTCFG_INTNUM2_SHIFT )
871#define GRSPW2_INTCFG_INTNUM2_SET( _reg, _val ) \
872 ( ( ( _reg ) & ~GRSPW2_INTCFG_INTNUM2_MASK ) | \
873 ( ( ( _val ) << GRSPW2_INTCFG_INTNUM2_SHIFT ) & \
874 GRSPW2_INTCFG_INTNUM2_MASK ) )
875#define GRSPW2_INTCFG_INTNUM2( _val ) \
876 ( ( ( _val ) << GRSPW2_INTCFG_INTNUM2_SHIFT ) & \
877 GRSPW2_INTCFG_INTNUM2_MASK )
878
879#define GRSPW2_INTCFG_INTNUM1_SHIFT 14
880#define GRSPW2_INTCFG_INTNUM1_MASK 0xfc000U
881#define GRSPW2_INTCFG_INTNUM1_GET( _reg ) \
882 ( ( ( _reg ) & GRSPW2_INTCFG_INTNUM1_MASK ) >> \
883 GRSPW2_INTCFG_INTNUM1_SHIFT )
884#define GRSPW2_INTCFG_INTNUM1_SET( _reg, _val ) \
885 ( ( ( _reg ) & ~GRSPW2_INTCFG_INTNUM1_MASK ) | \
886 ( ( ( _val ) << GRSPW2_INTCFG_INTNUM1_SHIFT ) & \
887 GRSPW2_INTCFG_INTNUM1_MASK ) )
888#define GRSPW2_INTCFG_INTNUM1( _val ) \
889 ( ( ( _val ) << GRSPW2_INTCFG_INTNUM1_SHIFT ) & \
890 GRSPW2_INTCFG_INTNUM1_MASK )
891
892#define GRSPW2_INTCFG_INTNUM0_SHIFT 8
893#define GRSPW2_INTCFG_INTNUM0_MASK 0x3f00U
894#define GRSPW2_INTCFG_INTNUM0_GET( _reg ) \
895 ( ( ( _reg ) & GRSPW2_INTCFG_INTNUM0_MASK ) >> \
896 GRSPW2_INTCFG_INTNUM0_SHIFT )
897#define GRSPW2_INTCFG_INTNUM0_SET( _reg, _val ) \
898 ( ( ( _reg ) & ~GRSPW2_INTCFG_INTNUM0_MASK ) | \
899 ( ( ( _val ) << GRSPW2_INTCFG_INTNUM0_SHIFT ) & \
900 GRSPW2_INTCFG_INTNUM0_MASK ) )
901#define GRSPW2_INTCFG_INTNUM0( _val ) \
902 ( ( ( _val ) << GRSPW2_INTCFG_INTNUM0_SHIFT ) & \
903 GRSPW2_INTCFG_INTNUM0_MASK )
904
905#define GRSPW2_INTCFG_NUMINT_SHIFT 4
906#define GRSPW2_INTCFG_NUMINT_MASK 0xf0U
907#define GRSPW2_INTCFG_NUMINT_GET( _reg ) \
908 ( ( ( _reg ) & GRSPW2_INTCFG_NUMINT_MASK ) >> \
909 GRSPW2_INTCFG_NUMINT_SHIFT )
910#define GRSPW2_INTCFG_NUMINT_SET( _reg, _val ) \
911 ( ( ( _reg ) & ~GRSPW2_INTCFG_NUMINT_MASK ) | \
912 ( ( ( _val ) << GRSPW2_INTCFG_NUMINT_SHIFT ) & \
913 GRSPW2_INTCFG_NUMINT_MASK ) )
914#define GRSPW2_INTCFG_NUMINT( _val ) \
915 ( ( ( _val ) << GRSPW2_INTCFG_NUMINT_SHIFT ) & \
916 GRSPW2_INTCFG_NUMINT_MASK )
917
918#define GRSPW2_INTCFG_PR 0x8U
919
920#define GRSPW2_INTCFG_IR 0x4U
921
922#define GRSPW2_INTCFG_IT 0x2U
923
924#define GRSPW2_INTCFG_EE 0x1U
925
936#define GRSPW2_ISR_ISR_SHIFT 0
937#define GRSPW2_ISR_ISR_MASK 0xffffffffU
938#define GRSPW2_ISR_ISR_GET( _reg ) \
939 ( ( ( _reg ) & GRSPW2_ISR_ISR_MASK ) >> \
940 GRSPW2_ISR_ISR_SHIFT )
941#define GRSPW2_ISR_ISR_SET( _reg, _val ) \
942 ( ( ( _reg ) & ~GRSPW2_ISR_ISR_MASK ) | \
943 ( ( ( _val ) << GRSPW2_ISR_ISR_SHIFT ) & \
944 GRSPW2_ISR_ISR_MASK ) )
945#define GRSPW2_ISR_ISR( _val ) \
946 ( ( ( _val ) << GRSPW2_ISR_ISR_SHIFT ) & \
947 GRSPW2_ISR_ISR_MASK )
948
960#define GRSPW2_ISREXT_ISR_SHIFT 0
961#define GRSPW2_ISREXT_ISR_MASK 0xffffffffU
962#define GRSPW2_ISREXT_ISR_GET( _reg ) \
963 ( ( ( _reg ) & GRSPW2_ISREXT_ISR_MASK ) >> \
964 GRSPW2_ISREXT_ISR_SHIFT )
965#define GRSPW2_ISREXT_ISR_SET( _reg, _val ) \
966 ( ( ( _reg ) & ~GRSPW2_ISREXT_ISR_MASK ) | \
967 ( ( ( _val ) << GRSPW2_ISREXT_ISR_SHIFT ) & \
968 GRSPW2_ISREXT_ISR_MASK ) )
969#define GRSPW2_ISREXT_ISR( _val ) \
970 ( ( ( _val ) << GRSPW2_ISREXT_ISR_SHIFT ) & \
971 GRSPW2_ISREXT_ISR_MASK )
972
984#define GRSPW2_PRESCALER_R 0x80000000U
985
986#define GRSPW2_PRESCALER_RL_SHIFT 0
987#define GRSPW2_PRESCALER_RL_MASK 0x7fffffffU
988#define GRSPW2_PRESCALER_RL_GET( _reg ) \
989 ( ( ( _reg ) & GRSPW2_PRESCALER_RL_MASK ) >> \
990 GRSPW2_PRESCALER_RL_SHIFT )
991#define GRSPW2_PRESCALER_RL_SET( _reg, _val ) \
992 ( ( ( _reg ) & ~GRSPW2_PRESCALER_RL_MASK ) | \
993 ( ( ( _val ) << GRSPW2_PRESCALER_RL_SHIFT ) & \
994 GRSPW2_PRESCALER_RL_MASK ) )
995#define GRSPW2_PRESCALER_RL( _val ) \
996 ( ( ( _val ) << GRSPW2_PRESCALER_RL_SHIFT ) & \
997 GRSPW2_PRESCALER_RL_MASK )
998
1010#define GRSPW2_ISRTIMER_EN 0x80000000U
1011
1012#define GRSPW2_ISRTIMER_RL_SHIFT 0
1013#define GRSPW2_ISRTIMER_RL_MASK 0x7fffffffU
1014#define GRSPW2_ISRTIMER_RL_GET( _reg ) \
1015 ( ( ( _reg ) & GRSPW2_ISRTIMER_RL_MASK ) >> \
1016 GRSPW2_ISRTIMER_RL_SHIFT )
1017#define GRSPW2_ISRTIMER_RL_SET( _reg, _val ) \
1018 ( ( ( _reg ) & ~GRSPW2_ISRTIMER_RL_MASK ) | \
1019 ( ( ( _val ) << GRSPW2_ISRTIMER_RL_SHIFT ) & \
1020 GRSPW2_ISRTIMER_RL_MASK ) )
1021#define GRSPW2_ISRTIMER_RL( _val ) \
1022 ( ( ( _val ) << GRSPW2_ISRTIMER_RL_SHIFT ) & \
1023 GRSPW2_ISRTIMER_RL_MASK )
1024
1036#define GRSPW2_IATIMER_EN 0x80000000U
1037
1038#define GRSPW2_IATIMER_RL_SHIFT 0
1039#define GRSPW2_IATIMER_RL_MASK 0x7fffffffU
1040#define GRSPW2_IATIMER_RL_GET( _reg ) \
1041 ( ( ( _reg ) & GRSPW2_IATIMER_RL_MASK ) >> \
1042 GRSPW2_IATIMER_RL_SHIFT )
1043#define GRSPW2_IATIMER_RL_SET( _reg, _val ) \
1044 ( ( ( _reg ) & ~GRSPW2_IATIMER_RL_MASK ) | \
1045 ( ( ( _val ) << GRSPW2_IATIMER_RL_SHIFT ) & \
1046 GRSPW2_IATIMER_RL_MASK ) )
1047#define GRSPW2_IATIMER_RL( _val ) \
1048 ( ( ( _val ) << GRSPW2_IATIMER_RL_SHIFT ) & \
1049 GRSPW2_IATIMER_RL_MASK )
1050
1062#define GRSPW2_ICTIMER_EN 0x80000000U
1063
1064#define GRSPW2_ICTIMER_RL_SHIFT 0
1065#define GRSPW2_ICTIMER_RL_MASK 0x7fffffffU
1066#define GRSPW2_ICTIMER_RL_GET( _reg ) \
1067 ( ( ( _reg ) & GRSPW2_ICTIMER_RL_MASK ) >> \
1068 GRSPW2_ICTIMER_RL_SHIFT )
1069#define GRSPW2_ICTIMER_RL_SET( _reg, _val ) \
1070 ( ( ( _reg ) & ~GRSPW2_ICTIMER_RL_MASK ) | \
1071 ( ( ( _val ) << GRSPW2_ICTIMER_RL_SHIFT ) & \
1072 GRSPW2_ICTIMER_RL_MASK ) )
1073#define GRSPW2_ICTIMER_RL( _val ) \
1074 ( ( ( _val ) << GRSPW2_ICTIMER_RL_SHIFT ) & \
1075 GRSPW2_ICTIMER_RL_MASK )
1076
1088#define GRSPW2_PNPVEND_VEND_SHIFT 16
1089#define GRSPW2_PNPVEND_VEND_MASK 0xffff0000U
1090#define GRSPW2_PNPVEND_VEND_GET( _reg ) \
1091 ( ( ( _reg ) & GRSPW2_PNPVEND_VEND_MASK ) >> \
1092 GRSPW2_PNPVEND_VEND_SHIFT )
1093#define GRSPW2_PNPVEND_VEND_SET( _reg, _val ) \
1094 ( ( ( _reg ) & ~GRSPW2_PNPVEND_VEND_MASK ) | \
1095 ( ( ( _val ) << GRSPW2_PNPVEND_VEND_SHIFT ) & \
1096 GRSPW2_PNPVEND_VEND_MASK ) )
1097#define GRSPW2_PNPVEND_VEND( _val ) \
1098 ( ( ( _val ) << GRSPW2_PNPVEND_VEND_SHIFT ) & \
1099 GRSPW2_PNPVEND_VEND_MASK )
1100
1101#define GRSPW2_PNPVEND_PROD_SHIFT 0
1102#define GRSPW2_PNPVEND_PROD_MASK 0xffffU
1103#define GRSPW2_PNPVEND_PROD_GET( _reg ) \
1104 ( ( ( _reg ) & GRSPW2_PNPVEND_PROD_MASK ) >> \
1105 GRSPW2_PNPVEND_PROD_SHIFT )
1106#define GRSPW2_PNPVEND_PROD_SET( _reg, _val ) \
1107 ( ( ( _reg ) & ~GRSPW2_PNPVEND_PROD_MASK ) | \
1108 ( ( ( _val ) << GRSPW2_PNPVEND_PROD_SHIFT ) & \
1109 GRSPW2_PNPVEND_PROD_MASK ) )
1110#define GRSPW2_PNPVEND_PROD( _val ) \
1111 ( ( ( _val ) << GRSPW2_PNPVEND_PROD_SHIFT ) & \
1112 GRSPW2_PNPVEND_PROD_MASK )
1113
1125#define GRSPW2_PNPOA0_RA_SHIFT 0
1126#define GRSPW2_PNPOA0_RA_MASK 0xffffffffU
1127#define GRSPW2_PNPOA0_RA_GET( _reg ) \
1128 ( ( ( _reg ) & GRSPW2_PNPOA0_RA_MASK ) >> \
1129 GRSPW2_PNPOA0_RA_SHIFT )
1130#define GRSPW2_PNPOA0_RA_SET( _reg, _val ) \
1131 ( ( ( _reg ) & ~GRSPW2_PNPOA0_RA_MASK ) | \
1132 ( ( ( _val ) << GRSPW2_PNPOA0_RA_SHIFT ) & \
1133 GRSPW2_PNPOA0_RA_MASK ) )
1134#define GRSPW2_PNPOA0_RA( _val ) \
1135 ( ( ( _val ) << GRSPW2_PNPOA0_RA_SHIFT ) & \
1136 GRSPW2_PNPOA0_RA_MASK )
1137
1149#define GRSPW2_PNPOA1_RA_SHIFT 0
1150#define GRSPW2_PNPOA1_RA_MASK 0xffffffffU
1151#define GRSPW2_PNPOA1_RA_GET( _reg ) \
1152 ( ( ( _reg ) & GRSPW2_PNPOA1_RA_MASK ) >> \
1153 GRSPW2_PNPOA1_RA_SHIFT )
1154#define GRSPW2_PNPOA1_RA_SET( _reg, _val ) \
1155 ( ( ( _reg ) & ~GRSPW2_PNPOA1_RA_MASK ) | \
1156 ( ( ( _val ) << GRSPW2_PNPOA1_RA_SHIFT ) & \
1157 GRSPW2_PNPOA1_RA_MASK ) )
1158#define GRSPW2_PNPOA1_RA( _val ) \
1159 ( ( ( _val ) << GRSPW2_PNPOA1_RA_SHIFT ) & \
1160 GRSPW2_PNPOA1_RA_MASK )
1161
1173#define GRSPW2_PNPOA2_RA_SHIFT 0
1174#define GRSPW2_PNPOA2_RA_MASK 0xffffffffU
1175#define GRSPW2_PNPOA2_RA_GET( _reg ) \
1176 ( ( ( _reg ) & GRSPW2_PNPOA2_RA_MASK ) >> \
1177 GRSPW2_PNPOA2_RA_SHIFT )
1178#define GRSPW2_PNPOA2_RA_SET( _reg, _val ) \
1179 ( ( ( _reg ) & ~GRSPW2_PNPOA2_RA_MASK ) | \
1180 ( ( ( _val ) << GRSPW2_PNPOA2_RA_SHIFT ) & \
1181 GRSPW2_PNPOA2_RA_MASK ) )
1182#define GRSPW2_PNPOA2_RA( _val ) \
1183 ( ( ( _val ) << GRSPW2_PNPOA2_RA_SHIFT ) & \
1184 GRSPW2_PNPOA2_RA_MASK )
1185
1197#define GRSPW2_PNPDEVID_DID_SHIFT 0
1198#define GRSPW2_PNPDEVID_DID_MASK 0xffffffffU
1199#define GRSPW2_PNPDEVID_DID_GET( _reg ) \
1200 ( ( ( _reg ) & GRSPW2_PNPDEVID_DID_MASK ) >> \
1201 GRSPW2_PNPDEVID_DID_SHIFT )
1202#define GRSPW2_PNPDEVID_DID_SET( _reg, _val ) \
1203 ( ( ( _reg ) & ~GRSPW2_PNPDEVID_DID_MASK ) | \
1204 ( ( ( _val ) << GRSPW2_PNPDEVID_DID_SHIFT ) & \
1205 GRSPW2_PNPDEVID_DID_MASK ) )
1206#define GRSPW2_PNPDEVID_DID( _val ) \
1207 ( ( ( _val ) << GRSPW2_PNPDEVID_DID_SHIFT ) & \
1208 GRSPW2_PNPDEVID_DID_MASK )
1209
1221#define GRSPW2_PNPUVEND_VEND_SHIFT 16
1222#define GRSPW2_PNPUVEND_VEND_MASK 0xffff0000U
1223#define GRSPW2_PNPUVEND_VEND_GET( _reg ) \
1224 ( ( ( _reg ) & GRSPW2_PNPUVEND_VEND_MASK ) >> \
1225 GRSPW2_PNPUVEND_VEND_SHIFT )
1226#define GRSPW2_PNPUVEND_VEND_SET( _reg, _val ) \
1227 ( ( ( _reg ) & ~GRSPW2_PNPUVEND_VEND_MASK ) | \
1228 ( ( ( _val ) << GRSPW2_PNPUVEND_VEND_SHIFT ) & \
1229 GRSPW2_PNPUVEND_VEND_MASK ) )
1230#define GRSPW2_PNPUVEND_VEND( _val ) \
1231 ( ( ( _val ) << GRSPW2_PNPUVEND_VEND_SHIFT ) & \
1232 GRSPW2_PNPUVEND_VEND_MASK )
1233
1234#define GRSPW2_PNPUVEND_PROD_SHIFT 0
1235#define GRSPW2_PNPUVEND_PROD_MASK 0xffffU
1236#define GRSPW2_PNPUVEND_PROD_GET( _reg ) \
1237 ( ( ( _reg ) & GRSPW2_PNPUVEND_PROD_MASK ) >> \
1238 GRSPW2_PNPUVEND_PROD_SHIFT )
1239#define GRSPW2_PNPUVEND_PROD_SET( _reg, _val ) \
1240 ( ( ( _reg ) & ~GRSPW2_PNPUVEND_PROD_MASK ) | \
1241 ( ( ( _val ) << GRSPW2_PNPUVEND_PROD_SHIFT ) & \
1242 GRSPW2_PNPUVEND_PROD_MASK ) )
1243#define GRSPW2_PNPUVEND_PROD( _val ) \
1244 ( ( ( _val ) << GRSPW2_PNPUVEND_PROD_SHIFT ) & \
1245 GRSPW2_PNPUVEND_PROD_MASK )
1246
1258#define GRSPW2_PNPUSN_USN_SHIFT 0
1259#define GRSPW2_PNPUSN_USN_MASK 0xffffffffU
1260#define GRSPW2_PNPUSN_USN_GET( _reg ) \
1261 ( ( ( _reg ) & GRSPW2_PNPUSN_USN_MASK ) >> \
1262 GRSPW2_PNPUSN_USN_SHIFT )
1263#define GRSPW2_PNPUSN_USN_SET( _reg, _val ) \
1264 ( ( ( _reg ) & ~GRSPW2_PNPUSN_USN_MASK ) | \
1265 ( ( ( _val ) << GRSPW2_PNPUSN_USN_SHIFT ) & \
1266 GRSPW2_PNPUSN_USN_MASK ) )
1267#define GRSPW2_PNPUSN_USN( _val ) \
1268 ( ( ( _val ) << GRSPW2_PNPUSN_USN_SHIFT ) & \
1269 GRSPW2_PNPUSN_USN_MASK )
1270
1276typedef struct grspw2 {
1280 uint32_t ctrl;
1281
1285 uint32_t sts;
1286
1290 uint32_t defaddr;
1291
1295 uint32_t clkdiv;
1296
1300 uint32_t dkey;
1301
1305 uint32_t tc;
1306
1307 uint32_t reserved_18_20[ 2 ];
1308
1312 grspw2_dma dma[ 4 ];
1313
1317 uint32_t intctrl;
1318
1322 uint32_t intrx;
1323
1324 uint32_t reserved_a8_ac;
1325
1329 uint32_t intto;
1330
1334 uint32_t inttoext;
1335
1339 uint32_t tickmask;
1340
1344 uint32_t autoack_tickmaskext;
1345
1349 uint32_t intcfg;
1350
1351 uint32_t reserved_c0_c4;
1352
1356 uint32_t isr;
1357
1361 uint32_t isrext;
1362
1363 uint32_t reserved_cc_d0;
1364
1368 uint32_t prescaler;
1369
1373 uint32_t isrtimer;
1374
1378 uint32_t iatimer;
1379
1383 uint32_t ictimer;
1384
1388 uint32_t pnpvend;
1389
1390 uint32_t reserved_e4_e8;
1391
1395 uint32_t pnpoa0;
1396
1400 uint32_t pnpoa1;
1401
1405 uint32_t pnpoa2;
1406
1410 uint32_t pnpdevid;
1411
1415 uint32_t pnpuvend;
1416
1420 uint32_t pnpusn;
1421} grspw2;
1422
1425#ifdef __cplusplus
1426}
1427#endif
1428
1429#endif /* _GRLIB_GRSPW2_REGS_H */
grspw2_dma
struct grspw2_dma grspw2_dma
This structure defines the GRSPW2 DMA register block memory map.
grspw2
struct grspw2 grspw2
This structure defines the GRSPW2 register block memory map.
grspw2_dma
This structure defines the GRSPW2 DMA register block memory map.
Definition: grspw2-regs.h:309
grspw2_dma::dmarxdesc
uint32_t dmarxdesc
See DMA receive descriptor table address (DMARXDESC).
Definition: grspw2-regs.h:328
grspw2_dma::dmatxdesc
uint32_t dmatxdesc
See DMA transmit descriptor table address (DMATXDESC).
Definition: grspw2-regs.h:323
grspw2_dma::dmamaxlen
uint32_t dmamaxlen
See DMA RX maximum length (DMAMAXLEN).
Definition: grspw2-regs.h:318
grspw2_dma::dmactrl
uint32_t dmactrl
See DMA control/status (DMACTRL).
Definition: grspw2-regs.h:313
grspw2_dma::dmaaddr
uint32_t dmaaddr
See DMA address (DMAADDR).
Definition: grspw2-regs.h:333
grspw2
This structure defines the GRSPW2 register block memory map.
Definition: grspw2-regs.h:1276
grspw2::intto
uint32_t intto
See Interrupt timeout (INTTO).
Definition: grspw2-regs.h:1329
grspw2::sts
uint32_t sts
See Status (STS).
Definition: grspw2-regs.h:1285
grspw2::ctrl
uint32_t ctrl
See Control (CTRL).
Definition: grspw2-regs.h:1280
grspw2::prescaler
uint32_t prescaler
See Interrupt distribution prescaler reload (PRESCALER).
Definition: grspw2-regs.h:1368
grspw2::dkey
uint32_t dkey
See Destination key (DKEY).
Definition: grspw2-regs.h:1300
grspw2::pnpoa2
uint32_t pnpoa2
See SpaceWire Plug-and-Play - Owner Address 2 (PNPOA2).
Definition: grspw2-regs.h:1405
grspw2::intrx
uint32_t intrx
See Interrupt-code receive (INTRX).
Definition: grspw2-regs.h:1322
grspw2::clkdiv
uint32_t clkdiv
See Clock divisor (CLKDIV).
Definition: grspw2-regs.h:1295
grspw2::iatimer
uint32_t iatimer
See Interrupt distribution INT / ACK timer reload (IATIMER).
Definition: grspw2-regs.h:1378
grspw2::isr
uint32_t isr
See Interrupt distribution ISR (ISR).
Definition: grspw2-regs.h:1356
grspw2::pnpdevid
uint32_t pnpdevid
See SpaceWire Plug-and-Play - Device ID (PNPDEVID).
Definition: grspw2-regs.h:1410
grspw2::pnpusn
uint32_t pnpusn
See SpaceWire Plug-and-Play - Unit Serial Number (PNPUSN).
Definition: grspw2-regs.h:1420
grspw2::pnpvend
uint32_t pnpvend
See SpaceWire Plug-and-Play - Device Vendor and Product ID (PNPVEND).
Definition: grspw2-regs.h:1388
grspw2::isrext
uint32_t isrext
See Interrupt distribution ISR extended (ISREXT).
Definition: grspw2-regs.h:1361
grspw2::tickmask
uint32_t tickmask
See Interrupt tick-out mask (TICKMASK).
Definition: grspw2-regs.h:1339
grspw2::ictimer
uint32_t ictimer
See Interrupt distribution change timer reload (ICTIMER).
Definition: grspw2-regs.h:1383
grspw2::pnpuvend
uint32_t pnpuvend
See SpaceWire Plug-and-Play - Unit Vendor and Product ID (PNPUVEND).
Definition: grspw2-regs.h:1415
grspw2::isrtimer
uint32_t isrtimer
See Interrupt distribution ISR timer reload (ISRTIMER).
Definition: grspw2-regs.h:1373
grspw2::pnpoa0
uint32_t pnpoa0
See SpaceWire Plug-and-Play - Owner Address 0 (PNPOA0).
Definition: grspw2-regs.h:1395
grspw2::defaddr
uint32_t defaddr
See Default address (DEFADDR).
Definition: grspw2-regs.h:1290
grspw2::autoack_tickmaskext
uint32_t autoack_tickmaskext
See Interrupt-code auto acknowledge mask / interrupt tick-out mask extended (AUTOACK_TICKMASKEXT).
Definition: grspw2-regs.h:1344
grspw2::intctrl
uint32_t intctrl
See Interrupt distribution control (INTCTRL).
Definition: grspw2-regs.h:1317
grspw2::inttoext
uint32_t inttoext
See Interrupt timeout extended (INTTOEXT).
Definition: grspw2-regs.h:1334
grspw2::pnpoa1
uint32_t pnpoa1
See SpaceWire Plug-and-Play - Owner Address 1 (PNPOA1).
Definition: grspw2-regs.h:1400
grspw2::tc
uint32_t tc
See Time-code (TC).
Definition: grspw2-regs.h:1305
grspw2::intcfg
uint32_t intcfg
See Interrupt distribution configuration (INTCFG).
Definition: grspw2-regs.h:1349
grspw2::dma
grspw2_dma dma[4]
See GRSPW2 DMA.
Definition: grspw2-regs.h:1312
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