This header file defines the GRSPW2 register block interface. More...

#include <stdint.h>

Data Structures
struct	grspw2_dma
	This structure defines the GRSPW2 DMA register block memory map. More...

struct	grspw2
	This structure defines the GRSPW2 register block memory map. More...

Macros
#define	GRSPW2_DMACTRL_INTNUM_SHIFT 26

#define	GRSPW2_DMACTRL_INTNUM_MASK 0xfc000000U

#define	GRSPW2_DMACTRL_INTNUM_GET(_reg)

#define	GRSPW2_DMACTRL_INTNUM_SET(_reg, _val)

#define	GRSPW2_DMACTRL_INTNUM(_val)

#define	GRSPW2_DMACTRL_RES_SHIFT 24

#define	GRSPW2_DMACTRL_RES_MASK 0x3000000U

#define	GRSPW2_DMACTRL_RES_GET(_reg)

#define	GRSPW2_DMACTRL_RES_SET(_reg, _val)

#define	GRSPW2_DMACTRL_RES(_val)

#define	GRSPW2_DMACTRL_EP 0x800000U

#define	GRSPW2_DMACTRL_TR 0x400000U

#define	GRSPW2_DMACTRL_IE 0x200000U

#define	GRSPW2_DMACTRL_IT 0x100000U

#define	GRSPW2_DMACTRL_RP 0x80000U

#define	GRSPW2_DMACTRL_TP 0x40000U

#define	GRSPW2_DMACTRL_TL 0x20000U

#define	GRSPW2_DMACTRL_LE 0x10000U

#define	GRSPW2_DMACTRL_SP 0x8000U

#define	GRSPW2_DMACTRL_SA 0x4000U

#define	GRSPW2_DMACTRL_EN 0x2000U

#define	GRSPW2_DMACTRL_NS 0x1000U

#define	GRSPW2_DMACTRL_RD 0x800U

#define	GRSPW2_DMACTRL_RX 0x400U

#define	GRSPW2_DMACTRL_AT 0x200U

#define	GRSPW2_DMACTRL_RA 0x100U

#define	GRSPW2_DMACTRL_TA 0x80U

#define	GRSPW2_DMACTRL_PR 0x40U

#define	GRSPW2_DMACTRL_PS 0x20U

#define	GRSPW2_DMACTRL_AI 0x10U

#define	GRSPW2_DMACTRL_RI 0x8U

#define	GRSPW2_DMACTRL_TI 0x4U

#define	GRSPW2_DMACTRL_RE 0x2U

#define	GRSPW2_DMACTRL_TE 0x1U

#define	GRSPW2_DMAMAXLEN_RXMAXLEN_SHIFT 2

#define	GRSPW2_DMAMAXLEN_RXMAXLEN_MASK 0x1fffffcU

#define	GRSPW2_DMAMAXLEN_RXMAXLEN_GET(_reg)

#define	GRSPW2_DMAMAXLEN_RXMAXLEN_SET(_reg, _val)

#define	GRSPW2_DMAMAXLEN_RXMAXLEN(_val)

#define	GRSPW2_DMAMAXLEN_RES_SHIFT 0

#define	GRSPW2_DMAMAXLEN_RES_MASK 0x3U

#define	GRSPW2_DMAMAXLEN_RES_GET(_reg)

#define	GRSPW2_DMAMAXLEN_RES_SET(_reg, _val)

#define	GRSPW2_DMAMAXLEN_RES(_val)

#define	GRSPW2_DMATXDESC_DESCBASEADDR_SHIFT 0

#define	GRSPW2_DMATXDESC_DESCBASEADDR_MASK 0xffffffffU

#define	GRSPW2_DMATXDESC_DESCBASEADDR_GET(_reg)

#define	GRSPW2_DMATXDESC_DESCBASEADDR_SET(_reg, _val)

#define	GRSPW2_DMATXDESC_DESCBASEADDR(_val)

#define	GRSPW2_DMATXDESC_DESCSEL_SHIFT 4

#define	GRSPW2_DMATXDESC_DESCSEL_MASK 0xfffffff0U

#define	GRSPW2_DMATXDESC_DESCSEL_GET(_reg)

#define	GRSPW2_DMATXDESC_DESCSEL_SET(_reg, _val)

#define	GRSPW2_DMATXDESC_DESCSEL(_val)

#define	GRSPW2_DMARXDESC_DESCBASEADDR_SHIFT 10

#define	GRSPW2_DMARXDESC_DESCBASEADDR_MASK 0xfffffc00U

#define	GRSPW2_DMARXDESC_DESCBASEADDR_GET(_reg)

#define	GRSPW2_DMARXDESC_DESCBASEADDR_SET(_reg, _val)

#define	GRSPW2_DMARXDESC_DESCBASEADDR(_val)

#define	GRSPW2_DMARXDESC_DESCSEL_SHIFT 3

#define	GRSPW2_DMARXDESC_DESCSEL_MASK 0x3f8U

#define	GRSPW2_DMARXDESC_DESCSEL_GET(_reg)

#define	GRSPW2_DMARXDESC_DESCSEL_SET(_reg, _val)

#define	GRSPW2_DMARXDESC_DESCSEL(_val)

#define	GRSPW2_DMAADDR_MASK_SHIFT 8

#define	GRSPW2_DMAADDR_MASK_MASK 0xff00U

#define	GRSPW2_DMAADDR_MASK_GET(_reg)

#define	GRSPW2_DMAADDR_MASK_SET(_reg, _val)

#define	GRSPW2_DMAADDR_MASK(_val)

#define	GRSPW2_DMAADDR_ADDR_SHIFT 0

#define	GRSPW2_DMAADDR_ADDR_MASK 0xffU

#define	GRSPW2_DMAADDR_ADDR_GET(_reg)

#define	GRSPW2_DMAADDR_ADDR_SET(_reg, _val)

#define	GRSPW2_DMAADDR_ADDR(_val)

#define	GRSPW2_CTRL_RA 0x80000000U

#define	GRSPW2_CTRL_RX 0x40000000U

#define	GRSPW2_CTRL_RC 0x20000000U

#define	GRSPW2_CTRL_NCH_SHIFT 27

#define	GRSPW2_CTRL_NCH_MASK 0x18000000U

#define	GRSPW2_CTRL_NCH_GET(_reg)

#define	GRSPW2_CTRL_NCH_SET(_reg, _val)

#define	GRSPW2_CTRL_NCH(_val)

#define	GRSPW2_CTRL_PO 0x4000000U

#define	GRSPW2_CTRL_CC 0x2000000U

#define	GRSPW2_CTRL_ID 0x1000000U

#define	GRSPW2_CTRL_R 0x800000U

#define	GRSPW2_CTRL_LE 0x400000U

#define	GRSPW2_CTRL_PS 0x200000U

#define	GRSPW2_CTRL_NP 0x100000U

#define	GRSPW2_CTRL_PNPA_SHIFT 18

#define	GRSPW2_CTRL_PNPA_MASK 0xc0000U

#define	GRSPW2_CTRL_PNPA_GET(_reg)

#define	GRSPW2_CTRL_PNPA_SET(_reg, _val)

#define	GRSPW2_CTRL_PNPA(_val)

#define	GRSPW2_CTRL_RD 0x20000U

#define	GRSPW2_CTRL_RE 0x10000U

#define	GRSPW2_CTRL_PE 0x8000U

#define	GRSPW2_CTRL_R 0x4000U

#define	GRSPW2_CTRL_TL 0x2000U

#define	GRSPW2_CTRL_TF 0x1000U

#define	GRSPW2_CTRL_TR 0x800U

#define	GRSPW2_CTRL_TT 0x400U

#define	GRSPW2_CTRL_LI 0x200U

#define	GRSPW2_CTRL_TQ 0x100U

#define	GRSPW2_CTRL_R 0x80U

#define	GRSPW2_CTRL_RS 0x40U

#define	GRSPW2_CTRL_PM 0x20U

#define	GRSPW2_CTRL_TI 0x10U

#define	GRSPW2_CTRL_IE 0x8U

#define	GRSPW2_CTRL_AS 0x4U

#define	GRSPW2_CTRL_LS 0x2U

#define	GRSPW2_CTRL_LD 0x1U

#define	GRSPW2_STS_NRXD_SHIFT 26

#define	GRSPW2_STS_NRXD_MASK 0xc000000U

#define	GRSPW2_STS_NRXD_GET(_reg)

#define	GRSPW2_STS_NRXD_SET(_reg, _val)

#define	GRSPW2_STS_NRXD(_val)

#define	GRSPW2_STS_NTXD 0x2000000U

#define	GRSPW2_STS_LS_SHIFT 21

#define	GRSPW2_STS_LS_MASK 0xe00000U

#define	GRSPW2_STS_LS_GET(_reg)

#define	GRSPW2_STS_LS_SET(_reg, _val)

#define	GRSPW2_STS_LS(_val)

#define	GRSPW2_STS_AP 0x200U

#define	GRSPW2_STS_EE 0x100U

#define	GRSPW2_STS_IA 0x80U

#define	GRSPW2_STS_RES_SHIFT 5

#define	GRSPW2_STS_RES_MASK 0x60U

#define	GRSPW2_STS_RES_GET(_reg)

#define	GRSPW2_STS_RES_SET(_reg, _val)

#define	GRSPW2_STS_RES(_val)

#define	GRSPW2_STS_PE 0x10U

#define	GRSPW2_STS_DE 0x8U

#define	GRSPW2_STS_ER 0x4U

#define	GRSPW2_STS_CE 0x2U

#define	GRSPW2_STS_TO 0x1U

#define	GRSPW2_DEFADDR_DEFMASK_SHIFT 8

#define	GRSPW2_DEFADDR_DEFMASK_MASK 0xff00U

#define	GRSPW2_DEFADDR_DEFMASK_GET(_reg)

#define	GRSPW2_DEFADDR_DEFMASK_SET(_reg, _val)

#define	GRSPW2_DEFADDR_DEFMASK(_val)

#define	GRSPW2_DEFADDR_DEFADDR_SHIFT 0

#define	GRSPW2_DEFADDR_DEFADDR_MASK 0xffU

#define	GRSPW2_DEFADDR_DEFADDR_GET(_reg)

#define	GRSPW2_DEFADDR_DEFADDR_SET(_reg, _val)

#define	GRSPW2_DEFADDR_DEFADDR(_val)

#define	GRSPW2_CLKDIV_CLKDIVSTART_SHIFT 8

#define	GRSPW2_CLKDIV_CLKDIVSTART_MASK 0xff00U

#define	GRSPW2_CLKDIV_CLKDIVSTART_GET(_reg)

#define	GRSPW2_CLKDIV_CLKDIVSTART_SET(_reg, _val)

#define	GRSPW2_CLKDIV_CLKDIVSTART(_val)

#define	GRSPW2_CLKDIV_CLKDIVRUN_SHIFT 0

#define	GRSPW2_CLKDIV_CLKDIVRUN_MASK 0xffU

#define	GRSPW2_CLKDIV_CLKDIVRUN_GET(_reg)

#define	GRSPW2_CLKDIV_CLKDIVRUN_SET(_reg, _val)

#define	GRSPW2_CLKDIV_CLKDIVRUN(_val)

#define	GRSPW2_DKEY_DESTKEY_SHIFT 0

#define	GRSPW2_DKEY_DESTKEY_MASK 0xffU

#define	GRSPW2_DKEY_DESTKEY_GET(_reg)

#define	GRSPW2_DKEY_DESTKEY_SET(_reg, _val)

#define	GRSPW2_DKEY_DESTKEY(_val)

#define	GRSPW2_TC_TCTRL_SHIFT 6

#define	GRSPW2_TC_TCTRL_MASK 0xc0U

#define	GRSPW2_TC_TCTRL_GET(_reg)

#define	GRSPW2_TC_TCTRL_SET(_reg, _val)

#define	GRSPW2_TC_TCTRL(_val)

#define	GRSPW2_TC_TIMECNT_SHIFT 0

#define	GRSPW2_TC_TIMECNT_MASK 0x3fU

#define	GRSPW2_TC_TIMECNT_GET(_reg)

#define	GRSPW2_TC_TIMECNT_SET(_reg, _val)

#define	GRSPW2_TC_TIMECNT(_val)

#define	GRSPW2_INTCTRL_INTNUM_SHIFT 26

#define	GRSPW2_INTCTRL_INTNUM_MASK 0xfc000000U

#define	GRSPW2_INTCTRL_INTNUM_GET(_reg)

#define	GRSPW2_INTCTRL_INTNUM_SET(_reg, _val)

#define	GRSPW2_INTCTRL_INTNUM(_val)

#define	GRSPW2_INTCTRL_RS 0x2000000U

#define	GRSPW2_INTCTRL_EE 0x1000000U

#define	GRSPW2_INTCTRL_IA 0x800000U

#define	GRSPW2_INTCTRL_RES 0x2U

#define	GRSPW2_INTCTRL_TQ_SHIFT 21

#define	GRSPW2_INTCTRL_TQ_MASK 0x600000U

#define	GRSPW2_INTCTRL_TQ_GET(_reg)

#define	GRSPW2_INTCTRL_TQ_SET(_reg, _val)

#define	GRSPW2_INTCTRL_TQ(_val)

#define	GRSPW2_INTCTRL_AQ 0x100000U

#define	GRSPW2_INTCTRL_IQ 0x80000U

#define	GRSPW2_INTCTRL_RES 0x40000U

#define	GRSPW2_INTCTRL_AA_SHIFT 16

#define	GRSPW2_INTCTRL_AA_MASK 0x30000U

#define	GRSPW2_INTCTRL_AA_GET(_reg)

#define	GRSPW2_INTCTRL_AA_SET(_reg, _val)

#define	GRSPW2_INTCTRL_AA(_val)

#define	GRSPW2_INTCTRL_AT 0x8000U

#define	GRSPW2_INTCTRL_IT 0x4000U

#define	GRSPW2_INTCTRL_RES 0x2000U

#define	GRSPW2_INTCTRL_ID_SHIFT 8

#define	GRSPW2_INTCTRL_ID_MASK 0x1f00U

#define	GRSPW2_INTCTRL_ID_GET(_reg)

#define	GRSPW2_INTCTRL_ID_SET(_reg, _val)

#define	GRSPW2_INTCTRL_ID(_val)

#define	GRSPW2_INTCTRL_II 0x80U

#define	GRSPW2_INTCTRL_TXINT 0x40U

#define	GRSPW2_INTRX_RXIRQ_SHIFT 0

#define	GRSPW2_INTRX_RXIRQ_MASK 0xffffffffU

#define	GRSPW2_INTRX_RXIRQ_GET(_reg)

#define	GRSPW2_INTRX_RXIRQ_SET(_reg, _val)

#define	GRSPW2_INTRX_RXIRQ(_val)

#define	GRSPW2_INTTO_INTTO_SHIFT 0

#define	GRSPW2_INTTO_INTTO_MASK 0xffffffffU

#define	GRSPW2_INTTO_INTTO_GET(_reg)

#define	GRSPW2_INTTO_INTTO_SET(_reg, _val)

#define	GRSPW2_INTTO_INTTO(_val)

#define	GRSPW2_INTTOEXT_INTTOEXT_SHIFT 0

#define	GRSPW2_INTTOEXT_INTTOEXT_MASK 0xffffffffU

#define	GRSPW2_INTTOEXT_INTTOEXT_GET(_reg)

#define	GRSPW2_INTTOEXT_INTTOEXT_SET(_reg, _val)

#define	GRSPW2_INTTOEXT_INTTOEXT(_val)

#define	GRSPW2_TICKMASK_MASK_SHIFT 0

#define	GRSPW2_TICKMASK_MASK_MASK 0xffffffffU

#define	GRSPW2_TICKMASK_MASK_GET(_reg)

#define	GRSPW2_TICKMASK_MASK_SET(_reg, _val)

#define	GRSPW2_TICKMASK_MASK(_val)

#define	GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_SHIFT 0

#define	GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_MASK 0xffffffffU

#define	GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_GET(_reg)

#define	GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_SET(_reg, _val)

#define	GRSPW2_AUTOACK_TICKMASKEXT_AAMASK(_val)

#define	GRSPW2_INTCFG_INTNUM3_SHIFT 26

#define	GRSPW2_INTCFG_INTNUM3_MASK 0xfc000000U

#define	GRSPW2_INTCFG_INTNUM3_GET(_reg)

#define	GRSPW2_INTCFG_INTNUM3_SET(_reg, _val)

#define	GRSPW2_INTCFG_INTNUM3(_val)

#define	GRSPW2_INTCFG_INTNUM2_SHIFT 20

#define	GRSPW2_INTCFG_INTNUM2_MASK 0x3f00000U

#define	GRSPW2_INTCFG_INTNUM2_GET(_reg)

#define	GRSPW2_INTCFG_INTNUM2_SET(_reg, _val)

#define	GRSPW2_INTCFG_INTNUM2(_val)

#define	GRSPW2_INTCFG_INTNUM1_SHIFT 14

#define	GRSPW2_INTCFG_INTNUM1_MASK 0xfc000U

#define	GRSPW2_INTCFG_INTNUM1_GET(_reg)

#define	GRSPW2_INTCFG_INTNUM1_SET(_reg, _val)

#define	GRSPW2_INTCFG_INTNUM1(_val)

#define	GRSPW2_INTCFG_INTNUM0_SHIFT 8

#define	GRSPW2_INTCFG_INTNUM0_MASK 0x3f00U

#define	GRSPW2_INTCFG_INTNUM0_GET(_reg)

#define	GRSPW2_INTCFG_INTNUM0_SET(_reg, _val)

#define	GRSPW2_INTCFG_INTNUM0(_val)

#define	GRSPW2_INTCFG_NUMINT_SHIFT 4

#define	GRSPW2_INTCFG_NUMINT_MASK 0xf0U

#define	GRSPW2_INTCFG_NUMINT_GET(_reg)

#define	GRSPW2_INTCFG_NUMINT_SET(_reg, _val)

#define	GRSPW2_INTCFG_NUMINT(_val)

#define	GRSPW2_INTCFG_PR 0x8U

#define	GRSPW2_INTCFG_IR 0x4U

#define	GRSPW2_INTCFG_IT 0x2U

#define	GRSPW2_INTCFG_EE 0x1U

#define	GRSPW2_ISR_ISR_SHIFT 0

#define	GRSPW2_ISR_ISR_MASK 0xffffffffU

#define	GRSPW2_ISR_ISR_GET(_reg)

#define	GRSPW2_ISR_ISR_SET(_reg, _val)

#define	GRSPW2_ISR_ISR(_val)

#define	GRSPW2_ISREXT_ISR_SHIFT 0

#define	GRSPW2_ISREXT_ISR_MASK 0xffffffffU

#define	GRSPW2_ISREXT_ISR_GET(_reg)

#define	GRSPW2_ISREXT_ISR_SET(_reg, _val)

#define	GRSPW2_ISREXT_ISR(_val)

#define	GRSPW2_PRESCALER_R 0x80000000U

#define	GRSPW2_PRESCALER_RL_SHIFT 0

#define	GRSPW2_PRESCALER_RL_MASK 0x7fffffffU

#define	GRSPW2_PRESCALER_RL_GET(_reg)

#define	GRSPW2_PRESCALER_RL_SET(_reg, _val)

#define	GRSPW2_PRESCALER_RL(_val)

#define	GRSPW2_ISRTIMER_EN 0x80000000U

#define	GRSPW2_ISRTIMER_RL_SHIFT 0

#define	GRSPW2_ISRTIMER_RL_MASK 0x7fffffffU

#define	GRSPW2_ISRTIMER_RL_GET(_reg)

#define	GRSPW2_ISRTIMER_RL_SET(_reg, _val)

#define	GRSPW2_ISRTIMER_RL(_val)

#define	GRSPW2_IATIMER_EN 0x80000000U

#define	GRSPW2_IATIMER_RL_SHIFT 0

#define	GRSPW2_IATIMER_RL_MASK 0x7fffffffU

#define	GRSPW2_IATIMER_RL_GET(_reg)

#define	GRSPW2_IATIMER_RL_SET(_reg, _val)

#define	GRSPW2_IATIMER_RL(_val)

#define	GRSPW2_ICTIMER_EN 0x80000000U

#define	GRSPW2_ICTIMER_RL_SHIFT 0

#define	GRSPW2_ICTIMER_RL_MASK 0x7fffffffU

#define	GRSPW2_ICTIMER_RL_GET(_reg)

#define	GRSPW2_ICTIMER_RL_SET(_reg, _val)

#define	GRSPW2_ICTIMER_RL(_val)

#define	GRSPW2_PNPVEND_VEND_SHIFT 16

#define	GRSPW2_PNPVEND_VEND_MASK 0xffff0000U

#define	GRSPW2_PNPVEND_VEND_GET(_reg)

#define	GRSPW2_PNPVEND_VEND_SET(_reg, _val)

#define	GRSPW2_PNPVEND_VEND(_val)

#define	GRSPW2_PNPVEND_PROD_SHIFT 0

#define	GRSPW2_PNPVEND_PROD_MASK 0xffffU

#define	GRSPW2_PNPVEND_PROD_GET(_reg)

#define	GRSPW2_PNPVEND_PROD_SET(_reg, _val)

#define	GRSPW2_PNPVEND_PROD(_val)

#define	GRSPW2_PNPOA0_RA_SHIFT 0

#define	GRSPW2_PNPOA0_RA_MASK 0xffffffffU

#define	GRSPW2_PNPOA0_RA_GET(_reg)

#define	GRSPW2_PNPOA0_RA_SET(_reg, _val)

#define	GRSPW2_PNPOA0_RA(_val)

#define	GRSPW2_PNPOA1_RA_SHIFT 0

#define	GRSPW2_PNPOA1_RA_MASK 0xffffffffU

#define	GRSPW2_PNPOA1_RA_GET(_reg)

#define	GRSPW2_PNPOA1_RA_SET(_reg, _val)

#define	GRSPW2_PNPOA1_RA(_val)

#define	GRSPW2_PNPOA2_RA_SHIFT 0

#define	GRSPW2_PNPOA2_RA_MASK 0xffffffffU

#define	GRSPW2_PNPOA2_RA_GET(_reg)

#define	GRSPW2_PNPOA2_RA_SET(_reg, _val)

#define	GRSPW2_PNPOA2_RA(_val)

#define	GRSPW2_PNPDEVID_DID_SHIFT 0

#define	GRSPW2_PNPDEVID_DID_MASK 0xffffffffU

#define	GRSPW2_PNPDEVID_DID_GET(_reg)

#define	GRSPW2_PNPDEVID_DID_SET(_reg, _val)

#define	GRSPW2_PNPDEVID_DID(_val)

#define	GRSPW2_PNPUVEND_VEND_SHIFT 16

#define	GRSPW2_PNPUVEND_VEND_MASK 0xffff0000U

#define	GRSPW2_PNPUVEND_VEND_GET(_reg)

#define	GRSPW2_PNPUVEND_VEND_SET(_reg, _val)

#define	GRSPW2_PNPUVEND_VEND(_val)

#define	GRSPW2_PNPUVEND_PROD_SHIFT 0

#define	GRSPW2_PNPUVEND_PROD_MASK 0xffffU

#define	GRSPW2_PNPUVEND_PROD_GET(_reg)

#define	GRSPW2_PNPUVEND_PROD_SET(_reg, _val)

#define	GRSPW2_PNPUVEND_PROD(_val)

#define	GRSPW2_PNPUSN_USN_SHIFT 0

#define	GRSPW2_PNPUSN_USN_MASK 0xffffffffU

#define	GRSPW2_PNPUSN_USN_GET(_reg)

#define	GRSPW2_PNPUSN_USN_SET(_reg, _val)

#define	GRSPW2_PNPUSN_USN(_val)

Typedefs
typedef struct grspw2_dma	grspw2_dma
	This structure defines the GRSPW2 DMA register block memory map.

typedef struct grspw2	grspw2
	This structure defines the GRSPW2 register block memory map.

Detailed Description

This header file defines the GRSPW2 register block interface.

Data Structures

Macros

Typedefs

Detailed Description