RTEMS 6.1-rc1
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This group contains register bit definitions. More...
Macros | |
#define | L2CACHE_L2CERR_AHB_MASTER_INDEX_SHIFT 28 |
#define | L2CACHE_L2CERR_AHB_MASTER_INDEX_MASK 0xf0000000U |
#define | L2CACHE_L2CERR_AHB_MASTER_INDEX_GET(_reg) |
#define | L2CACHE_L2CERR_AHB_MASTER_INDEX_SET(_reg, _val) |
#define | L2CACHE_L2CERR_AHB_MASTER_INDEX(_val) |
#define | L2CACHE_L2CERR_SCRUB 0x8000000U |
#define | L2CACHE_L2CERR_TYPE_SHIFT 24 |
#define | L2CACHE_L2CERR_TYPE_MASK 0x7000000U |
#define | L2CACHE_L2CERR_TYPE_GET(_reg) |
#define | L2CACHE_L2CERR_TYPE_SET(_reg, _val) |
#define | L2CACHE_L2CERR_TYPE(_val) |
#define | L2CACHE_L2CERR_TAG_DATA 0x800000U |
#define | L2CACHE_L2CERR_COR_UCOR 0x400000U |
#define | L2CACHE_L2CERR_MULTI 0x200000U |
#define | L2CACHE_L2CERR_VALID 0x100000U |
#define | L2CACHE_L2CERR_DISERESP 0x80000U |
#define | L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_SHIFT 16 |
#define | L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_MASK 0x70000U |
#define | L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_GET(_reg) |
#define | L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_SET(_reg, _val) |
#define | L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER(_val) |
#define | L2CACHE_L2CERR_IRQ_PENDING_SHIFT 12 |
#define | L2CACHE_L2CERR_IRQ_PENDING_MASK 0xf000U |
#define | L2CACHE_L2CERR_IRQ_PENDING_GET(_reg) |
#define | L2CACHE_L2CERR_IRQ_PENDING_SET(_reg, _val) |
#define | L2CACHE_L2CERR_IRQ_PENDING(_val) |
#define | L2CACHE_L2CERR_IRQ_MASK_SHIFT 8 |
#define | L2CACHE_L2CERR_IRQ_MASK_MASK 0xf00U |
#define | L2CACHE_L2CERR_IRQ_MASK_GET(_reg) |
#define | L2CACHE_L2CERR_IRQ_MASK_SET(_reg, _val) |
#define | L2CACHE_L2CERR_IRQ_MASK(_val) |
#define | L2CACHE_L2CERR_SELECT_CB_SHIFT 6 |
#define | L2CACHE_L2CERR_SELECT_CB_MASK 0xc0U |
#define | L2CACHE_L2CERR_SELECT_CB_GET(_reg) |
#define | L2CACHE_L2CERR_SELECT_CB_SET(_reg, _val) |
#define | L2CACHE_L2CERR_SELECT_CB(_val) |
#define | L2CACHE_L2CERR_SELECT_TCB_SHIFT 4 |
#define | L2CACHE_L2CERR_SELECT_TCB_MASK 0x30U |
#define | L2CACHE_L2CERR_SELECT_TCB_GET(_reg) |
#define | L2CACHE_L2CERR_SELECT_TCB_SET(_reg, _val) |
#define | L2CACHE_L2CERR_SELECT_TCB(_val) |
#define | L2CACHE_L2CERR_XCB 0x8U |
#define | L2CACHE_L2CERR_RCB 0x4U |
#define | L2CACHE_L2CERR_COMP 0x2U |
#define | L2CACHE_L2CERR_RST 0x1U |
This group contains register bit definitions.
#define L2CACHE_L2CERR_AHB_MASTER_INDEX | ( | _val | ) |
#define L2CACHE_L2CERR_AHB_MASTER_INDEX_GET | ( | _reg | ) |
#define L2CACHE_L2CERR_AHB_MASTER_INDEX_SET | ( | _reg, | |
_val | |||
) |
#define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER | ( | _val | ) |
#define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_GET | ( | _reg | ) |
#define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_SET | ( | _reg, | |
_val | |||
) |
#define L2CACHE_L2CERR_IRQ_MASK | ( | _val | ) |
#define L2CACHE_L2CERR_IRQ_MASK_GET | ( | _reg | ) |
#define L2CACHE_L2CERR_IRQ_MASK_SET | ( | _reg, | |
_val | |||
) |
#define L2CACHE_L2CERR_IRQ_PENDING | ( | _val | ) |
#define L2CACHE_L2CERR_IRQ_PENDING_GET | ( | _reg | ) |
#define L2CACHE_L2CERR_IRQ_PENDING_SET | ( | _reg, | |
_val | |||
) |
#define L2CACHE_L2CERR_SELECT_CB | ( | _val | ) |
#define L2CACHE_L2CERR_SELECT_CB_GET | ( | _reg | ) |
#define L2CACHE_L2CERR_SELECT_CB_SET | ( | _reg, | |
_val | |||
) |
#define L2CACHE_L2CERR_SELECT_TCB | ( | _val | ) |
#define L2CACHE_L2CERR_SELECT_TCB_GET | ( | _reg | ) |
#define L2CACHE_L2CERR_SELECT_TCB_SET | ( | _reg, | |
_val | |||
) |
#define L2CACHE_L2CERR_TYPE | ( | _val | ) |
#define L2CACHE_L2CERR_TYPE_GET | ( | _reg | ) |
#define L2CACHE_L2CERR_TYPE_SET | ( | _reg, | |
_val | |||
) |