DSU debug mode mask register (DBGM)

This group contains register bit definitions. More...

Macros
#define	DSU4_DBGM_DM_3_0_SHIFT   16
#define	DSU4_DBGM_DM_3_0_MASK   0xf0000U
#define	DSU4_DBGM_DM_3_0_GET(_reg)
#define	DSU4_DBGM_DM_3_0_SET(_reg, _val)
#define	DSU4_DBGM_DM_3_0(_val)
#define	DSU4_DBGM_ED_3_0_SHIFT   0
#define	DSU4_DBGM_ED_3_0_MASK   0xfU
#define	DSU4_DBGM_ED_3_0_GET(_reg)
#define	DSU4_DBGM_ED_3_0_SET(_reg, _val)
#define	DSU4_DBGM_ED_3_0(_val)

Detailed Description

This group contains register bit definitions.

Macro Definition Documentation

DSU4_DBGM_DM_3_0

#define DSU4_DBGM_DM_3_0

(

_val

)

Value:

  ( ( ( _val ) << DSU4_DBGM_DM_3_0_SHIFT ) & \
    DSU4_DBGM_DM_3_0_MASK )

DSU4_DBGM_DM_3_0_GET

#define DSU4_DBGM_DM_3_0_GET

(

_reg

)

Value:

  ( ( ( _reg ) & DSU4_DBGM_DM_3_0_MASK ) >> \
    DSU4_DBGM_DM_3_0_SHIFT )

DSU4_DBGM_DM_3_0_SET

#define DSU4_DBGM_DM_3_0_SET	(		_reg,
			_val
	)

Value:

  ( ( ( _reg ) & ~DSU4_DBGM_DM_3_0_MASK ) | \
    ( ( ( _val ) << DSU4_DBGM_DM_3_0_SHIFT ) & \
      DSU4_DBGM_DM_3_0_MASK ) )

DSU4_DBGM_ED_3_0

#define DSU4_DBGM_ED_3_0

(

_val

)

Value:

  ( ( ( _val ) << DSU4_DBGM_ED_3_0_SHIFT ) & \
    DSU4_DBGM_ED_3_0_MASK )

DSU4_DBGM_ED_3_0_GET

#define DSU4_DBGM_ED_3_0_GET

(

_reg

)

Value:

  ( ( ( _reg ) & DSU4_DBGM_ED_3_0_MASK ) >> \
    DSU4_DBGM_ED_3_0_SHIFT )

DSU4_DBGM_ED_3_0_SET

#define DSU4_DBGM_ED_3_0_SET	(		_reg,
			_val
	)

Value:

  ( ( ( _reg ) & ~DSU4_DBGM_ED_3_0_MASK ) | \
    ( ( ( _val ) << DSU4_DBGM_ED_3_0_SHIFT ) & \
      DSU4_DBGM_ED_3_0_MASK ) )