Functions
ALT_STATUS_CODE	alt_l2_addr_filter_cfg_get (uint32_t addr_filt_start, uint32_t addr_filt_end)

ALT_STATUS_CODE	alt_l2_addr_filter_cfg_set (uint32_t addr_filt_start, uint32_t addr_filt_end)

Detailed Description

The L2 cache address filter controls where physical addresses within certain ranges of the MPU address space are directed.

The L2 cache has master port connections to the L3 interconnect and the SDRAM controller. A programmable address filter controls which portions of the 32-bit physical address space use each master.

When l2 address filtering is configured and enabled, a physical address will be redirected to one master or the other based upon the address filter configuration.

If address_filter_start <= physical_address < address_filter_end:

then redirect physical_address to AXI Master Port M1 (SDRAM controller)
else redirect physical_address to AXI Master Port M0 (L3 interconnect)

See: ARM DDI 0246F, CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual, Section 3.3.12 Address Filtering for more information.

Function Documentation

◆ alt_l2_addr_filter_cfg_get()

ALT_STATUS_CODE alt_l2_addr_filter_cfg_get	(	uint32_t *	addr_filt_start,
		uint32_t *	addr_filt_end
	)

Get the L2 cache address filtering configuration settings.

Parameters

addr_filt_start	[out] An output parameter variable for the address filtering start address for the range of physical addresses redirected to the SDRAM AXI master port. The value returned is always a 1 MiB aligned address.
addr_filt_end	[out] An output parameter variable for the address filtering end address for the range of physical addresses redirected to the SDRAM AXI master port. The value returned is always a 1 MiB aligned address.

Return values

ALT_E_SUCCESS	The operation was successful.
ALT_E_ERROR	The operation failed.
ALT_E_BAD_ARG	An bad argument was passed. Either addr_filt_start or addr_filt_end or both are invalid addresses.

◆ alt_l2_addr_filter_cfg_set()

ALT_STATUS_CODE alt_l2_addr_filter_cfg_set	(	uint32_t	addr_filt_start,
		uint32_t	addr_filt_end
	)

Set the L2 cache address filtering configuration settings.

Address filtering start and end values must be 1 MiB aligned.