DMA Controller Common API Definitions

Typedefs
typedef enum ALT_DMA_CHANNEL_e	ALT_DMA_CHANNEL_t
typedef enum ALT_DMA_PERIPH_e	ALT_DMA_PERIPH_t
typedef enum ALT_DMA_SECURITY_e	ALT_DMA_SECURITY_t
typedef enum ALT_DMA_EVENT_e	ALT_DMA_EVENT_t

Enumerations
enum	ALT_DMA_CHANNEL_e {   ALT_DMA_CHANNEL_0 = 0 , ALT_DMA_CHANNEL_1 = 1 , ALT_DMA_CHANNEL_2 = 2 , ALT_DMA_CHANNEL_3 = 3 ,   ALT_DMA_CHANNEL_4 = 4 , ALT_DMA_CHANNEL_5 = 5 , ALT_DMA_CHANNEL_6 = 6 , ALT_DMA_CHANNEL_7 = 7 }
enum	ALT_DMA_PERIPH_e {   ALT_DMA_PERIPH_FPGA_0 = 0 , ALT_DMA_PERIPH_FPGA_1 = 1 , ALT_DMA_PERIPH_FPGA_2 = 2 , ALT_DMA_PERIPH_FPGA_3 = 3 ,   ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 = 4 , ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 = 5 , ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 = 6 , ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 = 7 ,   ALT_DMA_PERIPH_FPGA_4 = 4 , ALT_DMA_PERIPH_FPGA_5 = 5 , ALT_DMA_PERIPH_FPGA_6 = 6 , ALT_DMA_PERIPH_FPGA_7 = 7 ,   ALT_DMA_PERIPH_CAN0_IF1 = 4 , ALT_DMA_PERIPH_CAN0_IF2 = 5 , ALT_DMA_PERIPH_CAN1_IF1 = 6 , ALT_DMA_PERIPH_CAN1_IF2 = 7 ,   ALT_DMA_PERIPH_I2C0_TX = 8 , ALT_DMA_PERIPH_I2C0_RX = 9 , ALT_DMA_PERIPH_I2C1_TX = 10 , ALT_DMA_PERIPH_I2C1_RX = 11 ,   ALT_DMA_PERIPH_I2C2_TX = 12 , ALT_DMA_PERIPH_I2C2_RX = 13 , ALT_DMA_PERIPH_I2C3_TX = 14 , ALT_DMA_PERIPH_I2C3_RX = 15 ,   ALT_DMA_PERIPH_SPI0_MASTER_TX = 16 , ALT_DMA_PERIPH_SPI0_MASTER_RX = 17 , ALT_DMA_PERIPH_SPI0_SLAVE_TX = 18 , ALT_DMA_PERIPH_SPI0_SLAVE_RX = 19 ,   ALT_DMA_PERIPH_SPI1_MASTER_TX = 20 , ALT_DMA_PERIPH_SPI1_MASTER_RX = 21 , ALT_DMA_PERIPH_SPI1_SLAVE_TX = 22 , ALT_DMA_PERIPH_SPI1_SLAVE_RX = 23 ,   ALT_DMA_PERIPH_QSPI_FLASH_TX = 24 , ALT_DMA_PERIPH_QSPI_FLASH_RX = 25 , ALT_DMA_PERIPH_STM = 26 , ALT_DMA_PERIPH_RESERVED = 27 ,   ALT_DMA_PERIPH_UART0_TX = 28 , ALT_DMA_PERIPH_UART0_RX = 29 , ALT_DMA_PERIPH_UART1_TX = 30 , ALT_DMA_PERIPH_UART1_RX = 31 }
enum	ALT_DMA_SECURITY_e { ALT_DMA_SECURITY_DEFAULT = 0 , ALT_DMA_SECURITY_SECURE = 1 , ALT_DMA_SECURITY_NONSECURE = 2 }
enum	ALT_DMA_EVENT_e {   ALT_DMA_EVENT_0 = 0 , ALT_DMA_EVENT_1 = 1 , ALT_DMA_EVENT_2 = 2 , ALT_DMA_EVENT_3 = 3 ,   ALT_DMA_EVENT_4 = 4 , ALT_DMA_EVENT_5 = 5 , ALT_DMA_EVENT_6 = 6 , ALT_DMA_EVENT_7 = 7 ,   ALT_DMA_EVENT_ABORT = 8 }

Detailed Description

This module contains the common definitions for the DMA controller related APIs.

Typedef Documentation

ALT_DMA_CHANNEL_t

typedef enum ALT_DMA_CHANNEL_e ALT_DMA_CHANNEL_t

This type definition enumerates the DMA controller channel threads.

ALT_DMA_EVENT_t

typedef enum ALT_DMA_EVENT_e ALT_DMA_EVENT_t

This type definition enumerates the DMA event-interrupt resources.

ALT_DMA_PERIPH_t

typedef enum ALT_DMA_PERIPH_e ALT_DMA_PERIPH_t

This type definition enumerates the SoC system peripherals implementing the required request interface that enables direct DMA transfers to/from the device.

FPGA soft IP interface to the DMA are required to comply with the Synopsys protocol.

Request interface numbers 4 through 7 are multiplexed between the CAN controllers and soft logic implemented in the FPGA fabric. The selection between the CAN controller and FPGA interfaces is determined at DMA initialization.

ALT_DMA_SECURITY_t

typedef enum ALT_DMA_SECURITY_e ALT_DMA_SECURITY_t

This type enumerates the DMA security state options available.

Enumeration Type Documentation

ALT_DMA_CHANNEL_e

enum ALT_DMA_CHANNEL_e

This type definition enumerates the DMA controller channel threads.

Enumerator
ALT_DMA_CHANNEL_0	DMA Channel Thread 0
ALT_DMA_CHANNEL_1	DMA Channel Thread 1
ALT_DMA_CHANNEL_2	DMA Channel Thread 2
ALT_DMA_CHANNEL_3	DMA Channel Thread 3
ALT_DMA_CHANNEL_4	DMA Channel Thread 4
ALT_DMA_CHANNEL_5	DMA Channel Thread 5
ALT_DMA_CHANNEL_6	DMA Channel Thread 6
ALT_DMA_CHANNEL_7	DMA Channel Thread 7

ALT_DMA_EVENT_e

enum ALT_DMA_EVENT_e

This type definition enumerates the DMA event-interrupt resources.

Enumerator
ALT_DMA_EVENT_0	DMA Event 0
ALT_DMA_EVENT_1	DMA Event 1
ALT_DMA_EVENT_2	DMA Event 2
ALT_DMA_EVENT_3	DMA Event 3
ALT_DMA_EVENT_4	DMA Event 4
ALT_DMA_EVENT_5	DMA Event 5
ALT_DMA_EVENT_6	DMA Event 6
ALT_DMA_EVENT_7	DMA Event 7
ALT_DMA_EVENT_ABORT	DMA Abort Event

ALT_DMA_PERIPH_e

enum ALT_DMA_PERIPH_e

This type definition enumerates the SoC system peripherals implementing the required request interface that enables direct DMA transfers to/from the device.

FPGA soft IP interface to the DMA are required to comply with the Synopsys protocol.

Request interface numbers 4 through 7 are multiplexed between the CAN controllers and soft logic implemented in the FPGA fabric. The selection between the CAN controller and FPGA interfaces is determined at DMA initialization.

Enumerator
ALT_DMA_PERIPH_FPGA_0	FPGA soft IP interface 0
ALT_DMA_PERIPH_FPGA_1	FPGA soft IP interface 1
ALT_DMA_PERIPH_FPGA_2	FPGA soft IP interface 2
ALT_DMA_PERIPH_FPGA_3	FPGA soft IP interface 3
ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1	Selectively MUXed FPGA 4 or CAN 0 interface 1
ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2	Selectively MUXed FPGA 5 or CAN 0 interface 2
ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1	Selectively MUXed FPGA 6 or CAN 1 interface 1
ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2	Selectively MUXed FPGA 7 or CAN 1 interface 2
ALT_DMA_PERIPH_FPGA_4	Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1
ALT_DMA_PERIPH_FPGA_5	Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2
ALT_DMA_PERIPH_FPGA_6	Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1
ALT_DMA_PERIPH_FPGA_7	Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2
ALT_DMA_PERIPH_CAN0_IF1	Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1
ALT_DMA_PERIPH_CAN0_IF2	Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2
ALT_DMA_PERIPH_CAN1_IF1	Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1
ALT_DMA_PERIPH_CAN1_IF2	Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2
ALT_DMA_PERIPH_I2C0_TX	I2C 0 TX
ALT_DMA_PERIPH_I2C0_RX	I2C 0 RX
ALT_DMA_PERIPH_I2C1_TX	I2C 1 TX
ALT_DMA_PERIPH_I2C1_RX	I2C 1 RX
ALT_DMA_PERIPH_I2C2_TX	I2C 2 TX
ALT_DMA_PERIPH_I2C2_RX	I2C 2 RX
ALT_DMA_PERIPH_I2C3_TX	I2C 3 TX
ALT_DMA_PERIPH_I2C3_RX	I2C 3 RX
ALT_DMA_PERIPH_SPI0_MASTER_TX	SPI 0 Master TX
ALT_DMA_PERIPH_SPI0_MASTER_RX	SPI 0 Master RX
ALT_DMA_PERIPH_SPI0_SLAVE_TX	SPI 0 Slave TX
ALT_DMA_PERIPH_SPI0_SLAVE_RX	SPI 0 Slave RX
ALT_DMA_PERIPH_SPI1_MASTER_TX	SPI 1 Master TX
ALT_DMA_PERIPH_SPI1_MASTER_RX	SPI 1 Master RX
ALT_DMA_PERIPH_SPI1_SLAVE_TX	SPI 1 Slave TX
ALT_DMA_PERIPH_SPI1_SLAVE_RX	SPI 1 Slave RX
ALT_DMA_PERIPH_QSPI_FLASH_TX	QSPI Flash TX
ALT_DMA_PERIPH_QSPI_FLASH_RX	QSPI Flash RX
ALT_DMA_PERIPH_STM	System Trace Macrocell
ALT_DMA_PERIPH_RESERVED	Reserved
ALT_DMA_PERIPH_UART0_TX	UART 0 TX
ALT_DMA_PERIPH_UART0_RX	UART 0 RX
ALT_DMA_PERIPH_UART1_TX	UART 1 TX
ALT_DMA_PERIPH_UART1_RX	UART 1 RX

ALT_DMA_SECURITY_e

enum ALT_DMA_SECURITY_e

This type enumerates the DMA security state options available.

Enumerator
ALT_DMA_SECURITY_DEFAULT	Use the default security value (e.g. reset default)
ALT_DMA_SECURITY_SECURE	Secure
ALT_DMA_SECURITY_NONSECURE	Non-secure