This header file contains interfaces to access an Arm GICv3. More...

#include <dev/irq/arm-gic.h>
#include <dev/irq/arm-gic-arch.h>

Macros
#define	PRIORITY_DEFAULT 127

#define	MPIDR_AFFINITY2(val) BSP_FLD64(val, 16, 23)

#define	MPIDR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 16, 23)

#define	MPIDR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23)

#define	MPIDR_AFFINITY1(val) BSP_FLD64(val, 8, 15)

#define	MPIDR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 8, 15)

#define	MPIDR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 8, 15)

#define	MPIDR_AFFINITY0(val) BSP_FLD64(val, 0, 7)

#define	MPIDR_AFFINITY0_GET(reg) BSP_FLD64GET(reg, 0, 7)

#define	MPIDR_AFFINITY0_SET(reg, val) BSP_FLD64SET(reg, val, 0, 7)

#define	ICC_SGIR_AFFINITY3(val) BSP_FLD64(val, 48, 55)

#define	ICC_SGIR_AFFINITY3_GET(reg) BSP_FLD64GET(reg, 48, 55)

#define	ICC_SGIR_AFFINITY3_SET(reg, val) BSP_FLD64SET(reg, val, 48, 55)

#define	ICC_SGIR_IRM BSP_BIT32(40)

#define	ICC_SGIR_AFFINITY2(val) BSP_FLD64(val, 32, 39)

#define	ICC_SGIR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 32, 39)

#define	ICC_SGIR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39)

#define	ICC_SGIR_INTID(val) BSP_FLD64(val, 24, 27)

#define	ICC_SGIR_INTID_GET(reg) BSP_FLD64GET(reg, 24, 27)

#define	ICC_SGIR_INTID_SET(reg, val) BSP_FLD64SET(reg, val, 24, 27)

#define	ICC_SGIR_AFFINITY1(val) BSP_FLD64(val, 16, 23)

#define	ICC_SGIR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 16, 23)

#define	ICC_SGIR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23)

#define	ICC_SGIR_CPU_TARGET_LIST(val) BSP_FLD64(val, 0, 15)

#define	ICC_SGIR_CPU_TARGET_LIST_GET(reg) BSP_FLD64GET(reg, 0, 15)

#define	ICC_SGIR_CPU_TARGET_LIST_SET(reg, val) BSP_FLD64SET(reg, val, 0, 15)

#define	ICC_IGRPEN0_EL1 "S3_0_C12_C12_6, %0"

#define	ICC_IGRPEN1_EL1 "S3_0_C12_C12_7, %0"

#define	ICC_IGRPEN1_EL3 "S3_6_C12_C12_7, %0"

#define	ICC_IGRPEN0 ICC_IGRPEN0_EL1

#define	ICC_IGRPEN1 ICC_IGRPEN1_EL1

#define	ICC_PMR "S3_0_C4_C6_0, %0"

#define	ICC_EOIR1 "S3_0_C12_C12_1, %0"

#define	ICC_SRE "S3_0_C12_C12_5, %0"

#define	ICC_BPR0 "S3_0_C12_C8_3, %0"

#define	ICC_BPR1 "S3_0_C12_C12_3, %0"

#define	ICC_CTLR "S3_0_C12_C12_4, %0"

#define	ICC_IAR1 "%0, S3_0_C12_C12_0"

#define	MPIDR "%0, mpidr_el1"

#define	MPIDR_AFFINITY3(val) BSP_FLD64(val, 32, 39)

#define	MPIDR_AFFINITY3_GET(reg) BSP_FLD64GET(reg, 32, 39)

#define	MPIDR_AFFINITY3_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39)

#define	ICC_SGI1 "S3_0_C12_C11_5, %0"

#define	WRITE64_SR(SR_NAME, VALUE) __asm__ volatile("msr " SR_NAME " \n" : : "r" (VALUE) );

#define	WRITE_SR(SR_NAME, VALUE) WRITE64_SR(SR_NAME, VALUE)

#define	READ_SR(SR_NAME)

Detailed Description

This header file contains interfaces to access an Arm GICv3.

Macro Definition Documentation

◆ READ_SR

#define READ_SR ( SR_NAME )

Value:

({ \
  uint64_t value; \
  __asm__ volatile("mrs    " SR_NAME : "=&r" (value) ); \
  value; \
})

Macros

Detailed Description

Macro Definition Documentation

◆ READ_SR