This header file provides the API to manage an Arm PMSAv8-32 based Memory Protection Unit (MPU).
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#define | AARCH32_PMSA_MIN_REGION_ALIGN 64 |
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#define | AARCH32_PMSA_ATTR_EN 0x1U |
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#define | AARCH32_PMSA_ATTR_IDX_SHIFT 1 |
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#define | AARCH32_PMSA_ATTR_IDX_MASK 0xeU |
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#define | AARCH32_PMSA_ATTR_IDX(_idx) ( ( _idx ) << AARCH32_PMSA_ATTR_IDX_SHIFT ) |
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#define | AARCH32_PMSA_ATTR_XN 0x40U |
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#define | AARCH32_PMSA_ATTR_AP_SHIFT 7 |
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#define | AARCH32_PMSA_ATTR_AP_MASK 0x18U |
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#define | AARCH32_PMSA_ATTR_AP(_ap) ( ( _ap ) << AARCH32_PMSA_ATTR_AP_SHIFT ) |
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#define | AARCH32_PMSA_ATTR_AP_EL1_RW_EL0_NO 0x0U |
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#define | AARCH32_PMSA_ATTR_AP_EL1_RW_EL0_RW 0x1U |
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#define | AARCH32_PMSA_ATTR_AP_EL1_RO_EL0_NO 0x2U |
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#define | AARCH32_PMSA_ATTR_AP_EL1_RO_EL0_RO 0x3U |
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#define | AARCH32_PMSA_ATTR_SH_SHIFT 9 |
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#define | AARCH32_PMSA_ATTR_SH_MASK 0x600U |
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#define | AARCH32_PMSA_ATTR_SH(_sh) ( ( _sh ) << AARCH32_PMSA_ATTR_SH_SHIFT ) |
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#define | AARCH32_PMSA_ATTR_SH_NO 0x0U |
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#define | AARCH32_PMSA_ATTR_SH_RES 0x1U |
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#define | AARCH32_PMSA_ATTR_SH_OUTER 0x2U |
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#define | AARCH32_PMSA_ATTR_SH_INNER 0x3U |
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#define | AARCH32_PMSA_MEM_DEVICE_NG_NR_NE 0x00U |
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#define | AARCH32_PMSA_MEM_DEVICE_NG_NR_E 0x04U |
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#define | AARCH32_PMSA_MEM_DEVICE_NG_R_E 0x08U |
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#define | AARCH32_PMSA_MEM_DEVICE_G_R_E 0x0cU |
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#define | AARCH32_PMSA_MEM_OUTER_WTT 0x00U |
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#define | AARCH32_PMSA_MEM_OUTER_NC 0x40U |
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#define | AARCH32_PMSA_MEM_OUTER_WBT 0x40U |
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#define | AARCH32_PMSA_MEM_OUTER_WTNT 0x80U |
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#define | AARCH32_PMSA_MEM_OUTER_WBNT 0xc0U |
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#define | AARCH32_PMSA_MEM_OUTER_RA 0x20U |
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#define | AARCH32_PMSA_MEM_OUTER_WA 0x10U |
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#define | AARCH32_PMSA_MEM_INNER_WTT 0x00U |
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#define | AARCH32_PMSA_MEM_INNER_NC 0x04U |
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#define | AARCH32_PMSA_MEM_INNER_WBT 0x04U |
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#define | AARCH32_PMSA_MEM_INNER_WTNT 0x08U |
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#define | AARCH32_PMSA_MEM_INNER_WBNT 0x0cU |
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#define | AARCH32_PMSA_MEM_INNER_RA 0x02U |
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#define | AARCH32_PMSA_MEM_INNER_WA 0x01U |
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#define | AARCH32_PMSA_MEM_ATTR(_ma0, _ma1, _ma2, _ma3) ( ( _ma0 ) | ( ( _ma1 ) << 8 ) | ( ( _ma2 ) << 16 ) | ( ( _ma3 ) << 24 ) ) |
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#define | AARCH32_PMSA_MEM_ATTR_DEFAULT_CACHED |
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#define | AARCH32_PMSA_MEM_ATTR_DEFAULT_UNCACHED |
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#define | AARCH32_PMSA_MEM_ATTR_DEFAULT_DEVICE AARCH32_PMSA_MEM_DEVICE_NG_NR_NE |
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#define | AARCH32_PMSA_CODE_CACHED |
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#define | AARCH32_PMSA_CODE_UNCACHED |
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#define | AARCH32_PMSA_DATA_READ_ONLY_CACHED |
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#define | AARCH32_PMSA_DATA_READ_ONLY_UNCACHED |
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#define | AARCH32_PMSA_DATA_READ_WRITE_CACHED |
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#define | AARCH32_PMSA_DATA_READ_WRITE_UNCACHED |
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#define | AARCH32_PMSA_DATA_READ_WRITE_SHARED |
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#define | AARCH32_PMSA_DEVICE |
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#define | AARCH32_PMSA_DATA_READ_WRITE_DEFAULT AARCH32_PMSA_DATA_READ_WRITE_CACHED |
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#define | AARCH32_PMSA_DEFAULT_SECTIONS |
| The default section definitions shall be used by the BSP to define _AArch32_PMSA_Sections. More...
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This header file provides the API to manage an Arm PMSAv8-32 based Memory Protection Unit (MPU).