RTEMS 6.3
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imx_srcreg.h
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/*
4 * Copyright (c) 2017 embedded brains GmbH & Co. KG
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#ifndef IMX_SRCREG_H
29#define IMX_SRCREG_H
30
31#include <bsp/utility.h>
32
33typedef struct {
34 uint32_t scr;
35#define IMX_SRC_SCR_DOM_EN BSP_BIT32(31)
36#define IMX_SRC_SCR_LOCK BSP_BIT32(30)
37#define IMX_SRC_SCR_DOMAIN3 BSP_BIT32(27)
38#define IMX_SRC_SCR_DOMAIN2 BSP_BIT32(26)
39#define IMX_SRC_SCR_DOMAIN1 BSP_BIT32(25)
40#define IMX_SRC_SCR_DOMAIN0 BSP_BIT32(24)
41#define IMX_SRC_SCR_MASK_TEMPSENSE_RESET(val) BSP_FLD32(val, 4, 7)
42#define IMX_SRC_SCR_MASK_TEMPSENSE_RESET_GET(reg) BSP_FLD32GET(reg, 4, 7)
43#define IMX_SRC_SCR_MASK_TEMPSENSE_RESET_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
44 uint32_t a7rcr0;
45#define IMX_SRC_A7RCR0_DOM_EN BSP_BIT32(31)
46#define IMX_SRC_A7RCR0_LOCK BSP_BIT32(30)
47#define IMX_SRC_A7RCR0_DOMAIN3 BSP_BIT32(27)
48#define IMX_SRC_A7RCR0_DOMAIN2 BSP_BIT32(26)
49#define IMX_SRC_A7RCR0_DOMAIN1 BSP_BIT32(25)
50#define IMX_SRC_A7RCR0_DOMAIN0 BSP_BIT32(24)
51#define IMX_SRC_A7RCR0_A7_L2RESET BSP_BIT32(21)
52#define IMX_SRC_A7RCR0_A7_SOC_DBG_RESET BSP_BIT32(20)
53#define IMX_SRC_A7RCR0_MASK_WDOG1_RST(val) BSP_FLD32(val, 16, 19)
54#define IMX_SRC_A7RCR0_MASK_WDOG1_RST_GET(reg) BSP_FLD32GET(reg, 16, 19)
55#define IMX_SRC_A7RCR0_MASK_WDOG1_RST_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19)
56#define IMX_SRC_A7RCR0_A7_ETM_RESET1 BSP_BIT32(13)
57#define IMX_SRC_A7RCR0_A7_ETM_RESET0 BSP_BIT32(12)
58#define IMX_SRC_A7RCR0_A7_DBG_RESET1 BSP_BIT32(9)
59#define IMX_SRC_A7RCR0_A7_DBG_RESET0 BSP_BIT32(8)
60#define IMX_SRC_A7RCR0_A7_CORE_RESET1 BSP_BIT32(5)
61#define IMX_SRC_A7RCR0_A7_CORE_RESET0 BSP_BIT32(4)
62#define IMX_SRC_A7RCR0_A7_CORE_POR_RESET1 BSP_BIT32(1)
63#define IMX_SRC_A7RCR0_A7_CORE_POR_RESET0 BSP_BIT32(0)
64 uint32_t a7rcr1;
65#define IMX_SRC_A7RCR1_DOM_EN BSP_BIT32(31)
66#define IMX_SRC_A7RCR1_LOCK BSP_BIT32(30)
67#define IMX_SRC_A7RCR1_DOMAIN3 BSP_BIT32(27)
68#define IMX_SRC_A7RCR1_DOMAIN2 BSP_BIT32(26)
69#define IMX_SRC_A7RCR1_DOMAIN1 BSP_BIT32(25)
70#define IMX_SRC_A7RCR1_DOMAIN0 BSP_BIT32(24)
71#define IMX_SRC_A7RCR1_A7_CORE1_ENABLE BSP_BIT32(1)
72 uint32_t m4rcr;
73#define IMX_SRC_M4RCR_DOM_EN BSP_BIT32(31)
74#define IMX_SRC_M4RCR_LOCK BSP_BIT32(30)
75#define IMX_SRC_M4RCR_DOMAIN3 BSP_BIT32(27)
76#define IMX_SRC_M4RCR_DOMAIN2 BSP_BIT32(26)
77#define IMX_SRC_M4RCR_DOMAIN1 BSP_BIT32(25)
78#define IMX_SRC_M4RCR_DOMAIN0 BSP_BIT32(24)
79#define IMX_SRC_M4RCR_WDOG3_RST_OPTION BSP_BIT32(9)
80#define IMX_SRC_M4RCR_WDOG3_RST_OPTION_M4 BSP_BIT32(8)
81#define IMX_SRC_M4RCR_MASK_WDOG3_RST(val) BSP_FLD32(val, 4, 7)
82#define IMX_SRC_M4RCR_MASK_WDOG3_RST_GET(reg) BSP_FLD32GET(reg, 4, 7)
83#define IMX_SRC_M4RCR_MASK_WDOG3_RST_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
84#define IMX_SRC_M4RCR_ENABLE_M4 BSP_BIT32(3)
85#define IMX_SRC_M4RCR_SW_M4P_RST BSP_BIT32(2)
86#define IMX_SRC_M4RCR_SW_M4C_RST BSP_BIT32(1)
87#define IMX_SRC_M4RCR_SW_M4C_NON_SCLR_RST BSP_BIT32(0)
88 uint32_t reserved_10;
89 uint32_t ercr;
90 uint32_t reserved_18;
91 uint32_t hsicphy_rcr;
92 uint32_t usbophy1_rcr;
93 uint32_t usbophy2_rcr;
94 uint32_t mipiphy_rcr;
95 uint32_t pciephy_rcr;
96 uint32_t reserved_30[10];
97 uint32_t sbmr1;
98 uint32_t srsr;
99 uint32_t reserved_60[2];
100 uint32_t sisr;
101 uint32_t simr;
102 uint32_t sbmr2;
103 uint32_t gpr1;
104 uint32_t gpr2;
105 uint32_t gpr3;
106 uint32_t gpr4;
107 uint32_t gpr5;
108 uint32_t gpr6;
109 uint32_t gpr7;
110 uint32_t gpr8;
111 uint32_t gpr9;
112 uint32_t gpr10;
113 uint32_t reserved_9c[985];
114 uint32_t ddrc_rcr;
115} imx_src;
116
117#endif /* IMX_SRCREG_H */
utility.h
This header file provides utility macros for BSPs.
imx_src
Definition imx_srcreg.h:33
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