RTEMS 6.3
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apic.h
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1
6
7/*
8 * Author: Erich Boleyn <erich@uruk.org>
9 * http://www.uruk.org/~erich/
10 *
11 * Copyright (c) 1997-2011 Erich Boleyn. All rights reserved.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 3. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
42
43/*
44 * Header file for Intel Architecture local and I/O APIC definitions.
45 *
46 * This file was created from information in the Intel Pentium Pro
47 * Family Developer's Manual, Volume 3: Operating System Writer's
48 * Manual, order number 242692-001, which can be ordered from the
49 * Intel literature center.
50 */
51
52#ifndef _APIC_H
53#define _APIC_H
54
55/*
56 * APIC Defines.
57 */
58
59/*
60 * Recommendation: Don't use this except for MSI interrupt delivery.
61 * In general, the "Destination Mode" can be used to control this, since
62 * it is DIFFERENT (0xF) for Pentium and P6, but not on the same APIC
63 * version for AMD Opteron.
64 */
65#define APIC_BCAST_ID 0xFF
66
67/*
68 * APIC register definitions
69 */
70
71/*
72 * Shared defines for I/O and local APIC definitions
73 */
75#define APIC_VERSION(x) ((x) & 0xFF)
76#define APIC_MAXREDIR(x) (((x) >> 16) & 0xFF)
78#define APIC_ID(x) ((x) >> 24)
79#define APIC_VER_NEW 0x10
80
81#define IOAPIC_REGSEL 0
82#define IOAPIC_RW 0x10
83#define IOAPIC_ID 0
84#define IOAPIC_VER 1
85#define IOAPIC_REDIR 0x10
86
87#define LAPIC_ID 0x20
88#define LAPIC_VER 0x30
89#define LAPIC_TPR 0x80
90#define LAPIC_APR 0x90
91#define LAPIC_PPR 0xA0
92#define LAPIC_EOI 0xB0
93#define LAPIC_LDR 0xD0
94#define LAPIC_DFR 0xE0
95#define LAPIC_SPIV 0xF0
96#define LAPIC_SPIV_ENABLE_APIC 0x100
97#define LAPIC_ISR 0x100
98#define LAPIC_TMR 0x180
99#define LAPIC_IRR 0x200
100#define LAPIC_ESR 0x280
101#define LAPIC_ICR 0x300
102#define LAPIC_ICR_DS_SELF 0x40000
103#define LAPIC_ICR_DS_ALLINC 0x80000
104#define LAPIC_ICR_DS_ALLEX 0xC0000
105#define LAPIC_ICR_TM_LEVEL 0x8000
106#define LAPIC_ICR_LEVELASSERT 0x4000
107#define LAPIC_ICR_STATUS_PEND 0x1000
108#define LAPIC_ICR_DM_LOGICAL 0x800
109#define LAPIC_ICR_DM_LOWPRI 0x100
110#define LAPIC_ICR_DM_SMI 0x200
111#define LAPIC_ICR_DM_NMI 0x400
112#define LAPIC_ICR_DM_INIT 0x500
113#define LAPIC_ICR_DM_SIPI 0x600
114#define LAPIC_LVTT 0x320
115#define LAPIC_LVTPC 0x340
116#define LAPIC_LVT0 0x350
117#define LAPIC_LVT1 0x360
118#define LAPIC_LVTE 0x370
119#define LAPIC_TICR 0x380
120#define LAPIC_TCCR 0x390
121#define LAPIC_TDCR 0x3E0
122
123#endif /* _APIC_H */
124
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