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RTEMS 6.3
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This group contains register bit definitions. More...
Macros | |
| #define | GRSPW2_STS_NRXD_SHIFT 26 |
| #define | GRSPW2_STS_NRXD_MASK 0xc000000U |
| #define | GRSPW2_STS_NRXD_GET(_reg) |
| #define | GRSPW2_STS_NRXD_SET(_reg, _val) |
| #define | GRSPW2_STS_NRXD(_val) |
| #define | GRSPW2_STS_NTXD 0x2000000U |
| #define | GRSPW2_STS_LS_SHIFT 21 |
| #define | GRSPW2_STS_LS_MASK 0xe00000U |
| #define | GRSPW2_STS_LS_GET(_reg) |
| #define | GRSPW2_STS_LS_SET(_reg, _val) |
| #define | GRSPW2_STS_LS(_val) |
| #define | GRSPW2_STS_AP 0x200U |
| #define | GRSPW2_STS_EE 0x100U |
| #define | GRSPW2_STS_IA 0x80U |
| #define | GRSPW2_STS_RES_SHIFT 5 |
| #define | GRSPW2_STS_RES_MASK 0x60U |
| #define | GRSPW2_STS_RES_GET(_reg) |
| #define | GRSPW2_STS_RES_SET(_reg, _val) |
| #define | GRSPW2_STS_RES(_val) |
| #define | GRSPW2_STS_PE 0x10U |
| #define | GRSPW2_STS_DE 0x8U |
| #define | GRSPW2_STS_ER 0x4U |
| #define | GRSPW2_STS_CE 0x2U |
| #define | GRSPW2_STS_TO 0x1U |
This group contains register bit definitions.
| #define GRSPW2_STS_LS | ( | _val | ) |
| #define GRSPW2_STS_LS_GET | ( | _reg | ) |
| #define GRSPW2_STS_LS_SET | ( | _reg, | |
| _val ) |
| #define GRSPW2_STS_NRXD | ( | _val | ) |
| #define GRSPW2_STS_NRXD_GET | ( | _reg | ) |
| #define GRSPW2_STS_NRXD_SET | ( | _reg, | |
| _val ) |
| #define GRSPW2_STS_RES | ( | _val | ) |
| #define GRSPW2_STS_RES_GET | ( | _reg | ) |
| #define GRSPW2_STS_RES_SET | ( | _reg, | |
| _val ) |