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RTEMS 6.3
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This group contains register bit definitions. More...
Macros | |
| #define | GRPCI2_CTRL_RE 0x80000000U |
| #define | GRPCI2_CTRL_MR 0x40000000U |
| #define | GRPCI2_CTRL_TR 0x20000000U |
| #define | GRPCI2_CTRL_SI 0x8000000U |
| #define | GRPCI2_CTRL_PE 0x4000000U |
| #define | GRPCI2_CTRL_ER 0x2000000U |
| #define | GRPCI2_CTRL_EI 0x1000000U |
| #define | GRPCI2_CTRL_BUS_NUMBER_SHIFT 16 |
| #define | GRPCI2_CTRL_BUS_NUMBER_MASK 0xff0000U |
| #define | GRPCI2_CTRL_BUS_NUMBER_GET(_reg) |
| #define | GRPCI2_CTRL_BUS_NUMBER_SET(_reg, _val) |
| #define | GRPCI2_CTRL_BUS_NUMBER(_val) |
| #define | GRPCI2_CTRL_DFA 0x800U |
| #define | GRPCI2_CTRL_IB 0x400U |
| #define | GRPCI2_CTRL_CB 0x200U |
| #define | GRPCI2_CTRL_DIF 0x100U |
| #define | GRPCI2_CTRL_DEVICE_INT_MASK_SHIFT 4 |
| #define | GRPCI2_CTRL_DEVICE_INT_MASK_MASK 0xf0U |
| #define | GRPCI2_CTRL_DEVICE_INT_MASK_GET(_reg) |
| #define | GRPCI2_CTRL_DEVICE_INT_MASK_SET(_reg, _val) |
| #define | GRPCI2_CTRL_DEVICE_INT_MASK(_val) |
| #define | GRPCI2_CTRL_HOST_INT_MASK_SHIFT 0 |
| #define | GRPCI2_CTRL_HOST_INT_MASK_MASK 0xfU |
| #define | GRPCI2_CTRL_HOST_INT_MASK_GET(_reg) |
| #define | GRPCI2_CTRL_HOST_INT_MASK_SET(_reg, _val) |
| #define | GRPCI2_CTRL_HOST_INT_MASK(_val) |
This group contains register bit definitions.
| #define GRPCI2_CTRL_BUS_NUMBER | ( | _val | ) |
| #define GRPCI2_CTRL_BUS_NUMBER_GET | ( | _reg | ) |
| #define GRPCI2_CTRL_BUS_NUMBER_SET | ( | _reg, | |
| _val ) |
| #define GRPCI2_CTRL_DEVICE_INT_MASK | ( | _val | ) |
| #define GRPCI2_CTRL_DEVICE_INT_MASK_GET | ( | _reg | ) |
| #define GRPCI2_CTRL_DEVICE_INT_MASK_SET | ( | _reg, | |
| _val ) |
| #define GRPCI2_CTRL_HOST_INT_MASK | ( | _val | ) |
| #define GRPCI2_CTRL_HOST_INT_MASK_GET | ( | _reg | ) |
| #define GRPCI2_CTRL_HOST_INT_MASK_SET | ( | _reg, | |
| _val ) |