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#define | SPICTRL_MODE_LOOP 0x40000000U |
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#define | SPICTRL_MODE_CPOL 0x20000000U |
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#define | SPICTRL_MODE_CPHA 0x10000000U |
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#define | SPICTRL_MODE_DIV_16 0x8000000U |
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#define | SPICTRL_MODE_REV 0x4000000U |
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#define | SPICTRL_MODE_MX 0x2000000U |
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#define | SPICTRL_MODE_EN 0x1000000U |
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#define | SPICTRL_MODE_LEN_SHIFT 20 |
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#define | SPICTRL_MODE_LEN_MASK 0xf00000U |
| #define | SPICTRL_MODE_LEN_GET(_reg) |
| #define | SPICTRL_MODE_LEN_SET(_reg, _val) |
| #define | SPICTRL_MODE_LEN(_val) |
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#define | SPICTRL_MODE_PM_SHIFT 16 |
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#define | SPICTRL_MODE_PM_MASK 0xf0000U |
| #define | SPICTRL_MODE_PM_GET(_reg) |
| #define | SPICTRL_MODE_PM_SET(_reg, _val) |
| #define | SPICTRL_MODE_PM(_val) |
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#define | SPICTRL_MODE_TWEN 0x8000U |
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#define | SPICTRL_MODE_ASEL 0x4000U |
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#define | SPICTRL_MODE_FACT 0x2000U |
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#define | SPICTRL_MODE_OD 0x1000U |
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#define | SPICTRL_MODE_CG_SHIFT 7 |
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#define | SPICTRL_MODE_CG_MASK 0xf80U |
| #define | SPICTRL_MODE_CG_GET(_reg) |
| #define | SPICTRL_MODE_CG_SET(_reg, _val) |
| #define | SPICTRL_MODE_CG(_val) |
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#define | SPICTRL_MODE_ASELDEL_SHIFT 5 |
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#define | SPICTRL_MODE_ASELDEL_MASK 0x60U |
| #define | SPICTRL_MODE_ASELDEL_GET(_reg) |
| #define | SPICTRL_MODE_ASELDEL_SET(_reg, _val) |
| #define | SPICTRL_MODE_ASELDEL(_val) |
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#define | SPICTRL_MODE_TAC 0x10U |
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#define | SPICTRL_MODE_TTO 0x8U |
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#define | SPICTRL_MODE_IGSEL 0x4U |
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#define | SPICTRL_MODE_CITE 0x2U |
This group contains register bit definitions.