LVDS and memory clock pad enable register (LVDSMCLK)

This group contains register bit definitions. More...

Macros
#define	GR740_IOPLL_LVDSMCLK_SMEM   0x20000U
#define	GR740_IOPLL_LVDSMCLK_DMEM   0x10000U
#define	GR740_IOPLL_LVDSMCLK_SPWOE_SHIFT   0
#define	GR740_IOPLL_LVDSMCLK_SPWOE_MASK   0xffU
#define	GR740_IOPLL_LVDSMCLK_SPWOE_GET(_reg)
#define	GR740_IOPLL_LVDSMCLK_SPWOE_SET(_reg, _val)
#define	GR740_IOPLL_LVDSMCLK_SPWOE(_val)

Detailed Description

This group contains register bit definitions.

Macro Definition Documentation

GR740_IOPLL_LVDSMCLK_SPWOE

#define GR740_IOPLL_LVDSMCLK_SPWOE

(

_val

)

Value:

( ( ( _val ) << GR740_IOPLL_LVDSMCLK_SPWOE_SHIFT ) & \
  GR740_IOPLL_LVDSMCLK_SPWOE_MASK )

GR740_IOPLL_LVDSMCLK_SPWOE_GET

#define GR740_IOPLL_LVDSMCLK_SPWOE_GET

(

_reg

)

Value:

( ( ( _reg ) & GR740_IOPLL_LVDSMCLK_SPWOE_MASK ) >> \
  GR740_IOPLL_LVDSMCLK_SPWOE_SHIFT )

GR740_IOPLL_LVDSMCLK_SPWOE_SET

#define GR740_IOPLL_LVDSMCLK_SPWOE_SET	(		_reg,
			_val )

Value:

( ( ( _reg ) & ~GR740_IOPLL_LVDSMCLK_SPWOE_MASK ) | \
  ( ( ( _val ) << GR740_IOPLL_LVDSMCLK_SPWOE_SHIFT ) & \
    GR740_IOPLL_LVDSMCLK_SPWOE_MASK ) )