Drive strength configuration register 1 (DRVSTR1)

This group contains register bit definitions. More...

Macros
#define	GR740_IOPLL_DRVSTR1_S9_SHIFT   18
#define	GR740_IOPLL_DRVSTR1_S9_MASK   0xc0000U
#define	GR740_IOPLL_DRVSTR1_S9_GET(_reg)
#define	GR740_IOPLL_DRVSTR1_S9_SET(_reg, _val)
#define	GR740_IOPLL_DRVSTR1_S9(_val)
#define	GR740_IOPLL_DRVSTR1_S8_SHIFT   16
#define	GR740_IOPLL_DRVSTR1_S8_MASK   0x30000U
#define	GR740_IOPLL_DRVSTR1_S8_GET(_reg)
#define	GR740_IOPLL_DRVSTR1_S8_SET(_reg, _val)
#define	GR740_IOPLL_DRVSTR1_S8(_val)
#define	GR740_IOPLL_DRVSTR1_S7_SHIFT   14
#define	GR740_IOPLL_DRVSTR1_S7_MASK   0xc000U
#define	GR740_IOPLL_DRVSTR1_S7_GET(_reg)
#define	GR740_IOPLL_DRVSTR1_S7_SET(_reg, _val)
#define	GR740_IOPLL_DRVSTR1_S7(_val)
#define	GR740_IOPLL_DRVSTR1_S6_SHIFT   12
#define	GR740_IOPLL_DRVSTR1_S6_MASK   0x3000U
#define	GR740_IOPLL_DRVSTR1_S6_GET(_reg)
#define	GR740_IOPLL_DRVSTR1_S6_SET(_reg, _val)
#define	GR740_IOPLL_DRVSTR1_S6(_val)
#define	GR740_IOPLL_DRVSTR1_S5_SHIFT   10
#define	GR740_IOPLL_DRVSTR1_S5_MASK   0xc00U
#define	GR740_IOPLL_DRVSTR1_S5_GET(_reg)
#define	GR740_IOPLL_DRVSTR1_S5_SET(_reg, _val)
#define	GR740_IOPLL_DRVSTR1_S5(_val)
#define	GR740_IOPLL_DRVSTR1_S4_SHIFT   8
#define	GR740_IOPLL_DRVSTR1_S4_MASK   0x300U
#define	GR740_IOPLL_DRVSTR1_S4_GET(_reg)
#define	GR740_IOPLL_DRVSTR1_S4_SET(_reg, _val)
#define	GR740_IOPLL_DRVSTR1_S4(_val)
#define	GR740_IOPLL_DRVSTR1_S3_SHIFT   6
#define	GR740_IOPLL_DRVSTR1_S3_MASK   0xc0U
#define	GR740_IOPLL_DRVSTR1_S3_GET(_reg)
#define	GR740_IOPLL_DRVSTR1_S3_SET(_reg, _val)
#define	GR740_IOPLL_DRVSTR1_S3(_val)
#define	GR740_IOPLL_DRVSTR1_S2_SHIFT   4
#define	GR740_IOPLL_DRVSTR1_S2_MASK   0x30U
#define	GR740_IOPLL_DRVSTR1_S2_GET(_reg)
#define	GR740_IOPLL_DRVSTR1_S2_SET(_reg, _val)
#define	GR740_IOPLL_DRVSTR1_S2(_val)
#define	GR740_IOPLL_DRVSTR1_S1_SHIFT   2
#define	GR740_IOPLL_DRVSTR1_S1_MASK   0xcU
#define	GR740_IOPLL_DRVSTR1_S1_GET(_reg)
#define	GR740_IOPLL_DRVSTR1_S1_SET(_reg, _val)
#define	GR740_IOPLL_DRVSTR1_S1(_val)
#define	GR740_IOPLL_DRVSTR1_S0_SHIFT   0
#define	GR740_IOPLL_DRVSTR1_S0_MASK   0x3U
#define	GR740_IOPLL_DRVSTR1_S0_GET(_reg)
#define	GR740_IOPLL_DRVSTR1_S0_SET(_reg, _val)
#define	GR740_IOPLL_DRVSTR1_S0(_val)

Detailed Description

This group contains register bit definitions.

Macro Definition Documentation

GR740_IOPLL_DRVSTR1_S0

#define GR740_IOPLL_DRVSTR1_S0

(

_val

)

Value:

( ( ( _val ) << GR740_IOPLL_DRVSTR1_S0_SHIFT ) & \
  GR740_IOPLL_DRVSTR1_S0_MASK )

GR740_IOPLL_DRVSTR1_S0_GET

#define GR740_IOPLL_DRVSTR1_S0_GET

(

_reg

)

Value:

( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S0_MASK ) >> \
  GR740_IOPLL_DRVSTR1_S0_SHIFT )

GR740_IOPLL_DRVSTR1_S0_SET

#define GR740_IOPLL_DRVSTR1_S0_SET	(		_reg,
			_val )

Value:

( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S0_MASK ) | \
  ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S0_SHIFT ) & \
    GR740_IOPLL_DRVSTR1_S0_MASK ) )

GR740_IOPLL_DRVSTR1_S1

#define GR740_IOPLL_DRVSTR1_S1

(

_val

)

Value:

( ( ( _val ) << GR740_IOPLL_DRVSTR1_S1_SHIFT ) & \
  GR740_IOPLL_DRVSTR1_S1_MASK )

GR740_IOPLL_DRVSTR1_S1_GET

#define GR740_IOPLL_DRVSTR1_S1_GET

(

_reg

)

Value:

( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S1_MASK ) >> \
  GR740_IOPLL_DRVSTR1_S1_SHIFT )

GR740_IOPLL_DRVSTR1_S1_SET

#define GR740_IOPLL_DRVSTR1_S1_SET	(		_reg,
			_val )

Value:

( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S1_MASK ) | \
  ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S1_SHIFT ) & \
    GR740_IOPLL_DRVSTR1_S1_MASK ) )

GR740_IOPLL_DRVSTR1_S2

#define GR740_IOPLL_DRVSTR1_S2

(

_val

)

Value:

( ( ( _val ) << GR740_IOPLL_DRVSTR1_S2_SHIFT ) & \
  GR740_IOPLL_DRVSTR1_S2_MASK )

GR740_IOPLL_DRVSTR1_S2_GET

#define GR740_IOPLL_DRVSTR1_S2_GET

(

_reg

)

Value:

( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S2_MASK ) >> \
  GR740_IOPLL_DRVSTR1_S2_SHIFT )

GR740_IOPLL_DRVSTR1_S2_SET

#define GR740_IOPLL_DRVSTR1_S2_SET	(		_reg,
			_val )

Value:

( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S2_MASK ) | \
  ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S2_SHIFT ) & \
    GR740_IOPLL_DRVSTR1_S2_MASK ) )

GR740_IOPLL_DRVSTR1_S3

#define GR740_IOPLL_DRVSTR1_S3

(

_val

)

Value:

( ( ( _val ) << GR740_IOPLL_DRVSTR1_S3_SHIFT ) & \
  GR740_IOPLL_DRVSTR1_S3_MASK )

GR740_IOPLL_DRVSTR1_S3_GET

#define GR740_IOPLL_DRVSTR1_S3_GET

(

_reg

)

Value:

( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S3_MASK ) >> \
  GR740_IOPLL_DRVSTR1_S3_SHIFT )

GR740_IOPLL_DRVSTR1_S3_SET

#define GR740_IOPLL_DRVSTR1_S3_SET	(		_reg,
			_val )

Value:

( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S3_MASK ) | \
  ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S3_SHIFT ) & \
    GR740_IOPLL_DRVSTR1_S3_MASK ) )

GR740_IOPLL_DRVSTR1_S4

#define GR740_IOPLL_DRVSTR1_S4

(

_val

)

Value:

( ( ( _val ) << GR740_IOPLL_DRVSTR1_S4_SHIFT ) & \
  GR740_IOPLL_DRVSTR1_S4_MASK )

GR740_IOPLL_DRVSTR1_S4_GET

#define GR740_IOPLL_DRVSTR1_S4_GET

(

_reg

)

Value:

( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S4_MASK ) >> \
  GR740_IOPLL_DRVSTR1_S4_SHIFT )

GR740_IOPLL_DRVSTR1_S4_SET

#define GR740_IOPLL_DRVSTR1_S4_SET	(		_reg,
			_val )

Value:

( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S4_MASK ) | \
  ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S4_SHIFT ) & \
    GR740_IOPLL_DRVSTR1_S4_MASK ) )

GR740_IOPLL_DRVSTR1_S5

#define GR740_IOPLL_DRVSTR1_S5

(

_val

)

Value:

( ( ( _val ) << GR740_IOPLL_DRVSTR1_S5_SHIFT ) & \
  GR740_IOPLL_DRVSTR1_S5_MASK )

GR740_IOPLL_DRVSTR1_S5_GET

#define GR740_IOPLL_DRVSTR1_S5_GET

(

_reg

)

Value:

( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S5_MASK ) >> \
  GR740_IOPLL_DRVSTR1_S5_SHIFT )

GR740_IOPLL_DRVSTR1_S5_SET

#define GR740_IOPLL_DRVSTR1_S5_SET	(		_reg,
			_val )

Value:

( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S5_MASK ) | \
  ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S5_SHIFT ) & \
    GR740_IOPLL_DRVSTR1_S5_MASK ) )

GR740_IOPLL_DRVSTR1_S6

#define GR740_IOPLL_DRVSTR1_S6

(

_val

)

Value:

( ( ( _val ) << GR740_IOPLL_DRVSTR1_S6_SHIFT ) & \
  GR740_IOPLL_DRVSTR1_S6_MASK )

GR740_IOPLL_DRVSTR1_S6_GET

#define GR740_IOPLL_DRVSTR1_S6_GET

(

_reg

)

Value:

( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S6_MASK ) >> \
  GR740_IOPLL_DRVSTR1_S6_SHIFT )

GR740_IOPLL_DRVSTR1_S6_SET

#define GR740_IOPLL_DRVSTR1_S6_SET	(		_reg,
			_val )

Value:

( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S6_MASK ) | \
  ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S6_SHIFT ) & \
    GR740_IOPLL_DRVSTR1_S6_MASK ) )

GR740_IOPLL_DRVSTR1_S7

#define GR740_IOPLL_DRVSTR1_S7

(

_val

)

Value:

( ( ( _val ) << GR740_IOPLL_DRVSTR1_S7_SHIFT ) & \
  GR740_IOPLL_DRVSTR1_S7_MASK )

GR740_IOPLL_DRVSTR1_S7_GET

#define GR740_IOPLL_DRVSTR1_S7_GET

(

_reg

)

Value:

( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S7_MASK ) >> \
  GR740_IOPLL_DRVSTR1_S7_SHIFT )

GR740_IOPLL_DRVSTR1_S7_SET

#define GR740_IOPLL_DRVSTR1_S7_SET	(		_reg,
			_val )

Value:

( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S7_MASK ) | \
  ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S7_SHIFT ) & \
    GR740_IOPLL_DRVSTR1_S7_MASK ) )

GR740_IOPLL_DRVSTR1_S8

#define GR740_IOPLL_DRVSTR1_S8

(

_val

)

Value:

( ( ( _val ) << GR740_IOPLL_DRVSTR1_S8_SHIFT ) & \
  GR740_IOPLL_DRVSTR1_S8_MASK )

GR740_IOPLL_DRVSTR1_S8_GET

#define GR740_IOPLL_DRVSTR1_S8_GET

(

_reg

)

Value:

( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S8_MASK ) >> \
  GR740_IOPLL_DRVSTR1_S8_SHIFT )

GR740_IOPLL_DRVSTR1_S8_SET

#define GR740_IOPLL_DRVSTR1_S8_SET	(		_reg,
			_val )

Value:

( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S8_MASK ) | \
  ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S8_SHIFT ) & \
    GR740_IOPLL_DRVSTR1_S8_MASK ) )

GR740_IOPLL_DRVSTR1_S9

#define GR740_IOPLL_DRVSTR1_S9

(

_val

)

Value:

( ( ( _val ) << GR740_IOPLL_DRVSTR1_S9_SHIFT ) & \
  GR740_IOPLL_DRVSTR1_S9_MASK )

GR740_IOPLL_DRVSTR1_S9_GET

#define GR740_IOPLL_DRVSTR1_S9_GET

(

_reg

)

Value:

( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S9_MASK ) >> \
  GR740_IOPLL_DRVSTR1_S9_SHIFT )

GR740_IOPLL_DRVSTR1_S9_SET

#define GR740_IOPLL_DRVSTR1_S9_SET	(		_reg,
			_val )

Value:

( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S9_MASK ) | \
  ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S9_SHIFT ) & \
    GR740_IOPLL_DRVSTR1_S9_MASK ) )