RTEMS
6.3
Toggle main menu visibility
Loading...
Searching...
No Matches
bsps
arm
csb337
include
at91rm9200_usart.h
Go to the documentation of this file.
1
8
9
/*
10
* Atmel AT91RM9200_USART Register definitions, used in KIT637_V6 (CSB637)
11
*
12
* Copyright (c) 2003 by Cogent Computer Systems
13
* Written by Mike Kelly <mike@cogcomp.com>
14
*
15
* Modified by Fernando Nicodemos <fgnicodemos@terra.com.br>
16
* from NCB - Sistemas Embarcados Ltda. (Brazil)
17
*
18
* The license and distribution terms for this file may be
19
* found in the file LICENSE in this distribution or at
20
* http://www.rtems.org/license/LICENSE.
21
*/
22
23
#ifndef __AT91RM9200_USART_H__
24
#define __AT91RM9200_USART_H__
25
26
#include <
bits.h
>
27
28
/* Register Offsets */
29
#define US_CR 0x00
/* Control Register */
30
#define US_MR 0x04
/* Mode Register */
31
#define US_IER 0x08
/* Interrupt Enable Register */
32
#define US_IDR 0x0C
/* Interrupt Disable Register */
33
#define US_IMR 0x10
/* Interrupt Mask Register */
34
#define US_SR 0x14
/* Channel Status Register */
35
#define US_RHR 0x18
/* Receiver Holding Register */
36
#define US_THR 0x1C
/* Transmitter Holding Register */
37
#define US_BRGR 0x20
/* Baud Rate Generator Register */
38
#define US_RTOR 0x24
/* Receiver Time-out Register */
39
#define US_TTGR 0x28
/* Transmitter Timeguard Register */
40
#define US_C1R 0x40
/* Chip ID1 Register - FI DI Ratio Register */
41
#define US_C2R 0x44
/* Chip ID2 Register - Number of Erros Register */
42
#define US_FNTR 0x48
/* Force NTRST Register */
43
#define US_IF 0x4C
/* IrDA Filter Register */
44
45
/* Bit Defines */
46
/* Control Register, US_CR, Offset 0x00 */
47
#define US_CR_RSTRX BIT2
/* 1 = Reset and disable receiver */
48
#define US_CR_RSTTX BIT3
/* 1 = Reset and disable transmitter */
49
#define US_CR_RXEN BIT4
/* 1 = Receiver enable */
50
#define US_CR_RXDIS BIT5
/* 1 = Receiver disable */
51
#define US_CR_TXEN BIT6
/* 1 = Transmitter enable */
52
#define US_CR_TXDIS BIT7
/* 1 = Transmitter disable */
53
#define US_CR_RSTSTA BIT8
/* 1 = Reset PARE, FRAME and OVRE in DBGU_SR. */
54
#define US_CR_STTBRK BIT9
/* 1 = Start transmission of a Break */
55
#define US_CR_STPBRK BIT10
/* 1 = Stop transmission of a Break */
56
#define US_CR_STTTO BIT11
/* 1 = Start Time-out */
57
#define US_CR_SENDA BIT12
/* 1 = Send Address - MDROP mode only */
58
#define US_CR_RSTIT BIT13
/* 1 = Reset Iteration */
59
#define US_CR_RSTNACK BIT14
/* 1 = Reset Non Acknowledge */
60
#define US_CR_RETTO BIT15
/* 1 = Restart Time-out */
61
#define US_CR_DTREN BIT16
/* 1 = Data Terminal Ready Enable - AT91RM9200 only */
62
#define US_CR_DTRDIS BIT17
/* 1 = Data Terminal Ready Disable - AT91RM9200 only */
63
#define US_CR_RTSEN BIT18
/* 1 = Request To Send Enable */
64
#define US_CR_RTSDIS BIT19
/* 1 = Request To Send Disable */
65
66
67
/* Mode Register. US_MR. Offset 0x04 */
68
#define US_MR_USMODE (0xF << 0)
/* Mode of the USART */
69
#define US_MR_USMODE_NORMAL 0
70
#define US_MR_USMODE_RS485 1
71
#define US_MR_USMODE_HWHS 2
72
#define US_MR_USMODE_MODEM 3
73
#define US_MR_USMODE_ISO7816_T0 4
74
#define US_MR_USMODE_ISO7816_T1 6
75
#define US_MR_USMODE_IRDA 8
76
#define US_MR_USCLKS (3 << 4)
/* Clock Selection */
77
#define US_MR_USCLKS_MCK (0 << 4)
78
#define US_MR_USCLKS_MCK_DIV8 (1 << 4)
79
#define US_MR_USCLKS_SCK (3 << 4)
80
#define US_MR_CHRL (3 << 6)
/* Character Length */
81
#define US_MR_CHRL_5 (0 << 6)
82
#define US_MR_CHRL_6 (1 << 6)
83
#define US_MR_CHRL_7 (2 << 6)
84
#define US_MR_CHRL_8 (3 << 6)
85
#define US_MR_SYNC (1 << 8)
/* Synchronous Mode Select */
86
#define US_MR_PAR (7 << 9)
/* Parity Type */
87
#define US_MR_PAR_EVEN (0 << 9)
/* Even Parity */
88
#define US_MR_PAR_ODD (1 << 9)
/* Odd Parity */
89
#define US_MR_PAR_SPACE (2 << 9)
/* Parity forced to 0 (Space) */
90
#define US_MR_PAR_MARK (3 << 9)
/* Parity forced to 1 (Mark) */
91
#define US_MR_PAR_NONE (4 << 9)
/* No Parity */
92
#define US_MR_PAR_MDROP (6 << 9)
/* Multi-drop mode */
93
#define US_MR_NBSTOP (3 << 12)
/* Number of Stop Bits */
94
#define US_MR_NBSTOP_1 (0 << 12)
95
#define US_MR_NBSTOP_1_5 (1 << 12)
96
#define US_MR_NBSTOP_2 (2 << 12)
97
#define US_MR_CHMODE (3 << 14)
/* Channel Mode */
98
#define US_MR_CHMODE_NORM (0 << 14)
/* Normal Mode */
99
#define US_MR_CHMODE_AUTO (1 << 14)
/* Auto Echo: RXD drives TXD */
100
#define US_MR_CHMODE_LOC (2 << 14)
/* Local Loopback: TXD drives RXD */
101
#define US_MR_CHMODE_REM (3 << 14)
/* Remote Loopback: RXD pin connected to TXD pin. */
102
#define US_MR_MSBF (1 << 16)
/* Bit Order */
103
#define US_MR_MODE9 (1 << 17)
/* 9-bit Character Length */
104
#define US_MR_CLKO (1 << 18)
/* Clock Output Select */
105
#define US_MR_OVER (1 << 19)
/* Oversampling Mode */
106
#define US_MR_INACK (1 << 20)
/* Inhibit Non Acknowledge */
107
#define US_MR_DSNACK (1 << 21)
/* Disable Successive NACK */
108
#define US_MR_MAX_ITER (7 << 24)
/* Max Iterations */
109
#define US_MR_FILTER (1 << 28)
/* Infrared Receive Line Filter */
110
111
/* Interrupt Enable Register, US_IER, Offset 0x08 */
112
/* Interrupt Disable Register, US_IDR, Offset 0x0C */
113
/* Interrupt Mask Register, US_IMR, Offset 0x10 */
114
/* Channel Status Register, US_SR, Offset 0x14 */
115
#define US_IER_RXRDY BIT0
/* RXRDY Interrupt */
116
#define US_IER_TXRDY BIT1
/* TXRDY Interrupt */
117
#define US_IER_RXBRK BIT2
/* End of Receive Transfer Interrupt */
118
#define US_IER_ENDRX BIT3
/* End of Receiver Transfer */
119
//#define US_IER_ENDTX BIT4 /* End of Transmit Interrupt */
120
#define US_IER_OVRE BIT5
/* Overrun Interrupt */
121
#define US_IER_FRAME BIT6
/* Framing Error Interrupt */
122
#define US_IER_PARE BIT7
/* Parity Error */
123
#define US_IER_TIMEOUT BIT8
/* Receiver Time-out */
124
#define US_IER_TXEMPTY BIT9
/* Transmitter Empty */
125
#define US_IER_ITERATION BIT10
/* Max number of Repetitions Reached */
126
#define US_IER_TXBUFE BIT11
/* Transmission Buffer Empty */
127
#define US_IER_RXBUFF BIT12
/* Reception Buffer Full */
128
#define US_IER_NACK BIT13
/* Non Acknowledge */
129
#define US_IER_RIIC BIT16
/* Ring Indicator Input Change [AT91RM9200 only] */
130
#define US_IER_DSRIC BIT17
/* Data Set Ready Input Change [AT91RM9200 only] */
131
#define US_IER_DCDIC BIT18
/* Data Carrier Detect Input Change [AT91RM9200 only] */
132
#define US_IER_CTSIC BIT19
/* Clear to Send Input Change */
133
#define US_IER_ALL 0xC0001AFB
/* all assigned bits */
134
135
/* FORCE_NTRST Register, US_FNTR, Offset 0x48 */
136
#define US_FNTR_NTRST BIT0
/* 1 = Force NTRST low in JTAG */
137
138
typedef
struct
{
139
volatile
uint32_t cr;
140
volatile
uint32_t mr;
141
volatile
uint32_t ier;
142
volatile
uint32_t idr;
143
volatile
uint32_t imr;
144
volatile
uint32_t sr;
145
volatile
uint32_t rhr;
146
volatile
uint32_t thr;
147
volatile
uint32_t brgr;
148
volatile
uint32_t _res0[7];
149
volatile
uint32_t cidr;
150
volatile
uint32_t exid;
151
volatile
uint32_t fnr;
152
}
at91rm9200_usart_regs_t
;
153
154
#endif
/* __AT91RM9200_USART_H__ */
bits.h
Contains Defined Bits.
at91rm9200_usart_regs_t
Definition
at91rm9200_usart.h:138
Generated by
1.18.0
1.18.0