RTEMS  5.1
xilinx-axi-i2c.h
1 /*
2  * Copyright (c) 2016-2017 Chris Johns <chrisj@rtems.org> All rights reserved.
3  *
4  * The license and distribution terms for this file may be
5  * found in the file LICENSE in this distribution or at
6  * http://www.rtems.org/license/LICENSE.
7  */
8 
9 /*
10  * Xilinx AXI IIC Interface v2.0. See PG090.pdf.
11  *
12  * Note, only master support is provided and no dynamic mode by design.
13  *
14  * The clock set up is to be handled by the IP integrator. There are too many
15  * factors handling this in software.
16  */
17 
18 
19 #ifndef XILINX_AXI_I2C_H
20 #define XILINX_AXI_I2C_H
21 
22 #include <dev/i2c/i2c.h>
23 
24 /*
25  * The PL integrator controls the timing. This interface allows software to
26  * override those settings. It pays to check the timing with ChipScope.
27  *
28  * If you set the AXI bus frequency you can use the clock speed ioctl call to
29  * change the speed dymanically. The ioctl call overrides the defaults passed
30  * in.
31  *
32  * Set the valid mask to the values that are to be set.
33  */
34 #define XILINX_AIX_I2C_AXI_CLOCK (1 << 0)
35 #define XILINX_AIX_I2C_TSUSTA (1 << 1)
36 #define XILINX_AIX_I2C_TSUSTO (1 << 2)
37 #define XILINX_AIX_I2C_THDSTA (1 << 3)
38 #define XILINX_AIX_I2C_TSUDAT (1 << 4)
39 #define XILINX_AIX_I2C_TBUF (1 << 5)
40 #define XILINX_AIX_I2C_THIGH (1 << 6)
41 #define XILINX_AIX_I2C_TLOW (1 << 7)
42 #define XILINX_AIX_I2C_THDDAT (1 << 8)
43 #define XILINX_AIX_I2C_ALL_REGS (XILINX_AIX_I2C_TSUSTA | \
44  XILINX_AIX_I2C_TSUSTO | \
45  XILINX_AIX_I2C_THDSTA | \
46  XILINX_AIX_I2C_TSUDAT | \
47  XILINX_AIX_I2C_TBUF | \
48  XILINX_AIX_I2C_THIGH | \
49  XILINX_AIX_I2C_TLOW | \
50  XILINX_AIX_I2C_THDDAT)
51 typedef struct
52 {
53  uint32_t valid_mask;
54  uint32_t AXI_CLOCK;
55  uint32_t SCL_INERTIAL_DELAY;
56  uint32_t TSUSTA;
57  uint32_t TSUSTO;
58  uint32_t THDSTA;
59  uint32_t TSUDAT;
60  uint32_t TBUF;
61  uint32_t THIGH;
62  uint32_t TLOW;
63  uint32_t THDDAT;
65 
66 /*
67  * Register the driver.
68  *
69  * The driver can multipex a number of I2C buses (in master mode only) using
70  * the GPO port. The PL designer can use the output pins to select a bus. This
71  * is useful if connecting a number of slave devices that have limit selectable
72  * addresses.
73  *
74  * @param bus_path The driver's device path.
75  * @param register_base AXI base address.
76  * @param irq AXI FPGA interrupt.
77  * @param gpio_address Bits 12:15 of a slave address it written to the GPO.
78  * @param timing Override the default timing. NULL means no changes.
79  */
80 int i2c_bus_register_xilinx_aix_i2c(const char* bus_path,
81  uintptr_t register_base,
83  bool ten_gpio,
84  const xilinx_aix_i2c_timing* timing);
85 
86 #endif
ISR_Vector_number rtems_vector_number
Control block type used to manage the vectors.
Definition: intr.h:47
Definition: xilinx-axi-i2c.h:51
Inter-Integrated Circuit (I2C) Driver API.