78 #include <../../../../utils/utility.h> 91 #define XDMAC_CONTROLLER_NUM 1 93 #define XDMAC_CHANNEL_NUM 24 95 #define XDMAC_MAX_BT_SIZE 0xFFFF 101 #define XDMA_GET_DATASIZE(size) ((size==0)? XDMAC_CC_DWIDTH_BYTE : \ 102 ((size==1)? XDMAC_CC_DWIDTH_HALFWORD : \ 103 (XDMAC_CC_DWIDTH_WORD))) 104 #define XDMA_GET_CC_SAM(s) ((s==0)? XDMAC_CC_SAM_FIXED_AM : \ 105 ((s==1)? XDMAC_CC_SAM_INCREMENTED_AM : \ 106 ((s==2)? XDMAC_CC_SAM_UBS_AM : \ 107 XDMAC_CC_SAM_UBS_DS_AM))) 108 #define XDMA_GET_CC_DAM(d) ((d==0)? XDMAC_CC_DAM_FIXED_AM : \ 109 ((d==1)? XDMAC_CC_DAM_INCREMENTED_AM : \ 110 ((d==2)? XDMAC_CC_DAM_UBS_AM : \ 111 XDMAC_CC_DAM_UBS_DS_AM))) 112 #define XDMA_GET_CC_MEMSET(m) ((m==0)? XDMAC_CC_MEMSET_NORMAL_MODE : \ 113 XDMAC_CC_MEMSET_HW_MODE) 131 static inline uint32_t XDMAC_GetType(
Xdmac *pXdmac)
142 static inline uint32_t XDMAC_GetConfig(
Xdmac *pXdmac)
153 static inline uint32_t XDMAC_GetArbiter(
Xdmac *pXdmac)
165 static inline void XDMAC_EnableGIt (
Xdmac *pXdmac, uint8_t dwInteruptMask)
177 static inline void XDMAC_DisableGIt (
Xdmac *pXdmac, uint8_t dwInteruptMask)
188 static inline uint32_t XDMAC_GetGItMask(
Xdmac *pXdmac)
199 static inline uint32_t XDMAC_GetGIsr(
Xdmac *pXdmac)
210 static inline uint32_t XDMAC_GetMaskedGIsr(
Xdmac *pXdmac)
225 static inline void XDMAC_EnableChannel(
Xdmac *pXdmac, uint8_t channel)
238 static inline void XDMAC_EnableChannels(
Xdmac *pXdmac, uint32_t bmChannels)
250 static inline void XDMAC_DisableChannel(
Xdmac *pXdmac, uint8_t channel)
263 static inline void XDMAC_DisableChannels(
Xdmac *pXdmac, uint32_t bmChannels)
277 static inline uint32_t XDMAC_GetGlobalChStatus(
Xdmac *pXdmac)
289 static inline void XDMAC_SuspendReadChannel(
Xdmac *pXdmac, uint8_t channel)
302 static inline void XDMAC_SuspendWriteChannel(
Xdmac *pXdmac, uint8_t channel)
315 static inline void XDMAC_SuspendReadWriteChannel(
Xdmac *pXdmac, uint8_t channel)
328 static inline void XDMAC_ResumeReadWriteChannel(
Xdmac *pXdmac, uint8_t channel)
341 static inline void XDMAC_SoftwareTransferReq(
Xdmac *pXdmac, uint8_t channel)
354 static inline uint32_t XDMAC_GetSoftwareTransferStatus(
Xdmac *pXdmac)
367 static inline uint32_t XDMAC_GetChannelIsr (
Xdmac *pXdmac, uint8_t channel)
381 static inline void XDMAC_SoftwareFlushReq(
Xdmac *pXdmac, uint8_t channel)
387 while (!(XDMAC_GetChannelIsr(pXdmac, channel) &
XDMAC_CIS_FIS));
397 static inline void XDMAC_EnableChannelIt (
Xdmac *pXdmac, uint8_t channel,
398 uint8_t dwInteruptMask)
412 static inline void XDMAC_DisableChannelIt (
Xdmac *pXdmac, uint8_t channel,
413 uint8_t dwInteruptMask)
426 static inline uint32_t XDMAC_GetChannelItMask (
Xdmac *pXdmac, uint8_t channel)
439 static inline uint32_t XDMAC_GetMaskChannelIsr (
Xdmac *pXdmac, uint8_t channel)
457 static inline void XDMAC_SetSourceAddr(
Xdmac *pXdmac, uint8_t channel, uint32_t addr)
471 static inline void XDMAC_SetDestinationAddr(
Xdmac *pXdmac, uint8_t channel, uint32_t addr)
487 static inline void XDMAC_SetDescriptorAddr(
Xdmac *pXdmac, uint8_t channel,
488 uint32_t addr, uint8_t ndaif)
504 static inline void XDMAC_SetDescriptorControl(
Xdmac *pXdmac, uint8_t channel, uint8_t
config)
518 static inline void XDMAC_SetMicroblockControl(
Xdmac *pXdmac, uint8_t channel, uint32_t ublen)
532 static inline void XDMAC_SetBlockControl(
Xdmac *pXdmac, uint8_t channel, uint16_t blen)
546 static inline void XDMAC_SetChannelConfig(
Xdmac *pXdmac, uint8_t channel, uint32_t
config)
559 static inline uint32_t XDMAC_GetChannelConfig(
Xdmac *pXdmac, uint8_t channel)
573 static inline void XDMAC_SetDataStride_MemPattern(
Xdmac *pXdmac, uint8_t channel,
589 static inline void XDMAC_SetSourceMicroBlockStride(
Xdmac *pXdmac, uint8_t channel,
604 static inline void XDMAC_SetDestinationMicroBlockStride(
Xdmac *pXdmac, uint8_t channel,
618 static inline uint32_t XDMAC_GetChDestinationAddr(
Xdmac *pXdmac, uint8_t channel)
625 static inline void XDMAC_StartTransfer(
Xdmac *pXdmac, uint8_t channel)
639 #endif //#ifndef DMAC_H __O uint32_t XDMAC_CIE
(XdmacChid Offset: 0x0) Channel Interrupt Enable Register
Definition: component_xdmac.h:42
#define XDMAC_GSWR_SWREQ0
(XDMAC_GSWR) XDMAC Channel 0 Software Request Bit
Definition: component_xdmac.h:387
Definition: deflate.c:115
#define XDMAC_GWS_WS0
(XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit
Definition: component_xdmac.h:312
__IO uint32_t XDMAC_CNDC
(XdmacChid Offset: 0x1C) Channel Next Descriptor Control Register
Definition: component_xdmac.h:49
__I uint32_t XDMAC_CIS
(XdmacChid Offset: 0xC) Channel Interrupt Status Register
Definition: component_xdmac.h:45
#define XDMAC_GID_ID0
(XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit
Definition: component_xdmac.h:137
__O uint32_t XDMAC_CID
(XdmacChid Offset: 0x4) Channel Interrupt Disable Register
Definition: component_xdmac.h:43
__IO uint32_t XDMAC_CDS_MSP
(XdmacChid Offset: 0x2C) Channel Data Stride Memory Set Pattern
Definition: component_xdmac.h:53
__O uint32_t XDMAC_GSWF
(Xdmac Offset: 0x40) Global Channel Software Flush Request Register
Definition: component_xdmac.h:77
#define XDMAC_GSWF_SWF0
(XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit
Definition: component_xdmac.h:437
__IO uint32_t XDMAC_GWAC
(Xdmac Offset: 0x08) Global Weighted Arbiter Configuration Register
Definition: component_xdmac.h:63
__IO uint32_t XDMAC_GTYPE
(Xdmac Offset: 0x00) Global Type Register
Definition: component_xdmac.h:61
#define XDMAC_GRWR_RWR0
(XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit
Definition: component_xdmac.h:362
XdmacChid XDMAC_CHID[XDMACCHID_NUMBER]
(Xdmac Offset: 0x50) chid = 0 .. 23
Definition: component_xdmac.h:79
__IO uint32_t XDMAC_GRS
(Xdmac Offset: 0x28) Global Channel Read Suspend Register
Definition: component_xdmac.h:71
#define XDMAC_GRWS_RWS0
(XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit
Definition: component_xdmac.h:337
#define XDMAC_GIE_IE0
(XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit
Definition: component_xdmac.h:112
__O uint32_t XDMAC_GRWS
(Xdmac Offset: 0x30) Global Channel Read Write Suspend Register
Definition: component_xdmac.h:73
__O uint32_t XDMAC_GSWR
(Xdmac Offset: 0x38) Global Channel Software Request Register
Definition: component_xdmac.h:75
__I uint32_t XDMAC_GIM
(Xdmac Offset: 0x14) Global Interrupt Mask Register
Definition: component_xdmac.h:66
__O uint32_t XDMAC_GID
(Xdmac Offset: 0x10) Global Interrupt Disable Register
Definition: component_xdmac.h:65
#define XDMAC_CHANNEL_NUM
Definition: xdmac.h:93
__O uint32_t XDMAC_GD
(Xdmac Offset: 0x20) Global Channel Disable Register
Definition: component_xdmac.h:69
Information for the Assert Handler.
__IO uint32_t XDMAC_CUBC
(XdmacChid Offset: 0x20) Channel Microblock Control Register
Definition: component_xdmac.h:50
#define XDMAC_GD_DI0
(XDMAC_GD) XDMAC Channel 0 Disable Bit
Definition: component_xdmac.h:237
__I uint32_t XDMAC_GSWS
(Xdmac Offset: 0x3C) Global Channel Software Request Status Register
Definition: component_xdmac.h:76
__IO uint32_t XDMAC_CDA
(XdmacChid Offset: 0x14) Channel Destination Address Register
Definition: component_xdmac.h:47
__IO uint32_t XDMAC_CSA
(XdmacChid Offset: 0x10) Channel Source Address Register
Definition: component_xdmac.h:46
__IO uint32_t XDMAC_GWS
(Xdmac Offset: 0x2C) Global Channel Write Suspend Register
Definition: component_xdmac.h:72
#define XDMAC_GRS_RS0
(XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit
Definition: component_xdmac.h:287
__I uint32_t XDMAC_GS
(Xdmac Offset: 0x24) Global Channel Status Register
Definition: component_xdmac.h:70
__O uint32_t XDMAC_GE
(Xdmac Offset: 0x1C) Global Channel Enable Register
Definition: component_xdmac.h:68
__IO uint32_t XDMAC_CSUS
(XdmacChid Offset: 0x30) Channel Source Microblock Stride
Definition: component_xdmac.h:54
__O uint32_t XDMAC_GIE
(Xdmac Offset: 0x0C) Global Interrupt Enable Register
Definition: component_xdmac.h:64
Definition: component_xdmac.h:60
__IO uint32_t XDMAC_CC
(XdmacChid Offset: 0x28) Channel Configuration Register
Definition: component_xdmac.h:52
__IO uint32_t XDMAC_CBC
(XdmacChid Offset: 0x24) Channel Block Control Register
Definition: component_xdmac.h:51
__I uint32_t XDMAC_GIS
(Xdmac Offset: 0x18) Global Interrupt Status Register
Definition: component_xdmac.h:67
__IO uint32_t XDMAC_CDUS
(XdmacChid Offset: 0x34) Channel Destination Microblock Stride
Definition: component_xdmac.h:55
#define XDMAC_CIS_FIS
(XDMAC_CIS) End of Flush Interrupt Status Bit
Definition: component_xdmac.h:489
#define XDMAC_GE_EN0
(XDMAC_GE) XDMAC Channel 0 Enable Bit
Definition: component_xdmac.h:212
__O uint32_t XDMAC_GRWR
(Xdmac Offset: 0x34) Global Channel Read Write Resume Register
Definition: component_xdmac.h:74
__I uint32_t XDMAC_GCFG
(Xdmac Offset: 0x04) Global Configuration Register
Definition: component_xdmac.h:62
__O uint32_t XDMAC_CIM
(XdmacChid Offset: 0x8) Channel Interrupt Mask Register
Definition: component_xdmac.h:44
__IO uint32_t XDMAC_CNDA
(XdmacChid Offset: 0x18) Channel Next Descriptor Address Register
Definition: component_xdmac.h:48
#define _Assert(_e)
Assertion similar to assert() controlled via RTEMS_DEBUG instead of NDEBUG.
Definition: assert.h:100