|
|
| LPC32XX_RESERVE (0x034, 0x040) |
| |
|
| LPC32XX_RESERVE (0x05c, 0x060) |
| |
|
| LPC32XX_RESERVE (0x07c, 0x110) |
| |
|
| LPC32XX_RESERVE (0x11c, 0x120) |
| |
|
| LPC32XX_RESERVE (0x12c, 0x130) |
| |
|
|
uint32_t | p3_inp_state |
| |
|
uint32_t | p3_outp_set |
| |
|
uint32_t | p3_outp_clr |
| |
|
uint32_t | p3_outp_state |
| |
|
uint32_t | p2_dir_set |
| |
|
uint32_t | p2_dir_clr |
| |
|
uint32_t | p2_dir_state |
| |
|
uint32_t | p2_inp_state |
| |
|
uint32_t | p2_outp_set |
| |
|
uint32_t | p2_outp_clr |
| |
|
uint32_t | p2_mux_set |
| |
|
uint32_t | p2_mux_clr |
| |
|
uint32_t | p2_mux_state |
| |
|
uint32_t | p0_inp_state |
| |
|
uint32_t | p0_outp_set |
| |
|
uint32_t | p0_outp_clr |
| |
|
uint32_t | p0_outp_state |
| |
|
uint32_t | p0_dir_set |
| |
|
uint32_t | p0_dir_clr |
| |
|
uint32_t | p0_dir_state |
| |
|
uint32_t | p1_inp_state |
| |
|
uint32_t | p1_outp_set |
| |
|
uint32_t | p1_outp_clr |
| |
|
uint32_t | p1_outp_state |
| |
|
uint32_t | p1_dir_set |
| |
|
uint32_t | p1_dir_clr |
| |
|
uint32_t | p1_dir_state |
| |
|
uint32_t | p3_mux_set |
| |
|
uint32_t | p3_mux_clr |
| |
|
uint32_t | p3_mux_state |
| |
|
uint32_t | p0_mux_set |
| |
|
uint32_t | p0_mux_clr |
| |
|
uint32_t | p0_mux_state |
| |
|
uint32_t | p1_mux_set |
| |
|
uint32_t | p1_mux_clr |
| |
|
uint32_t | p1_mux_state |
| |
The documentation for this struct was generated from the following file:
1.8.15