Register definitions. More...

Files
file	lpc32xx.h
	Register base addresses.

Data Structures
struct	lpc32xx_nand_slc

struct	lpc32xx_ssp

struct	lpc32xx_spi

struct	lpc32xx_sd_card

struct	lpc32xx_usb

struct	lpc32xx_lcd

struct	lpc32xx_etb

struct	lpc32xx_syscon

struct	lpc32xx_uart_ctrl

struct	lpc32xx_uart

struct	lpc32xx_ms_timer

struct	lpc32xx_hs_timer

struct	lpc32xx_wdt

struct	lpc32xx_debug

struct	lpc32xx_adc

struct	lpc32xx_keyscan

struct	lpc32xx_pwm

struct	lpc32xx_mcpwm

struct	lpc32xx_eth

struct	lpc32xx_irq

struct	lpc32xx_gpio

struct	lpc32xx_i2c

struct	lpc32xx_rtc

struct	lpc32xx_emc_ahb

struct	lpc32xx_nand_mlc

struct	lpc32xx_registers

Macros
#define	LPC32XX_FILL(a, b, s) uint8_t reserved_ ## b [b - a - sizeof(s)]

#define	LPC32XX_RESERVE(a, b) uint8_t reserved_ ## b [b - a]

Variables
volatile lpc32xx_registers	lpc32xx

Register Base Addresses
#define	LPC32XX_BASE_ADC 0x40048000

#define	LPC32XX_BASE_SYSCON 0x40004000

#define	LPC32XX_BASE_DEBUG_CTRL 0x40040000

#define	LPC32XX_BASE_DMA 0x31000000

#define	LPC32XX_BASE_EMC 0x31080000

#define	LPC32XX_BASE_EMC_CS_0 0xe0000000

#define	LPC32XX_BASE_EMC_CS_1 0xe1000000

#define	LPC32XX_BASE_EMC_CS_2 0xe2000000

#define	LPC32XX_BASE_EMC_CS_3 0xe3000000

#define	LPC32XX_BASE_EMC_DYCS_0 0x80000000

#define	LPC32XX_BASE_EMC_DYCS_1 0xa0000000

#define	LPC32XX_BASE_ETB_CFG 0x310c0000

#define	LPC32XX_BASE_ETB_DATA 0x310e0000

#define	LPC32XX_BASE_ETHERNET 0x31060000

#define	LPC32XX_BASE_GPIO 0x40028000

#define	LPC32XX_BASE_I2C_1 0x400a0000

#define	LPC32XX_BASE_I2C_2 0x400a8000

#define	LPC32XX_BASE_I2S_0 0x20094000

#define	LPC32XX_BASE_I2S_1 0x2009c000

#define	LPC32XX_BASE_IRAM 0x08000000

#define	LPC32XX_BASE_IROM 0x0c000000

#define	LPC32XX_BASE_KEYSCAN 0x40050000

#define	LPC32XX_BASE_LCD 0x31040000

#define	LPC32XX_BASE_MCPWM 0x400e8000

#define	LPC32XX_BASE_MIC 0x40008000

#define	LPC32XX_BASE_NAND_MLC 0x200a8000

#define	LPC32XX_BASE_NAND_SLC 0x20020000

#define	LPC32XX_BASE_PWM_1 0x4005c000

#define	LPC32XX_BASE_PWM_2 0x4005c004

#define	LPC32XX_BASE_PWM_3 0x4002c000

#define	LPC32XX_BASE_PWM_4 0x40030000

#define	LPC32XX_BASE_RTC 0x40024000

#define	LPC32XX_BASE_RTC_RAM 0x40024080

#define	LPC32XX_BASE_SDCARD 0x20098000

#define	LPC32XX_BASE_SIC_1 0x4000c000

#define	LPC32XX_BASE_SIC_2 0x40010000

#define	LPC32XX_BASE_SPI_1 0x20088000

#define	LPC32XX_BASE_SPI_2 0x20090000

#define	LPC32XX_BASE_SSP_0 0x20084000

#define	LPC32XX_BASE_SSP_1 0x2008c000

#define	LPC32XX_BASE_TIMER_0 0x40044000

#define	LPC32XX_BASE_TIMER_1 0x4004c000

#define	LPC32XX_BASE_TIMER_2 0x40058000

#define	LPC32XX_BASE_TIMER_3 0x40060000

#define	LPC32XX_BASE_TIMER_5 0x4002c000

#define	LPC32XX_BASE_TIMER_6 0x40030000

#define	LPC32XX_BASE_TIMER_HS 0x40038000

#define	LPC32XX_BASE_TIMER_MS 0x40034000

#define	LPC32XX_BASE_UART_1 0x40014000

#define	LPC32XX_BASE_UART_2 0x40018000

#define	LPC32XX_BASE_UART_3 0x40080000

#define	LPC32XX_BASE_UART_4 0x40088000

#define	LPC32XX_BASE_UART_5 0x40090000

#define	LPC32XX_BASE_UART_6 0x40098000

#define	LPC32XX_BASE_UART_7 0x4001c000

#define	LPC32XX_BASE_USB 0x31020000

#define	LPC32XX_BASE_USB_OTG_I2C 0x31020300

#define	LPC32XX_BASE_WDT 0x4003c000

Miscanellanous Registers
#define	LPC32XX_U3CLK ((volatile uint32_t ) 0x400040d0)

#define	LPC32XX_U4CLK ((volatile uint32_t ) 0x400040d4)

#define	LPC32XX_U5CLK ((volatile uint32_t ) 0x400040d8)

#define	LPC32XX_U6CLK ((volatile uint32_t ) 0x400040dc)

#define	LPC32XX_IRDACLK ((volatile uint32_t ) 0x400040e0)

#define	LPC32XX_UART_CTRL ((volatile uint32_t ) 0x40054000)

#define	LPC32XX_UART_CLKMODE ((volatile uint32_t ) 0x40054004)

#define	LPC32XX_UART_LOOP ((volatile uint32_t ) 0x40054008)

#define	LPC32XX_SW_INT ((volatile uint32_t ) 0x400040a8)

#define	LPC32XX_MAC_CLK_CTRL ((volatile uint32_t ) 0x40004090)

#define	LPC32XX_USB_DIV ((volatile uint32_t ) 0x4000401c)

#define	LPC32XX_OTG_CLK_CTRL ((volatile uint32_t ) 0x31020ff4)

#define	LPC32XX_OTG_CLK_STAT ((volatile uint32_t ) 0x31020ff8)

#define	LPC32XX_OTG_STAT_CTRL ((volatile uint32_t ) 0x31020110)

#define	LPC32XX_I2C_RX ((volatile uint32_t ) 0x31020300)

#define	LPC32XX_I2C_TX ((volatile uint32_t ) 0x31020300)

#define	LPC32XX_I2C_STS ((volatile uint32_t ) 0x31020304)

#define	LPC32XX_I2C_CTL ((volatile uint32_t ) 0x31020308)

#define	LPC32XX_I2C_CLKHI ((volatile uint32_t ) 0x3102030c)

#define	LPC32XX_I2C_CLKLO ((volatile uint32_t ) 0x31020310)

#define	LPC32XX_PWR_CTRL ((volatile uint32_t ) 0x40004044)

#define	LPC32XX_OSC_CTRL ((volatile uint32_t ) 0x4000404c)

#define	LPC32XX_SYSCLK_CTRL ((volatile uint32_t ) 0x40004050)

#define	LPC32XX_PLL397_CTRL ((volatile uint32_t ) 0x40004048)

#define	LPC32XX_HCLKPLL_CTRL ((volatile uint32_t ) 0x40004058)

#define	LPC32XX_HCLKDIV_CTRL ((volatile uint32_t ) 0x40004040)

#define	LPC32XX_TEST_CLK ((volatile uint32_t ) 0x400040a4)

#define	LPC32XX_AUTOCLK_CTRL ((volatile uint32_t ) 0x400040ec)

#define	LPC32XX_START_ER_PIN ((volatile uint32_t ) 0x40004030)

#define	LPC32XX_START_ER_INT ((volatile uint32_t ) 0x40004020)

#define	LPC32XX_P0_INTR_ER ((volatile uint32_t ) 0x40004018)

#define	LPC32XX_START_SR_PIN ((volatile uint32_t ) 0x40004038)

#define	LPC32XX_START_SR_INT ((volatile uint32_t ) 0x40004028)

#define	LPC32XX_START_RSR_PIN ((volatile uint32_t ) 0x40004034)

#define	LPC32XX_START_RSR_INT ((volatile uint32_t ) 0x40004024)

#define	LPC32XX_START_APR_PIN ((volatile uint32_t ) 0x4000403c)

#define	LPC32XX_START_APR_INT ((volatile uint32_t ) 0x4000402c)

#define	LPC32XX_USB_CTRL ((volatile uint32_t ) 0x40004064)

#define	LPC32XX_USBDIV_CTRL ((volatile uint32_t ) 0x4000401c)

#define	LPC32XX_MS_CTRL ((volatile uint32_t ) 0x40004080)

#define	LPC32XX_DMACLK_CTRL ((volatile uint32_t ) 0x400040e8)

#define	LPC32XX_FLASHCLK_CTRL ((volatile uint32_t ) 0x400040c8)

#define	LPC32XX_MACCLK_CTRL ((volatile uint32_t ) 0x40004090)

#define	LPC32XX_LCDCLK_CTRL ((volatile uint32_t ) 0x40004054)

#define	LPC32XX_I2S_CTRL ((volatile uint32_t ) 0x4000407c)

#define	LPC32XX_SSP_CTRL ((volatile uint32_t ) 0x40004078)

#define	LPC32XX_SPI_CTRL ((volatile uint32_t ) 0x400040c4)

#define	LPC32XX_I2CCLK_CTRL ((volatile uint32_t ) 0x400040ac)

#define	LPC32XX_TIMCLK_CTRL1 ((volatile uint32_t ) 0x400040c0)

#define	LPC32XX_TIMCLK_CTRL ((volatile uint32_t ) 0x400040bc)

#define	LPC32XX_ADCLK_CTRL ((volatile uint32_t ) 0x400040b4)

#define	LPC32XX_ADCLK_CTRL1 ((volatile uint32_t ) 0x40004060)

#define	LPC32XX_KEYCLK_CTRL ((volatile uint32_t ) 0x400040b0)

#define	LPC32XX_PWMCLK_CTRL ((volatile uint32_t ) 0x400040b8)

#define	LPC32XX_UARTCLK_CTRL ((volatile uint32_t ) 0x400040e4)

#define	LPC32XX_POS0_IRAM_CTRL ((volatile uint32_t ) 0x40004110)

#define	LPC32XX_POS1_IRAM_CTRL ((volatile uint32_t ) 0x40004114)

#define	LPC32XX_SDRAMCLK_CTRL ((volatile uint32_t ) 0x40004068)

Power Control Register (PWR_CTRL)
#define	PWR_STOP BSP_BIT32(0)

#define	PWR_HIGHCORE_ALWAYS BSP_BIT32(1)

#define	PWR_NORMAL_RUN_MODE BSP_BIT32(2)

#define	PWR_SYSCLKEN_ALWAYS BSP_BIT32(3)

#define	PWR_SYSCLKEN_HIGH BSP_BIT32(4)

#define	PWR_HIGHCORE_HIGH BSP_BIT32(5)

#define	PWR_SDRAM_AUTO_REFRESH BSP_BIT32(7)

#define	PWR_UPDATE_EMCSREFREQ BSP_BIT32(8)

#define	PWR_EMCSREFREQ BSP_BIT32(9)

#define	PWR_HCLK_USES_PERIPH_CLK BSP_BIT32(10)

HCLK PLL Control Register (HCLKPLL_CTRL)
#define	HCLK_PLL_LOCK BSP_BIT32(0)

#define	HCLK_PLL_M(val) BSP_FLD32(val, 1, 8)

#define	HCLK_PLL_M_GET(reg) BSP_FLD32GET(reg, 1, 8)

#define	HCLK_PLL_N(val) BSP_FLD32(val, 9, 10)

#define	HCLK_PLL_N_GET(reg) BSP_FLD32GET(reg, 9, 10)

#define	HCLK_PLL_P(val) BSP_FLD32(val, 11, 12)

#define	HCLK_PLL_P_GET(reg) BSP_FLD32GET(reg, 11, 12)

#define	HCLK_PLL_FBD_FCLKOUT BSP_BIT32(13)

#define	HCLK_PLL_DIRECT BSP_BIT32(14)

#define	HCLK_PLL_BYPASS BSP_BIT32(15)

#define	HCLK_PLL_POWER BSP_BIT32(16)

HCLK Divider Control Register (HCLKDIV_CTRL)
#define	HCLK_DIV_HCLK(val) BSP_FLD32(val, 0, 1)

#define	HCLK_DIV_HCLK_GET(reg) BSP_FLD32GET(reg, 0, 1)

#define	HCLK_DIV_PERIPH_CLK(val) BSP_FLD32(val, 2, 6)

#define	HCLK_DIV_PERIPH_CLK_GET(reg) BSP_FLD32GET(reg, 2, 6)

#define	HCLK_DIV_DDRAM_CLK(val) BSP_FLD32(val, 7, 8)

#define	HCLK_DIV_DDRAM_CLK_GET(reg) BSP_FLD32GET(reg, 7, 8)

Timer Clock Control Register (TIMCLK_CTRL)
#define	TIMCLK_CTRL_WDT BSP_BIT32(0)

#define	TIMCLK_CTRL_HST BSP_BIT32(1)

Watchdog Timer Interrupt Status Register (WDTIM_INT)
#define	WDTTIM_INT_MATCH_INT BSP_BIT32(0)

Watchdog Timer Control Register (WDTIM_CTRL)
#define	WDTTIM_CTRL_COUNT_ENAB BSP_BIT32(0)

#define	WDTTIM_CTRL_RESET_COUNT BSP_BIT32(1)

#define	WDTTIM_CTRL_PAUSE_EN BSP_BIT32(2)

Watchdog Timer Match Control Register (WDTIM_MCTRL)
#define	WDTTIM_MCTRL_MR0_INT BSP_BIT32(0)

#define	WDTTIM_MCTRL_RESET_COUNT0 BSP_BIT32(1)

#define	WDTTIM_MCTRL_STOP_COUNT0 BSP_BIT32(2)

#define	WDTTIM_MCTRL_M_RES1 BSP_BIT32(3)

#define	WDTTIM_MCTRL_M_RES2 BSP_BIT32(4)

#define	WDTTIM_MCTRL_RESFRC1 BSP_BIT32(5)

#define	WDTTIM_MCTRL_RESFRC2 BSP_BIT32(6)

Watchdog Timer External Match Control Register (WDTIM_EMR)
#define	WDTTIM_EMR_EXT_MATCH0 BSP_BIT32(0)

#define	WDTTIM_EMR_MATCH_CTRL(val) BSP_FLD32(val, 4, 5)

#define	WDTTIM_EMR_MATCH_CTRL_SET(reg, val) BSP_FLD32SET(reg, val, 4, 5)

Watchdog Timer Reset Source Register (WDTIM_RES)
#define	WDTTIM_RES_WDT BSP_BIT32(0)

Detailed Description

Register definitions.

Files

Data Structures

Macros

Variables

Register Base Addresses

Miscanellanous Registers

Power Control Register (PWR_CTRL)

HCLK PLL Control Register (HCLKPLL_CTRL)

HCLK Divider Control Register (HCLKDIV_CTRL)

Timer Clock Control Register (TIMCLK_CTRL)

Watchdog Timer Interrupt Status Register (WDTIM_INT)

Watchdog Timer Control Register (WDTIM_CTRL)

Watchdog Timer Match Control Register (WDTIM_MCTRL)

Watchdog Timer External Match Control Register (WDTIM_EMR)

Watchdog Timer Reset Source Register (WDTIM_RES)

Detailed Description