Twihs hardware registers. More...

Data Fields
__O uint32_t	TWIHS_CR
	(Twihs Offset: 0x00) Control Register

__IO uint32_t	TWIHS_MMR
	(Twihs Offset: 0x04) Master Mode Register

__IO uint32_t	TWIHS_SMR
	(Twihs Offset: 0x08) Slave Mode Register

__IO uint32_t	TWIHS_IADR
	(Twihs Offset: 0x0C) Internal Address Register

__IO uint32_t	TWIHS_CWGR
	(Twihs Offset: 0x10) Clock Waveform Generator Register

__I uint32_t	Reserved1 [3]

__I uint32_t	TWIHS_SR
	(Twihs Offset: 0x20) Status Register

__O uint32_t	TWIHS_IER
	(Twihs Offset: 0x24) Interrupt Enable Register

__O uint32_t	TWIHS_IDR
	(Twihs Offset: 0x28) Interrupt Disable Register

__I uint32_t	TWIHS_IMR
	(Twihs Offset: 0x2C) Interrupt Mask Register

__I uint32_t	TWIHS_RHR
	(Twihs Offset: 0x30) Receive Holding Register

__O uint32_t	TWIHS_THR
	(Twihs Offset: 0x34) Transmit Holding Register

__IO uint32_t	TWIHS_SMBTR
	(Twihs Offset: 0x38) SMBus Timing Register

__I uint32_t	Reserved2 [2]

__IO uint32_t	TWIHS_FILTR
	(Twihs Offset: 0x44) Filter Register

__I uint32_t	Reserved3 [1]

__IO uint32_t	TWIHS_SWMR
	(Twihs Offset: 0x4C) SleepWalking Matching Register

__I uint32_t	Reserved4 [37]

__IO uint32_t	TWIHS_WPMR
	(Twihs Offset: 0xE4) Write Protection Mode Register

__I uint32_t	TWIHS_WPSR
	(Twihs Offset: 0xE8) Write Protection Status Register

__I uint32_t	TWIHS_DR
	(Twihs Offset: 0xD0) Debug Register

__I uint32_t	Reserved5 [4]

__I uint32_t	Reserved6 [4]

__I uint32_t	TWIHS_VER
	(Twihs Offset: 0xFC) Version Register

Detailed Description

Twihs hardware registers.

The documentation for this struct was generated from the following file:

Data Fields