RTEMS  5.1
smc91111.h
1 #ifndef _SMC91111_H_
2 #define _SMC91111_H_
3 
4 #include <libchip/smc91111exp.h>
5 #include <rtems/bspIo.h>
6 
7 #define LAN91CXX_TCR 0x00
8 #define LAN91CXX_EPH_STATUS 0x01
9 #define LAN91CXX_RCR 0x02
10 #define LAN91CXX_COUNTER 0x03
11 #define LAN91CXX_MIR 0x04
12 #define LAN91CXX_MCR 0x05 /* Other than 91C111*/
13 #define LAN91CXX_RPCR 0x05 /* 91C111 only*/
14 #define LAN91CXX_RESERVED_0 0x06
15 #define LAN91CXX_BS 0x07
16 #define LAN91CXX_CONFIG 0x08
17 #define LAN91CXX_BASE_REG 0x09
18 #define LAN91CXX_IA01 0x0a
19 #define LAN91CXX_IA23 0x0b
20 #define LAN91CXX_IA45 0x0c
21 #define LAN91CXX_GENERAL 0x0d /* 91C96 - was "RESERVED_1" for others*/
22 #define LAN91CXX_CONTROL 0x0e
23 #define LAN91CXX_BS2 0x0f
24 #define LAN91CXX_MMU_COMMAND 0x10
25 #define LAN91CXX_PNR 0x11
26 #define LAN91CXX_FIFO_PORTS 0x12
27 #define LAN91CXX_POINTER 0x13
28 #define LAN91CXX_DATA_HIGH 0x14
29 #define LAN91CXX_DATA 0x15
30 #define LAN91CXX_INTERRUPT 0x16
31 #define LAN91CXX_BS3 0x17
32 #define LAN91CXX_MT01 0x18
33 #define LAN91CXX_MT23 0x19
34 #define LAN91CXX_MT45 0x1a
35 #define LAN91CXX_MT67 0x1b
36 #define LAN91CXX_MGMT 0x1c
37 #define LAN91CXX_REVISION 0x1d
38 #define LAN91CXX_ERCV 0x1e
39 #define LAN91CXX_BS4 0x1f
40 
41 #define LAN91CXX_RCR_SOFT_RST 0x8000 /* soft reset*/
42 #define LAN91CXX_RCR_FILT_CAR 0x4000 /* filter carrier*/
43 #define LAN91CXX_RCR_ABORT_ENB 0x2000 /* abort on collision*/
44 #define LAN91CXX_RCR_STRIP_CRC 0x0200 /* strip CRC*/
45 #define LAN91CXX_RCR_RXEN 0x0100 /* enable RX*/
46 #define LAN91CXX_RCR_ALMUL 0x0004 /* receive all muticasts*/
47 #define LAN91CXX_RCR_PRMS 0x0002 /* promiscuous*/
48 #define LAN91CXX_RCR_RX_ABORT 0x0001 /* set when abort due to long frame*/
49 
50 #define LAN91CXX_TCR_SWFDUP 0x8000 /* Switched Full Duplex mode*/
51 #define LAN91CXX_TCR_ETEN_TYPE 0x4000 /* ETEN type (91C96) 0 <=> like a 91C94*/
52 #define LAN91CXX_TCR_EPH_LOOP 0x2000 /* loopback mode*/
53 #define LAN91CXX_TCR_STP_SQET 0x1000 /* Stop transmission on SQET error*/
54 #define LAN91CXX_TCR_FDUPLX 0x0800 /* full duplex*/
55 #define LAN91CXX_TCR_MON_CSN 0x0400 /* monitor carrier during tx (91C96)*/
56 #define LAN91CXX_TCR_NOCRC 0x0100 /* does not append CRC to frames*/
57 #define LAN91CXX_TCR_PAD_EN 0x0080 /* pads frames with 00 to min length*/
58 #define LAN91CXX_TCR_FORCOL 0x0004 /* force collision*/
59 #define LAN91CXX_TCR_LLOOP 0x0002 /* local loopback (91C96)*/
60 #define LAN91CXX_TCR_TXENA 0x0001 /* enable*/
61 
62 #define LAN91CXX_POINTER_RCV 0x8000
63 #define LAN91CXX_POINTER_AUTO_INCR 0x4000
64 #define LAN91CXX_POINTER_READ 0x2000
65 #define LAN91CXX_POINTER_ETEN 0x1000
66 #define LAN91CXX_POINTER_NOT_EMPTY 0x0800
67 
68 
69 #define LAN91CXX_INTERRUPT_TX_IDLE_M 0x8000 /* (91C96)*/
70 #define LAN91CXX_INTERRUPT_ERCV_INT_M 0x4000
71 #define LAN91CXX_INTERRUPT_EPH_INT_M 0x2000
72 #define LAN91CXX_INTERRUPT_RX_OVRN_INT_M 0x1000
73 #define LAN91CXX_INTERRUPT_ALLOC_INT_M 0x0800
74 #define LAN91CXX_INTERRUPT_TX_EMPTY_INT_M 0x0400
75 #define LAN91CXX_INTERRUPT_TX_INT_M 0x0200
76 #define LAN91CXX_INTERRUPT_RCV_INT_M 0x0100
77 #define LAN91CXX_INTERRUPT_TX_IDLE 0x0080 /* (91C96)*/
78 #define LAN91CXX_INTERRUPT_ERCV_INT 0x0040 /* also ack*/
79 #define LAN91CXX_INTERRUPT_EPH_INT 0x0020
80 #define LAN91CXX_INTERRUPT_RX_OVRN_INT 0x0010 /* also ack*/
81 #define LAN91CXX_INTERRUPT_ALLOC_INT 0x0008
82 #define LAN91CXX_INTERRUPT_TX_EMPTY_INT 0x0004 /* also ack*/
83 #define LAN91CXX_INTERRUPT_TX_INT 0x0002 /* also ack*/
84 #define LAN91CXX_INTERRUPT_RCV_INT 0x0001
85 
86 #define LAN91CXX_INTERRUPT_TX_SET 0x0006 /* TX_EMPTY + TX*/
87 #define LAN91CXX_INTERRUPT_TX_SET_ACK 0x0004 /* TX_EMPTY and not plain TX*/
88 #define LAN91CXX_INTERRUPT_TX_FIFO_ACK 0x0002 /* TX alone*/
89 #define LAN91CXX_INTERRUPT_TX_SET_M 0x0600 /* TX_EMPTY + TX*/
90 
91 #define LAN91CXX_CONTROL_RCV_BAD 0x4000
92 #define LAN91CXX_CONTROL_AUTO_RELEASE 0x0800
93 #define LAN91CXX_CONTROL_LE_ENABLE 0x0080
94 #define LAN91CXX_CONTROL_CR_ENABLE 0x0040
95 #define LAN91CXX_CONTROL_TE_ENABLE 0x0020
96 
97 /* These are for setting the MAC address in the 91C96 serial EEPROM*/
98 #define LAN91CXX_CONTROL_EEPROM_SELECT 0x0004
99 #define LAN91CXX_CONTROL_RELOAD 0x0002
100 #define LAN91CXX_CONTROL_STORE 0x0001
101 #define LAN91CXX_CONTROL_EEPROM_BUSY 0x0003
102 #define LAN91CXX_ESA_EEPROM_OFFSET 0x0020
103 
104 #define LAN91CXX_STATUS_TX_UNRN 0x8000
105 #define LAN91CXX_STATUS_LINK_OK 0x4000
106 #define LAN91CXX_STATUS_CTR_ROL 0x1000
107 #define LAN91CXX_STATUS_EXC_DEF 0x0800
108 #define LAN91CXX_STATUS_LOST_CARR 0x0400
109 #define LAN91CXX_STATUS_LATCOL 0x0200
110 #define LAN91CXX_STATUS_WAKEUP 0x0100
111 #define LAN91CXX_STATUS_TX_DEFR 0x0080
112 #define LAN91CXX_STATUS_LTX_BRD 0x0040
113 #define LAN91CXX_STATUS_SQET 0x0020
114 #define LAN91CXX_STATUS_16COL 0x0010
115 #define LAN91CXX_STATUS_LTX_MULT 0x0008
116 #define LAN91CXX_STATUS_MUL_COL 0x0004
117 #define LAN91CXX_STATUS_SNGL_COL 0x0002
118 #define LAN91CXX_STATUS_TX_SUC 0x0001
119 
120 #define LAN91CXX_MMU_COMMAND_BUSY 0x0001
121 
122 #define LAN91CXX_MMU_noop 0x0000
123 #define LAN91CXX_MMU_alloc_for_tx 0x0020
124 #define LAN91CXX_MMU_reset_mmu 0x0040
125 #define LAN91CXX_MMU_rem_rx_frame 0x0060
126 #define LAN91CXX_MMU_rem_tx_frame 0x0070 /* (91C96) only when TX stopped*/
127 #define LAN91CXX_MMU_remrel_rx_frame 0x0080
128 #define LAN91CXX_MMU_rel_packet 0x00a0
129 #define LAN91CXX_MMU_enq_packet 0x00c0
130 #define LAN91CXX_MMU_reset_tx_fifo 0x00e0
131 
132 #define LAN91CXX_CONTROLBYTE_CRC 0x1000
133 #define LAN91CXX_CONTROLBYTE_ODD 0x2000
134 #define LAN91CXX_CONTROLBYTE_RX 0x4000
135 
136 #define LAN91CXX_RX_STATUS_ALIGNERR 0x8000
137 #define LAN91CXX_RX_STATUS_BCAST 0x4000
138 #define LAN91CXX_RX_STATUS_BADCRC 0x2000
139 #define LAN91CXX_RX_STATUS_ODDFRM 0x1000
140 #define LAN91CXX_RX_STATUS_TOOLONG 0x0800
141 #define LAN91CXX_RX_STATUS_TOOSHORT 0x0400
142 #define LAN91CXX_RX_STATUS_HASHVALMASK 0x007e /* MASK*/
143 #define LAN91CXX_RX_STATUS_MCAST 0x0001
144 #define LAN91CXX_RX_STATUS_BAD \
145  (LAN91CXX_RX_STATUS_ALIGNERR | \
146  LAN91CXX_RX_STATUS_BADCRC | \
147  LAN91CXX_RX_STATUS_TOOLONG | \
148  LAN91CXX_RX_STATUS_TOOSHORT)
149 
150 #define LAN91CXX_RX_STATUS_IS_ODD(__cpd,__stat) ((__stat) & LAN91CXX_RX_STATUS_ODDFRM)
151 #define LAN91CXX_CONTROLBYTE_IS_ODD(__cpd,__val) ((__val) & LAN91CXX_CONTROLBYTE_ODD)
152 
153 /* Attribute memory registers in PCMCIA mode*/
154 #define LAN91CXX_ECOR 0x8000
155 #define LAN91CXX_ECOR_RESET (1<<7)
156 #define LAN91CXX_ECOR_LEVIRQ (1<<6)
157 #define LAN91CXX_ECOR_ATTWR (1<<2)
158 #define LAN91CXX_ECOR_ENABLE (1<<0)
159 
160 #define LAN91CXX_ECSR 0x8002
161 #define LAN91CXX_ECSR_IOIS8 (1<<5)
162 #define LAN91CXX_ECSR_PWRDWN (1<<2)
163 #define LAN91CXX_ECSR_INTR (1<<1)
164 
165 /* These are for manipulating the MII interface*/
166 #define LAN91CXX_MGMT_MDO 0x0001
167 #define LAN91CXX_MGMT_MDI 0x0002
168 #define LAN91CXX_MGMT_MCLK 0x0004
169 #define LAN91CXX_MGMT_MDOE 0x0008
170 
171 /* Internal PHY registers (91c111)*/
172 #define LAN91CXX_PHY_CTRL 0
173 #define LAN91CXX_PHY_STAT 1
174 #define LAN91CXX_PHY_ID1 2
175 #define LAN91CXX_PHY_ID2 3
176 #define LAN91CXX_PHY_AUTO_AD 4
177 #define LAN91CXX_PHY_AUTO_CAP 5
178 #define LAN91CXX_PHY_CONFIG1 16
179 #define LAN91CXX_PHY_CONFIG2 17
180 #define LAN91CXX_PHY_STATUS_OUT 18
181 #define LAN91CXX_PHY_MASK 19
182 
183 /* PHY control bits*/
184 #define LAN91CXX_PHY_CTRL_COLTST (1 << 7)
185 #define LAN91CXX_PHY_CTRL_DPLX (1 << 8)
186 #define LAN91CXX_PHY_CTRL_ANEG_RST (1 << 9)
187 #define LAN91CXX_PHY_CTRL_MII_DIS (1 << 10)
188 #define LAN91CXX_PHY_CTRL_PDN (1 << 11)
189 #define LAN91CXX_PHY_CTRL_ANEG_EN (1 << 12)
190 #define LAN91CXX_PHY_CTRL_SPEED (1 << 13)
191 #define LAN91CXX_PHY_CTRL_LPBK (1 << 14)
192 #define LAN91CXX_PHY_CTRL_RST (1 << 15)
193 
194 /* PHY Configuration Register 1 */
195 #define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */
196 #define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */
197 #define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */
198 #define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */
199 #define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */
200 #define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */
201 #define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */
202 #define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */
203 #define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */
204 #define PHY_CFG1_TLVL_MASK 0x003C
205 #define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */
206 
207 /* PHY Configuration Register 2 */
208 #define PHY_CFG2_REG 0x11
209 #define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */
210 #define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */
211 #define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */
212 #define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */
213 
214 /* PHY Status Output (and Interrupt status) Register */
215 #define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */
216 #define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */
217 #define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */
218 #define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */
219 #define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */
220 #define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */
221 #define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */
222 #define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */
223 #define PHY_INT_JAB 0x0100 /* 1=Jabber detected */
224 #define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */
225 #define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */
226 
227 /* PHY Interrupt/Status Mask Register */
228 #define PHY_MASK_REG 0x13 /* Interrupt Mask */
229 
230 #define LAN91CXX_RPCR_LEDA_LINK (0 << 2)
231 #define LAN91CXX_RPCR_LEDA_TXRX (4 << 2)
232 #define LAN91CXX_RPCR_LEDA_RX (6 << 2)
233 #define LAN91CXX_RPCR_LEDA_TX (7 << 2)
234 #define LAN91CXX_RPCR_LEDB_LINK (0 << 5)
235 #define LAN91CXX_RPCR_LEDB_TXRX (4 << 5)
236 #define LAN91CXX_RPCR_LEDB_RX (6 << 5)
237 #define LAN91CXX_RPCR_LEDB_TX (7 << 5)
238 #define LAN91CXX_RPCR_ANEG (1 << 11)
239 #define LAN91CXX_RPCR_DPLX (1 << 12)
240 #define LAN91CXX_RPCR_SPEED (1 << 13)
241 
242 /* PHY Control Register */
243 #define PHY_CNTL_REG 0x00
244 #define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */
245 #define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */
246 #define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */
247 #define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */
248 #define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */
249 #define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */
250 #define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */
251 #define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */
252 #define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */
253 
254 /* PHY Status Register */
255 #define PHY_STAT_REG 0x01
256 #define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */
257 #define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */
258 #define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */
259 #define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */
260 #define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */
261 #define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */
262 #define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */
263 #define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */
264 #define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */
265 #define PHY_STAT_LINK 0x0004 /* 1=valid link */
266 #define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */
267 #define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */
268 #define PHY_STAT_RESERVED 0x0780 /* Reserved bits mask. */
269 
270 /* PHY Identifier Registers */
271 #define PHY_ID1_REG 0x02 /* PHY Identifier 1 */
272 #define PHY_ID2_REG 0x03 /* PHY Identifier 2 */
273 
274 /* PHY Auto-Negotiation Advertisement Register */
275 #define PHY_AD_REG 0x04
276 #define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */
277 #define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */
278 #define PHY_AD_RF 0x2000 /* 1=advertise remote fault */
279 #define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */
280 #define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */
281 #define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */
282 #define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */
283 #define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */
284 #define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */
285 
286 
287 static int debugflag_out = 0;
288 
289 #define dbc_printf(lvl,format, args...) do { \
290  if (!debugflag_out) { \
291  if (lvl & DEBUG) { \
292  printk(format,##args); \
293  } \
294  } \
295 } while(0)
296 
297 #define db64_printf(format, args...) dbc_printf(64,format,##args);
298 #define db16_printf(format, args...) dbc_printf(16,format,##args);
299 #define db9_printf(format, args...) dbc_printf(9,format,##args);
300 #define db4_printf(format, args...) dbc_printf(4,format,##args);
301 #define db2_printf(format, args...) dbc_printf(2,format,##args);
302 #define db1_printf(format, args...) dbc_printf(1,format,##args);
303 #define db_printf(format, args...) dbc_printf(0xffff,format,##args);
304 
305 #if DEBUG & 1
306 #define DEBUG_FUNCTION() do { db_printf("# %s\n", __FUNCTION__); } while (0)
307 #else
308 #define DEBUG_FUNCTION() do {} while(0)
309 #endif
310 
311 
312 /* ------------------------------------------------------------------------*/
313 
314 struct smsc_lan91cxx_stats {
315  unsigned int tx_good ;
316  unsigned int tx_max_collisions ;
317  unsigned int tx_late_collisions ;
318  unsigned int tx_underrun ;
319  unsigned int tx_carrier_loss ;
320  unsigned int tx_deferred ;
321  unsigned int tx_sqetesterrors ;
322  unsigned int tx_single_collisions;
323  unsigned int tx_mult_collisions ;
324  unsigned int tx_total_collisions ;
325  unsigned int rx_good ;
326  unsigned int rx_crc_errors ;
327  unsigned int rx_align_errors ;
328  unsigned int rx_resource_errors ;
329  unsigned int rx_overrun_errors ;
330  unsigned int rx_collisions ;
331  unsigned int rx_short_frames ;
332  unsigned int rx_too_long_frames ;
333  unsigned int rx_symbol_errors ;
334  unsigned int interrupts ;
335  unsigned int rx_count ;
336  unsigned int rx_deliver ;
337  unsigned int rx_resource ;
338  unsigned int rx_restart ;
339  unsigned int tx_count ;
340  unsigned int tx_complete ;
341  unsigned int tx_dropped ;
342 };
343 #define INCR_STAT(c,n) (((c)->stats.n)++)
344 
345 struct lan91cxx_priv_data;
346 
347 typedef struct lan91cxx_priv_data {
348 
349  /* frontend */
350  struct arpcom arpcom;
351  rtems_id rxDaemonTid;
352  rtems_id txDaemonTid;
353 
354  scmv91111_configuration_t config;
355 
356  /* backend */
357  int rpc_cur_mode;
358  int autoneg_active;
359  int phyaddr;
360  unsigned int lastPhy18;
361 
362  int txbusy; /* A packet has been sent*/
363  unsigned long txkey; /* Used to ack when packet sent*/
364  unsigned short* base; /* Base I/O address of controller*/
365  /* (as it comes out of reset)*/
366  int interrupt; /* Interrupt vector used by controller*/
367  unsigned char enaddr[6]; /* Controller ESA*/
368  /* Function to configure the ESA - may fetch ESA from EPROM or */
369  /* RedBoot config option. Use of the 'config_enaddr()' function*/
370  /* is depreciated in favor of the 'provide_esa()' function and*/
371  /* 'hardwired_esa' boolean*/
372  void (*config_enaddr)(struct lan91cxx_priv_data* cpd);
373  int hardwired_esa;
374  int txpacket;
375  int rxpacket;
376  int within_send;
377  int c111_reva; /* true if this is a revA LAN91C111*/
378  struct smsc_lan91cxx_stats stats;
379 } lan91cxx_priv_data;
380 
381 /* ------------------------------------------------------------------------*/
382 
383 #ifdef LAN91CXX_32BIT_RX
384 typedef unsigned int rxd_t;
385 #else
386 typedef unsigned short rxd_t;
387 #endif
388 
389 typedef struct _debug_regs_pair {
390  int reg; char *name; struct _debug_regs_pair *bits;
391 } debug_regs_pair;
392 
393 static debug_regs_pair debug_regs[] = {
394  {LAN91CXX_TCR , "LAN91CXX_TCR" ,0},
395  {LAN91CXX_EPH_STATUS , "LAN91CXX_EPH_STATUS",0},
396  {LAN91CXX_RCR , "LAN91CXX_RCR" ,0},
397  {LAN91CXX_COUNTER , "LAN91CXX_COUNTER" ,0},
398  {LAN91CXX_MIR , "LAN91CXX_MIR" ,0},
399  {LAN91CXX_MCR , "LAN91CXX_MCR" ,0},
400  {LAN91CXX_RPCR , "LAN91CXX_RPCR" ,0},
401  {LAN91CXX_RESERVED_0 , "LAN91CXX_RESERVED_0",0},
402  {LAN91CXX_BS , "LAN91CXX_BS" ,0},
403  {LAN91CXX_CONFIG , "LAN91CXX_CONFIG" ,0},
404  {LAN91CXX_BASE_REG , "LAN91CXX_BASE_REG" ,0},
405  {LAN91CXX_IA01 , "LAN91CXX_IA01" ,0},
406  {LAN91CXX_IA23 , "LAN91CXX_IA23" ,0},
407  {LAN91CXX_IA45 , "LAN91CXX_IA45" ,0},
408  {LAN91CXX_GENERAL , "LAN91CXX_GENERAL" ,0},
409  {LAN91CXX_CONTROL , "LAN91CXX_CONTROL" ,0},
410  {LAN91CXX_BS2 , "LAN91CXX_BS2" ,0},
411  {LAN91CXX_MMU_COMMAND, "LAN91CXX_MMU_COMMAND",0},
412  {LAN91CXX_PNR , "LAN91CXX_PNR" ,0},
413  {LAN91CXX_FIFO_PORTS , "LAN91CXX_FIFO_PORTS" ,0},
414  {LAN91CXX_POINTER , "LAN91CXX_POINTER" ,0},
415  {LAN91CXX_DATA_HIGH , "LAN91CXX_DATA_HIGH" ,0},
416  {LAN91CXX_DATA , "LAN91CXX_DATA" ,0},
417  {LAN91CXX_INTERRUPT , "LAN91CXX_INTERRUPT" ,0},
418  {LAN91CXX_BS3 , "LAN91CXX_BS3" ,0},
419  {LAN91CXX_MT01 , "LAN91CXX_MT01" ,0},
420  {LAN91CXX_MT23 , "LAN91CXX_MT23" ,0},
421  {LAN91CXX_MT45 , "LAN91CXX_MT45" ,0},
422  {LAN91CXX_MT67 , "LAN91CXX_MT67" ,0},
423 /*{LAN91CXX_MGMT , "LAN91CXX_MGMT" ,0}, */
424  {LAN91CXX_REVISION , "LAN91CXX_REVISION" ,0},
425  {LAN91CXX_ERCV , "LAN91CXX_ERCV" ,0},
426  {LAN91CXX_BS4 , "LAN91CXX_BS4" ,0},
427 
428 
429 
430  {-1,0}
431 };
432 
433 static char *dbg_prefix = "";
434 
435 #ifndef SMSC_PLATFORM_DEFINED_GET_REG
436 static __inline__ unsigned short
437 get_reg(struct lan91cxx_priv_data *cpd, int regno)
438 {
439  unsigned short val; debug_regs_pair *dbg = debug_regs; int c;
440  uint32_t Irql;
441 
442  /*rtems_interrupt_disable(Irql);*/
443 
444  HAL_WRITE_UINT16(cpd->base+(LAN91CXX_BS), CYG_CPU_TO_LE16(regno>>3));
445  HAL_READ_UINT16(cpd->base+((regno&0x7)), val);
446  val = CYG_LE16_TO_CPU(val);
447 
448  /*rtems_interrupt_enable(Irql);*/
449 
450 #if DEBUG & 32
451  while ((c = dbg->reg) != -1) {
452  if (c == regno) {
453  db_printf("%sread reg [%d:%x] -> 0x%04x (%-20s)\n", dbg_prefix, regno>>3,(regno&0x7)*2, val, dbg->name);
454  break;
455  }
456  dbg++;
457  }
458 #else
459  db2_printf("%sread reg %d:%x -> 0x%04x\n", dbg_prefix, regno>>3,(regno&0x7)*2, val);
460 #endif
461 
462  return val;
463 }
464 #endif /* SMSC_PLATFORM_DEFINED_GET_REG*/
465 
466 #ifndef SMSC_PLATFORM_DEFINED_PUT_REG
467 static __inline__ void
468 put_reg(struct lan91cxx_priv_data *cpd, int regno, unsigned short val)
469 {
470  debug_regs_pair *dbg = debug_regs; int c;
471  uint32_t Irql;
472 
473 #if DEBUG & 32
474  while ((c = dbg->reg) != -1) {
475  if (c == regno) {
476  db_printf("%swrite reg [%d:%x] <- 0x%04x (%-20s)\n", dbg_prefix, regno>>3, (regno&0x07)*2, val, dbg->name);
477  break;
478  }
479  dbg++;
480  }
481 #else
482  db2_printf("%swrite reg %d:%x <- 0x%04x\n", dbg_prefix, regno>>3,(regno&0x7)*2, val);
483 #endif
484 
485  /*rtems_interrupt_disable(Irql);*/
486 
487  HAL_WRITE_UINT16(cpd->base+(LAN91CXX_BS), CYG_CPU_TO_LE16(regno>>3));
488  HAL_WRITE_UINT16(cpd->base+((regno&0x7)), CYG_CPU_TO_LE16(val));
489 
490  /*rtems_interrupt_enable(Irql);*/
491 
492 }
493 #endif /* SMSC_PLATFORM_DEFINED_PUT_REG*/
494 
495 #ifndef SMSC_PLATFORM_DEFINED_PUT_DATA
496 /* ------------------------------------------------------------------------*/
497 /* Assumes bank2 has been selected*/
498 static __inline__ void
499 put_data(struct lan91cxx_priv_data *cpd, unsigned short val)
500 {
501  db2_printf("%s[wdata] <- 0x%04x\n", dbg_prefix, val);
502 
503  HAL_WRITE_UINT16(cpd->base+((LAN91CXX_DATA & 0x7)), val);
504 
505 }
506 
507 /* Assumes bank2 has been selected*/
508 static __inline__ void
509 put_data8(struct lan91cxx_priv_data *cpd, unsigned char val)
510 {
511  db2_printf("%s[bdata] <- 0x%02x\n", dbg_prefix, val);
512 
513  HAL_WRITE_UINT8(((unsigned char *)(cpd->base+((LAN91CXX_DATA & 0x7))))+1, val);
514 
515 }
516 
517 #endif /* SMSC_PLATFORM_DEFINED_PUT_DATA*/
518 
519 #ifndef SMSC_PLATFORM_DEFINED_GET_DATA
520 /* Assumes bank2 has been selected*/
521 static __inline__ rxd_t
522 get_data(struct lan91cxx_priv_data *cpd)
523 {
524  rxd_t val;
525 
526 #ifdef LAN91CXX_32BIT_RX
527  HAL_READ_UINT32(cpd->base+((LAN91CXX_DATA_HIGH & 0x7)), val);
528 #else
529  HAL_READ_UINT16(cpd->base+((LAN91CXX_DATA & 0x7)), val);
530 #endif
531 
532  db2_printf("%s[rdata] -> 0x%08x\n", dbg_prefix, val);
533  return val;
534 }
535 #endif /* SMSC_PLATFORM_DEFINED_GET_DATA*/
536 
537 /* ------------------------------------------------------------------------*/
538 /* Read the bank register (this one is bank-independent)*/
539 #ifndef SMSC_PLATFORM_DEFINED_GET_BANKSEL
540 static __inline__ unsigned short
541 get_banksel(struct lan91cxx_priv_data *cpd)
542 {
543  unsigned short val;
544 
545  HAL_READ_UINT16(cpd->base+(LAN91CXX_BS), val);
546  val = CYG_LE16_TO_CPU(val);
547  db2_printf("read bank sel val 0x%04x\n", val);
548  return val;
549 }
550 #endif
551 
552 
553 
554 
555 
556 #endif /* _SMC_91111_H_ */
557 
558 
config_s
Definition: deflate.c:115
lan91cxx_priv_data
Definition: smc91111.h:347
_debug_regs_pair
Definition: smc91111.h:389
scmv91111_configuration
Definition: smc91111exp.h:6
bspIo.h
Interface to Kernel Print Methods.
rtems_id
Objects_Id rtems_id
Used to manage and manipulate RTEMS object identifiers.
Definition: types.h:83
smsc_lan91cxx_stats
Definition: smc91111.h:314
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