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#define | SED1356_REG_REV_and_MISC SED_REG16(0x00) |
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#define | SED1356_REG_GPIO_CFG SED_REG16(0x04) |
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#define | SED1356_REG_GPIO_CTL SED_REG16(0x08) |
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#define | SED1356_REG_MD_CFG_RD_LO_and_HI SED_REG16(0x0c) |
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#define | SED1356_REG_MCLK_CFG SED_REG16(0x10) |
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#define | SED1356_REG_LCD_PCLK_CFG SED_REG16(0x14) |
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#define | SED1356_REG_CRT_PCLK_CFG SED_REG16(0x18) |
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#define | SED1356_REG_MEDIA_PCLK_CFG SED_REG16(0x1c) |
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#define | SED1356_REG_WAIT_STATE SED_REG16(0x1e) |
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#define | SED1356_REG_MEM_CFG_and_REF_RATE SED_REG16(0x20) |
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#define | SED1356_REG_MEM_TMG0_and_1 SED_REG16(0x2a) |
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#define | SED1356_REG_PANEL_TYPE_and_MOD_RATE SED_REG16(0x30) |
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#define | SED1356_REG_LCD_HOR_DISP SED_REG16(0x32) |
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#define | SED1356_REG_LCD_HOR_NONDISP_and_START SED_REG16(0x34) |
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#define | SED1356_REG_LCD_HOR_PULSE SED_REG16(0x36) |
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#define | SED1356_REG_LCD_VER_DISP_HT_LO_and_HI SED_REG16(0x38) |
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#define | SED1356_REG_LCD_VER_NONDISP_and_START SED_REG16(0x3a) |
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#define | SED1356_REG_LCD_VER_PULSE SED_REG16(0x3c) |
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#define | SED1356_REG_LCD_DISP_MODE_and_MISC SED_REG16(0x40) |
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#define | SED1356_REG_LCD_DISP_START_LO_and_MID SED_REG16(0x42) |
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#define | SED1356_REG_LCD_DISP_START_HI SED_REG16(0x44) |
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#define | SED1356_REG_LCD_ADD_OFFSET_LO_and_HI SED_REG16(0x46) |
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#define | SED1356_REG_LCD_PIXEL_PAN SED_REG16(0x48) |
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#define | SED1356_REG_LCD_FIFO_THRESH_LO_and_HI SED_REG16(0x4a) |
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#define | SED1356_REG_CRT_HOR_DISP SED_REG16(0x50) |
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#define | SED1356_REG_CRT_HOR_NONDISP_and_START SED_REG16(0x52) |
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#define | SED1356_REG_CRT_HOR_PULSE SED_REG16(0x54) |
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#define | SED1356_REG_CRT_VER_DISP_HT_LO_and_HI SED_REG16(0x56) |
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#define | SED1356_REG_CRT_VER_NONDISP_and_START SED_REG16(0x58) |
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#define | SED1356_REG_CRT_VER_PULSE_and_OUT_CTL SED_REG16(0x5a) |
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#define | SED1356_REG_CRT_DISP_MODE SED_REG16(0x60) |
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#define | SED1356_REG_CRT_DISP_START_LO_and_MID SED_REG16(0x62) |
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#define | SED1356_REG_CRT_DISP_START_HI SED_REG16(0x64) |
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#define | SED1356_REG_CRT_ADD_OFFSET_LO_and_HI SED_REG16(0x66) |
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#define | SED1356_REG_CRT_PIXEL_PAN SED_REG16(0x68) |
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#define | SED1356_REG_CRT_FIFO_THRESH_LO_and_HI SED_REG16(0x6a) |
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#define | SED1356_REG_LCD_CURSOR_CTL_and_START_ADD SED_REG16(0x70) |
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#define | SED1356_REG_LCD_CURSOR_X_POS_LO_and_HI SED_REG16(0x72) |
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#define | SED1356_REG_LCD_CURSOR_Y_POS_LO_and_HI SED_REG16(0x74) |
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#define | SED1356_REG_LCD_CURSOR_BLUE_and_GREEN_CLR_0 SED_REG16(0x76) |
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#define | SED1356_REG_LCD_CURSOR_RED_CLR_0 SED_REG16(0x78) |
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#define | SED1356_REG_LCD_CURSOR_BLUE_and_GREEN_CLR_1 SED_REG16(0x7a) |
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#define | SED1356_REG_LCD_CURSOR_RED_CLR_1 SED_REG16(0x7c) |
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#define | SED1356_REG_LCD_CURSOR_FIFO_THRESH SED_REG16(0x7e) |
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#define | SED1356_REG_CRT_CURSOR_CTL_and_START_ADD SED_REG16(0x80) |
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#define | SED1356_REG_CRT_CURSOR_X_POS_LO_and_HI SED_REG16(0x82) |
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#define | SED1356_REG_CRT_CURSOR_Y_POS_LO_and_HI SED_REG16(0x84) |
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#define | SED1356_REG_CRT_CURSOR_BLUE_and_GREEN_CLR_0 SED_REG16(0x86) |
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#define | SED1356_REG_CRT_CURSOR_RED_CLR_0 SED_REG16(0x88) |
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#define | SED1356_REG_CRT_CURSOR_BLUE_and_GREEN_CLR_1 SED_REG16(0x8a) |
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#define | SED1356_REG_CRT_CURSOR_RED_CLR_1 SED_REG16(0x8c) |
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#define | SED1356_REG_CRT_CURSOR_FIFO_THRESH SED_REG16(0x8e) |
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#define | SED1356_REG_BLT_CTL_0_and_1 SED_REG16(0x100) |
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#define | SED1356_REG_BLT_ROP_CODE_and_BLT_OP SED_REG16(0x102) |
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#define | SED1356_REG_BLT_SRC_START_LO_and_MID SED_REG16(0x104) |
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#define | SED1356_REG_BLT_SRC_START_HI SED_REG16(0x106) |
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#define | SED1356_REG_BLT_DEST_START_LO_and_MID SED_REG16(0x108) |
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#define | SED1356_REG_BLT_DEST_START_HI SED_REG16(0x10a) |
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#define | SED1356_REG_BLT_ADD_OFFSET_LO_and_HI SED_REG16(0x10c) |
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#define | SED1356_REG_BLT_WID_LO_and_HI SED_REG16(0x110) |
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#define | SED1356_REG_BLT_HGT_LO_and_HI SED_REG16(0x112) |
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#define | SED1356_REG_BLT_BG_CLR_LO_and_HI SED_REG16(0x114) |
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#define | SED1356_REG_BLT_FG_CLR_LO_and_HI SED_REG16(0x118) |
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#define | SED1356_REG_LUT_MODE SED_REG16(0x1e0) |
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#define | SED1356_REG_LUT_ADD SED_REG16(0x1e2) |
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#define | SED1356_REG_LUT_DATA SED_REG16(0x1e4) |
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#define | SED1356_REG_PWR_CFG_and_STAT SED_REG16(0x1f0) |
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#define | SED1356_REG_WATCHDOG_CTL SED_REG16(0x1f4) |
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#define | SED1356_REG_DISP_MODE SED_REG16(0x1fc) |
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#define | SED1356_REV_ID_MASK 0xfc /* ID bits - masks off the rev bits */ |
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#define | SED1356_REV_ID_1356 BIT4 |
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#define | SED1356_REV_ID_1355 BIT3 |
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#define | SED1356_MISC_HOST_DIS BIT7 << 8 /* 0 = enable host access, 1 = disable */ |
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#define | SED1356_GPIO_GPIO3 BIT3 /* 0 = input, 1 = output, if configured as GPIO */ |
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#define | SED1356_GPIO_GPIO2 BIT2 |
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#define | SED1356_GPIO_GPIO1 BIT1 |
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#define | SED1356_MCLK_DIV2 BIT4 |
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#define | SED1356_MCLK_SRC_BCLK BIT0 |
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#define | SED1356_MCLK_SRC_CLKI 0x00 |
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#define | SED1356_PCLK_X2 BIT7 /* SED1356_REG_CRT_PCLK_CFG only */ |
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#define | SED1356_PCLK_DIV1 0x00 << 4 |
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#define | SED1356_PCLK_DIV2 0x01 << 4 |
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#define | SED1356_PCLK_DIV3 0x02 << 4 |
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#define | SED1356_PCLK_DIV4 0x03 << 4 |
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#define | SED1356_PCLK_SRC_CLKI 0x00 |
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#define | SED1356_PCLK_SRC_BCLK 0x01 |
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#define | SED1356_PCLK_SRC_CLKI2 0x02 |
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#define | SED1356_PCLK_SRC_MCLK 0x03 |
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#define | SED1356_MEM_CFG_2CAS_EDO 0x00 |
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#define | SED1356_MEM_CFG_2CAS_FPM 0x01 |
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#define | SED1356_MEM_CFG_2WE_EDO 0x02 |
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#define | SED1356_MEM_CFG_2WE_FPM 0x03 |
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#define | SED1356_MEM_CFG_MASK 0x03 |
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#define | SED1356_REF_TYPE_CBR 0x00 << 6 << 8 |
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#define | SED1356_REF_TYPE_SELF 0x01 << 6 << 8 |
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#define | SED1356_REF_TYPE_NONE 0x02 << 6 << 8 |
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#define | SED1356_REF_TYPE_MASK 0x03 << 6 << 8 |
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#define | SED1356_REF_RATE_64 0x00 << 0 << 8 /* MCLK / 64 */ |
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#define | SED1356_REF_RATE_128 0x01 << 0 << 8 /* MCLK / 128 */ |
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#define | SED1356_REF_RATE_256 0x02 << 0 << 8 /* MCLK / 256 */ |
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#define | SED1356_REF_RATE_512 0x03 << 0 << 8 /* MCLK / 512 */ |
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#define | SED1356_REF_RATE_1024 0x04 << 0 << 8 /* MCLK / 1024 */ |
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#define | SED1356_REF_RATE_2048 0x05 << 0 << 8 /* MCLK / 2048 */ |
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#define | SED1356_REF_RATE_4096 0x06 << 0 << 8 /* MCLK / 4096 */ |
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#define | SED1356_REF_RATE_8192 0x07 << 0 << 8 /* MCLK / 8192 */ |
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#define | SED1356_REF_RATE_MASK 0x07 << 0 << 8 /* MCLK / 8192 */ |
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#define | SED1356_MEM_TMG0_EDO50_MCLK40 0x01 |
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#define | SED1356_MEM_TMG0_EDO50_MCLK33 0x01 |
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#define | SED1356_MEM_TMG0_EDO60_MCLK33 0x01 |
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#define | SED1356_MEM_TMG0_EDO50_MCLK30 0x12 |
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#define | SED1356_MEM_TMG0_EDO60_MCLK30 0x01 |
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#define | SED1356_MEM_TMG0_EDO70_MCLK30 0x00 |
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#define | SED1356_MEM_TMG0_EDO50_MCLK25 0x12 |
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#define | SED1356_MEM_TMG0_EDO60_MCLK25 0x12 |
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#define | SED1356_MEM_TMG0_EDO70_MCLK25 0x01 |
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#define | SED1356_MEM_TMG0_EDO80_MCLK25 0x00 |
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#define | SED1356_MEM_TMG0_EDO50_MCLK20 0x12 |
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#define | SED1356_MEM_TMG0_EDO60_MCLK20 0x12 |
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#define | SED1356_MEM_TMG0_EDO70_MCLK20 0x12 |
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#define | SED1356_MEM_TMG0_EDO80_MCLK20 0x01 |
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#define | SED1356_MEM_TMG0_FPM50_MCLK25 0x12 |
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#define | SED1356_MEM_TMG0_FPM60_MCLK25 0x01 |
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#define | SED1356_MEM_TMG0_FPM50_MCLK20 0x12 |
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#define | SED1356_MEM_TMG0_FPM60_MCLK20 0x12 |
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#define | SED1356_MEM_TMG0_FPM70_MCLK20 0x11 |
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#define | SED1356_MEM_TMG0_FPM80_MCLK20 0x01 |
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#define | SED1356_MEM_TMG1_EDO50_MCLK40 0x01 << 8 |
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#define | SED1356_MEM_TMG1_EDO50_MCLK33 0x01 << 8 |
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#define | SED1356_MEM_TMG1_EDO60_MCLK33 0x01 << 8 |
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#define | SED1356_MEM_TMG1_EDO50_MCLK30 0x02 << 8 |
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#define | SED1356_MEM_TMG1_EDO60_MCLK30 0x01 << 8 |
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#define | SED1356_MEM_TMG1_EDO70_MCLK30 0x00 << 8 |
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#define | SED1356_MEM_TMG1_EDO50_MCLK25 0x02 << 8 |
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#define | SED1356_MEM_TMG1_EDO60_MCLK25 0x02 << 8 |
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#define | SED1356_MEM_TMG1_EDO70_MCLK25 0x01 << 8 |
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#define | SED1356_MEM_TMG1_EDO80_MCLK25 0x01 << 8 |
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#define | SED1356_MEM_TMG1_EDO50_MCLK20 0x02 << 8 |
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#define | SED1356_MEM_TMG1_EDO60_MCLK20 0x02 << 8 |
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#define | SED1356_MEM_TMG1_EDO70_MCLK20 0x02 << 8 |
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#define | SED1356_MEM_TMG1_EDO80_MCLK20 0x01 << 8 |
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#define | SED1356_MEM_TMG1_FPM50_MCLK25 0x02 << 8 |
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#define | SED1356_MEM_TMG1_FPM60_MCLK25 0x01 << 8 |
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#define | SED1356_MEM_TMG1_FPM50_MCLK20 0x02 << 8 |
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#define | SED1356_MEM_TMG1_FPM60_MCLK20 0x02 << 8 |
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#define | SED1356_MEM_TMG1_FPM70_MCLK20 0x02 << 8 |
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#define | SED1356_MEM_TMG1_FPM80_MCLK20 0x01 << 8 |
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#define | SED1356_PANEL_TYPE_EL BIT7 |
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#define | SED1356_PANEL_TYPE_4_9 (0x00 << 4) /* Passive 4-Bit, TFT 9-Bit */ |
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#define | SED1356_PANEL_TYPE_8_12 (0x01 << 4) /* Passive 8-Bit, TFT 12-Bit */ |
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#define | SED1356_PANEL_TYPE_16 (0x02 << 4) /* Passive 16-Bit, or TFT 18-Bit */ |
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#define | SED1356_PANEL_TYPE_MASK (0x03 << 4) |
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#define | SED1356_PANEL_TYPE_FMT BIT3 /* 0 = Passive Format 1, 1 = Passive Format 2 */ |
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#define | SED1356_PANEL_TYPE_CLR BIT2 /* 0 = Passive Mono, 1 = Passive Color */ |
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#define | SED1356_PANEL_TYPE_DUAL BIT1 /* 0 = Passive Single, 1 = Passive Dual */ |
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#define | SED1356_PANEL_TYPE_TFT BIT0 /* 0 = Passive, 1 = TFT (DUAL, FMT & CLR are don't cares) */ |
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#define | SED1356_PULSE_POL_HIGH BIT7 /* 0 = CRT/TFT Pulse is Low, Passive is High, 1 = CRT/TFT Pulse is High, Passive is Low */ |
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#define | SED1356_PULSE_POL_LOW 0x00 /* 0 = CRT/TFT Pulse is Low, Passive is High, 1 = CRT/TFT Pulse is High, Passive is Low */ |
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#define | SED1356_PULSE_WID(_x_) (_x_ & 0x0f) /* Pulse Width in Pixels */ |
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#define | SED1356_LCD_DISP_BLANK BIT7 /* 1 = Blank LCD Display */ |
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#define | SED1356_LCD_DISP_SWIV_NORM (0x00 << 4) /* Used with SED1356_REG_DISP_MODE Bit 6 */ |
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#define | SED1356_LCD_DISP_SWIV_90 (0x00 << 4) |
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#define | SED1356_LCD_DISP_SWIV_180 (0x01 << 4) |
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#define | SED1356_LCD_DISP_SWIV_270 (0x01 << 4) |
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#define | SED1356_LCD_DISP_SWIV_MASK (0x01 << 4) |
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#define | SED1356_LCD_DISP_16BPP 0x05 /* Bit Per Pixel Selection */ |
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#define | SED1356_LCD_DISP_15BPP 0x04 |
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#define | SED1356_LCD_DISP_8BPP 0x03 |
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#define | SED1356_LCD_DISP_4BPP 0x02 |
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#define | SED1356_LCD_DISP_BPP_MASK 0x07 |
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#define | SED1356_LCD_MISC_DITH BIT1 << 8 /* 1 = Dither Disable, Passive Panel Only */ |
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#define | SED1356_LCD_MISC_DUAL BIT0 << 8 /* 1 = Dual Panel Disable, Passive Panel Only */ |
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#define | SED1356_CRT_OUT_CHROM BIT5 << 8 /* 1 = TV Chrominance Filter Enable */ |
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#define | SED1356_CRT_OUT_LUM BIT4 << 8 /* 1 = TV Luminance Filter Enable */ |
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#define | SED1356_CRT_OUT_DAC_LVL BIT3 << 8 /* 1 = 4.6ma IREF, 0 = 9.2 IREF */ |
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#define | SED1356_CRT_OUT_SVIDEO BIT1 << 8 /* 1 = S-Video Output, 0 = Composite Video Output */ |
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#define | SED1356_CRT_OUT_PAL BIT0 << 8 /* 1 = PAL Format Output, 0 = NTSC Format Output */ |
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#define | SED1356_CRT_DISP_BLANK BIT7 /* 1 = Blank CRT Display */ |
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#define | SED1356_CRT_DISP_16BPP 0x05 /* Bit Per Pixel Selection */ |
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#define | SED1356_CRT_DISP_15BPP 0x04 |
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#define | SED1356_CRT_DISP_8BPP 0x03 |
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#define | SED1356_CRT_DISP_4BPP 0x02 |
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#define | SED1356_CRT_DISP_BPP_MASK 0x07 |
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#define | SED1356_DISP_SWIV_NORM (0x00 << 6) /* Used with SED1356_LCD_DISP_MODE Bit 4 */ |
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#define | SED1356_DISP_SWIV_90 (0x01 << 6) |
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#define | SED1356_DISP_SWIV_180 (0x00 << 6) |
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#define | SED1356_DISP_SWIV_270 (0x01 << 6) |
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#define | SED1356_DISP_MODE_OFF 0x00 /* All Displays Off */ |
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#define | SED1356_DISP_MODE_LCD 0x01 /* LCD Only */ |
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#define | SED1356_DISP_MODE_CRT 0x02 /* CRT Only */ |
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#define | SED1356_DISP_MODE_LCD_CRT 0x03 /* Simultaneous LCD and CRT */ |
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#define | SED1356_DISP_MODE_TV 0x04 /* TV Only, Flicker Filter Off */ |
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#define | SED1356_DISP_MODE_TV_LCD 0x05 /* Simultaneous LCD and TV, Flicker Filter Off */ |
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#define | SED1356_DISP_MODE_TV_FLICK 0x06 /* TV Only, Flicker Filter On */ |
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#define | SED1356_DISP_MODE_TV_LCD_FLICK 0x07 /* Simultaneous LCD and TV, Flicker Filter On */ |
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#define | SED1356_PWR_PCLK BIT1 /* SED1356_REG_PWR_STAT only */ |
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#define | SED1356_PWR_MCLK BIT0 |
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#define | SED1356_VER_NONDISP BIT7 /* vertical retrace status 1 = in retrace */ |
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#define | BYTES_PER_PIXEL 2 |
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#define | RED_SUBPIXEL(n) ((n & 0x1f) << 11) |
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#define | GREEN_SUBPIXEL(n) ((n & 0x1f) << 5) |
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#define | BLUE_SUBPIXEL(n) ((n & 0x1f) << 0) |
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#define | BLUE (0x14 << 0) |
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#define | GREEN (0x14 << 6) |
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#define | RED (0x14 << 11) |
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#define | HALF_BLUE (0x0a << 0) |
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#define | HALF_GREEN (0x0a << 6) |
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#define | HALF_RED (0x0a << 11) |
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#define | BRT_BLUE (0x1e << 0) |
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#define | BRT_GREEN (0x1e << 6) |
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#define | BRT_RED (0x1e << 11) |
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#define | LU_BLACK 0 |
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#define | LU_BLUE (BLUE) |
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#define | LU_GREEN (GREEN) |
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#define | LU_CYAN (GREEN | BLUE) |
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#define | LU_RED (RED) |
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#define | LU_VIOLET (RED | BLUE) |
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#define | LU_YELLOW (RED | GREEN) |
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#define | LU_WHITE (RED | GREEN | BLUE) |
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#define | LU_GREY (HALF_RED | HALF_GREEN | HALF_BLUE) |
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#define | LU_BRT_BLUE (HALF_RED | HALF_GREEN | BRT_BLUE) |
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#define | LU_BRT_GREEN (HALF_RED | BRT_GREEN | HALF_BLUE) |
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#define | LU_BRT_CYAN (HALF_RED | BRT_GREEN | BRT_BLUE) |
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#define | LU_BRT_RED (BRT_RED | HALF_GREEN | HALF_BLUE) |
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#define | LU_BRT_VIOLET (BRT_RED | HALF_GREEN | BRT_BLUE) |
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#define | LU_BRT_YELLOW (BRT_RED | BRT_GREEN | HALF_BLUE) |
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#define | LU_BRT_WHITE (BRT_RED | BRT_GREEN | BRT_BLUE) |
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#define | SED_BG_DEF 1 |
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#define | SED_FG_DEF 14 |
| |
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#define | TOP 0 |
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#define | BOTTOM (PIXELS_PER_COL-1) |
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#define | LEFT 0 |
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#define | RIGHT (PIXELS_PER_ROW-1) |
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#define | CENTER_X (PIXELS_PER_ROW/2) |
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#define | CENTER_Y (PIXELS_PER_COL/2) |
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#define | SED_HOR_PULSE_WIDTH_CRT 0x07 /* Horizontal Pulse Width Register = (Thp/8) - 1 */ |
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#define | SED_HOR_PULSE_START_CRT 0x02 /* Horizontal Pulse Start Position Register = ((Thfp + 2)/8) - 1 */ |
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#define | SED_HOR_NONDISP_CRT 0x17 /* Horizontal Non-Display Period Register = ((Thp + Thfp + Thbp)/8) - 1 */ |
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#define | SED_VER_PULSE_WIDTH_CRT 0x02 |
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#define | SED_VER_PULSE_START_CRT 0x08 |
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#define | SED_VER_NONDISP_CRT 0x27 |
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1.8.15