RTEMS  5.1
component_afec.h
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3 /* SAM Software Package License */
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29 
30 #ifndef _SAMV71_AFEC_COMPONENT_
31 #define _SAMV71_AFEC_COMPONENT_
32 
33 /* ============================================================================= */
35 /* ============================================================================= */
38 
39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40 
41 typedef struct {
42  __O uint32_t AFEC_CR;
43  __IO uint32_t AFEC_MR;
44  __IO uint32_t AFEC_EMR;
45  __IO uint32_t AFEC_SEQ1R;
46  __IO uint32_t AFEC_SEQ2R;
47  __O uint32_t AFEC_CHER;
48  __O uint32_t AFEC_CHDR;
49  __I uint32_t AFEC_CHSR;
50  __I uint32_t AFEC_LCDR;
51  __O uint32_t AFEC_IER;
52  __O uint32_t AFEC_IDR;
53  __I uint32_t AFEC_IMR;
54  __I uint32_t AFEC_ISR;
55  __I uint32_t Reserved1[6];
56  __I uint32_t AFEC_OVER;
57  __IO uint32_t AFEC_CWR;
58  __IO uint32_t AFEC_CGR;
59  __I uint32_t Reserved2[2];
60  __IO uint32_t AFEC_DIFFR;
61  __IO uint32_t AFEC_CSELR;
62  __I uint32_t AFEC_CDR;
63  __IO uint32_t AFEC_COCR;
64  __IO uint32_t AFEC_TEMPMR;
65  __IO uint32_t AFEC_TEMPCWR;
66  __I uint32_t Reserved3[7];
67  __IO uint32_t AFEC_ACR;
68  __I uint32_t Reserved4[2];
69  __IO uint32_t AFEC_SHMR;
70  __I uint32_t Reserved5[11];
71  __IO uint32_t AFEC_COSR;
72  __IO uint32_t AFEC_CVR;
73  __IO uint32_t AFEC_CECR;
74  __I uint32_t Reserved6[2];
75  __IO uint32_t AFEC_WPMR;
76  __I uint32_t AFEC_WPSR;
77  __I uint32_t Reserved7[4];
78  __I uint32_t AFEC_VERSION;
79 } Afec;
80 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
81 /* -------- AFEC_CR : (AFEC Offset: 0x00) AFEC Control Register -------- */
82 #define AFEC_CR_SWRST (0x1u << 0)
83 #define AFEC_CR_START (0x1u << 1)
84 /* -------- AFEC_MR : (AFEC Offset: 0x04) AFEC Mode Register -------- */
85 #define AFEC_MR_TRGEN (0x1u << 0)
86 #define AFEC_MR_TRGEN_DIS (0x0u << 0)
87 #define AFEC_MR_TRGEN_EN (0x1u << 0)
88 #define AFEC_MR_TRGSEL_Pos 1
89 #define AFEC_MR_TRGSEL_Msk (0x7u << AFEC_MR_TRGSEL_Pos)
90 #define AFEC_MR_TRGSEL(value) ((AFEC_MR_TRGSEL_Msk & ((value) << AFEC_MR_TRGSEL_Pos)))
91 #define AFEC_MR_TRGSEL_AFEC_TRIG0 (0x0u << 1)
92 #define AFEC_MR_TRGSEL_AFEC_TRIG1 (0x1u << 1)
93 #define AFEC_MR_TRGSEL_AFEC_TRIG2 (0x2u << 1)
94 #define AFEC_MR_TRGSEL_AFEC_TRIG3 (0x3u << 1)
95 #define AFEC_MR_TRGSEL_AFEC_TRIG4 (0x4u << 1)
96 #define AFEC_MR_TRGSEL_AFEC_TRIG5 (0x5u << 1)
97 #define AFEC_MR_TRGSEL_AFEC_TRIG6 (0x6u << 1)
98 #define AFEC_MR_SLEEP (0x1u << 5)
99 #define AFEC_MR_SLEEP_NORMAL (0x0u << 5)
100 #define AFEC_MR_SLEEP_SLEEP (0x1u << 5)
101 #define AFEC_MR_FWUP (0x1u << 6)
102 #define AFEC_MR_FWUP_OFF (0x0u << 6)
103 #define AFEC_MR_FWUP_ON (0x1u << 6)
104 #define AFEC_MR_FREERUN (0x1u << 7)
105 #define AFEC_MR_FREERUN_OFF (0x0u << 7)
106 #define AFEC_MR_FREERUN_ON (0x1u << 7)
107 #define AFEC_MR_PRESCAL_Pos 8
108 #define AFEC_MR_PRESCAL_Msk (0xffu << AFEC_MR_PRESCAL_Pos)
109 #define AFEC_MR_PRESCAL(value) ((AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos)))
110 #define AFEC_MR_STARTUP_Pos 16
111 #define AFEC_MR_STARTUP_Msk (0xfu << AFEC_MR_STARTUP_Pos)
112 #define AFEC_MR_STARTUP(value) ((AFEC_MR_STARTUP_Msk & ((value) << AFEC_MR_STARTUP_Pos)))
113 #define AFEC_MR_STARTUP_SUT0 (0x0u << 16)
114 #define AFEC_MR_STARTUP_SUT8 (0x1u << 16)
115 #define AFEC_MR_STARTUP_SUT16 (0x2u << 16)
116 #define AFEC_MR_STARTUP_SUT24 (0x3u << 16)
117 #define AFEC_MR_STARTUP_SUT64 (0x4u << 16)
118 #define AFEC_MR_STARTUP_SUT80 (0x5u << 16)
119 #define AFEC_MR_STARTUP_SUT96 (0x6u << 16)
120 #define AFEC_MR_STARTUP_SUT112 (0x7u << 16)
121 #define AFEC_MR_STARTUP_SUT512 (0x8u << 16)
122 #define AFEC_MR_STARTUP_SUT576 (0x9u << 16)
123 #define AFEC_MR_STARTUP_SUT640 (0xAu << 16)
124 #define AFEC_MR_STARTUP_SUT704 (0xBu << 16)
125 #define AFEC_MR_STARTUP_SUT768 (0xCu << 16)
126 #define AFEC_MR_STARTUP_SUT832 (0xDu << 16)
127 #define AFEC_MR_STARTUP_SUT896 (0xEu << 16)
128 #define AFEC_MR_STARTUP_SUT960 (0xFu << 16)
129 #define AFEC_MR_ONE (0x1u << 23)
130 #define AFEC_MR_TRACKTIM_Pos 24
131 #define AFEC_MR_TRACKTIM_Msk (0xfu << AFEC_MR_TRACKTIM_Pos)
132 #define AFEC_MR_TRACKTIM(value) ((AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos)))
133 #define AFEC_MR_TRANSFER_Pos 28
134 #define AFEC_MR_TRANSFER_Msk (0x3u << AFEC_MR_TRANSFER_Pos)
135 #define AFEC_MR_TRANSFER(value) ((AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos)))
136 #define AFEC_MR_USEQ (0x1u << 31)
137 #define AFEC_MR_USEQ_NUM_ORDER (0x0u << 31)
138 #define AFEC_MR_USEQ_REG_ORDER (0x1u << 31)
139 /* -------- AFEC_EMR : (AFEC Offset: 0x08) AFEC Extended Mode Register -------- */
140 #define AFEC_EMR_CMPMODE_Pos 0
141 #define AFEC_EMR_CMPMODE_Msk (0x3u << AFEC_EMR_CMPMODE_Pos)
142 #define AFEC_EMR_CMPMODE(value) ((AFEC_EMR_CMPMODE_Msk & ((value) << AFEC_EMR_CMPMODE_Pos)))
143 #define AFEC_EMR_CMPMODE_LOW (0x0u << 0)
144 #define AFEC_EMR_CMPMODE_HIGH (0x1u << 0)
145 #define AFEC_EMR_CMPMODE_IN (0x2u << 0)
146 #define AFEC_EMR_CMPMODE_OUT (0x3u << 0)
147 #define AFEC_EMR_CMPSEL_Pos 3
148 #define AFEC_EMR_CMPSEL_Msk (0x1fu << AFEC_EMR_CMPSEL_Pos)
149 #define AFEC_EMR_CMPSEL(value) ((AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos)))
150 #define AFEC_EMR_CMPALL (0x1u << 9)
151 #define AFEC_EMR_CMPFILTER_Pos 12
152 #define AFEC_EMR_CMPFILTER_Msk (0x3u << AFEC_EMR_CMPFILTER_Pos)
153 #define AFEC_EMR_CMPFILTER(value) ((AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos)))
154 #define AFEC_EMR_RES_Pos 16
155 #define AFEC_EMR_RES_Msk (0x7u << AFEC_EMR_RES_Pos)
156 #define AFEC_EMR_RES(value) ((AFEC_EMR_RES_Msk & ((value) << AFEC_EMR_RES_Pos)))
157 #define AFEC_EMR_RES_NO_AVERAGE (0x0u << 16)
158 #define AFEC_EMR_RES_OSR4 (0x2u << 16)
159 #define AFEC_EMR_RES_OSR16 (0x3u << 16)
160 #define AFEC_EMR_RES_OSR64 (0x4u << 16)
161 #define AFEC_EMR_RES_OSR256 (0x5u << 16)
162 #define AFEC_EMR_TAG (0x1u << 24)
163 #define AFEC_EMR_STM (0x1u << 25)
164 #define AFEC_EMR_SIGNMODE_Pos 28
165 #define AFEC_EMR_SIGNMODE_Msk (0x3u << AFEC_EMR_SIGNMODE_Pos)
166 #define AFEC_EMR_SIGNMODE(value) ((AFEC_EMR_SIGNMODE_Msk & ((value) << AFEC_EMR_SIGNMODE_Pos)))
167 #define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN (0x0u << 28)
168 #define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG (0x1u << 28)
169 #define AFEC_EMR_SIGNMODE_ALL_UNSIGNED (0x2u << 28)
170 #define AFEC_EMR_SIGNMODE_ALL_SIGNED (0x3u << 28)
171 /* -------- AFEC_SEQ1R : (AFEC Offset: 0x0C) AFEC Channel Sequence 1 Register -------- */
172 #define AFEC_SEQ1R_USCH0_Pos 0
173 #define AFEC_SEQ1R_USCH0_Msk (0xfu << AFEC_SEQ1R_USCH0_Pos)
174 #define AFEC_SEQ1R_USCH0(value) ((AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos)))
175 #define AFEC_SEQ1R_USCH1_Pos 4
176 #define AFEC_SEQ1R_USCH1_Msk (0xfu << AFEC_SEQ1R_USCH1_Pos)
177 #define AFEC_SEQ1R_USCH1(value) ((AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos)))
178 #define AFEC_SEQ1R_USCH2_Pos 8
179 #define AFEC_SEQ1R_USCH2_Msk (0xfu << AFEC_SEQ1R_USCH2_Pos)
180 #define AFEC_SEQ1R_USCH2(value) ((AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos)))
181 #define AFEC_SEQ1R_USCH3_Pos 12
182 #define AFEC_SEQ1R_USCH3_Msk (0xfu << AFEC_SEQ1R_USCH3_Pos)
183 #define AFEC_SEQ1R_USCH3(value) ((AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos)))
184 #define AFEC_SEQ1R_USCH4_Pos 16
185 #define AFEC_SEQ1R_USCH4_Msk (0xfu << AFEC_SEQ1R_USCH4_Pos)
186 #define AFEC_SEQ1R_USCH4(value) ((AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos)))
187 #define AFEC_SEQ1R_USCH5_Pos 20
188 #define AFEC_SEQ1R_USCH5_Msk (0xfu << AFEC_SEQ1R_USCH5_Pos)
189 #define AFEC_SEQ1R_USCH5(value) ((AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos)))
190 #define AFEC_SEQ1R_USCH6_Pos 24
191 #define AFEC_SEQ1R_USCH6_Msk (0xfu << AFEC_SEQ1R_USCH6_Pos)
192 #define AFEC_SEQ1R_USCH6(value) ((AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos)))
193 #define AFEC_SEQ1R_USCH7_Pos 28
194 #define AFEC_SEQ1R_USCH7_Msk (0xfu << AFEC_SEQ1R_USCH7_Pos)
195 #define AFEC_SEQ1R_USCH7(value) ((AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos)))
196 /* -------- AFEC_SEQ2R : (AFEC Offset: 0x10) AFEC Channel Sequence 2 Register -------- */
197 #define AFEC_SEQ2R_USCH8_Pos 0
198 #define AFEC_SEQ2R_USCH8_Msk (0xfu << AFEC_SEQ2R_USCH8_Pos)
199 #define AFEC_SEQ2R_USCH8(value) ((AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos)))
200 #define AFEC_SEQ2R_USCH9_Pos 4
201 #define AFEC_SEQ2R_USCH9_Msk (0xfu << AFEC_SEQ2R_USCH9_Pos)
202 #define AFEC_SEQ2R_USCH9(value) ((AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos)))
203 #define AFEC_SEQ2R_USCH10_Pos 8
204 #define AFEC_SEQ2R_USCH10_Msk (0xfu << AFEC_SEQ2R_USCH10_Pos)
205 #define AFEC_SEQ2R_USCH10(value) ((AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos)))
206 #define AFEC_SEQ2R_USCH11_Pos 12
207 #define AFEC_SEQ2R_USCH11_Msk (0xfu << AFEC_SEQ2R_USCH11_Pos)
208 #define AFEC_SEQ2R_USCH11(value) ((AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos)))
209 #define AFEC_SEQ2R_USCH12_Pos 16
210 #define AFEC_SEQ2R_USCH12_Msk (0xfu << AFEC_SEQ2R_USCH12_Pos)
211 #define AFEC_SEQ2R_USCH12(value) ((AFEC_SEQ2R_USCH12_Msk & ((value) << AFEC_SEQ2R_USCH12_Pos)))
212 #define AFEC_SEQ2R_USCH13_Pos 20
213 #define AFEC_SEQ2R_USCH13_Msk (0xfu << AFEC_SEQ2R_USCH13_Pos)
214 #define AFEC_SEQ2R_USCH13(value) ((AFEC_SEQ2R_USCH13_Msk & ((value) << AFEC_SEQ2R_USCH13_Pos)))
215 #define AFEC_SEQ2R_USCH14_Pos 24
216 #define AFEC_SEQ2R_USCH14_Msk (0xfu << AFEC_SEQ2R_USCH14_Pos)
217 #define AFEC_SEQ2R_USCH14(value) ((AFEC_SEQ2R_USCH14_Msk & ((value) << AFEC_SEQ2R_USCH14_Pos)))
218 #define AFEC_SEQ2R_USCH15_Pos 28
219 #define AFEC_SEQ2R_USCH15_Msk (0xfu << AFEC_SEQ2R_USCH15_Pos)
220 #define AFEC_SEQ2R_USCH15(value) ((AFEC_SEQ2R_USCH15_Msk & ((value) << AFEC_SEQ2R_USCH15_Pos)))
221 /* -------- AFEC_CHER : (AFEC Offset: 0x14) AFEC Channel Enable Register -------- */
222 #define AFEC_CHER_CH0 (0x1u << 0)
223 #define AFEC_CHER_CH1 (0x1u << 1)
224 #define AFEC_CHER_CH2 (0x1u << 2)
225 #define AFEC_CHER_CH3 (0x1u << 3)
226 #define AFEC_CHER_CH4 (0x1u << 4)
227 #define AFEC_CHER_CH5 (0x1u << 5)
228 #define AFEC_CHER_CH6 (0x1u << 6)
229 #define AFEC_CHER_CH7 (0x1u << 7)
230 #define AFEC_CHER_CH8 (0x1u << 8)
231 #define AFEC_CHER_CH9 (0x1u << 9)
232 #define AFEC_CHER_CH10 (0x1u << 10)
233 #define AFEC_CHER_CH11 (0x1u << 11)
234 /* -------- AFEC_CHDR : (AFEC Offset: 0x18) AFEC Channel Disable Register -------- */
235 #define AFEC_CHDR_CH0 (0x1u << 0)
236 #define AFEC_CHDR_CH1 (0x1u << 1)
237 #define AFEC_CHDR_CH2 (0x1u << 2)
238 #define AFEC_CHDR_CH3 (0x1u << 3)
239 #define AFEC_CHDR_CH4 (0x1u << 4)
240 #define AFEC_CHDR_CH5 (0x1u << 5)
241 #define AFEC_CHDR_CH6 (0x1u << 6)
242 #define AFEC_CHDR_CH7 (0x1u << 7)
243 #define AFEC_CHDR_CH8 (0x1u << 8)
244 #define AFEC_CHDR_CH9 (0x1u << 9)
245 #define AFEC_CHDR_CH10 (0x1u << 10)
246 #define AFEC_CHDR_CH11 (0x1u << 11)
247 /* -------- AFEC_CHSR : (AFEC Offset: 0x1C) AFEC Channel Status Register -------- */
248 #define AFEC_CHSR_CH0 (0x1u << 0)
249 #define AFEC_CHSR_CH1 (0x1u << 1)
250 #define AFEC_CHSR_CH2 (0x1u << 2)
251 #define AFEC_CHSR_CH3 (0x1u << 3)
252 #define AFEC_CHSR_CH4 (0x1u << 4)
253 #define AFEC_CHSR_CH5 (0x1u << 5)
254 #define AFEC_CHSR_CH6 (0x1u << 6)
255 #define AFEC_CHSR_CH7 (0x1u << 7)
256 #define AFEC_CHSR_CH8 (0x1u << 8)
257 #define AFEC_CHSR_CH9 (0x1u << 9)
258 #define AFEC_CHSR_CH10 (0x1u << 10)
259 #define AFEC_CHSR_CH11 (0x1u << 11)
260 /* -------- AFEC_LCDR : (AFEC Offset: 0x20) AFEC Last Converted Data Register -------- */
261 #define AFEC_LCDR_LDATA_Pos 0
262 #define AFEC_LCDR_LDATA_Msk (0xffffu << AFEC_LCDR_LDATA_Pos)
263 #define AFEC_LCDR_CHNB_Pos 24
264 #define AFEC_LCDR_CHNB_Msk (0xfu << AFEC_LCDR_CHNB_Pos)
265 /* -------- AFEC_IER : (AFEC Offset: 0x24) AFEC Interrupt Enable Register -------- */
266 #define AFEC_IER_EOC0 (0x1u << 0)
267 #define AFEC_IER_EOC1 (0x1u << 1)
268 #define AFEC_IER_EOC2 (0x1u << 2)
269 #define AFEC_IER_EOC3 (0x1u << 3)
270 #define AFEC_IER_EOC4 (0x1u << 4)
271 #define AFEC_IER_EOC5 (0x1u << 5)
272 #define AFEC_IER_EOC6 (0x1u << 6)
273 #define AFEC_IER_EOC7 (0x1u << 7)
274 #define AFEC_IER_EOC8 (0x1u << 8)
275 #define AFEC_IER_EOC9 (0x1u << 9)
276 #define AFEC_IER_EOC10 (0x1u << 10)
277 #define AFEC_IER_EOC11 (0x1u << 11)
278 #define AFEC_IER_DRDY (0x1u << 24)
279 #define AFEC_IER_GOVRE (0x1u << 25)
280 #define AFEC_IER_COMPE (0x1u << 26)
281 #define AFEC_IER_TEMPCHG (0x1u << 30)
282 /* -------- AFEC_IDR : (AFEC Offset: 0x28) AFEC Interrupt Disable Register -------- */
283 #define AFEC_IDR_EOC0 (0x1u << 0)
284 #define AFEC_IDR_EOC1 (0x1u << 1)
285 #define AFEC_IDR_EOC2 (0x1u << 2)
286 #define AFEC_IDR_EOC3 (0x1u << 3)
287 #define AFEC_IDR_EOC4 (0x1u << 4)
288 #define AFEC_IDR_EOC5 (0x1u << 5)
289 #define AFEC_IDR_EOC6 (0x1u << 6)
290 #define AFEC_IDR_EOC7 (0x1u << 7)
291 #define AFEC_IDR_EOC8 (0x1u << 8)
292 #define AFEC_IDR_EOC9 (0x1u << 9)
293 #define AFEC_IDR_EOC10 (0x1u << 10)
294 #define AFEC_IDR_EOC11 (0x1u << 11)
295 #define AFEC_IDR_DRDY (0x1u << 24)
296 #define AFEC_IDR_GOVRE (0x1u << 25)
297 #define AFEC_IDR_COMPE (0x1u << 26)
298 #define AFEC_IDR_TEMPCHG (0x1u << 30)
299 /* -------- AFEC_IMR : (AFEC Offset: 0x2C) AFEC Interrupt Mask Register -------- */
300 #define AFEC_IMR_EOC0 (0x1u << 0)
301 #define AFEC_IMR_EOC1 (0x1u << 1)
302 #define AFEC_IMR_EOC2 (0x1u << 2)
303 #define AFEC_IMR_EOC3 (0x1u << 3)
304 #define AFEC_IMR_EOC4 (0x1u << 4)
305 #define AFEC_IMR_EOC5 (0x1u << 5)
306 #define AFEC_IMR_EOC6 (0x1u << 6)
307 #define AFEC_IMR_EOC7 (0x1u << 7)
308 #define AFEC_IMR_EOC8 (0x1u << 8)
309 #define AFEC_IMR_EOC9 (0x1u << 9)
310 #define AFEC_IMR_EOC10 (0x1u << 10)
311 #define AFEC_IMR_EOC11 (0x1u << 11)
312 #define AFEC_IMR_DRDY (0x1u << 24)
313 #define AFEC_IMR_GOVRE (0x1u << 25)
314 #define AFEC_IMR_COMPE (0x1u << 26)
315 #define AFEC_IMR_TEMPCHG (0x1u << 30)
316 /* -------- AFEC_ISR : (AFEC Offset: 0x30) AFEC Interrupt Status Register -------- */
317 #define AFEC_ISR_EOC0 (0x1u << 0)
318 #define AFEC_ISR_EOC1 (0x1u << 1)
319 #define AFEC_ISR_EOC2 (0x1u << 2)
320 #define AFEC_ISR_EOC3 (0x1u << 3)
321 #define AFEC_ISR_EOC4 (0x1u << 4)
322 #define AFEC_ISR_EOC5 (0x1u << 5)
323 #define AFEC_ISR_EOC6 (0x1u << 6)
324 #define AFEC_ISR_EOC7 (0x1u << 7)
325 #define AFEC_ISR_EOC8 (0x1u << 8)
326 #define AFEC_ISR_EOC9 (0x1u << 9)
327 #define AFEC_ISR_EOC10 (0x1u << 10)
328 #define AFEC_ISR_EOC11 (0x1u << 11)
329 #define AFEC_ISR_DRDY (0x1u << 24)
330 #define AFEC_ISR_GOVRE (0x1u << 25)
331 #define AFEC_ISR_COMPE (0x1u << 26)
332 #define AFEC_ISR_TEMPCHG (0x1u << 30)
333 /* -------- AFEC_OVER : (AFEC Offset: 0x4C) AFEC Overrun Status Register -------- */
334 #define AFEC_OVER_OVRE0 (0x1u << 0)
335 #define AFEC_OVER_OVRE1 (0x1u << 1)
336 #define AFEC_OVER_OVRE2 (0x1u << 2)
337 #define AFEC_OVER_OVRE3 (0x1u << 3)
338 #define AFEC_OVER_OVRE4 (0x1u << 4)
339 #define AFEC_OVER_OVRE5 (0x1u << 5)
340 #define AFEC_OVER_OVRE6 (0x1u << 6)
341 #define AFEC_OVER_OVRE7 (0x1u << 7)
342 #define AFEC_OVER_OVRE8 (0x1u << 8)
343 #define AFEC_OVER_OVRE9 (0x1u << 9)
344 #define AFEC_OVER_OVRE10 (0x1u << 10)
345 #define AFEC_OVER_OVRE11 (0x1u << 11)
346 /* -------- AFEC_CWR : (AFEC Offset: 0x50) AFEC Compare Window Register -------- */
347 #define AFEC_CWR_LOWTHRES_Pos 0
348 #define AFEC_CWR_LOWTHRES_Msk (0xffffu << AFEC_CWR_LOWTHRES_Pos)
349 #define AFEC_CWR_LOWTHRES(value) ((AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos)))
350 #define AFEC_CWR_HIGHTHRES_Pos 16
351 #define AFEC_CWR_HIGHTHRES_Msk (0xffffu << AFEC_CWR_HIGHTHRES_Pos)
352 #define AFEC_CWR_HIGHTHRES(value) ((AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos)))
353 /* -------- AFEC_CGR : (AFEC Offset: 0x54) AFEC Channel Gain Register -------- */
354 #define AFEC_CGR_GAIN0_Pos 0
355 #define AFEC_CGR_GAIN0_Msk (0x3u << AFEC_CGR_GAIN0_Pos)
356 #define AFEC_CGR_GAIN0(value) ((AFEC_CGR_GAIN0_Msk & ((value) << AFEC_CGR_GAIN0_Pos)))
357 #define AFEC_CGR_GAIN1_Pos 2
358 #define AFEC_CGR_GAIN1_Msk (0x3u << AFEC_CGR_GAIN1_Pos)
359 #define AFEC_CGR_GAIN1(value) ((AFEC_CGR_GAIN1_Msk & ((value) << AFEC_CGR_GAIN1_Pos)))
360 #define AFEC_CGR_GAIN2_Pos 4
361 #define AFEC_CGR_GAIN2_Msk (0x3u << AFEC_CGR_GAIN2_Pos)
362 #define AFEC_CGR_GAIN2(value) ((AFEC_CGR_GAIN2_Msk & ((value) << AFEC_CGR_GAIN2_Pos)))
363 #define AFEC_CGR_GAIN3_Pos 6
364 #define AFEC_CGR_GAIN3_Msk (0x3u << AFEC_CGR_GAIN3_Pos)
365 #define AFEC_CGR_GAIN3(value) ((AFEC_CGR_GAIN3_Msk & ((value) << AFEC_CGR_GAIN3_Pos)))
366 #define AFEC_CGR_GAIN4_Pos 8
367 #define AFEC_CGR_GAIN4_Msk (0x3u << AFEC_CGR_GAIN4_Pos)
368 #define AFEC_CGR_GAIN4(value) ((AFEC_CGR_GAIN4_Msk & ((value) << AFEC_CGR_GAIN4_Pos)))
369 #define AFEC_CGR_GAIN5_Pos 10
370 #define AFEC_CGR_GAIN5_Msk (0x3u << AFEC_CGR_GAIN5_Pos)
371 #define AFEC_CGR_GAIN5(value) ((AFEC_CGR_GAIN5_Msk & ((value) << AFEC_CGR_GAIN5_Pos)))
372 #define AFEC_CGR_GAIN6_Pos 12
373 #define AFEC_CGR_GAIN6_Msk (0x3u << AFEC_CGR_GAIN6_Pos)
374 #define AFEC_CGR_GAIN6(value) ((AFEC_CGR_GAIN6_Msk & ((value) << AFEC_CGR_GAIN6_Pos)))
375 #define AFEC_CGR_GAIN7_Pos 14
376 #define AFEC_CGR_GAIN7_Msk (0x3u << AFEC_CGR_GAIN7_Pos)
377 #define AFEC_CGR_GAIN7(value) ((AFEC_CGR_GAIN7_Msk & ((value) << AFEC_CGR_GAIN7_Pos)))
378 #define AFEC_CGR_GAIN8_Pos 16
379 #define AFEC_CGR_GAIN8_Msk (0x3u << AFEC_CGR_GAIN8_Pos)
380 #define AFEC_CGR_GAIN8(value) ((AFEC_CGR_GAIN8_Msk & ((value) << AFEC_CGR_GAIN8_Pos)))
381 #define AFEC_CGR_GAIN9_Pos 18
382 #define AFEC_CGR_GAIN9_Msk (0x3u << AFEC_CGR_GAIN9_Pos)
383 #define AFEC_CGR_GAIN9(value) ((AFEC_CGR_GAIN9_Msk & ((value) << AFEC_CGR_GAIN9_Pos)))
384 #define AFEC_CGR_GAIN10_Pos 20
385 #define AFEC_CGR_GAIN10_Msk (0x3u << AFEC_CGR_GAIN10_Pos)
386 #define AFEC_CGR_GAIN10(value) ((AFEC_CGR_GAIN10_Msk & ((value) << AFEC_CGR_GAIN10_Pos)))
387 #define AFEC_CGR_GAIN11_Pos 22
388 #define AFEC_CGR_GAIN11_Msk (0x3u << AFEC_CGR_GAIN11_Pos)
389 #define AFEC_CGR_GAIN11(value) ((AFEC_CGR_GAIN11_Msk & ((value) << AFEC_CGR_GAIN11_Pos)))
390 /* -------- AFEC_DIFFR : (AFEC Offset: 0x60) AFEC Channel Differential Register -------- */
391 #define AFEC_DIFFR_DIFF0 (0x1u << 0)
392 #define AFEC_DIFFR_DIFF1 (0x1u << 1)
393 #define AFEC_DIFFR_DIFF2 (0x1u << 2)
394 #define AFEC_DIFFR_DIFF3 (0x1u << 3)
395 #define AFEC_DIFFR_DIFF4 (0x1u << 4)
396 #define AFEC_DIFFR_DIFF5 (0x1u << 5)
397 #define AFEC_DIFFR_DIFF6 (0x1u << 6)
398 #define AFEC_DIFFR_DIFF7 (0x1u << 7)
399 #define AFEC_DIFFR_DIFF8 (0x1u << 8)
400 #define AFEC_DIFFR_DIFF9 (0x1u << 9)
401 #define AFEC_DIFFR_DIFF10 (0x1u << 10)
402 #define AFEC_DIFFR_DIFF11 (0x1u << 11)
403 /* -------- AFEC_CSELR : (AFEC Offset: 0x64) AFEC Channel Selection Register -------- */
404 #define AFEC_CSELR_CSEL_Pos 0
405 #define AFEC_CSELR_CSEL_Msk (0xfu << AFEC_CSELR_CSEL_Pos)
406 #define AFEC_CSELR_CSEL(value) ((AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos)))
407 /* -------- AFEC_CDR : (AFEC Offset: 0x68) AFEC Channel Data Register -------- */
408 #define AFEC_CDR_DATA_Pos 0
409 #define AFEC_CDR_DATA_Msk (0xffffu << AFEC_CDR_DATA_Pos)
410 /* -------- AFEC_COCR : (AFEC Offset: 0x6C) AFEC Channel Offset Compensation Register -------- */
411 #define AFEC_COCR_AOFF_Pos 0
412 #define AFEC_COCR_AOFF_Msk (0x3ffu << AFEC_COCR_AOFF_Pos)
413 #define AFEC_COCR_AOFF(value) ((AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos)))
414 /* -------- AFEC_TEMPMR : (AFEC Offset: 0x70) AFEC Temperature Sensor Mode Register -------- */
415 #define AFEC_TEMPMR_RTCT (0x1u << 0)
416 #define AFEC_TEMPMR_TEMPCMPMOD_Pos 4
417 #define AFEC_TEMPMR_TEMPCMPMOD_Msk (0x3u << AFEC_TEMPMR_TEMPCMPMOD_Pos)
418 #define AFEC_TEMPMR_TEMPCMPMOD(value) ((AFEC_TEMPMR_TEMPCMPMOD_Msk & ((value) << AFEC_TEMPMR_TEMPCMPMOD_Pos)))
419 #define AFEC_TEMPMR_TEMPCMPMOD_LOW (0x0u << 4)
420 #define AFEC_TEMPMR_TEMPCMPMOD_HIGH (0x1u << 4)
421 #define AFEC_TEMPMR_TEMPCMPMOD_IN (0x2u << 4)
422 #define AFEC_TEMPMR_TEMPCMPMOD_OUT (0x3u << 4)
423 /* -------- AFEC_TEMPCWR : (AFEC Offset: 0x74) AFEC Temperature Compare Window Register -------- */
424 #define AFEC_TEMPCWR_TLOWTHRES_Pos 0
425 #define AFEC_TEMPCWR_TLOWTHRES_Msk (0xffffu << AFEC_TEMPCWR_TLOWTHRES_Pos)
426 #define AFEC_TEMPCWR_TLOWTHRES(value) ((AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos)))
427 #define AFEC_TEMPCWR_THIGHTHRES_Pos 16
428 #define AFEC_TEMPCWR_THIGHTHRES_Msk (0xffffu << AFEC_TEMPCWR_THIGHTHRES_Pos)
429 #define AFEC_TEMPCWR_THIGHTHRES(value) ((AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos)))
430 /* -------- AFEC_ACR : (AFEC Offset: 0x94) AFEC Analog Control Register -------- */
431 #define AFEC_ACR_PGA0EN (0x1u << 2)
432 #define AFEC_ACR_PGA1EN (0x1u << 3)
433 #define AFEC_ACR_IBCTL_Pos 8
434 #define AFEC_ACR_IBCTL_Msk (0x3u << AFEC_ACR_IBCTL_Pos)
435 #define AFEC_ACR_IBCTL(value) ((AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos)))
436 /* -------- AFEC_SHMR : (AFEC Offset: 0xA0) AFEC Sample & Hold Mode Register -------- */
437 #define AFEC_SHMR_DUAL0 (0x1u << 0)
438 #define AFEC_SHMR_DUAL1 (0x1u << 1)
439 #define AFEC_SHMR_DUAL2 (0x1u << 2)
440 #define AFEC_SHMR_DUAL3 (0x1u << 3)
441 #define AFEC_SHMR_DUAL4 (0x1u << 4)
442 #define AFEC_SHMR_DUAL5 (0x1u << 5)
443 #define AFEC_SHMR_DUAL6 (0x1u << 6)
444 #define AFEC_SHMR_DUAL7 (0x1u << 7)
445 #define AFEC_SHMR_DUAL8 (0x1u << 8)
446 #define AFEC_SHMR_DUAL9 (0x1u << 9)
447 #define AFEC_SHMR_DUAL10 (0x1u << 10)
448 #define AFEC_SHMR_DUAL11 (0x1u << 11)
449 /* -------- AFEC_COSR : (AFEC Offset: 0xD0) AFEC Correction Select Register -------- */
450 #define AFEC_COSR_CSEL (0x1u << 0)
451 /* -------- AFEC_CVR : (AFEC Offset: 0xD4) AFEC Correction Values Register -------- */
452 #define AFEC_CVR_OFFSETCORR_Pos 0
453 #define AFEC_CVR_OFFSETCORR_Msk (0xffffu << AFEC_CVR_OFFSETCORR_Pos)
454 #define AFEC_CVR_OFFSETCORR(value) ((AFEC_CVR_OFFSETCORR_Msk & ((value) << AFEC_CVR_OFFSETCORR_Pos)))
455 #define AFEC_CVR_GAINCORR_Pos 16
456 #define AFEC_CVR_GAINCORR_Msk (0xffffu << AFEC_CVR_GAINCORR_Pos)
457 #define AFEC_CVR_GAINCORR(value) ((AFEC_CVR_GAINCORR_Msk & ((value) << AFEC_CVR_GAINCORR_Pos)))
458 /* -------- AFEC_CECR : (AFEC Offset: 0xD8) AFEC Channel Error Correction Register -------- */
459 #define AFEC_CECR_ECORR0 (0x1u << 0)
460 #define AFEC_CECR_ECORR1 (0x1u << 1)
461 #define AFEC_CECR_ECORR2 (0x1u << 2)
462 #define AFEC_CECR_ECORR3 (0x1u << 3)
463 #define AFEC_CECR_ECORR4 (0x1u << 4)
464 #define AFEC_CECR_ECORR5 (0x1u << 5)
465 #define AFEC_CECR_ECORR6 (0x1u << 6)
466 #define AFEC_CECR_ECORR7 (0x1u << 7)
467 #define AFEC_CECR_ECORR8 (0x1u << 8)
468 #define AFEC_CECR_ECORR9 (0x1u << 9)
469 #define AFEC_CECR_ECORR10 (0x1u << 10)
470 #define AFEC_CECR_ECORR11 (0x1u << 11)
471 /* -------- AFEC_WPMR : (AFEC Offset: 0xE4) AFEC Write Protection Mode Register -------- */
472 #define AFEC_WPMR_WPEN (0x1u << 0)
473 #define AFEC_WPMR_WPKEY_Pos 8
474 #define AFEC_WPMR_WPKEY_Msk (0xffffffu << AFEC_WPMR_WPKEY_Pos)
475 #define AFEC_WPMR_WPKEY(value) ((AFEC_WPMR_WPKEY_Msk & ((value) << AFEC_WPMR_WPKEY_Pos)))
476 #define AFEC_WPMR_WPKEY_PASSWD (0x414443u << 8)
477 /* -------- AFEC_WPSR : (AFEC Offset: 0xE8) AFEC Write Protection Status Register -------- */
478 #define AFEC_WPSR_WPVS (0x1u << 0)
479 #define AFEC_WPSR_WPVSRC_Pos 8
480 #define AFEC_WPSR_WPVSRC_Msk (0xffffu << AFEC_WPSR_WPVSRC_Pos)
481 /* -------- AFEC_VERSION : (AFEC Offset: 0xFC) AFEC Version Register -------- */
482 #define AFEC_VERSION_VERSION_Pos 0
483 #define AFEC_VERSION_VERSION_Msk (0xfffu << AFEC_VERSION_VERSION_Pos)
484 #define AFEC_VERSION_MFN_Pos 16
485 #define AFEC_VERSION_MFN_Msk (0x7u << AFEC_VERSION_MFN_Pos)
488 
489 
490 #endif /* _SAMV71_AFEC_COMPONENT_ */
__IO
#define __IO
Definition: core_cm7.h:287
__O
#define __O
Definition: core_cm7.h:286
Afec::AFEC_VERSION
__I uint32_t AFEC_VERSION
(Afec Offset: 0xFC) AFEC Version Register
Definition: component_afec.h:78
Afec
Afec hardware registers.
Definition: component_afec.h:41
__I
#define __I
Definition: core_cm7.h:284
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