component_acc.h

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#ifndef _SAMV71_ACC_COMPONENT_
#define _SAMV71_ACC_COMPONENT_

/* ============================================================================= */
/* ============================================================================= */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {
  __O  uint32_t ACC_CR;        
  __IO uint32_t ACC_MR;        
  __I  uint32_t Reserved1[7];
  __O  uint32_t ACC_IER;       
  __O  uint32_t ACC_IDR;       
  __I  uint32_t ACC_IMR;       
  __I  uint32_t ACC_ISR;       
  __I  uint32_t Reserved2[24];
  __IO uint32_t ACC_ACR;       
  __I  uint32_t Reserved3[19];
  __IO uint32_t ACC_WPMR;      
  __I  uint32_t ACC_WPSR;      
  __I  uint32_t Reserved4[4];
  __I  uint32_t ACC_VER;       
} Acc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */
#define ACC_CR_SWRST (0x1u << 0) 
/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */
#define ACC_MR_SELMINUS_Pos 0
#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) 
#define ACC_MR_SELMINUS(value) ((ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos)))
#define   ACC_MR_SELMINUS_TS (0x0u << 0) 
#define   ACC_MR_SELMINUS_VREFP (0x1u << 0) 
#define   ACC_MR_SELMINUS_DAC0 (0x2u << 0) 
#define   ACC_MR_SELMINUS_DAC1 (0x3u << 0) 
#define   ACC_MR_SELMINUS_AFE0_AD0 (0x4u << 0) 
#define   ACC_MR_SELMINUS_AFE0_AD1 (0x5u << 0) 
#define   ACC_MR_SELMINUS_AFE0_AD2 (0x6u << 0) 
#define   ACC_MR_SELMINUS_AFE0_AD3 (0x7u << 0) 
#define ACC_MR_SELPLUS_Pos 4
#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) 
#define ACC_MR_SELPLUS(value) ((ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos)))
#define   ACC_MR_SELPLUS_AFE0_AD0 (0x0u << 4) 
#define   ACC_MR_SELPLUS_AFE0_AD1 (0x1u << 4) 
#define   ACC_MR_SELPLUS_AFE0_AD2 (0x2u << 4) 
#define   ACC_MR_SELPLUS_AFE0_AD3 (0x3u << 4) 
#define   ACC_MR_SELPLUS_AFE0_AD4 (0x4u << 4) 
#define   ACC_MR_SELPLUS_AFE0_AD5 (0x5u << 4) 
#define   ACC_MR_SELPLUS_AFE1_AD0 (0x6u << 4) 
#define   ACC_MR_SELPLUS_AFE1_AD1 (0x7u << 4) 
#define ACC_MR_ACEN (0x1u << 8) 
#define   ACC_MR_ACEN_DIS (0x0u << 8) 
#define   ACC_MR_ACEN_EN (0x1u << 8) 
#define ACC_MR_EDGETYP_Pos 9
#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) 
#define ACC_MR_EDGETYP(value) ((ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos)))
#define   ACC_MR_EDGETYP_RISING (0x0u << 9) 
#define   ACC_MR_EDGETYP_FALLING (0x1u << 9) 
#define   ACC_MR_EDGETYP_ANY (0x2u << 9) 
#define ACC_MR_INV (0x1u << 12) 
#define   ACC_MR_INV_DIS (0x0u << 12) 
#define   ACC_MR_INV_EN (0x1u << 12) 
#define ACC_MR_SELFS (0x1u << 13) 
#define   ACC_MR_SELFS_CE (0x0u << 13) 
#define   ACC_MR_SELFS_OUTPUT (0x1u << 13) 
#define ACC_MR_FE (0x1u << 14) 
#define   ACC_MR_FE_DIS (0x0u << 14) 
#define   ACC_MR_FE_EN (0x1u << 14) 
/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */
#define ACC_IER_CE (0x1u << 0) 
/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */
#define ACC_IDR_CE (0x1u << 0) 
/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */
#define ACC_IMR_CE (0x1u << 0) 
/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */
#define ACC_ISR_CE (0x1u << 0) 
#define ACC_ISR_SCO (0x1u << 1) 
#define ACC_ISR_MASK (0x1u << 31) 
/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */
#define ACC_ACR_ISEL (0x1u << 0) 
#define   ACC_ACR_ISEL_LOPW (0x0u << 0) 
#define   ACC_ACR_ISEL_HISP (0x1u << 0) 
#define ACC_ACR_HYST_Pos 1
#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) 
#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos)))
/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protection Mode Register -------- */
#define ACC_WPMR_WPEN (0x1u << 0) 
#define ACC_WPMR_WPKEY_Pos 8
#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) 
#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos)))
#define   ACC_WPMR_WPKEY_PASSWD (0x414343u << 8) 
/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protection Status Register -------- */
#define ACC_WPSR_WPVS (0x1u << 0) 
/* -------- ACC_VER : (ACC Offset: 0xFC) Version Register -------- */
#define ACC_VER_VERSION_Pos 0
#define ACC_VER_VERSION_Msk (0xfffu << ACC_VER_VERSION_Pos) 
#define ACC_VER_MFN_Pos 16
#define ACC_VER_MFN_Msk (0x7u << ACC_VER_MFN_Pos) 


#endif /* _SAMV71_ACC_COMPONENT_ */