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#define | SAM(a, b, c) ((a << b) & c) |
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#define | QSM_CRB 0x7ffc00 |
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#define | QSMCR (volatile unsigned short int * const)(0x00 + QSM_CRB) |
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#define | STOP 0x8000 /* Stop Enable */ |
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#define | FRZ 0x6000 /* Freeze Control */ |
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#define | SUPV 0x0080 /* Supervisor/Unrestricted */ |
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#define | IARB 0x000f /* Inerrupt Arbitration */ |
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#define | QTEST (volatile unsigned short int * const)(0x02 + QSM_CRB) |
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#define | QILR (volatile unsigned char * const)(0x04 + QSM_CRB) |
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#define | ILQSPI 0x38 /* Interrupt Level for QSPI */ |
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#define | ILSCI 0x07 /* Interrupt Level for SCI */ |
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#define | QIVR (volatile unsigned char * const)(0x05 + QSM_CRB) |
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#define | INTV 0xff /* Interrupt Vector Number */ |
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#define | SCCR0 (volatile unsigned short int * const)(0x08 + QSM_CRB) |
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#define | SCBR 0x1fff /* SCI Baud Rate */ |
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#define | SCCR1 (volatile unsigned short int * const)(0x0a + QSM_CRB) |
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#define | LOOPS 0x4000 /* Loop Mode */ |
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#define | WOMS 0x2000 /* Wired-OR Mode for SCI Pins */ |
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#define | ILT 0x1000 /* Idle-Line Detect Type */ |
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#define | PT 0x0800 /* Parity Type */ |
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#define | PE 0x0400 /* Parity Enable */ |
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#define | M 0x0200 /* Mode Select */ |
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#define | WAKE 0x0100 /* Wakeup by Address Mark */ |
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#define | TIE 0x0080 /* Transmit Complete Interrupt Enable */ |
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#define | TCIE 0x0040 /* Transmit Complete Interrupt Enable */ |
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#define | RIE 0x0020 /* Receiver Interrupt Enable */ |
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#define | ILIE 0x0010 /* Idle-Line Interrupt Enable */ |
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#define | TE 0x0008 /* Transmitter Enable */ |
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#define | RE 0x0004 /* Receiver Enable */ |
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#define | RWU 0x0002 /* Receiver Wakeup */ |
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#define | SBK 0x0001 /* Send Break */ |
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#define | SCSR (volatile unsigned short int * const)(0x0c + QSM_CRB) |
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#define | TDRE 0x0100 /* Transmit Data Register Empty */ |
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#define | TC 0x0080 /* Transmit Complete */ |
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#define | RDRF 0x0040 /* Receive Data Register Full */ |
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#define | RAF 0x0020 /* Receiver Active */ |
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#define | IDLE 0x0010 /* Idle-Line Detected */ |
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#define | OR 0x0008 /* Overrun Error */ |
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#define | NF 0x0004 /* Noise Error Flag */ |
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#define | FE 0x0002 /* Framing Error */ |
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#define | PF 0x0001 /* Parity Error */ |
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#define | SCDR (volatile unsigned short int * const)(0x0e + QSM_CRB) |
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#define | PORTQS (volatile unsigned char * const)(0x15 + QSM_CRB) |
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#define | PQSPAR (volatile unsigned char * const)(0x16 + QSM_CRB) |
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#define | QSMFun 0x0 |
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#define | QSMDis 0x1 |
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#define | PQSPA0 0 /* MISO | PQS0 */ |
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#define | PQSPA1 1 /* MOSI | PQS1 */ |
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#define | PQSPA2 2 /* SCK | PQS2 (see note)*/ |
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#define | PQSPA3 3 /* PCSO/!SS | PQS3 */ |
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#define | PQSPA4 4 /* PCS1 | PQS4 */ |
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#define | PQSPA5 5 /* PCS2 | PQS5 */ |
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#define | PQSPA6 6 /* PCS3 | PQS6 */ |
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#define | PQSPA7 7 /* TxD | PQS7 (see note)*/ |
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#define | DDRQS (volatile unsigned char * const)(0x17 + QSM_CRB) |
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#define | SPCR0 (volatile unsigned short int * const)(0x18 + QSM_CRB) |
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#define | MSTR 0x8000 /* Master/Slave Mode Select */ |
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#define | WOMQ 0x4000 /* Wired-OR Mode for QSPI Pins */ |
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#define | BITS 0x3c00 /* Bits Per Transfer */ |
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#define | CPOL 0x0200 /* Clock Polarity */ |
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#define | CPHA 0x0100 /* Clock Phase */ |
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#define | SPBR 0x00ff /* Serial Clock Baud Rate */ |
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#define | SPCR1 (volatile unsigned short int * const)(0x1a + QSM_CRB) |
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#define | SPE 0x8000 /* QSPI Enable */ |
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#define | DSCKL 0x7f00 /* Delay before SCK */ |
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#define | DTL 0x00ff /* Length of Delay after Transfer */ |
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#define | SPCR2 (volatile unsigned short int * const)(0x1c + QSM_CRB) |
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#define | SPIFIE 0x8000 /* SPI Finished Interrupt Enable */ |
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#define | WREN 0x4000 /* Wrap Enable */ |
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#define | WRTO 0x2000 /* Wrap To */ |
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#define | ENDQP 0x0f00 /* Ending Queue Pointer */ |
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#define | NEWQP 0x000f /* New Queue Pointer Value */ |
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#define | SPCR3 (volatile unsigned char * const)(0x1e + QSM_CRB) |
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#define | LOOPQ 0x0400 /* QSPI Loop Mode */ |
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#define | HMIE 0x0200 /* HALTA and MODF Interrupt Enable */ |
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#define | HALT 0x0100 /* Halt */ |
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#define | SPSR (volatile unsigned char * const)(0x1f + QSM_CRB) |
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#define | SPIF 0x0080 /* QSPI Finished Flag */ |
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#define | MODF 0x0040 /* Mode Fault Flag */ |
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#define | HALTA 0x0020 /* Halt Acknowlwdge Flag */ |
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#define | CPTQP x0000f /* Completed Queue Pointer */ |
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#define | QSPIRR (volatile unsigned char * const)(0x100 + QSM_CRB) |
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#define | QSPITR (volatile unsigned char * const)(0x120 + QSM_CRB) |
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#define | QSPIcR (volatile unsigned char * const)(0x140 + QSM_CRB) |
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Motorola M68K Queued Serial Module.
The QSM contains two serial interfaces: (a) the queued serial peripheral interface (QSPI) and the serial communication interface (SCI). The QSPI provides peripheral expansion and/or interprocessor communication through a full-duplex, synchronous, three-wire bus. A self contained RAM queue permits serial data transfers without CPU intervention and automatic continuous sampling. The SCI provides a standard non-return to zero mark/space format with wakeup functions to allow the CPU to run uninterrupted until woken
For more information, refer to Motorola's "Modular Microcontroller
Family Queued Serial Module Reference Manual" (Motorola document QSMRM/AD).
1.8.15